BASIC DIGITAL ELECTRONIC

EXPERIMENTS FOR PHYSICISTS

A.Necmeddin YAZICI










University of GAZANTEP

B

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0
D
3
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BASIC DIGITAL ELECTRONIC
EXPERIMENTS FOR PHYSICISTS








A.Necmeddin YAZICI








Faculty of Engineering
Department of Engineering Physics






University of GAZANTEP
2001

iii



University of Gaziantep, (2001). All
rights reserved. This book, or therefore, may
not be reproduced in any form without
permission of the publisher.







Published by the University of Gaziantep
Gaziantep-Turkey






ISBN..







University of Gaziantep Presss

Tlf: 0 (342) 360 12 00 15 72


iv
CONTENTS
Page
1. Contents iv
2. Preface v
2. EP 427 Digital Electronic Introductory Remarks for the Student 1
3. Introduction 4
3a. Laboratory Rules 4
3b. Safety Precautions 4
3c. Laboratory Report 5
4. Experiment 1 : Basic Logic Gates 7
5. Experiment 2 : Boolean Algebra and Simplification of Logic Equations 17
6. Experiment 3 : DeMorgans Theorem 22
7. Experiment 4 : Exclusive-OR and Exclusive-NOR Gates 25
8. Experiment 5 : Half-Adder and Half-Subtractor 29
9. Experiment 6 : Binary Comparators 32
10. Experiment 7 : Parity Generators and Checkers 34
11. Experiment 8 : Full-Adder and Full-Subtractor 38
12. Experiment 9 : Code Converters 44
13. Experiment 10 : Decoders and Encoders 48
14. Experiment 11 : Multiplexers and Demultiplexers 55
15. Experiment 12 : Flip-Flops 62
16. References 67
17. Appendix A : Glossary of Login and Integrated-Circuit Terminology 68
18. Appendix B: Supplementary Index of ICs 74
19. Appendix C: TTL Pin Connections 76


v
PREFACE

This laboratory manual book has been developed to provide laboratory training and
experience in elementary digital electronic for physicists and physics engineers using
integrated circuits in the laboratory environment of the industrial electronics laboratory.
Thus, this manual has been prepared as an auxiliary book for EP 427 Digital Electronic
course. This course has been taught in the Department of Engineering Physics for many
years as a technical elective course at senior level.
Twelve experiments are included in this manual to provide through coverage of
basic digital principles. They begin with a series of experiments on the principles of basic
logic gates and their application in digital electronics and follow with the last experiment
of flip-flops. Many types of IC logic families have been explained in the relevant sections
and pin connections of many TTL have been given at the end of the laboratory manual
book.
Each experiment is divided into four sections: 1-) Purpose, 2-) Theory, 3-)
Experimental Procedure, and 4-) Discussion and Conclusions about the experiment. The
theory section gives required brief information about the experiments subject. Although the
theoretical background for the experiment is provided at the theory section through each
experiment, the necessary further information should be obtained during the theoretical
consideration of this course and from many auxiliary books that are available in our library.
The discussion and conclusion part should include the necessary interested questions about
the experiment and related subjects to understand very well the experiment and its related
subjects and also for the evaluation and the significance of the results of the experiment.
I wish to express my thanks to Expert Ziya GESOLU, MsC student V.Emir
KAFADAR and for all of the staffs in Engineering Physics Department for their assistance
and friendship during the preparation of this laboratory manual. Especially, I would like
extent my thanks and appreciation to my wife and daughters for their patience and
encouragement during the preparation of this book.


Assist.Prof.Dr.A.Necmeddin YAZICI
December 2001,Gaziantep University

1
EP 427 DIGITAL ELECTRONIC
INTRODUCTORY REMARKS FOR THE STUDENT

In analog electronic circuits, voltage levels can vary continuously in time. A
transistor amplifier, for example, can amplify any voltage level within a specified range.
Digital circuit voltage levels, however are restricted to values which are predetermined. In
most digital circuits there are only two allowed voltage levels which are 0 V and 5 V.
These voltage levels are referred to as logic levels. The levels 0 V and 5 V correspond to
logic-0 and logic-1 as binary variable. This shows that any logic function which uses
binary variables can be implemented by digital circuits. In digital circuits, logic-1 and
logic-0 may be represented by voltage regions. The voltage regions between 2 V and 4 V
may be accepted as logic-1. Similarly, the region between -0.5 and 0.5 is taken as logic-0.
The intermediate region between these allowed regions is crossed only during state
transition. The input terminals of digital circuits accept binary signal within the allowable
tolerances and respond at the output terminal with binary signals that fall within the
specified tolerances.
Digital circuits are invariably constructed with integrated circuits (IC). An IC is a
small silicon semiconductor crystal, called a chip containing various electrical components.
The various components are interconnected inside the chip to form an electronic circuit.
The chip is mounted on a metal or plastic package, and connections are welded to external
pins to form the IC. The envelope of the IC package is made of plastic or ceramic. Most
packages have standard sizes, and the number of pins ranges from 8 to 64. IC has a
numeric designation printed on the surface of the package for identification. Each vender
published a data book or catalog that provides the necessary information concerning the
various products.
The ICs in the experiment are all in the dual-in-time 14-pin or 16-pin
configuration. They do not have a great over voltage tolerance before their dissipation is
exceeded. The procedure of calibrating the cathode ray oscilloscope (CRO) and checking
the power supply voltage against IC will protect it against over voltage and at the same
time provide some additional CRO experience.
Although the wiring in some experiments is somewhat complex, a wiring layout as
clone as possible to the circuit drawing will help in trouble-shooting.
2
A long lead from a bistable, or counter, or intermediate outputs of a counter, or
monostable multivibrator may cause undesired loading and prevent the bistable from
toggling or dividing properly, or the monostable from functioning properly. If such
difficulties are encountered, a composition of 2200 O decoupling resistor at the IC end of
the lead can eliminate the loading problems. The lead length from the 2200 O resistor to
the IC should be kept short. This decoupling may be needed both for the CRO vertical
input and for external triggering.
The pin terminals progress in a counterclockwise direction seen from the top side
away from the pins. The ICs are in either 14-pin or l6-pin location by an identifying
symbol, or the location pins 1 and 14 (14 pin IC) or pins 1 and 16 (16 pin IC) are identified
by an index notch at the end of the case where these pins are located This is illustrated in
the below figure.

The laboratory sheets were developed to provide you with laboratory experiments
and experience to let you more easily understand the theoretical material covered in the
classroom, and to provide you practical illustrations of how combinations of these simple
building blocks can yield complex and useful systems.
To analyze the performance of these digital blocks, the most useful measuring tool
is the CRO because it not only measures voltage but it can measure time, displaying both
the waveforms of digital electronics and their relative time of occurrence. Almost all
measurements in the experiments are performed by the CRO.
While wiring the circuits diagrams use the connecting wires as short as possible.
Leads that are too long introduce capacitive loading and may introduce spurious pulses and
glitches. If trouble occurs, neat and orderly wiring will make it easier to locate the fault.
Measure voltages as accurately as possible. Be sure that the CRO is measuring
voltage correctly.
When CRO sketches are required, they should be drawn carefully on a scaled
paper. They should be drawn accurately enough so that you can read voltage and time from
3
them at any point. Generator waveforms should be displayed on the CRO with respect to
the graticule as closely as possible to those shown in manual.
Data obtained experimentally with the CRO are in volts. Then translate these
voltage readings into loqic-1 and logic-0, depending on the voltage ranges mentioned
before. In the discussion section these logic levels are analyzed. Careful study of the data
and of your textbook will enable you to answer the questions asked in discussion.

























4
INTRODUCTION
This part gives us brief information and general rules of laboratory work. It also
includes basic information of safety precautions, laboratory practice and laboratory report.

A-) LABORATORY RULES:
1. There are nine set in the circuit analysis laboratory room. If the student number is higher
than 18 then everybody has to choose a partner to perform the experiments together with.
Each pair will be given a group number. Nobody can change his partner unless
permission given by the instructor.
2. There should be no laud talking in the laboratory.
3. No smoking in the laboratory. If you must smoke ask for permission from your
laboratory instructor to go out into the hall.
4. No visitors are permitted in laboratory.
5. Bring your laboratory book each session.
6. Exactly, read the laboratory sheet and know procedure.
7. If an instrument in your set gets out of work, please inform the assistant or instructor.
8. No transfer of any equipment between the tables by the students.
9. During the experiments, some important subject will be given to you by your assistant or
instructor. If any point is not understood after you starting the experiment please ask your
assistant and instructor clearly.
10. Dont supply the high voltage to the circuit.
11. Before leaving the laboratory please arrange everything in your set to the first position.

B-) SAFETY PRECAUTIONS
1. Performing of an experiment requires a careful reading of laboratory manual, a clear
understanding of each step involved in the required procedure before its actual
performance and often a written, planned program (notes on references, rough outline of
proposed procedure, circuit to be investigated, preliminary calculations). Science
organization is a guiding principle to be followed throughout the preparation,
performance and reporting of an experiment.
2. Always disconnect the power supply before connecting or charging to your circuit.
3. Be sure that the measuring instruments such as voltmeter, ammeter, etc. are connected in
correct places with sufficient ranges on the circuit. i.e, please pay attention that the
ammeter is not used in the voltmeter position and vice versa.
5
4. If the power supply is active on the circuit, an ohmmeter is never connected to this
circuit.
5. After the planning good experimental organization entails the neat assembly of the
circuits so that they may be easily visualized and checked, and the neat entering of data
with descriptive headings and complete information regarding meters and apparatus
used.
6. Make a rough plot of the data in the laboratory as soon as they have been taken,
whenever possible. If there are points out of line, they can be rechecked while the
apparatus is still set up.
7. The laboratory notebook is the record of what you did in the laboratory, together with
the result, calculations, and conclusion which may be drawn from your experiments. The
recording of data on separate pages of paper and copying it into the notebook is not
permitted.
8. If you must correct an entry in your notebook, draw a line through the incorrect entry,
and write a brief explanation of the correction.
9. The lab report must be turned in due the next lab period (usually the following week).
Late lab reports will not be accepted.
10. Before you leave the laboratory, you must have your instructor or assistant sign his initials in
your notebook. This says he is satisfied that you have cleaned up properly and that the data is
satisfactorily recorded in your notebook. No lab report will be accepted without this signature.
11. Students are expected to do their own lab work and write their own lab reports.
12. Ratings of the components must be properly selected.

C-) LABORATORY REPORT
1. All laboratory reports should be written to an A4 paper.
2. Each report should give sufficient information about the experiment.
3. All pages should be numbered. The first page should contain course number and name,
all partners name, group number and also name of the experiment.
4. All reports must be written in pencil, ball-point pen, typewriter but only in the headings
colored pencil or ball-points are allowed.
5. Below is a brief outline of how your report should be kept:
At the top of second page:

6
- Title of the experiment and the data,
- A short statement of the object of the experiment,
- The necessary theoretical work or calculations about the preliminary work,
- For step "b" and "c", you should read the experiment at home and complete these
steps before coming to lab,
- Procedure, observation, and data. If the data is to be recorded in a chart, you may
prepare the chart before coming to lab.
- Calculations. Sometimes these must be done during the lab period; at other times
you will be permitted to complete them at home. It is suggested that you do the
rough calculations on a piece of scratch paper before making any entries in your
notebook.
- Discussion (or results). Conclusion which may be drawn from the experiment,
possible sources of errors (when applicable), and answers to the questions asked
in the discussion part.


















7
EP 427
DIGITAL ELECTRONIC
EXPERIMENT-1

BASIC LOGIC GATES

1-) PURPOSE :
To study the operation principles of basic digital logic gates AND, OR,
INVERTER, NAND, NOR and the representation of their functions by truth tables, logic
diagrams and Boolean algebra.

2-) THEORY :
In the Integrated Circuits (IC) inputs and outputs occur as voltage levels. These
voltage levels may be measured by some instruments and depending on the predefined
voltage ranges they are accepted as logic-1 or logic-0. The two digits in the binary system,
1 and 0, are called bits, which is contraction of binary digit. During our experiments, any
measured voltage between 2.5 and 5.0 V will be considered as logic-1 and the voltage
between 0.5 and 0.5 V will be accepted as logic-0. Due to the type of the ICs used, these
ranges may vary considering the supply voltage connected. Despite the difference in
voltage levels, a basic operation will be the same. As shown in Figure 1.1, each voltage
range has an acceptable deviation from each other by a transition region.








Figure 1.1 : Example of binary signals.
Electronic digital circuits are also called logic circuits. Logic gates are the basic
building blocks for forming digital electronic circuitry. Logic circuits that perform the
5.0
3.75
2.5
Volt
0.5
0
-0.5
Logic-1
Logic-0
Transition Region
Tolerance allowed
for logic-1
Tolerance allowed
for logic-0
8
logic operations of AND, OR, NOT (Inverter), NAND and NOR are shown with their
graphics symbols, algebraic functions and truth tables in Table 1.1. Digital circuits,
switching circuits, logic circuits and logic gates are used in the same means.

Table 1.1 : Truth table, algebraic function and graphic symbol of basic 2-input logic
gates.
Name Graphic Symbol Algebraic Function Truth Table
AND

F=x.y
x y F
0 0 0
0 1 0
1 0 0
1 1 1
OR

F=x+y
x y F
0 0 0
0 1 1
1 0 1
1 1 1
NOT

F=x
x F
0 1
1 0
NAND

F=(x.y)
x y F
0 0 1
0 1 1
1 0 1
1 1 0
NOR

F=(x+y)
x y F
0 0 1
0 1 0
1 0 0
1 1 0



x
y
F
F
x
y
F x
F
x
y
F
x
y
9
The operation principles of basic five logic gates can be explained as follows:

2.1-) The AND Gate : The AND gate is one of the basic gates from which all functions
are constructed. It is a multi-input circuit that may have two or more than two inputs in
which the output is a logic-1 only if all inputs are logic-1. The output produces a logic-0
signal if any input is logic-0. The truth table, algebraic function (Boolean equation) and
graphic symbol of 2-input AND Gate are shown in Table 1.1.

2.2-) The OR Gate: The OR gate is another of the basic gates from which all logic
functions are constructed. It is also a multi-input circuit that may have two or more than
two inputs in which the output is a logic-1 when any of the inputs is a logic-1. Its output
becomes logic-0 if all input signals are logic-0. The truth table, algebraic function
(Boolean equation) and graphic symbol of 2-input OR Gate are shown in Table 1.1.

2.3-) The INVERTER (NOT) Gate : The inverter (NOT circuit) performs the operation
called inversion or complementation. The inverter changes one logic level to the opposite
level. In terms of bits, the output is logic-0 when input is logic-1, and the output is logic-1
when the input is logic-0. The truth table, algebraic function (Boolean equation) and
graphic symbol of an INVERTER (NOT) Gate are shown in Table 1.1.

2.4-) The NAND Gate : The NAND gate is a popular logic element because it can be used
as a universal gate; that is, NAND gates can be used in combination to perform the AND,
OR and inverter operations. The NAND gate is simply AND followed by INVERTER
gate. Therefore, NAND gate produces a logic-0 output only all inputs are logic-1. When
any of the inputs is logic-0, the output will be logic-1. The truth table, algebraic function
(Boolean equation) and graphic symbol of 2-input NAND Gate are shown in Table 1.1.

2.5-) The NOR Gate : The NOR gate, like the NAND gate, is a useful logic element
because it can also be used as a universal gate, that is, NOR gates can be used in
combination to perform the AND, OR and inverter operations. Then it is simply OR
followed by INVERTER gate. The truth table, algebraic function (Boolean equation) and
graphic symbol of 2-input NOR Gate are shown in Table 1.1.
The NAND and NOR functions are the complements of AND and OR functions,
respectively. The NAND and NOR gates are extensively used as standard logic gates.

10
2.6-) VOLTAGE TABLE : Representation for the measured voltages at the indicated
points on a logic circuit for every possible combination of the inputs.

2.7-) TRUTH TABLE : Representation of the output logic levels of a logic circuit for
every possible combination of the inputs. This is the best done by means of a systematic
tabulation. The truth tables of some logic gates are given in Table 1.1.

2.8-) IC PIN CONNECTIONS : Each of the ICs used are in a 14-pin dual-in-line case.
The base pins progress in a counterclockwise direction as seen from the side away from the
pins, as shown in Figure 1.2.





Figure 1.2 : IC Pin location, 14-pin dual-in-line case.
The basic logic gates are available as integrated circuits (ICs). The logic behaviour of
various basic IC gates are given as:
7404 Hex inverters
7408 Quadruple 2-input AND gates
7432 Quadruple 2-input OR gates
7400 Quadruple 2-input NAND gates
7402 Quadruple 2-input NOR gates

the pin assignments of these gates are shown in Figure 1.3. In here, the terms Hex and
Quadruple means that there are six and four gates within the package, respectively.

PRELI MI NARY PRECAUTI ONS : It is extremely important that the exact required
voltage be applied to the IC. The power supply should be the last connections made.
Before connections to the power supply are made, its voltage should be checked with
power supplys voltmeter and a calibrated CRO. All measurements in this experiment are
made with a calibrated CRO. Before making any measurement, calibrate the CRO. After
the CRO is calibrated, use it to check the power supply voltage. If a disagreement occurs
between the power supply voltmeter reading and the CRO measurement, call the
laboratory assistant or your instructor.
1 2 3 4 5 6 7
14 13 12 11 10 9 8
| | | | | | |
| | | | | | |
Index notch
Pin 1 identification
Top view
(away from pins)
11



















Figure 1.3 : Basic digital gates in IC packages with identification number and
pin assignments.

3-) EXPERIMENTAL PROCEDURE :
For each part of the experiment apply the indicated voltage which is given below
and make voltage measurements at the points indicated to complete the voltage tables. Use
the Cathode Ray Oscilloscope (CRO) to measure the voltage. Use CRO in a sensitivity of
1 V/div and make measurements to within 0.1 Volt.
12
I mportant Note: Apply V
cc
= + 5.0 Volt is to the pin-14 and 0.0 (ground) apply to the pin-
7 for all ICs.

3.1-) INTGRATED CIRCUITS (ICs) :
Note : The ICs type 7408, 7432, 7400 and 7402 have four 2-input AND, OR, AND and
NOR gates within their packages, respectively. The IC type 7404 has six one-input
INVERT gates within its package. You must use only one of these gates in this
experiment. For example, the gate 7408 AND gate whose input pins are pins 1 and 2 and
whose output pin is pin 3. If it is defective, you must select one of the other gates in the
same package.
1-) Select one of the gate from IC,
2-) Set up the following circuit,
3-) Control the selected basic logic gates,
4-) If it is defective, you must select one of the other gates in the same package,
5-) Complete truth table of basic logic gates,
6-) Repeat above steps for all basic logic gates.

3.1.a-) OR Gate (7432) :







Figure 1.4 : IC OR gate.

Table 1.2 : IC OR gate.
Pin 1 Pin 2 Pin 3
0 0
0 +5
+5 0
+5 +5
5.0 V
+ -
Pin-1
Pin-2
Pin-3
0 +5
7432
13
3.2.b-) AND Gate (7408) :








Figure 1.5 : IC AND gate.

Table 1.3 : IC AND gate.
Pin 1 Pin 2 Pin 3
0 0
0 +5
+5 0
+5 +5

3.3.c-) INVERTER (NOT) Gate (7404) :








Figure 1.6 : IC INVERTER (NOT) gate.

Table 1.4 : IC NOT gate.
Pin 1 Pin 2
0
+5

5.0 V
+ -
Pin-1 Pin-2
0 +5
7404
Pin-2
5.0 V
+ -
Pin-1
Pin-3
0 +5
7408
14
3.4.d-) NOR Gate (7402) :




Figure 1.7 : IC NOR gate.

Table 1.5 : IC NOR gate.
Pin 1 Pin 2 Pin 3
0 0
0 +5
+5 0
+5 +5


3-5.e-) NAND Gate (7400) :



Figure 1.8 : IC NAND gate.

Table 1.6 : IC NAND gate.
Pin 1 Pin 2 Pin 3
0 0
0 +5
+5 0
+5 +5

5.0 V
+ -
Pin-1
Pin-2
Pin-3
0 +5
7402
5.0 V
+ -
Pin-1
Pin-3
0 +5
7400
Pin-2
15
4-) DISCUSSIONS :
4.1-) Convert all voltage tables completed in the experimental parts into logic tables.
4.2-) Compare your experimental results with theoretical results.
4.3-) Explain the basic logic gates, complete three and four input logic gates truth table.
4.4-) Realize NAND and NOR functions using only AND, OR and INVERT gates.
4.5-) What is the purpose of a truth table and algebraic function?
4.6-) What is the purpose of an inverter in a digital circuit?
4.7-) If we were to build a truth table for a 16-input AND gate, how many different
combinations of inputs would we have?
4.8-) Make a truth table for the diagram in Figure 1.9.
4.9-) Considering the given truth table, realize the function using with minimum number of
gates.






Figure 1.9 : A combinational basic logic circuit.
A B C D E F
0 0
0 1
1 0
1 1

4.10-) Sensors are used to monitor the pressure and the temperature of a chemical solution
stored in a vat. The circuitry for each sensor produces a HIGH voltage when a
specific maximum value is exceeded. An alarm requiring a LOW voltage input
must be activated when either the pressure or the temperature is excessive.
i-) Tabulate the truth table of the system.
ii-) Design a circuit for this application.
4.11-) Design a burglar alarm using basic logic gates.
A
B
C
D
E
F
16
4.12-) Give a brief explanation about Negative-OR and Negative-AND gates.
4.13-) How is a logic probe and logic pulser used to troubleshoot digital ICs?
4.14-) A particular logic family defines a LOW signal to be in the range 0.0-0.8 V and a
HIGH signal to be in the range 2.0-3.3 V. Under a positive-logic convention,
indicate the logic value associated with each of the following signal levels :
(a) 0.0 V (b) 3.0 V (c) 0.8 V (d) 1.9 V
(e) 2.0 V (f) 5.0 V (g) 0.7 V (h) 3.0 V
4.15-) Repeat 4.14 using a negative-logic convention.


















17
EP 427
DIGITAL ELECTRONIC
EXPERIMENT-2

BOOLEAN ALGEBRA AND SIMPLIFICATION OF LOGIC EQUATIONS

1-) PURPOSE :
To study the methods of representing and simplifying logic equations by Boolean
Algebra laws and rules.

2-) THEORY :
Generally, you will find that the simple gate functions AND, OR, NAND, NOR
and INVERTER are not enough by themselves to implement the complex requirements of
digital systems. The basic gates will be used as the building blocks for the more complex
logic that is implemented by using combinations of gates called combinational logic.
Combinational logic employs the use of two or more of the basic logic gates to form a
more useful, complex function. The systematic reduction of logic circuits is performed
using Boolean algebra.
Boolean algebra is the mathematics of digital systems. A basic knowledge of
Boolean algebra is indispensable to the study and analysis of logic circuits. In the previous
experiment (Ex.1), Boolean operations and expressions in terms of their relationship to
NOT, AND, OR, NAND, and NOR gates were introduced. This experiment reviews the
material and provides additional definitions and information. Additionally, it demonstrates
the relationship between a Boolean function and the corresponding logic diagram. The
complexity of the digital logic gates that implement a Boolean function is directly related
to the complexity of the algebraic expression from which the function is implemented. The
exact implementation of many digital logic circuits will result in a circuit those functions
as expected. Nevertheless, many such circuits can be reduced to a simpler form by the
application of Boolean algebra and by Karnaugh mapping. The basic Boolean reducing
equations are given below.


+ 5 V
A.1=A
A.A=A
+ 5 V
A+1=A
0 V
A.0=0
A.A=0
A+0=A
0 V
A+A=A
A+A=1
(A)=A
18
Many times a complex logic circuit can reduce its simplest form or change its form
to a more convenient one to implement the expression most efficiently by using these rules
as a base. In simplification procedures, a variable and its complement are treated as
separate variables and logic equations can be expanded and combined as in ordinary
algebra using the priorities of ordinary algebra. All Boolean expressions, regardless of their
form, can be converted into either of two standard forms: the sum-of-products for (SOP) or
the products-of-sum form (POS). Reductions can be made using the Boolean algebra
simplification techniques or Karnaugh maps which provide a graphical/visual means of
logic simplifications.

3-) EXPERIMENTAL PROCEDURES :
3.1-) To obtain the correct wave shapes it is necessary to calibrate your CRO using a
Square Wave Generator (SWG).
a-) Connect the output of SWG to the input of CRO.
b-) Adjust the output of SWG to +5.0 Volt at 1 kHz.
c-) View the shape of square wave and adjust the CRO horizontal sweep rate so that
each cycle occupies two horizontal division as shown in Figure 2.1.


Figure 2.1 : Cathode Ray Oscilloscope (CRO) connections to Square Wave
Generator (SWG) and its output waveform.

3.2-) There are two procedures in this section. In one; a voltage table must be made and in
the other, waveforms are viewed on the CRO and sketched on the graph paper.
a-) When a table must be made, use the CRO to make voltage measurements at the
points indicated to complete the table.
b-) When a signal input is applied from the SWG, view the waveforms on the CRO
and sketch the waveforms at the indicated points.
+ -
Function Generator
+ 5.0 Volt SWQ 1 kHz
CRO
19
PRECAUTI ONS! : For all ICs in this experiment V
cc
=+5.0 Volt to pin-14, pin-7 to
ground (0.0 Volt).
3.3.1-) Construct Figure 2.2 and make voltage tables and sketch the waveforms of
variables x and y at the points indicated on Figure 2.2.







Figure 2.2 : A combinational logic circuit with NAND and inverter gates.
Table 2.2 :
Pin 1 Pin 2 (A)
x
y




















+ -
5 Volt
Pin-1
Pin-3

0
+5
Pin-2 x
y
A
y
x
Pin 1 at
+ 5.0 V


Pin 1 at
+ 5.0 V


y
x
Pin 1 at
0 V


Pin 1 at
0 V


20
3.3.2-) Construct Figure 2.3 and complete its voltage tables at the indicated points and
sketch the waveforms of variable f.






Figure 2.3 :A basic logic circuit.
Table 2.3 :
A B
x y
f



















4-) DISCUSSIONS :
4.1-) Construct voltage and logic tables for all parts of the experimental procedure.
Comment about the implemented simplifications and any contradictions between
experimental observations and theoretical expectations.
+ -
5 Volt
x

0
+5
B
f
y
A
y
x
f
21
4.2-) Complete three and four input logic gates timing diagrams.
4.3-) Simplify the following functions using Boolean simplification techniques;
a-) F=A(A+B)
b-) F=AB+AB+AB
c-) F=(A+C)(A+D)(B+C)(B+D)
d-) F=A(A+B)+ A(A+B)
e-) F=A+ABC+AB+ABC

4.4-) Design of a logical device that receives a four-bit binary number A
4
A
3
A
2
A
1
, and
indicate the prime numbers.
4.5-) When the input waveforms (A,B) are supplied to a logic circuit, the output waveform
(F) is obtained as shown in figure 2.4. Implement the logic circuit inside the box
using minimum number of gates.

A


B


F



Figure 2.4 : Input and output waveforms of a logic circuit.



















A
B
F Logic Circuit
22
EP 427
DIGITAL ELECTRONIC
EXPERIMENT-3

DeMORGANS THEOREM

1-) PURPOSE :
To simplify and modify Boolen logic equations by means of DeMorgans theorem
to arrive at simplified equivalent equations.

2-) THEORY :
Frequently, the direct representation of a logic circuit results in a form that is not
the most desirable immediately. For example, the solution may yield OR/NOR, where as it
is desired to use AND/NAND. Sometimes the system solution results in a combination of
OR/NOR and AND/NAND when a single form of logic is desired.
To simplify circuits containing NANDs and NORs, we need to use a theorem
developed by the mathematicians Augustus De Morgan. DeMorgans theorem permits
conversion of logic for OR/NOR to AND/NAND and AND/NAND to OR/NOR.
DeMorgans is given by the equations.
(A+B)=AB
(AB)=A+B
Also, for three or more variables,
(A+B+C)=ABC
(ABC)=A+B+C
The procedure in applying DeMorgans theorem is the following:
1-) Replace AND with OR or OR with AND.
2-) Invert the variables.
3-) Invert the final result.
4-) If possible, simplify by applying double inversion.
DeMorgans theorem is applicable to any number of variables and to the whole or any part
of a Boolean equation.

3-) EXPERIMENTAL PROCEDURES :
For each part of the experiment, wire the circuits shown and use the Cathode-Ray-
Oscilloscope (CRO) to make voltage measurements at the points indicated to make the
associated table. As you perform the experiment, for each point on the logic diagram
23
express the Boolean equation in terms of the input variables and write it on the diagram.
For all the ICs in this experiment; apply V
cc
=5.0 Volt to pin-14 and ground 0 volt to pin-7.

3.1-) Set up the following logic circuit (Figure 3.1) and complete its voltage tables at the
indicated points and then verify the DeMorgans theorem.





Figure 3.1 : A combinational logic circuit to proof DeMorgans Theorem.
Table 3.1.
A B U V W X Y
0 0
0 5
5 0
5 5
3.2-) Set up the following logic circuit (Figure 3.2) and complete its voltage tables at the
indicated points and then verify the DeMorgans theorem.





Figure 3.2 : Another combinational logic circuit to proof DeMorgans theorem.

+ -
5 Volt
W
0
+5
B
U
V
A
X
Y
+ -
5 Volt
W
0
+5
B
U
V
A
X
Y
24
Table 3.2.
A B U V W X Y
0 0
0 5
5 0
5 5

4-) DISCUSSIONS :
4.1-) For part 3.1, what are the Boolean algebra equations of U, V, W, X and Y in terms of
the variables A and B? Express the DeMorgans relationship between A, B, X and Y.
Simplify the output using DeMorgans theorem and then draw them with a minimum
number of basic logic gates.
4.2-) Repeat above question for part 3.2.
4.3-) Apply DeMorgans theorems to the expressions ABC, A+B+C, ABCD,
A+B+C+D, and (ABCD).
4.4-) Why is DeMorgans theorem important in the simplification of Boolean equations?
4.5-) Use DeMorgans theorem to prove that a NOR gate with inverted inputs is equivalent
to an AND gate.
4.6-) Simplify the following Boolean equations applying DeMorgans theorem and
Boolean algebra simplification techniques.
a-) X=[(AB)+CD] + (ACD)
b-) Y=(ABC+D) + (AB+BC)
4.7-) According to DeMorgans theorem, the complement of X + YZ is XY + Z. Yet
both functions are 1 for XYZ = 110. How can both a function and its complement be
1 for the same input combination? What is wrong here?






25
EP 427
DIGITAL ELECTRONIC
EXPERIMENT-4

EXCLUSIVE-OR AND EXCLUSIVE-NOR GATES

1-) PURPOSE :
To describe the operation principles and methods of generating the Exclusive-OR
and Exclusive-NOR functions.

2-) THEORY :
The exclusive-OR and exclusive-NOR gates are actually formed by a combination
of other basic logic gates already discussed in experiment 1. However, because of their
fundamental importance in many applications, these gates are treated as basic logic
elements with their own unique symbols.

2.1-) The Exclusive-OR Gate :
The exclusive-OR, abbreviated XOR or EOR. The exclusive-OR gate has a graphic
symbol similar to that of the OR gate, except for the additional curved line on the input
side. The exclusive-OR is an odd function, i.e.; it is equal to 1 if the input variables have an
odd number of 1s. This means that when the bits are alike, the EOR output is a 0; and
when the bits are not alike, the EOR output is a 1 for a two bits inputs exclusive-OR gate.
If the inputs are represented by A and B, the equation of EOR is;
X=AB+AB=(AB+AB)=AB (4.1)
Although there are many ways of implementing the EOR, they can be shown to
reduce to one of the forms of equation 4.1. The graphic symbol, algebraic function and
truth table is shown in Figure 4.1. The XOR gate has only two inputs, unlike the other
gates we have discussed in experiment 1, it never has more than two inputs.
Graphic Symbol Algebraic Function Truth Table

A B X
0 0 0
0 1 1
1 0 1
1 1 0
Figure 4.1 : The exclusive-OR gate.
X=AB+AB
=AB
A
B
X
26
2.2-) The exclusive-NOR Gate :
Standard symbol for the exclusive-NOR (XNOR) gate, algebraic function and its
truth table are shown in Figure 4.2. Like the XOR gate, the XNOR has only two inputs.
The bubble on the output of the XNOR symbol indicates that is output is opposite that of
the XOR gate. When the two input logic levels are opposite, the output of the exclusive-
NOR gate is logic-0. If both of the input levels are logic-1 or logic-0, the output of the
exclusive-NOR gate becomes logic-1.

Graphic Symbol Algebraic Function Truth Table

A B X
0 0 1
0 1 0
1 0 0
1 1 1

Figure 4.2 : The exclusive-NOR gate.

3-) EXPERIMENTAL PROCEDURE :
For each part of the experiment, set-up the following circuit which shown in below
figures. Make voltage measurements at the points indicated to construct the necessary
tables.
3.1-) Set up the following logic circuit.

Figure 4.3 : Exclusive-OR generator.


+ -
5 Volt
W
0
+5
B
U
V
A
X
Y
X=AB+AB
=AB
A
B
X
27
Table 4.1.
A B U V W X Y
0 0
0 5
5 0
5 5
3.2-) Set up the following logic circuit.




Figure 4.4 : The exclusive-OR gate
Table 4.2.
A B X
0 0
0 5
5 0
5 5
3.3-) Set up the following logic circuit.





Figure 4.5 : The exclusive-NOR gate


+ -
5 Volt
0
+5
B
X
A

+ -
5 Volt
0
+5
B
X
A
28
Table 4.3.
A B X
0 0
0 5
5 0
5 5

4-) DISCUSSIONS :
4.1-) Show that the circuits in part 3.1 and 3.2 are equivalent to each other. (Hint : Use
DeMorgans theorem for the outputs of U and X, and draw a Karnaugh map)
4.2-) Show that (ABC)=ABC=ABC.
4.3-) How does an exclusive-OR gate differ from an OR gate in its logical operation?
4.4-) Design a logic circuit that to detect when two bits are different from each other.
4.5-) Describe in words the operation of an exclusive-OR gate; and exclusive-NOR gate.
4.6-) Design an exclusive-OR gate and exclusive-NOR gate constructed from all NOR and
NAND gates.












29
EP 427
DIGITAL ELECTRONIC
EXPERIMENT-5

HALF-ADDER AND HALF-SUBTRACTOR

1-) PURPOSE :
To study the half-adder and half-subtractor.

2-) THEORY :
2.1-) Half-Adder : A combination circuit that performs the addition of two bits is called
half-adder. The half-adder circuit needs two binary inputs and two binary outputs. The
input variables are designated as the augends and addend bits; the output variables produce
the sum and carry. The truth table is shown for a half-adder in Table 5.1.

Table 5.1.
X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

The simplified Boolean function for the two outputs can be obtained directly from
the truth table. The simplified sum of product expressions are;
S=XY+XY (5.1)
C=XY (5.2)
2.2-) Half-Subtractor : A half-subtractor is also a combinational circuit that subtracts two
bits and produces their difference. The half-subtractor needs two outputs. One output
generates the difference (D), and second output, designated as B for borrow. The truth
table for the input-output relationships of a half-subtractor is shown in Table 5.2.

Table 5.2.
X Y B D
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
30
The Boolean functions for the two outputs of the half-subtractor are derived
directly from the truth table;
D=XY+XY (5.3)
B=XY (5.4)

3-) EXPERIMENTAL PROCEDURE :
For each part of the experiment, set up the circuits shown. Make voltage
measurements at the points indicated to construct the necessary tables. Since the half-adder
and half-subtractor require the exclusive-OR as part of their logic.

3.1-) Half-Adder





Figure 5.1 : Half-adder.
Table 5.3.
X Y C S
0 0
0 1
1 0
1 1

3.2-) Half-Subtractor









Figure 5.2 : Half-subtractor.


+ -
5 Volt
0
+5
C
X
S
Y

+ -
5 Volt
0
+5
B
X
D
Y
31
Table 5.4.
X Y B D
0 0
0 1
1 0
1 1

4-) DISCUSSIONS :
4.1-) Write out a truth table for a half-adder and compare with the result of Table 5.3.
Discuss.
4.2-) Write out a truth table for a half-subtractor and compare with the result of Table 5.4.
Discuss.
4.3-) Implement the four Boolean functions listed using three half-adder circuits.
D = A B C
E = ABC + ABC
F = ABC + (A + B) C
G = ABC
























32
EP 427
DIGITAL ELECTRONIC
EXPERIMENT-6

BINARY COMPARATORS

1-) PURPOSE :
To study the binary comparators.

2-) THEORY :
The comparison of two numbers is an operation that determines if one number is
greater than, less than, or equal to the other number. A magnitude comparator is a
combinational circuit that compares the magnitude of two binary numbers, A and B, and
determines their relative magnitudes. The outcome of the comparison is specified by three
binary variables that indicate whether A>B, A=B, or A<B. The circuit for comparing two
n-bit numbers has 2
2n
entries in the truth table and becomes too cumbersome when n is
greater than 2.

3-) EXPERIMENTAL PROCEDURE :
3.1-) Set-up the following circuit.











Figure 6.1 : One-bit binary comparator.
Table 6.1
A B F
1
F
2
F
3
0 0
0 1
1 0
1 1


+ -
5 Volt
0
+5
F
2
A
0
B
0
F
3
F
1
33
3.2-) Set-up the following Figure 6.2








Figure 6.2 : A binary comparator.
4-) DISCUSSIONS :
4.1-) Complete the truth tables of one-bit binary comparators and then obtain simplified
Boolean expression of output functions.
4.2-) Determine the type of the comparator of circuit in Figure 6.2 and explain its function.
4.3-) Design a system-called a parallel binary comparator that compares the 4-bit string A
(A
3
A
2
A
1
A
0
) to the 4-bit binary string B (B
3
B
2
B
1
B
0
). If the strings are exactly equal,
provide a high-level output to drive a warning buzzer.
4.4-) Use two 4-bit binary comparators (7485) to compare the magnitudes of two 8-bit
numbers. Show the comparators with proper interconnections.
4.5-) The waveforms in below figure are applied to the 2-bit comparator as shown. Sketch
the output waveforms.
A
0

A
1


B
0

B
1

F
1

F
2

F
3

Figure 6.3 : Block-diagram of 2-bit binary comparator.


A
0
A
1
F
1
(A<B)
2-Bit Logic
Comparator
B
0
B
1
F
2
(A=B)
F
3
(A>B)

+ -
5 Volt
0
+5
B
1 A
0
B
0
A
1
F

34
EP 427
DIGITAL ELECTRONIC
EXPERIMENT-7

PARITY GENERATORS AND CHECKERS

1-) PURPOSE :
To explain the concept of parity and study the operation principles of basic parity
generators and checker.

2-) THEORY :
Errors can occur as digital codes are being transferred from one point to another (i.e
from one digital device (computer) to another (printer) within a digital system or while
codes are being transmitted from one system to another. The errors take the form of
undesired changes in the bits that make up the coded information; that is, a 1 can change to
a 0, or a 0 to a 1, because of component malfunctions, electrical noise or other
disturbances. In most digital systems, the probability that even a single bit error will occur
is very small, and the likelihood that more than one will occur is even smaller.
Nevertheless, when an error occurs undetected, it can cause serious problems in a digital
system.
Exclusive-OR and equivalence functions are very useful in systems requiring error-
detection and error-correction codes. A parity bit is a scheme for detecting errors during
transmission of binary information. A parity bit is an extra bit included with a binary
message to make the number of 1s either odd or even. The message, including the parity
bit, is transmitted and then checked at the receiving end for errors. An error is detected if
the checked parity does not correspond to the one transmitted. The circuit that generates
the parity bit in the transmitter is called a parity generator; the circuit that checks the parity
in the receiver is called a parity checker.
Parity systems are defined as either odd parity or even parity. The parity system
adds an extra bit to the digital information being transmitted. A 2-bit system will require a
third bit, an 3-bit system will require a forth bit, and so on. In an odd-parity system, the
parity bit that is added must make the sum of all n-bits odd. In an even-parity system, the
parity bit makes the sum of all bits even.
The parity generator is the circuit that creates the parity bit. On the receiving end, a
parity checker determines if the n-bits result is of the right parity. The type of system (odd
35
or even) must be agreed on before hand so that the parity checker knows what to look for
(this is called protocol). Also, the parity bit can be placed next to the MSB or LSB as long
as the device on the receiving end knows which bit is parity and which bits are data.
For example, during the transmission of BCD number 9 (1001) in an odd-parity
system, the parity generator puts a 1 on the parity-bit line to make the sum of all bits odd
(1+0+0+1+1=3). The parity checker at the receiving end checks to see that the transferred
all-bits are odd, it assumes that no error then BCD information is valid. Otherwise, an error
indicator indicates an error. The error indicator is actually a signal that initiates a
retransmission of the original signal or produces an error message on a computer display.
A block diagram of a parity generator and checker system is shown in Figure 7.1.







Figure 7.1 : A parity generator/checker system.
3-) EXPERIMENTAL PROCEDURE :
3.1-) Parity Generator : Set-up the following circuit.





Figure 7.2 : 3-bit parity generator


Parity
Generator

B
C
D

B
C
D

Parity
Checker



Transmitting Device
Receiving Device
Parity Bit
Error
Indicator

+ -
5 Volt
0
+5
Z
X
P
Y
36
Three-bit message
Parity bit
generated
X Y Z P
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
3.2-) Parity Checker : Set up the following circuit.




Figure 7.3 : A 3-bits parity checker.
Four-bits received
Parity error
generated
X Y Z P F
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

+ -
5 Volt
0
+5
P
X

Y

Z

F

37
4-) DISCUSSIONS :
4.1-) Determine the type of the system in part 3.1 and .2.
4.2-) Write the Boolean expression of P and F in the simplest form.
4.3-) Add a parity bit next to the LSB of the following hexadecimal codes to form even parity:
0011, 1000, 1101, 0111, 1010, 0001, 0000, 0100.
4.4-) Suppose that a computer and printer system uses 4-bit odd parity generator and checker,
a-) Tabulate the truth table of parity generator.
b-) Write and simplify the output function of parity generator using any simplification
technique which you learned.
c-) Implement the logic circuits of parity generator and checker in the simplest form.
d-) Discuss in which conditions parity checker gives error.

4.5-) Design a logic circuit that detects the errors occur when a binary information
transferring from a computer to a printer. Restrict that the long of binary information
are four bits.
4.6-) One popular 9-bit parity generator/checker is the 74280 TTL IC or 74HC280 CMOS
IC (see Figure 7.4). Using 74280s, design a complete parity generator/checking
system. It is to be used in an 8-bit, even parity computer configuration.

Function Table
Number of HIGH data
inputs (I - I )
Sum Output
E O
Even HIGH LOW
Odd LOW HIGH



4.7-) Which output of the 74280 parity generator is used as the parity bit in an odd system?
A
0

A
1

A
2

A
3

Figure 7.4 : Input waveforms and block diagram of parity generator.

8 9 10 11 12 13
1 2 4
5 6
E
E
E
o
I
0
I
1
I
2
I
3
I
4
I
5 I
6
I
7
I
8
74280 TTL IC
V
CC
= Pin-14
GND=Pin-7
A
0
A
1
Parity Generator
A
2
A
3
P
38
EP 427
DIGITAL ELECTRONIC
EXPERIMENT-8

FULL-ADDER AND FULL-SUBTRACTOR

1-) PURPOSE :
To study methods of generating circuits that perform the arithmetic operations of
full addition and full-subtraction.

2-) THEORY :
2.1-) Full-Adders : A full-adder is a combinational circuit that forms the arithmetic sum of
three input bits. It consists of three inputs and two outputs. Two of the input variables,
denoted by X and Y represent the two significant bits to be added. The third input, C
i
represents the carry from previous lower significant position. The outputs are designated
by symbols S for sum and C
o
for carry. The binary variable S gives the value of the least
significant bit of the sum. The binary variable C
o
gives the output carry. When all input
bits are 0s, the output is 0. The S output bits equal to 1 when only input is equal to 1 or
when all three inputs are equal to 1. The C
o
output has a carry of 1 if two or three inputs
are equal to 1. The input-output logical relationship of the full-adder circuit may be
expressed in two Boolean functions, one for each output variable. The truth table of the
full-adder is as follows :
X Y C
i
C
o
S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

We can simplify the representation of a full-adder by just drawing a box with the input and
output lines, as shown in Figure 8.1a. When drawing multibit adders, a block diagram is
used to represent the addition in each column, as shown in Figure 8.1b.


39








Figure 8.1 : Block diagrams of (a) full-adder; (b) 4-bit binary adder.

Medium-scale-integration (MSI) ICs are available with four full-adders in a single
package. Table 8.1 lists the most popular adder ICs. Each adder in table contains four full-
adders, and all are functionally equivalent; however, their pin layouts differ. They each
will add two 4-bit binary words plus one incoming carry. The binary sum appears on the
sum outputs (E
1
to E
4
) and the outgoing carry. Figure 8.2 shows the functional diagram and
the logic symbol for the 7483.
Table 8.1 : MSI Adder ICs
Device Family Description
7483 TTL 4-Bit binary full adder, fast carry
74LS83A TTL 4-Bit binary full adder, fast carry
74LS283 TTL 4-Bit binary full adder, fast carry
74HC283 CMOS 4-Bit binary full adder, fast carry
4008 CMOS 4-Bit binary full adder, fast carry


2.2-) Full-Subtractors : A full-subtractor is also a combinational circuit that performs a
subtraction between two bits, taking into account that a 1 may have been borrowed by a
lower significant stage. This circuit has three inputs and two outputs. Three inputs X, Y
and B
i
denote the minuend, D and B
o
represent the difference and output borrow,
respectively. The simplified Boolean functions for the two outputs of the full-subtractor are
derived from the maps.
The logic function for output D in the full-subtractor is exactly the same as S in the
full-adder. Moreover, the output B
o
resembles the function for C
o
in the full-adder, except
that the input variable X is complemented. Because of these similarities, it is possible to
convert a full-adder into a full-subtractor by merely complementing input X prior to its
application to the gates that from the carry output.

C
0 E
X Y C
i
FA
C
0
E
0
X
0
Y
0 C
i
FA
C
0
E
1
X
1 Y
1
C
i
FA
C
0 E
2
X
2
Y
2
C
i
FA
C
0
E
3
X
3
Y
3
C
i
FA
(a)
(b)
40

10 7 8 11 3 4
1 16
C
in
9 6
E
1
E
4
A
1
B
1
A
2
B
2
A
3
B
3
A
4
B
4
C
out
7483
15
13
E
2
E
3
2
14
V
cc
=Pin-5
GND=Pin-12
(b)
(a)



















Figure 8.2 : The 7483 4-bit full-adder :(a) functional diagram; (b) logic symbol.

X Y B
i
B
o
D
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1


C
0
E
1
X
4
Y
4
C
i
FA
4
C
0
E
3
X
3
Y
3
C
i
FA
3
C
0
E
2
X
2 Y
2
C
i
FA
2
C
0
E
4
X
1 Y
1
C
i
FA
1
C
in
Fast-look-
ahead carry
C
out
41
3-) EXPERIMENTAL PROCEDURE :
For each part, set up the circuit shown and make voltage measurements at the points
indicated to complete the table.
3.1-) Full-adder :





Figure 8.3 : A full-adder circuit constructed with two half-adders and one OR gate.
X Y C
i
C
o
S
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

3.2-) Full-Subtractor :

Figure 8.4 : A full-subtractor circuit constructed with two half-subtractors and one OR gate
and one INVERTER.

+ -
5 Volt
0
+5
X Y B
i B
o
D

+ -
5 Volt
0
+5
X Y C
i C
o
S
42
X Y B
i
B
o
D
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

4-) DISCUSSIONS :
4.1-) Compare the full-adder data of part 3.1 and full-subtractor data of part 3.2 with a truth
table for a full-adder and full-subtractor, respectively.
4.2-) Implement a full-adder circuit using only AND, OR and INVERTER gates.
4.3-) Does output in Figure 8.5 give the result of output carry of a full-adder circuit.
Explain its Boolean expression equivalence with Figure 8.1.










Figure 8.5

4.4-) The Boolean expression for the borrow out B
0
of a full-subtractor is given by
B
0
=XYB
i
+ XYB
i
+ XYB
i
+ XYB
i

by means of a Karnaugh map, this can be reduced to XY + YB
i
+ XB
i
. Using the
7400 and 7410 ICs, draw a logic diagram showing pin connections for this B
o

reduced.


+ -
5 Volt
0
+5
X Y C
i
C
o
43
4.5-) Show that carry four (C
4
) in a full-adder circuit (for 4-bits two-numbers A
3
A
2
A
1
A
0

and B
3
B
2
B
1
B
0
) can also be given in the form of
C
4
=G
3
+ F
3
G
2
+ F
3
F
2
G
1
+ F
3
F
2
F
1
G
0
+ F
3
F
2
F
1
F
0
C
0
4.5-) Show how two 74LS83A adders can be connected to form an 8-bit adder.
4.6-) Implement the 12-bit parallel adder with 74LS283 adders.
4.7-) In a full-adder circuit, the initial carry (C
in
) is always setted to zero (no carry).
Explain how could you implement initial carry with zero?
4.8-) The input waveforms in Figure 8.6 are applied to a 2-bit adder. Determine the
waveforms for the sum and the output carry in relation to the inputs by constructing a
timing diagram.
A
1

A
2

B
1

B
2

C
in

Figure 8.6.





















44
EP 427
DIGITAL ELECTRONIC
EXPERIMENT-9

CODE CONVERTERS

1-) PURPOSE :
To examine some methods or using combinational logic circuits to convert from
one code to another and generating their logic circuits.

2-) THEORY :
The availability of a large variety of codes for the same discrete elements of
information results in the use of different codes by different digital systems or by a
computer. It is sometimes necessary to use the output of one system as the input to
another. A conversion circuit must be inserted between the two systems if each uses
different codes for the same information. Thus, a code converter is a circuit that makes the
two systems compatible even though each uses a different binary code.
To convert from binary code A to binary code B, the input lines must supply the bit
combination of elements as specified by code A and the output lines must generate the
corresponding bit combination of code B. A combinational circuit performs this
transformation by means of logic gates. The design procedure of code converters will be
illustrated by means of a specific example of conversion from the BCD to the excess-3
code.
The most famous example of code conversion is between BCD and other base.
Because, the BCD is very important code for visual display communication; i.e., between a
computer and human beings. But BCD is very difficult to deal with arithmetically.
Algorithms, or procedures, have been developed for the conversion of BCD to binary by
computer programs (software) so that the computer will be able to perform all arithmetic
operations in binary. Calculators and other devices with numeric displays use another form
of code conversion involving BCD-to-seven-segment conversion. The term seven segment
come from the fact that these displays utilize seven different illuminating segments to
makeup each of the 10 possible numeric digits. The Gray code is another useful code used
in digital systems. It is used primarily for indicating the angular position of a shaft on
rotating machinery, such as automated lathes and drill presses. The determination of the
45
Gray code equivalents and the conversion between Gray code and binary code are done
very simple with exclusive-OR gates, as shown in Figure 9.1.







Figure 9.1 : (a) 4-bit binary-to-gray conversion logic; (b) 4-bit gray-to-binary conversion
logic.
The logic symbol in Figure 9.2 shows eight active-HIGH binary outputs. Y
1
to Y
5

are outputs for regulate BCD-to-binary conversion. Y
6
to Y
8
are used for a special BCD
code called nines complement and tens complement.







Figure 9.2 : Logic Symbol for the 74184 BCD-to-binary converter.

3-) EXPERIMENTAL PROCEDURE :
3.1-) Set up the following circuit and complete its truth table.




Binary
input
G
3
B
3
B
2
B
1
B
0
Gray code
output
G
2
G
1
G
0
(MSB)
(LSB)
(a)

Binary
input
G
3
B
3
B
2
B
1
B
0
Gray code
output
G
2
G
1
G
0
(MSB)
(LSB)
(b)
74184
Y
1 Y
2
Y
3
Y
4
Y
5 Y
6
Y
7
Y
8
1 2 3 4
5 6 7 9
G E D C
B A
10 11 12 13 14 15
V
cc
=Pin-16
GND=Pin-8
Inputs
Outputs
46










Figure 9.3 : A converter from BCD to 9s complement.
Table 9.1
A B C D F
3
F
2
F
1
F
0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1

3.2-) Set up the following Figure and complete its truth table.








Figure 9.4 : A code converter.

+ -
5 Volt
0
+5
D C
B

F
o
F
3
A
F
1
F
2

+ -
5 Volt
0
+5
D C
B

F
o
F
3
A
F
1
F
2
47
A B C D F
3
F
2
F
1
F
0
0 0 0 0
0 1 1 1
0 1 1 0
0 1 0 1
0 1 0 0
1 0 1 1
1 0 1 0
1 0 0 1
1 0 0 0
1 1 1 1

4-) DISCUSSIONS :
4.1-) Find and simplify the Boolean expression of output function in Figure 9.3 using
Boolean function simplification techniques.
4.2-) Find the Boolean expression of output functions in Figure 9.4 in their simplest form
and then discuss the type of the code converter.
4.3-) Implement 8-bit binary-to-Gray code and 5-bit Gray-to-binary code converter using
only exclusive-OR gates.
4.4-) Using 74184 ICs, implement a logic circuit to convert a 3-bit BCD number to binary.
4.5-) Design a combinational logic circuit that converts a decimal digit from 8421 code to
2214 code using a decoder and if necessary the other basic logic gates.
4.6-) Design of a combinational logical device that converts a decimal digit from 6,3,2,-1
BCD code to 8,4,2,1 BCD code.
4.7-) Design a combinational logic circuit that converts a decimal equivalent from 6461
code to 8421 code using minimum number of necessary logic gates.
4.8-) Design a combinational logic circuit either in block diagram or not that converts a
decimal digit from its decimal number system to binary number system when you
press the key of decimal digit.




48
EP 427
DIGITAL ELECTRONIC
EXPERIMENT-10

DECODERS AND ENCODERS
1-) PURPOSE :
To study the function of a decoder and encoder and design the internal circuitry for
encoding and decoding.

2-) THEORY :
2.1-) Decoder : Decoding is the process of converting some code (such as binary, BCD)
into a singular active output representing its numeric value. Therefore, a decoder is a
combinational circuit that converts binary information from n input lines to a maximum of
2
n
unique output lines. If the n-bit decoded information has unused or dont-care
combinations, the decoder output will have less than 2
n
outputs. In order to decode all
possible combinations of 2-bits, 4 decoding gates are required (2
2
=4). This type of decoder
is commonly called a 2-line-to-4-line decoder because there are two inputs and four
outputs. Therefore, the decoders are called as n-to-m line decoders where ms2
n
. To design
a decoder, it is useful first to make a truth table of all possible input/output combinations.
Before design is made, we must decide if we want an active-HIGH-level output or an
active-LOW-level output to indicate the value selected. For example, the active-HIGH truth
table shows that for an input 10 (2), output 2 is HIGH, and all other outputs are LOW. The
active-LOW truth table is just the opposite (output 2 is LOW, all other outputs are HIGH).
A list of the four binary codes and their corresponding decoding function is given in Table
10.1. In here, each output representing one of the minterms of the 2-input variables. The
two inverters provide the complement of the inputs, and each one of the four eight AND
gates generate one of the minterms as shown in Figure 10.1.
Table 10.1 : Decoding functions and truth table of a 2x4 decoder.
(a) Active-HIGH Outputs
Binary
Inputs
Decoding
Function
Outputs
A B D
0
D
1
D
2
D
3
0 0 AB 1 0 0 0
0 1 AB 0 1 0 0
1 0 AB 0 0 1 0
1 1 AB 0 0 0 1
49
(b) Active-LOW Outputs

Binary
Inputs
Decoding
Function
Outputs
A B D
0
D
1
D
2
D
3
0 0 AB 0 1 1 1
0 1 AB 1 0 1 1
1 0 AB 1 1 0 1
1 1 AB 1 1 1 0















Figure 10.1 : A 2-to-4 line docoder.
Integrated-circuit decoder chips provide basic decoding as well as several other
useful functions. Rather than designing decoders using combinational logic, it is much
more important to be able to use a data book to find the decoder that you need and to
determine the proper pin connections and operating procedure to perform a specific
decoding task. Table 10.2 lists some of the more popular TTL decoder ICs.

Table 10.2 : Decoder ICs.

Device Number Function
74138 1-of-8 octal decoder (3-to-8-line decoder)
7442 1-of-10 BCD decoder (4-to-10-line decoder)
74154 1-of-16 hex decoder (4-to-16-line decoder)
7447 BCD-to-seven-segment decoder

The 74138 is an octal decoder capable of decoding the eight possible octal codes
into eight separate active-LOW outputs, just like our combinational logic design. It also

+ -
5 Volt
0
+5
B

D
0
D
3
A
D
1
D
2
50
has three enable inputs for additional flexibility. The 7442 is a BCD-to-decimal decoder. It
has four pins for the BCD input bits (000 to 1001) and 10 active-LOW outputs for the
decoded decimal numbers. Decoders are used in many types of applications, i.e. in
computers for input/output selection.

2.1-) Encoder : Encoding is used to generate a coded output (such as BCD or binary) from
a singular active numeric input line. Therefore, an encoder is a combinational logic circuit
that essentially performs a reverse decoder function. An encoder accepts an active level on
one of its inputs representing a digit, such as a decimal or octal digit, and converts it to a
coded output, such as BCD. So, an encoder has 2
n
(or less) input lines and n output lines.
The design of encoders using combinational logic can be done by reviewing the truth table
(see Table 10.3) for the operation to determine the relationship each output has with the
inputs. For example, by studying Table 10.3 for a decimal-to-BCD encoder, we can see
that A output (2
0
) is HIGH for all odd decimal input numbers (1, 3, 5, 7, and 9). The B
output (2
1
) is HGH for decimal inputs 2, 3, 6, and 7. The C output (2
2
) is HIGH for
decimal inputs 4, 5, 6, and 7, and the D output (2
3
) is HIGH for decimal inputs 8 and 9.
The design of other encoders uses same procedures, but of course many of them are
available in ICs form. For example, the 74174 decimal-to BCD, and the 74184 octal-to-
binary. The 74147 is a priority encoder, which means that if more than one decimal
number is input, the highest numeric input has priority and will be encoded to the output.

Table 10.3 : Decimal-to-BCD Encoder Truth Table.

Decimal
Input
Inputs BCD Output
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D C B A
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 1 0 0 0 0 0 0 0 0 0 0 0 1
2 0 0 1 0 0 0 0 0 0 0 0 0 1 0
3 0 0 0 1 0 0 0 0 0 0 0 0 1 1
4 0 0 0 0 1 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 1 0 0 0 0 0 1 0 1
6 0 0 0 0 0 0 1 0 0 0 0 1 1 0
7 0 0 0 0 0 0 0 1 0 0 0 1 1 1
8 0 0 0 0 0 0 0 0 1 0 1 0 0 0
9 0 0 0 0 0 0 0 0 0 1 1 0 0 1

51

















Figure 10.2 : Basic decimal-to BCD encoder.

3-) EXPERIMENTAL PROCEDURE :

3.1-) Decoder : Set up the following circuit and sketch the output waveforms.










Figure 10.3 : The 74138 pin-connections.





8
9
D
C
7

4

A
6

5

3
2
1
B
74138
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
0
A
1
A
2
E
1

D
7
GND

E
2

E
3

D
0
D
1
D
2
D
3
D
4
D
5
D
6
V
cc
+5 V
+5 V
52
E
1


A
0

A
1

A
2

D
0

D
1

D
2

D
3

D
4

D
5

D
6

D
7

3.2-) Encoder : Set up the following circuit and sketch the output waveforms.









Figure 10.4 : The 74148 pin-connections.
74148
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 I
4

I
5

I
6

I
7

A
1

GND

EI

A
2

EO

GS

I
3

I
2

I
1

I
0

A
0

V
cc
+5 V
+5 V
53

EI

I
6


I
7


A
0


A
1


A
2


EO


GS


4-) DISCUSSIONS :
4.1-) Would you select a decoder/driver with active-HIGH or active-LOW outputs to drive
a common-cathode 7-segment LED display?
4.2-) BCD numbers are applied sequentially to the BCD-to-decimal decoder in below
Figure. Draw a timing diagram, showing each output in the proper relationship with
the others and with the inputs.


A
0

A
1

A
2

A
3



4.3-) How does an encoder differ from a decoder?
BCD/DEC
1
0
2
3
4
5
6
7
8
9
7442A
A
0
A
1
A
2
A
3
1
2
4
8
54
4.4-) If more than one input to a priority encoder is active, which input will be encoded?
4.5-) What are the five outputs of the 74148? Are they active-LOW or active-HIGH?
4.6-) Design a 4-line to 2-line priority encoder. Include an output E to indicate that at least
one input is a 1.
4.7-) Construct a 5 x 32 decoder with four 3 x 8 decoder / demultiplexers with an enable
input and a 2 x 4 decoder. Use block diagrams of all necessary circuits.
4.8-) Draw the logic diagram of a 2 x 4 decoder using only minimum number of NOR
gates.
4.9-) Implement a combinational logic circuit that converts a decimal equivalent from 6461
code to 8421 code using a decoder which is constructed with NAND gates and
minimum number of necessary basic logic gates.
4.10-) A combinational circuit is specified by the following three Boolean functions;
F
1
=xy + xz, F
2
= y + xz, F
3
= xy + yz. Implement the circuit with a decoder
which constructed with NAND gates and minimum number of external NAND gates.
4.11-) Design a combinational logic circuit that is converted a decimal digit from 8421
code to 2214 code using a decoder and if necessary the other basic logic gates.
4.12-) Design a logic circuit of a keyboard that converts decimal digits (0,1,2,,9) to its
binary number system when you press the keys on the keyboard.
4.13-) Consider the following functions
f
1
(x,y,z)=(0,1,2,4,5,7)
f
2
(x,y,z)=H(0,2,3,4,5,7)
Implement the both functions using a decoder and if necessary the other basic logic
gates.










55
EP 427
DIGITAL ELECTRONIC
EXPERIMENT-11

MULTIPLEXERS AND DEMULTIPLEXERS

1-) PURPOSE :
To explain the basic operation of a multiplexer and demultiplexer and their use as a
logic function generator.

2-) THEORY :
2.1-) Multiplexers (Data Selectors) : Multiplexing means transmitting a large number of
information units over a smaller number of channels or lines. A digital multiplexer (MUX)
is a device (combinational circuit) that selects binary information from one of many input
lines and directs it to a single output line. Because data can be selected from any one of the
input lines, a multiplexer is also known as a data selector. The multiplexer has two or more
digital input line signals connected to its input. The selection of a particular input line is
controlled by a set of selection lines. Normally, there are 2
n
input lines and n selection
lines. A logic symbol, logic diagram and data select input codes (function table) are shown
in Figure 11.1 for a 4-line to 1-line multiplexer. Each of the four input lines D
0
and D
3
is
applied to one input of an AND gate. The data select control inputs (S
1
and S
0
) are
responsible for determining which data input is selected to be transmitted to the data-
output line (Y). The S
1
and S
0
inputs will be a binary code that corresponds to the data-
input line that you want to select. If S
1
=0, S
0
=0, then D
0
is selected, if S
1
=0, S
0
=1, then D
1

is selected, and so on. We can therefore, derive a logic expression for the output in terms of
the data input and the select inputs. The total expression for the data output is
Y=D
0
S
1
S
0
+ D
1
S
1
S
0
+ D
2
S
1
S
0
+ D
3
S
1
S
0
The AND gates and inverters in the multiplexer resemble a decoder circuit and,
indeed, they decode the input selection lines. In general, a 2
n
-to-1 line multiplexer is
constructed from an n-to-2
n
decoder by adding to it 2
n
input lines, one to each AND gate.
The outputs of the AND gates are applied to a single OR gate to provide the 1-line output.
As in decoders, multiplexer ICs may have an enable input to control the operation of the
unit. When the enable input is in a given binary state, the outputs are disabled, and when it
is in the other state (the enable state), the circuit functions as a normal multiplexer. 2-, 4-,

56
8-, and 16-input multiplexers are readily available in MSI packages. Table 11.1 lists some
popular TTL and CMOS multiplexers.

Data Select Control
Inputs
Data Input
Selected
S
1
S
0
0 0 D
0
0 1 D
1
1 0 D
2
1 1 D
3




























Figure 11.1 : (a) Data selection, (b) Block diagram, and (c) logic diagram for a 4x1
multiplexer.

The 74157 consists of four separate 2-input multiplexers. Each of four multiplexers
shares a common data-select line and a common Enable, as shown in Figure 11.2. Because
there are only two inputs to be selected in each multiplexer, a single data-select input is
Y
S
0
D
0
D
3
S
1
D
1
D
2
D
0
D
1
D
2
D
3
S
1
S
0
Y
Data
Inputs
Data selection
lines
Output
4x1 MUX
(c)
(b)
(a)
57
sufficient. As you can see in the logic diagram, the data-select inputs is ANDed with the B
input of each 2-input multiplexer, and the component of data-select is ANDed with each A

Table 11.1 : TTL and CMOS Multiplexers
Function Device Logic Family
Quad 2-input
74157 TTL
74HC157 H-CMOS
4019 CMOS
Dual 8-input
74153 TTL
74HC153 H-CMOS
4539 CMOS
8-input
74151 TTL
74HC151 H-CMOS
4512 CMOS
16-input 74150 TTL

input. A LOW on the Enable input allows the selected input data pass through to the
output. A HIGH on the Enable input prevents data from going through to the output, that
is, it disables the multiplexers. The multiplexer is a very useful MSI function and has a
multitude of applications. It is used for connecting two or more sources to a single
destination among computer units, and it is useful for constructing a common bus system.
A useful application of the data selector/multiplexer is in the generation of combinational
logic functions in sum-of products form. When used in this way, the device can replace
discrete gates, can often greatly reduce the number of ICs, and can make design changes
much easier. Although multiplexers and decoders may be used in the implementation of
combinational circuits, it must be realized that decoders are mostly used for decoding
binary information and multiplexers are mostly used to form a selected path between
multiple sources and a single destination.

2.2-) Demultiplexers : Demultiplexing is the opposite procedure from multiplexing. It
takes data from one line and distributes them to a given number of output lines. For this
reason, we can think of a demultiplexer (DEMUX) is also known as a data distributor. As
you will learn, decoders can also be used as decoders/demultiplexers. Figure 11.3 shows a
1-line-to-4-line demultiplexer circuit. The data-input line goes to all of the AND gates. The
58
two data-select lines enable only one gate at a time, and the data appearing on the data-
input line will pass through the selected gate to the associated data-output line.
Decoder/demultiplexer circuits can be connected together to form a larger circuit. For
example two 3x8 decoders with enable inputs connected to form a 4x16 decoder.
Integrated-circuit demultiplexers come in several configurations of inputs/outputs. Two of
them are the 74139 dual 4-line demultiplexer.


Function Table
E S Y
1 X all 0's
0 0 select A
0 1 select B













Figure 11.2 : (a) Logic diagram and (b) function table for a quadruple 2-to-1 line
multiplexer.



Y
0
Y
1
A
0
A
3
A
1
A
2
B
0
B
3
B
1
B
2
Y
2
Y
3
S
(select)
E
(enable)
(b)
(a)
59
E A B D
0
D
1
D
2
D
3
1 X X 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0









Figure 11.3 : (a) Data selection, (b) Block diagram, and (c) logic diagram for a 1x4
demultiplexer.

3-) EXPERIMENTAL PROCEDURE :
3.1-) Multiplexer : Set up the following circuit and sketch the output waveform.
S
0


S
1


S
2


E


D
0


D
1


D
2


D
3


D
4


D
5


D
6


D
7


B

D
0
D
3
E

D
1
D
2
A
A B
E
D
0
D
1
D
2
D
3
Select
Input
1x4
DEMUX
(a)
(b)
(c)
MUX
7
11
10
9
4
3
2
1
15
14
13
12
D
6
D
7
D
5
D
4
D
3
D
2
D
1
D
0
S
2
S
1
S
0
E
5
6
Y
Y
74151A
60
3.2-) Demultiplexer : Set up the following circuit and sketch the output waveforms.
S


S

S

D

D

D

D


4-) DISCUSSIONS :
4.1-) Why is a multiplexer and demultiplexer sometimes called a data selector and data
distributor, respectively?
4.2-) Design the logic circuit of a 4x1 multiplexer using only NAND gates.
4.3-) Design the logic circuit of a 1x4 demultiplexer using only AND gates.
4.4-) Implement a full-subtractor logic circuit with multiplexers.
4.5-) The data-input and data-select waveforms in below figure are applied to the
multiplexer in Figure 11.1. Determine the output waveform in relation to the inputs.
D
o


D
1

D
2

D
3

S
0

S
1

Y

S
1
D
0
D
3
I

D
1
D
2
S
0
61
4.6-) Sketch the output waveforms at Y for the 7451 shown in below figure



















S
0





S
1





S
2





Y




4.7-) What is the function of the S
0
, S
1
, and S
2
pins on the 7451 multiplexer?
4.8-) Use a multiplexer to implement the function
X=ABCD + ABCD + ABCD + ABC + ABC
4.9-) Implement the logic function Y= E(1, 2,5,6,7,8, 10 ,12,13,15)by using a 74151A 8-
input data selector/multiplexer. Compare this method with a discrete logic gate
implementation.
4.10-) Using two 74151s, design a 16-line multiplexer controlled by four data select
control inputs.
4.11-) What is the function of the A
0
, A
1
, A
2
, and A
3
pins on the 74154 demultiplexer?
4.12-) Design a circuit that will output a LOW whenever a month has 31 days. The month
number (1 to 12) is input as a 4-bit binary number (January = 0001, and so on). Use
a 74150.
74151
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 I
3

I
2

I
1

I
0

E
GND

Y

Y
I
4
I
5
I
6

I
7

S
0

S
1

S
2

V
cc
+5 V
+5 V
0 V
62
EP 427
DIGITAL ELECTRONIC
EXPERIMENT-12

S-R FLIP-FLOPS

1-) PURPOSE :
To study the characteristics and operation principles of various type bistables.

2-) THEORY :
In this example, we cover bistable, monostable, and astable logic devices called
multivibrator. Two categories of bistable devices are the latch and the flip-flop. Bistable
devices have two stable states, called SET and RESET; they can retain either of these
states indefinitely, making them useful as storage devices. The latch is a type of bistable
storage device that is normally placed in a category separate from that of flip-flops.
Latches are basically similar to flip-flops because they are bistable devices that can reside
in either of two states by virtue of a feedback arrangement, in which the outputs are
connected back to the opposite inputs. The basic difference between latches and flip-flops
is the way in which they are changed from one state to the other. This type of digital
circuitry is called sequential logic, because it is controlled by and is used for controlling
other circuitry in a specific sequence dictated by a control clock or enable/disable control
signals. The flip-flop is a basic building for counters, registers, and other sequential control
logic.

2.1-) S-R Latches (Flip-Flops) : A latch is a bistable multivibrator and it is a data storage
circuit that can be constructed using the basic gates. An active-HIGH input S-R (SET-
RESET) flip-flops is formed using a cross-coupled two NOR gates an active-LOW input
S-R flip-flop is formed using a cross-coupled two NAND gates, as shown in Figure 12.1a
and b, respectively. Notice that the output of each gate is connected to an input of the
opposite gate. This produces the regenerative feedback that is characteristic of all
multivibrators.






Figure 12.1: (a) Active-HIGH input S-R flip-flop; (b) Active-LOW input S-R flip-flop.
Q

Q

S

R

Q

Q

S

R

63
To understand the operation principles of the flip-flop, lets start our analysis by
placing a 1 (HIGH) on the SET and a 0 (LOW) on the Reset (Figure 12.1a) This is defined
as the Set condition and should make the Q output 1 and Q output 0. A HIGH on the Set
will make the output of the upper NOR equal 0 (Q=0) and 0 is fed down to the lower
NOR, which together with a LOW on the Reset input will cause the lower NORs output to
equal a 1 (Q=1). Now, when the 1 is removed from the Set input, the flip-flop should
remember that it is Set (that is, Q=1, Q=0). So with Set=0, Reset=0, and Q=1 from
previous being set, lets continue our analysis. The upper NOR has a 0-1 at its inputs,
making Q=0, while the lower NOR has a 0-0 at its inputs, keeping Q=1. Great the flip-
flop remained Set even after the Set input was returned to 0 (called the Hold condition).
Now we should be able to Reset the flip-flop by making S=0, R=1. With R=1, the lower
NOR will output a 0 (Q=0), placing a 0-0 on the upper NOR, making its output 1 (Q=1);
thus the flip-flop flipped to its Reset state. The only other input condition is when both S
and R inputs are HIGH. In this case, both NORs will put out a LOW, making Q and Q
equal 0, which is a condition that is not used. Also when you return to the Hold condition
from S=1, R=1 you will get unpredictable results unless you know which input returned
LOW last. Table 12.1 summarizes the logic operation in truth table form.

Table 12.1 : Truth (Function) Table for (a) Figure 12.1a and (b) Figure 12.1b.
S R Q Q' Comments S R Q Q' Comments
0 0 Q Q' Hold Condition (no change) 0 0 Q Q' Hold Condition (no change)
1 0 1 0 Flip-Flop Set 1 0 1 0 Flip-Flop Set
0 1 0 1 Flip-Flop Reset 0 1 0 1 Flip-Flop Reset
1 1 0 0 Not used 1 1 1 1 Not used

The symbols used for an S-R flip-flop are shown in Figure 12.2. The symbols show
that both true and complemented Q outputs are available. The second symbol is technically
more accurate, but the first symbol is found most often is manufacturers data and through
this experimental manual book.

Figure 12.2 :Symbols for an S-R flip-flop.
S
R
Q
Q
S
R
Q
Q Q
64
2.2-) Gated S-R Flip-Flop : Simple gate circuits, combinational logic, and transparent S-R
flip-flops are called asynchronous (not synchronous) because the output responds
immediately to input changes. Synchronous circuits operate sequentially, in step, with
control input. To make an S-R flip-flop synchronous, we add a gated input to enable and
disable the S and R inputs. Figure 12.3 shows the connections that make the cross-NOR S-
R flip-flop into a gated S-R flip-flop.





Figure 12.3 : Gated S-R flip-flop.
The S
x
and R
x
lines in Figure 12.3 are the original Set and Reset inputs. With the
addition of the AND gates, however, the S
x
and R
x
lines will be kept LOW-LOW (Hold-
Condition) as long as the Gate Enable is LOW. The flip-flop will operate normally while
the Gate Enable is HIGH. The logic symbol and function chart (truth table) are illustrated
in Figure 12.4.

G S R Q Q' Comments

0 0 0 Q Q' Hold Condition
Gate inputs
disabled
0 0 1 Q Q' Hold Condition
0 1 0 Q Q' Hold Condition
0 1 1 Q Q' Hold Condition
1 0 0 Q Q' Hold Condition
Gate inputs
enabled
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 0 0 Unused

Figure 12.4 : Function table and logic symbol for the gated S-R flip-flop.
3-1 ) EXPERIMENTAL PROCEDURE :
3.1-) Set up the following circuit and applying below input waveforms, sketch the
waveform of output Q and Q.
Q

Q

S
x
R
x
Set

Reset

Gate
Enable
S
R
Q
Q
G
(b)
(a)
65










S

R

Q

Q

3.2-) Make the necessary connections to the 7408 quad AND and 7402 quad NOR gate ICs
to form the gated S-R flip-flop and then applying the below waveforms, sketch the output
waveforms of Q and Q.

G


S


R


Q


Q'


14 13 12 11 10 9 8
1 2 3 4 5 6 7
7402
S
Q
Q
R
+ 5 V
66
4-) DISCUSSIONS :
4.1-) What levels must be placed on S and R to Set and S-R flip-flop?
4.2-) What effects do S=0 and R=0 have on the output level at Q?
4.3-) Explain why the S-R flip-flop is called asynchrous and the gated S-R flip-flop is
called synchronous.
4.4-) Sketch the Q output waveform for a gated S-R flip-flop, given the inputs at S, R, and
G shown in below Figure.
G

S

R

Q

Q'












67


REFERENCES
1. William Kleitz, Digital Electronics, Prentice Hall, (1996).
2. Thmos L.Floyd, Digital Fundamentals, Prentice Hall, (1997).
3. M.Morris Mano, Digital Design, Prentice Hall, (1984).
4. Morris E.Levine, Digital Theory and Experimentation Integrated Circuits. Prentice
Hall, (1982).
5. John F.Wakerly, Digital Design, (2000).


















68
APPENDIX A

GLOSSARY OF LOGIN AND INTEGRATED-CIRCUIT TERMINILOGY
1


Access Time : Time required to obtain stored in a memory.
Active-LOW : An output of a logic circuit that is LOW when activated or an input that needs to be
LOW to be activated.
Adder : Circuitry that performs the operation of adding two numbers.
Adjacent Cell : Cells within a Karnaugh map that border each other on one side or the top or bottom
of the cell.
Address : A unique binary value that is used to distinguish the location of individual memory
bytes or peripheral devices.
Analog : A system that deals with continuously varying physical quantities such as voltage,
temperature, pressure, or velocity. Most quantities in nature occur in analog, yielding
an infinite number of different levels.
Analog-to-digital
(A/D)Conversion:
The process of converting an analog signal to digital form.
Analog-to-digital
converter (ADC):
A device used to convert an analog signal to a sequence of digital codes.
AND Gate : A logic circuit that produces a HIGH output only when all of the inputs are HIGH.
AND-OR-
INVERT Gate
(AOI) :
An integrated circuit containing combinational logic consisting of several AND
gates feeding into An OR gate and then an inverter. It is used to implement logic
equations that are in the SOP format.
ASCII Code : American Standard Code for Information Interchange. ASCII is a 7-bit code used in
digital systems to represent all letters, symbols, and numbers to be input or output to
the outside world.
Astable
Multivibrator:
An oscillator having two outputs. The output levels are complementary, when one
output is high, the other is low.
Asynchronous: (Not synchronous) A condition in which the output of a device will switch states
instantaneously as the inputs change without regard to an input clock signal.
Asynchronous
Input :
Inputs to a flip-flop which affect the output of the flip-flop independent of all other
inputs.
Asynchronous
Operation :
An operation that proceeds independently within a system independent of any clock
signals.
BCD : Binary-coded decimal. A 4-bit code used to represent the 10 decimal digits 0 to 9.
Bidirectional : A device capable of functioning in either of two directions, thus being able to reverse
its input/output functions.
Binary : The base 2 numbering system. Binary numbers are made up of 1a and 0s, each
position being equal to a different power of (2
3
, 2
2
, 2
1
, 2
0
, and so on).
Binary String : Two or more binary bits used collectively to form a meaningful binary
representation.
Binary Word : A group, or string, of binary bits. In a 4-bit system a word is 4 bits in a box format.
Bistable : A circuit having two stable states.
Bit : A single binary digit. The binary number 1101 is a 4-bit number.
Bit time : The interval of time occupied by a single bit in a sequence of bits; the period of the
clock.
Boolean Equation
:
An algebraic expression that illustrates the functional operation of a logic gate or
combination of logic gates.
Boolean
Reduction :
An algebraic technique that follows specific rules to convert a Boolean equation into
a simpler form.
Borrow : When subtracting numbers, if the number being subtracted from is not large enough,
it must borrow, or take an amount from, the next-more-significant digit.
Byte : A group of eight bits.
Cary generation: The process of producing an output carry in a full-adder when both input bits are 1s.

1
This section is completely taken from Digital Fundamentals by Thmos L.Floyd.

69
Carry
propagation :
The process of rippling an input carry an input carry to become the output carry in a
full-adder when either or both of the input bits are 1s and the input carry is a 1.
Carry-In : A amount from a less-significant-digit addition that is applied to the current addition.
Carry-Out : When adding numbers, when the sum is greater than the amount allowed in that
position, part of the sum must be applied to the next-more-significant position.
Cell : Each box within a Karnaugh map. Each cell corresponds to a particular combination
of input variable logic levels.
Chip : The term given to an integrated circuit. It comes from the fact that each integrated
circuit comes from a single chip of silicon crystal.
Clear : Set a binary to the 0 state.
Clock : A device used to produce a periodic digital signal that repeatedly switches from
LOW to HIGH and back at a predetermined rate.
Code : A set of bits arranged in a unique pattern and used to represent such information as
numbers, letters, and other symbols.
Code Converter : A device that converts one type of binary representation to another, such as BCD to
binary or binary to Gray code.
Comparator : A device used to compare the magnitude or size of two binary bit strings or words.
Combinational
Logic :
Logic circuits formed by combining several of the basic logic gates to form a more
complex function.
Comparator : A device or system that identifies an equality between two quantities.
Complement : A change to the opposite digital state. 1 becomes 0and 0 becomes 1.
Controlled
Inverter :
A digital circuit capable of complementing a binary string of bits based on an
external control signal.
Counter : A digital circuit capable of counting electronic events, such as pulses, by progressing
through a sequence of binary states.
CPU : Central processing unit; a major component of all computers that controls the
internal operations and processes data.
Data : Information in numeric, alphabetic- or other form.
De Morgans
Theorem :
A Boolean law used for equation reduction that allows the user to convert an
equation having an inversion bar over several variables into an equivalent equation
having inversion bars over single variables only.
Decade Counter: A digital counter having ten states.
Decimal : The base 10 numbering system. The 10 decimal digits are 0, 1, 2, 3, 4, 5, 6, 7, 8, and
9. Each decimal position is a different power of 10 (10
3
, 10, 10
1
, 10
0
, and so on).
Decoder : A device that converts a digital code such as hex or octal into a single output
representing its numeric value.
Demultiplexer : A device or circuit capable of routing a single data-input line to one of several data-
output lines; sometimes referred to as a data distributor.
D Flip-Flop : A type of bistable multivibrator in which the output follows the state of the D input.
Digit : A symbol used to express a quantity.
Digital : A system that deals with discrete digits or quantities. Digital electronics deals
exclusively with 1s and 0s, or ONs and OFFs. Digital codes (such as ASCII) are the
used to convert the 1s and 0s to a meaningful number, letter, or symbol for some
output display.
Digital-to-analog-
converter (DAC):
A device in which information in digital codes to an analog form.
Disable : To disallow or deactive a function or circuit.
Disabled : The condition in which a digital circuits inputs or outputs are not allowed to accept
or transmit digital states.
Dont Care : A variable appearing in a truth table or timing waveform that will have no effect on
the final output regardless of the logic level of the variable. Therefore, dont-care
variables can be ignored.
Dual Symbols: The negative-AND is the dual symbol for the NOR gate, and the negative-OR is the
dual symbol for the NAND gate.
Edge Triggered : The term given to a digital device that can accept inputs and change outputs only on
the positive or negative edge of some input control signal or clock.
Edge-triggered
flip-flop :
A type of flip-flop in which the data are entered and appear on the same clock edge.
70
Electrical Noise : Unwanted electrical irregularities that can cause a change in a digital logic level.
Enable : To allow or activate a function or circuit.
Enabled : The condition in which a digital circuits inputs or outputs are allowed to accept or
transmit digital states normally.
Encoder : A device that converts a weighted numeric input line to an equivalent digital code,
such as hex or octal.
Error Indicator : A visual display or digital signal that is used to signify that an error has occurred
within a digital system.
Equivalent
Circuit :
A simplified version of a logic circuit that can be used to perform the exact logic
function of the original complex circuit.
Excess-3 Code: An unweighted digital code in which each of the decimal digits is represented by a
4-bit code by adding 3 to the decimal digit and converting to binary.
Exclusive-NOR: A gate that produces a HIGH output for both inputs HIGH or both inputs LOW.
Exclusive-OR: A gate that produces a HIGH output for one or the other input HIGH, but not both.
Even Parity : The condition of having an even number of 1s in every group of bits.
Fast-Look-Ahead
Carry :
When cascading several full-adders end to end, the carry-out of the last full-adder
cant be determined until each of the previous full-adder additions is completed. The
internal carry must ripple or propagate through each of the lower-order adders before
reaching the last full-adder. A fast-look-ahead carry system is used to speed up the
process in a multibit system by reading all the input bits simultaneously to determine
ahead of time it a carry-out of the last full-adder is going to occur.
Flip-Flop : A basic storage circuit that can store only one bit at a time; a synchronous bistable
device.
Float : A logic level in a digital circuit that is neither HIGH nor LOW. It acts like an open
circuit to anything connected to it.
Full-Adder : An adder circuit having three inputs, used to add two binary digits plus a carry. It
produces their sum and carry as outputs.
Function Table: A chart that illustrates the input/output operating characteristics of an integrated
circuit.
Gate : The basic building block of digital electronics. The basic logic gate has one or more
inputs and one output and is used to perform one of the following logic functions:
AND, OR, NOR, NAND, INVERTER, exclusive-OR, or exclusive-NOR.
Gray Code : A binary coding system used primarily in rotating machinery to indicate a shaft
position. Each successive binary string within the code changes by only 1 bit.
Half-Adder : An adder circuit used in the LS position when adding two binary digits with no
carry-in to consider. It produces their sum and carry as outputs.
Hard disk : A magnetic storage device mounted in a sealed housing.
Hardware/
Software :
Sometimes solutions to digital applications can be done using hardware or software.
The software approach uses computer program statements to solve the application,
whereas the hardware approach uses digital electronic devices and ICs.
Hex : When dealing with integrated circuits, a term specifying that there are six gates on a
single IC package.
Hexadecimal : The base 16 numbering system. The 16 hexadecimal digits are 0, 1, 2, 3, 4, 5, 6, 7, 8,
9, A, B, C, D, E, and F. Each hexadecimal position represents a different power of
16 (16
3
, 16
2
, 16
1
, 16
0
, and so on).
Hex Inverter : An integrated circuit containing six inverters on a single DIP package.
Input : The signal or line going into a circuit; a signal that controls the operation of a circuit.
Integrated
Circuit :
The fabrication of several semiconductor and electronic devices (transistors, diodes,
and resistors) onto a single piece of silicon crystal. Integrated circuits are
increasingly being used to perform the functions that used to require several hundred
discrete semiconductors.
Inversion Bar : A line over variables in a Boolean equation signifying that the digital state of
variables is to be complemented. For example, the output of a two-input NAND gate
is written X= AB .
Inversion
Bubbles :
An alternative to drawing the triangular inversion symbol. The bubble (or circle) can
appear at the input or output of a logic gate.
Inverter : A logic circuit that changes its input into the opposite logic state at its output (0 to 1
and 1 to 0).
71
J-K flip flop : A type of flip-flop that can operate in the SET, RESET, no-change, and toggle
modes.
Johnson counter: A type of register in which a specific pattern of 1s and 0s is shifted through the
stages, creating a unique sequence of bit patterns.
Karnaugh Map: A two-dimensional table of Boolean output levels used as a tool to perform a
systematic reduction of complex logic circuits into simplified equivalent circuits.
Latch : A bistable digital device used for storing a bit.
Leading Edge : The first transition of a pulse.
Least Significant
Bit (LSB) :
The bit having the least significance in a binary string. The LSB will be in the
position of the lowest power of 2 within the binary number.
Logic Probe : An electronic tool used in the troubleshooting procedure to indicate a HIGH, LOW,
or float level at a particular point in a circuit.
Logic Pulser : An electronic tool used in the troubleshooting procedure to inject a pulse or pulse
into a particular point in a circuit.
Logic State : A 1 or 0 digital level.
Logic Symbol : Graphic representation of basic logic gates.
LSI : Large-scale integration; a level of IC complexity in which there are 100 to 9999
equivalent gates per chip.
Master-slave flip-
flop :
A type of flip-flop in which the input data are entered into the device on the leading
edge of the clock pulse and appear at the output on the trailing edge.
Microprocessor : A large-scale integration (LSI) integrated circuit that is the fundamental building
block of a digital computer. It is controlled by software programs that allow it to do
all digital arithmetic, logic, and I/O operations.
Minimization : The process that results in an SOP or POS Boolean expression containing the fewest
possible terms with the fewest possible literals per term.
Most Significant
Bit (MSB) :
The bit having the most significance in a binary string. The MSB will be in the
position of the highest power of 2 within the binary number.
MSI : Medium-scale integration. An IC chip containing combinational logic that is packed
more densely that a basic logic gate IC (small-scale integration, SSI) but not as dense
as a microprocessor IC (large-scale integration, LSI). There are 12 to 99 equivalent
gates per chip in a MSI.
Multiplexer : A device or circuit capable of selecting one of the several data input lines for output
to a single line; sometimes referred to as a data selector.

Multivibrator: A class of digital circuits in which the output is connected back to the input ( an
arrangement called feedback) to produce either two stable states, one stable state- or
no stable states, depending on the configuration.
NAND Gate : A logic circuit in which a LOW output occurs if and only if all the inputs are HIGH.
Negative Edge : The edge on a clock or triggered pulse that is making transition from HIGH to LOW.
Negative Logic: The 1 level is more negative than the 0 level.
Negative-AND: A NOR gate equivalent operation in which there is a HIGH output when all inputs
are LOW.
Negative-OR : A NAND gate equivalent operation in which there is a HIGH output when all inputs
are LOW.
Nibble : Four bits.
NOR Gate : A logic circuit in which the output is LOW when any or all of the inputs are HIGH.
NOT : When reading a Boolean equation, the word used to signify an inversion bar. For
example, the equation X=AB is read X equals NOT AB.
Octal : The base 8 numbering system. The eight octal numbers are 0, 1, 2, 3, 4, 5, 6, and 7.
Each octal position represents a different power of 8 (8
3
, 8
2
, 8
1
, 8
0
, and so on).
Odd Parity : The condition of having an odd number of 1s in every group of bits.
Ones
Complement :
A binary number that is a direct (true) complement, bit by bit, of some other number.
Ones catching: A feature of the master-slave flip-flop that allows the master section to latch on to
any 1 level that is felt at the inputs at any time while the input clock pulse is HIGH
and then transfer those levels to the slave when the clock goes LOW.
OR : A basic logic operation in which a true (HIGH) output occurs when one or more of
the input conditions are true (HIGH).
72
OR Gate : A logic circuit that produces a HIGH output when any of the inputs is HIGH.
Overflow : The condition that occurs when the number of bits in a sum exceeds the number of
bits in each of the numbers added.
Parallel Adder: An adder in which all bits are added simultaneously.
Parity : An error-detection scheme used to detect a change in the value of a bit.
PAL : Programmable Array Logic. A device with a programmable AND array and a fixed
OR array.
PIC : Programmable interrupt controller.
PLA : Programmable logic array. A device with programmable AND and OR arrays.
PLD : Programmable logic device.
Positive Edge : The edge on a clock or triggered pulse that is making the transition from LOW to
HIGH.
Priority : When more than one input to a device is activated and only one acted on, the one
with the highest priority will be acted on.
Priority Encoder
:
An encoder in which only the highest value input digit is encoded and any other
active input is ignored.
Product-of-Sums
(POS) Form :
A Boolean equation in the form of a group of ORed variables ANDed with another
group of ORed variables (for example, X=(A+B)(A+C+D)(B+D).
Pulse : A signal of short time.
Pulse Triggered : The term given to a digital device that can accept inputs during an entire positive or
negative pulse of some input control signal or clock. (Also called level triggered)
Quad : When dealing with integrated circuits, the term specifying that there are four gates
on a single IC package.
Register : A digital circuit capable of storing and shifting binary information; typically used as
a temporary storage device.
Registered : A PLD output configuration where the output comes from a flip-flop.
Reset : The state of a flip-flop or latch when the output is 0; the action of producing a
RESET state.
Ring Counter : A register in which a certain pattern of 1s and 0s is continuously recirculated.
Ripple Carry : A method of binary addition in which the output carry from each adder becomes the
input carry of the next higher-order adder.
Sequential Logic : Digital circuits that involve the use of a sequence of timing pulses in conjunction
with storage devices such as flip-flops and latches and functional ICs such as
counters and shift registers.
Set : The state of a flip-flop or latch when the output is 1; the action of producing a SET
state.
Setup Time : The length of time before the active edge of a triggered pulse (control signal) that the
inputs of a digital device be in a stable digital state. (That is, if the set up time of a
device is 20 ns, the inputs must be held stable 20 ns before the triggered edge)
Sign Bit : The leftmost, or MSB, in a twos-complement number, used to signify the sign of the
number (1=negative, 0=positive).
Shift : To move binary data from stage to stage within a shift register or other storage
device or to move binary data into or out of the device.
Sign Bit : The left-most bit of a binary number that designates whether the number is positive
(0) or negative (1).
S-R flip-flop : A SET-RESET flip-flop.
SSI : Small-scale integration; a level of IC complexity in which there are twelve fewer
equivalent gates per chip.
Stage : One storage element (flip-flop) in a register
State Diagram: A graphic depiction of a sequence of states or values
Storage : The capability of a digital device to retain bits; the process of retaining digital data
for later use.
Storage Register : Wo or more data storage circuits (such as flip-flops or latches) used in conjunction
with each other to hold several bits of information.
Strobe Gates : A control gate used to enable or disable inputs from reaching a particular digital
deice.
Sum-of-Products
(SOP) Form :
A Boolean equation in the form of a group of ANDed variables ORed with another
group of ANDed variables (for example, X= ABC + ACD + BD.
73
Synchronous : A condition in which the output of a device will operate only in synchronization with
(in step with) a specific HIGH or LOW timing pulse or trigger signal.
Synchronous
Counter :
A type of counter in which each stage is clocked by sample pulse.
Terminal Count: The final state in a counters sequence.
Timer : A circuit that can be used as a one-shot or as an oscillator.
Timing Diagram : A diagram used to display the price relationship between two or more digital
waveforms as they vary relative to time.
Toggle : The action of a flip-flop when it changes state on each clock pulse (Q changes to the
level Q and Q changes to the level of Q).
Trailing Edge: The second transition of a pulse.
Transmission : The transfer of digital signals from one location to another.
Transparent
Latch :
An asynchronous device whose outputs will hold onto the most recent digital state of
the inputs. The outputs immediately follow the state of the inputs without regard to
trigger input and remain in that state even after the inputs are removed or disabled.
Trigger : A pulse used to initiate a change in the state of a logic circuit.
Tristate : A type of output in logic circuits that exhibits three states : HIGH, LOW, and open
(disconnected). The open state is called the high-Z state.
Troubleshooting : The work that is done to find the problem in a faulty electrical circuit.
Truth Table : A tabular listing that is used to illustrate all the possible combinations of digital input
levels to gate and the output that will result.
TTL : Transistor-transistor logic. The most common integrated circuit used in digital
electronics today. A large family of different TTL ICs is used to perform all the logic
functions necessary in a complete digital system.
Twisted-Ring
Counter :
A ring counter in which the state of the input stage is the complement of the final
stage.
Twos
Complement :
A binary numbering representation that simplifies arithmetic in digital systems.
ULSI : Ultra large-scale integration; a level of IC complexity in which there are more than
100.000 equivalent gates per chip.
Universal Gates : The NOR and NAND logic gates are sometimes called universal gates because any
of the other logic gates can be formed from them.
Universal shift
register :
A register that has both serial and parallel input and output capability.
Up/Down
Counter :
A counter that can progress in either direction through a certain sequence.
Variable : A symbol used to represent a logic quantity that can have a value at 1 or 0, usually
designated by an italic letter.
VLSI : Very large-scale integration; a level of IC complexity in which there are 10.000 to
99.999 equivalent gates per chip.
Word : A complete unit of binary data.
Word Length : The number of bits in a word.













74
APPENDIX B

Supplementary Index of ICs

All the logic gates are available in various configurations in the TTL and CMOS families.
This is an index of the integrated circuits (ICs).

7400 Series ICs
7400 Quad 2-input NAND gate 74HC00 Quad 2-input NAND gate
74LV00 Quad 2-input NAND gate 7402 Quad 2-input NOR gate
7404 Hex Inverter 74HC04 Hex inverter
7408 Quad 2-input AND gate 74HC08 Quad 2-input AND gate
74HCT08 Quad 2-input AND gate 7411 Triple 3-input AND gate
74HC11 Triple 3-input AND gate 7414 Hex inverter Schmitt
trigger
74HC14 Hex inverter Schmitt trigger 7421 Dual 4-input AND gate
74HC21 Dual 4-input AND gate 7427 Triple 3-input NOR gate
7430 8-input NAND gate 7432 Quad 2-input OR gate
74HC32 Quad 2-input OR gate 74HCT32 Quad 2-input OR gate
7442 BCD-to decimal decoder 7447 BCD-to seven-segment
decoder/ driver
7454 4-wide 2- and 3-input AND-
OR-invert gate (AIO)
7474 Dual D-type flip-flop
7475 Quad bistable latch 7476 Dual J-K flip-flop
74LS76 Dual J-K flip-flop 7483 4-bit full adder
7485 4-bit magnitude comparator 74HC86 Quad input exclusive-OR
gate
7490 Decade counter 7492 Divide-by-twelve counter
7593 4-bit binary ripple counter 74H106 Dual J-K negative edge-
triggered flip-flop
74109 Dual J-K positive edge-
triggered flip-flop
74LS112 Dual J-K negative edge-
triggered flip-flop
74121 Monostable multivibrator 74123 Dual retriggered
monostable multivibrator
74S124 Voltage-controlled oscillator 74132 Quad 2-input NAND
Schmitt trigger
74138 1-of-8 decoder/demultiplexer 74LS138 1-of-8
decoder/demultiplexer
74HCT138 1-of-8 decoder/demultiplexer 74139 Dual 1-of-4
decoder/demultiplexer
74147 10-line-to-4-linr priority
encoder
74148 8-input priority encoder
74150 16-input multiplexer 74151 8-input multiplexer
74154 1-of-16
decoder/demultiplexer
74LS154 1-of-16
decoder/demultiplexer
74160 4-bit binary counter 74164 8-bit serial-in parallel-out
shift register
74165 8-bit serial/parallel-in, serial-
out shift register
74181 4-bit arithmetic logic unit
74184 BCD-to-binary converter 74185 Binary-to-BCD converter
75
74190 Presettable BCD decade
up/down counter
74191 Presettable 4-bit binary
up/down counter
74192 Presettable BCD decade
up/down counter
74193 Presettable 4-bit binary
up/down counter
74194 4-bit bi-directional universal
shift register
74HCT238 1-of-8 demultiplexer
74241 Octal buffer (3-state) 74LS244 Octal buffer (3-state)
74ABT244 Octal buffer (3-state) 74LS245 Octal transceiver (3-state)
74HCD273 Octal D flip-flop 74280 9-bit odd/even parity
generator/checker
74HC283 4-bit full adder with fast carry 74LS373 Octal D flip-flop with 3-
satate outputs
74395A 4-bit cascadable shift-register
with 3-state outputs
74HC583 4-bit BCD adder
74LS640 Inverting octal bus tarnsceiver 74HCT4543 BCD-to-seven-segment
latch/decoder/driver
Other ICs
4001 Quad 2-input NOR gate 4008 4-bit binary full adder
4011 Quad 2-input NAND 4049 Hex inverting buffer
4050 Hex non-inverting buffer 4051 8-channel analog
multiplexer/demultiplexer
4069B Hex inverter 4504B Level-shifting buffer
4543 BCD-to-seven-segment
latch/decoder/driver
2118 16K X 1 dynamic RAM
2147H 4K X 1 static RAM 2716 2K X 8 EPROM
2732 4K X 8 EPROM 3242 Dynamic RAM controller
LF198 Sample and hold circuit LH0084 Programmable-gain
instrumentation amplifier
ADC0801 Analog-to-digital converter DAC0808 Digital-to-analog converter
MC1408 Digital-to-analog converter AM3705 Analog multiplexer switch
NE5034 Analog-to-digital converter 10124 ECL level shifter
10125 ECL level shifter 82S100
(PLS100)
Field programmable logic
array
PAL16H2 Programmable array logic PAL16L8 Programmable array logic
PAL16R8 Programmable array logic 8085A 8-bit microprocessor
8051 8-bit microcontroller 68HC11 8-bit microcontroller
7805 Voltage regulator 555 Timer
741 Operational amplifier 4N35 Opto-coupler
IRF130 Power MOSFET TIL601 Phototransistor
LM35 Linear temperature sensor LM185 Precision reference diode
IN749 Zener diode







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APPENDIX C
TTL PIN CONFIGURATION







































77
EXPERIMENT-
DATA SHEET
Name of the Group Members Sign Date:./../20



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RESULTS



































Lab.Assistant:. Sign:..
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