1568 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO.

8, AUGUST 2013
New Approach to VLSI Buffer Modeling, Considering
Overshooting Effect
Milad Mehri, Mohammad Hossein Mazaheri Kouhani,
Nasser Masoumi, and Reza Sarvari
AbstractIn this brief, we use the alpha power law model for MOS
devices to reach a more accurate modeling of CMOS buffers in very
deep submicrometer technologies. We derive alpha model parameters of
a CMOS buffer for 90-, 65-, and 45-nm technologies using HSPICE
simulations. By analytical efforts we nd the output resistance of a
minimum-size buffer and compare it with those extracted from HSPICE
simulations. We propose a new model for the output resistance of a given-
size buffer in any technology, which demonstrates 3% error on average
as opposed to the conventional model. Also a new buffer resistance
is proposed analytically and numerically to calculate the crosstalk for
interconnect analysis applications. In addition, we propose a model for
the transfer function zero generated by the gate-drain capacitances of
MOS transistors, which cause the overshooting effect, and develop an
accurate expression for modeling this phenomenon. As the nal point,
together with the input-to-output capacitance, the equivalent output
resistors present a simple and accurate macromodel for the CMOS buffer.
Index TermsAlpha-power law, buffer overshooting effect, CMOS
buffer modeling, VLSI buffer.
I. INTRODUCTION
VLSI circuit analysis in the circuit level for the most important
measurements, such as delay and power consumption, depends on
rigorous modeling of their basic components. One of the most
prevailing and underlying elements in digital systems is the CMOS
buffer. A buffer is a simple but principal and critical component
and, as such, has many signicant applications and is vastly used for
signal cleaning and the reduction of delay, noise, and crosstalk. This
buffer is popular because of its low power consumption, mainly in
switching phases. With the scaling of CMOS technology into the very
deep submicrometer (VDSM), buffer modeling has been a critical
demand due to its many appearances in the design and analysis
of digital systems. Accurate modeling of this core component can
result in a better inspection through the system, whereas the models
simplicity can cause a fast design time. Hence, many researchers have
addressed this need by proposing various analytical models to present
the behavior of CMOS buffers.
Propagation time delay and power dissipation of buffer are its
major factors that are modeled. However, in some works, the input-
to-output capacitance, which results in overshoot and undershoot
effects, has not been taken into account [1][5] while some others
have incorporated this effect. In [6][11], power estimation models of
a CMOS buffer, accounting for the inuence of the input-to-output
coupling capacitance of the buffer in submicrometer technologies,
were given. In [6], [12][15], the nonlinearity induced by the input-
to-output coupling capacitance is taken into account for the analytical
modeling of the gate propagation delay time. The time duration when
the output gets out of the steady-state value of the signal level for
the rst time is known as overshoot time. This parameter is currently
one of the key parameters while coping with buffers, since it is
Manuscript received September 10, 2011; revised April 4, 2012; accepted
July 21, 2012. Date of publication August 31, 2012; date of current version
July 22, 2013.
M. Mehri, M. H. M. Kouhani, and N. Masoumi are with the Depart-
ment of Electrical and Computer Engineering, University of Tehran, Tehran
14395-515, Iran (e-mail: miladmehri@live.com; mhmazaheri.k@gmail.com;
nmasoumi@ut.ac.ir).
R. Sarvari is with the Sharif University of Technology, Tehran 16846-13114,
Iran (e-mail: sarvari@sharif.edu).
Digital Object Identier 10.1109/TVLSI.2012.2211629
1063-8210/$31.00 2012 IEEE
Fig. 1. CMOS buffer.
comparable to conventional propagation delay of the buffer [14]. We
have presented an expression for this parameter based on our novel
macromodel of the overshooting effect. The nonlinear operation of
a MOS transistor results in nonlinear resistance and capacitance in
the model. Averaging these parameters in time interval when the
input signal changes is a typical solution which is used in this brief.
Technology transportability is an advantage of this model which most
of the models may lack. The analytical model for delay in [16]
benets from the advantage of portability. Likewise, in this brief, we
develop a closed-form expression to estimate the output resistances of
a CMOS buffer. This model depends on device technology parameters
and the input signal transition time. Therefore, there is no need for
tting or extracting parameters, which makes the developed model
technology portable.
What distinguishes this brief from the others is the fact that most
of the overshoot models [6][15] have used the dynamic behavior
equation of an inverter derived from Kirchhoffs Current Law (KCL)
at the output node. In contrast, our new proposed overshoot model is
based on intuition and curve tting, simultaneously, still completely
in analytical form.
This brief is organized as follows. The alpha power modeling is
discussed in Section II. The output resistance of the buffer, and the
relevant derivations and integration expressions are addressed in this
section. Analytical expressions for the newly proposed model are
presented in Section III. Additionally, simulations and verication
procedures are performed in this section. In Section IV, the over-
shooting effect is modeled as a zero generated by the input-to-output
coupling capacitance of MOS transistors in the transfer function.
Finally, summary and conclusion are provided in Section V.
II. ALPHA POWER MODELING
In VDSM, the Shockley transistor model is no longer valid.
This happens because of short channel effects such as mobility
degradation, drain-induced barrier lowering, and velocity saturation.
Therefore, in order to accomplish a better analysis, a more accurate
model is required. As such, we utilize the currentvoltage character-
istic of an MOS transistor expressed in [1] and [2] as follows:
i
D
=
_

_
k
sub
e

(v
GS
v
TH
)
[1 exp(v
DS
)], @ sub.t hre.
k
l
(v
GS
v
TH
)

2
v
DS
, @ li n.
k
s
(v
GS
v
TH
)

(1 +v
DS
), @ sat .
(1)
A conventional CMOS buffer (simply an inverter) is made of
NMOS and PMOS transistors, as depicted in Fig. 1.
The C
in
, C
out
, and R
out
model the equivalent input and
output capacitances of the transistors, and the output equivalent
resistance, respectively. For timing analysis, all these model elements
must be averaged in time when the input signal transits between two
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 8, AUGUST 2013 1569
(a) (b)
Fig. 2. Buffer input V
in
. (a) Rise. (b) Fall.
low and high values. The R
out
can be written as
R
out
=
1
T
_
T
0

V
ds
i
D

dt (2)
where T is the time needed for the input to settle to V
dd
or gnd. For
the input signal, we consider a ramp input as in Fig. 2(a) and (b)
V
in
=
_
_
_
0, t 0
(
t
t
r
) V
dd
, 0 t t
r
V
dd
, t t
r
V
in
=
_
_
_
V
dd
, t 0
(1
t
t
f
) V
dd
, 0 t t
f
0, t t
f
.
(3)
During the transition in the input signal, the transistors change their
operating regions. The actual operating regions (linear or saturation)
in the time interval depend on the type of load driven by the buffer
[17]. In this brief, we have supposed a pure capacitive load, for
NMOS and PMOS transistors of the buffer. At the beginning of the
rising input, the PMOS transistor is in the subthreshold region. The
effect of this current is considerable in VDSM CMOS technologies
discussed in [15] and [11]. Accordingly, due to the complexity
of integration from subthreshold current, we start the interval of
integration from a new parameter instead of zero. This assumption
enables us to keep the subthreshold region away from the interval of
the integration. The parameter depends on the device technology,
which in this brief is supposed to be 1% of the rise time. We also
suppose that the output is just the inverted input with zero delay.
By this assumption, performing the integration and simplifying the
results, we have
R
NMOS,fall
= R
NMOS,rise
=
_
1
1 (
vt n
vdd
+

t r
)
_

__
(VddVdssat nVt n)
1
(Vdd(1)Vdssat nVt n)
Vdd ksn( 2)( 1)
_

_
(

t r
Vdd)
1
((2)Vt n+Vdd((

t r
1)+2

t r
))
Vdd ksn( 2)( 1)
_
+
_
2(VddVdssat n Vt n)
1

2 2(VddVt n)
1

2
Vdd( 2)kl n
_
_
.
(4)
R
PMOS,fall
= R
PMOS,rise
=
_
1
1 (
|Vt p|
Vdd
+

t r
)
_

__
(Vddvsdsat p|V t p|)
1
(Vdd(1)Vsdst p|Vt p|)
Vdd ksp( 2)( 1)
_
+
_
(

t r
Vdd)
1
(Vdd(1
|Vtp|
Vdd

t r
)2Vdd+2|Vtp|+

t r
Vdd)
VddKsp( 2)( 1)
_
+
_
2(Vdd Vsdsat p|Vtp|)
1

2
2(Vdd|Vtp|)
1

2
Vdd( 2)Kl n
_
_
.
(5)
TABLE I
RESULTS OF BALANCING THE BUFFER
Tech. W
n
/L
min
W
p
/L
min
t
pHL
= t
pLH
= t
pd
(ps)
90 nm 1.5 3.452 7.443
65 nm 1.5 3.997 8.264
45 nm 1.5 4.542 9.164
(a) (b)
(c) (d)
Fig. 3. (a) Single CMOS buffer. (b) Simple RC model for (a). (c) Cascaded
buffers. (d) RC model for (c).
Although it would be benecial to have equal input rise and fall
times, which is one assumption of this brief, we have also taken
the output as just the inverted form of the input. This results in
the equality of R
NMOS,fall
and R
NMOS,rise
and also the equivalence
of R
PMOS,fall
and R
PMOS,rise
. The output resistances of the buffer
R
out,fall
and R
out,rise
for the rising and falling input can be written
as follows:
R
out,fall
=
R
NMOS,fall
+ R
PMOS,fall
2
(6)
R
out,rise
=
R
NMOS,rise
+ R
PMOS,rise
2
. (7)
III. SIMULATION AND VERIFICATION
The alpha power law parameters of the buffer transistors for 3-nm
technology nodes utilizing predictive technology model parameters
discussed in [18] and [19] have been extracted using HSPICE
simulations. In order to reach the minimum transistor sizes of the
buffer to use minimum area for the buffer, we need another constraint
rather than assuming 1.5 for the size of the NMOS transistor.
The size of 1.5 Lmin for the width of NMOS is the minimum
achievable size in drawing layout, based on Lambda scalable model.
The constraint we use to obtain the minimum size of the PMOS is to
make the propagation delay of the buffer symmetric. By using this
constraint, we obtain the size of the PMOS. Table I carefully demon-
strates the size of the PMOS transistor in three different process
technologies.
So as to obtain the values of R
out
, C
out
, and C
in
, three steps are
used.
1) Averaging the |V
ds
/I
ds
| through the rise and fall times using
HSPICE to obtain the average resistance of the inverter, R
out
.
This averaging is done based on multiple loads and different
sizes of buffer transistors.
2) Using (8) to obtain C
out
having the values of R
out
and t
pdself
from HSPICE simulations. The structure used in this step and
its equivalent circuit are shown in Fig. 3(a) and (b). Based on
[20], for t
pdself
we have
t
pdself
= Ln(2) R
out
C
out
= 0.69 R
out
C
out
.
(8)
3) Using (9) to calculate C
in
having the values of R
out
, t
pd
, and
C
out
. The structure used in this step and its equivalent circuit
1570 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 8, AUGUST 2013
TABLE II
MINIMUM BUFFER OUTPUT CAPACITANCE, INPUT CAPACITANCE,
AND OUTPUT RESISTANCE
Tech. 90 nm 65 nm 45 nm
C
out,fall
0.534 fF 0.423 fF 0.304 fF
C
out,rise
0.891 fF 0.632 fF 0.439 fF
C
out_buffer
= (C
out,fall
+ C
out,rise
)/2
0.713 fF 0.528 fF 0.372 fF
C
in,fall
0.402 fF 0.289 fF 0.211 fF
C
in,rise
0.546 fF 0.327 fF 0.195 fF
C
out_buffer
= (C
in,fall
+ C
in,rise
)/2
0.474 fF 0.308 fF 0.203 fF
R
NMOS
7.50 k 12.50 k 20.94 k
R
PMOS
11.51 k 16.82 k 25.79 k
R
buffer
= (R
NMOS
+ R
PMOS
)/2
9.50 k 14.65 k 23.36 k
TABLE III
ANALYTICAL RESULTS FOR NMOS, PMOS, AND BUFFER
Tech. 90 nm 65 nm 45 nm
R
NMOS,fall
7.41 k 12.53 k 20.69 k
R
NMOS,rise
7.41 k 12.53 k 20.69 k
R
PMOS,fall
11.41 k 16.92 k 25.49 k
R
PMOS,rise
11.41 k 16.92 k 25.49 k
R
out,fall
9.41 k 9.41 k 9.41 k
R
out,rise
14.73 k 14.73 k 14.73 k
R
buffer
= (R
out,fall
+R
out,rise
)/ 2 23.09 k 23.09 k 23.09 k
TABLE IV
COMPARISON BETWEEN HSPICE AND ANALYTICAL RESULTS
Tech. Error =(R
buffer,HSPICE
R
buffer,Analytic
)/R
buffer,HSPICE
90 nm 0.95%
65 nm 0.55%
45 nm 1.16%
are shown in Fig. 3(c) and (d). Based on [20], for t
pd
we have
t
pd
= Ln(2) R
out
(C
in
+2C
out
)
= 0.69R
out
(C
in
+2C
out
). (9)
Inserting the model parameters from simulation into the analytical
expressions (4)(7) for the resistors, we obtain the results summarized
in Tables II and III.
Table IV shows a comparison between HSPICE simulation results
and those obtained from the analytical expressions. As it can be seen
from this table, the error is less than 2% for 45 nm.
The conventional model for an inverter of the size k with respect
to a minimum-size inverter in a given technology is given as follows:
R
out
=
R
out0
k
, C
out
= kC
out0
, C
in
= kC
in0
(10)
where
k =
W
P
W
P0
=
W
N
W
N0
(11)
and W
N0
and W
P0
are the minimum NMOS and PMOS transistor
sizes, respectively. Based on the HSPICE simulation results shown
in Table V, as the technology shrinks, the error of (10) decreases.
The new relations that are based on curve-tting results for R
out
TABLE V
PERCENTAGE ERROR OF AGREEMENT BETWEEN R
out
AND HSPICE
Tech. 90 nm 65 nm 45 nm
(10)
R
out0
7608 11 880 20 790
Min.
%Err.
0.00% 30.50% 10.31%
Max.
%Err.
0.24% 51.99% 17.08%
Avg.
%Err.
0.03% 45.55% 16.41%
(12)
a 0.002 0.073 0.086
R
out0
7621 12 620 21 480
Min.
%Err.
0.00% 0.03% 0.01%
Max.
%Err.
51.92% 42.57% 28.81%
Avg.
%Err.
17.02% 13.30% 8.76%
(13)
a 0.305 0.089 0.123
R
out0
7740 12 260 20 940
Min.
%Err.
0.03% 0.04% 0.13%
Max.
%Err.
51.23% 43.83% 30.04%
Avg.
%Err.
16.90% 14.32% 9.79%
(14)
a 0.004 0.004 0.003
R
out0
7130 11 730 20 000
Min.
%Err.
0.00% 0.00% 0.01%
Max.
%Err.
32.88% 19.79% 9.75%
Avg.
%Err.
9.85% 5.89% 2.67%
are as follows:
R
out
=
R
out0
k +a

k
(12)
R
out
=
R
out0
_
k
2
+ak
(13)
R
out
=
R
out0
k
e
ak
. (14)
Table V presents the results obtained from curve tting for these
models compared with HSPICE simulations.
For modeling crosstalk on neighboring interconnects in VLSI, one
should nd the value of R
out
in coupling situation. When the buffer
of the quiet line, known as victim line, is tied to V
dd
or gnd, the
NMOS or PMOS transistor, respectively, is ON and is operated in
the deep triode region. Therefore, the value of R
out
depends on the
transition of the signal on the quiet line, and new expressions must
be used. The deep triode region resistance is depicted by R
ON
, and
can be expressed as follows:
R
ON_N
=
v
DS
i
D |v
GS
=v
DD
=
v
DS
k
lN
(v
GS
v
TH
)

2 v
DS
=
1
k
lN
(v
DD
v
TH
)

2
(15)
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 8, AUGUST 2013 1571
TABLE VI
R
ONN
AND R
ONP
FOR 90-, 65-, AND 45-nm TECHNOLOGIES
Tech. HSPICE (15) and (16) %Error
R
ON_N
90 nm 2.18 k 3.01 k 38%
65 nm 3.42 k 5.12 k 50%
45 nm 6.17 k 10.20 k 65%
R
ON_P
90 nm 3.50 k 4.82 k 38%
65 nm 5.61 k 8.17 k 46%
45 nm 10.79 k 16.61 k 54%
Fig. 4. Accurate model for CMOS buffer.
R
ON_P
=
v
SD
i
D |v
SG
=v
DD
=
v
SD
k
lP
(v
SG
|v
TH
|)

2
v
SD
=
1
k
lP
(v
DD
|v
TH
|)

2
. (16)
In Table VI we have summarized the results obtained from HSPICE
and analytical expressions for R
ON_N
and R
ON_P
for 90-, 65-, and
45-nm technologies.
IV. MODELING THE OVERSHOOTING EFFECT
Due to the gate-to-drain capacitance of MOS transistors C
gd
, the
input can couple directly to the output. By taking such an inuence
into effect, we reach to an equivalent circuit for the buffer involving
the average output resistors as well, as illustrated in Fig. 4. In this
circuit, the transistors are modeled as switches, which are closed or
open depending on the input ramp, falling or rising for the PMOS and
vice versa for the NMOS. By carefully analyzing the circuit shown
in Fig. 4, we nd that it would result in the output waveform as an
outcome. However, the classic method of nding the transfer function
using the dynamic behavior equation of an inverter derived from KCL
at the output node would be a laborious. Besides, the topology of
the circuit in Fig. 4 varies several times as the input rises or falls.
This leads to a multistatement expression for the output waveform.
On the other hand, the exact times that the circuit topology varies
are also extra parameters, which must be calculated depending on
many characteristics of the circuit. Accordingly, by intuition we have
modeled the output waveform by simple and accurate expressions
[(17) and (18)], which comprised two poles and a zero. These simple
expressions, modeling the overshooting effect, are veried to be in
a good agreement with the HSPICE results. For modeling this fact,
we have assumed that V
out
can be written as (17) and (18) for step
fall and rise inputs, respectively.
As it can be seen from Fig. 5, the effect of zero makes the V
out
fall
down to 40 percent of V
dd
for the CMOS buffer in 90-nm technology.
This phenomenon produces error in estimating the propagation delay.
Fig. 5. Comparison between HSPICE simulation and (17).
Fig. 6. Comparison between HSPICE simulation and (18).
It may also damage the load buffer if it exceeds the breakdown
voltage of MOS in VDSM
V
out,rise
(t ) = V
dd
(1 +k exp(at) (k +1) exp(bt)) (17)
V
out,fall
(t ) = V
dd
(k exp(at) +(k +1) exp(bt)) (18)
where
a =
1 +
C
out
C
gd
R
out
C
gd
, b=
1
R
out
2
(C
out
+C
L
)
, k =
C
out
(C
out
+C
L
+C
gd
)
.
(19)
The parameters a, b, and k are achieved by intuition and curve
tting, simultaneously. Figs. 5 and 6 show the V
out
of the buffer
with C
L
= 1 fF, simulated by HSPICE and calculated using (17)
and (18) for the falling and rising input for the 90-nm technology
node
t
Overshoot
= t
Undershoot
=
1
a b
Ln
_
ak
b (k +1)
_
(20)
V
Overshoot
= V
dd

_
1 +k exp
_
a
b a
Ln
_
ak
b (k +1)
__
(k +1) exp
_
b
b a
Ln
_
ak
b (k +1)
___
(21)
V
Undershoot
= V
dd

_
k exp
_
a
b a
Ln
_
ak
b (k +1)
__
+(k +1) exp
_
b
b a
Ln
_
ak
b (k +1)
___
. (22)
V. CONCLUSION
In this brief, we studied buffer modeling and derived an expression
for minimum-size buffer resistance. In CMOS buffer modeling, we
employed alpha power law expression for MOS devices. HSPICE
simulations showed that using the alpha power model for the MOS
1572 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 8, AUGUST 2013
in buffer leads to very accurate results. This error was less than 2%
for 45-nm process technology. Also a new expression was proposed
for a buffer of k-size relative to the minimum buffer size. The average
error of the proposed model for 45-nm technology was less than 3%,
while with the conventional model error was 10% compared to the
HSPICE simulations. Also a new resistance was introduced for the
buffer that can be used in calculation of crosstalk. Eventually, we
improved our macromodel by taking into account the inuence of
the overshooting effect which was modeled as a zero generated by
the input-to-output coupling capacitance of MOS transistors in the
transfer function of the component.
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