Homework #8A Computer Architecture Exercises Name: ________________________________________________ EE ____ CE ____

MIPS Pipeline Architecture: In each problem, show the instruction data and control line flow. If you make a mistake on a problem, you can recopy the blank form on the next page to start fresh.
Assume $s0 contains 0x3e; $s1 contains 0x1c. The instruction labeled return is 0x20 instructions farther into program memory than the branch instruction (that is, the instruction labeled return has an address that is 0x20 words, or 0x80 bytes, greater than the branch instruction). The program counter reading for the branch instruction is 0x0040 0040. The information given will enable you to fill in all the actual numerical data required in the diagram. NOTE AT THE BOTTOM OF THE DIAGRAM WHETHER THE BRANCH IS TAKEN (circle the correct answer). Remember to highlight the five (5) control lines which are active.

Problem 1: Show data and control flow for bgt $s0,$s1,return.

Problem 2: Show data and control flow for add $t2,$t0,$t1.

Assume that $t0 contains 0x0000 0011 and $t1 contains 0x0000 002c. This will enable you to show the numerical data flow through the pipeline. Remember to highlight the five (5) control lines which are active.

Problem 3: Show data and control flow for bne $t0,$t5,next. Assume $t0 contains 0x11f; $t5 contains 0x11e. The instruction labeled next is 0x10 instructions (or words) farther into program memory than the branch instruction. The program counter reading for the branch instruction is 0x0040 0040. Remember to highlight all active control lines in this instruction.
Assume that $t7 contains 0x00ff 0812 and $t8 contains 0xfe77 4956. This will enable you to show the numerical data values through the pipeline. Remember to highlight the five (5) control lines which are active. Assume that $t1 contains 0x1001 0248, and that the data memory location contains 0x7a61394f. This will enable you to show the numerical data values through the pipeline. Remember to highlight the six (6) control lines which are active.

Problem 4: Show data and control flow for and $t9,$t8,$t7.

Problem 5: Show data and control flow for lw $t0,16($t1).

EE 2310, Homework #8

MIPS R-2000 Pipeline Diagram

Branch Register Write

M U X
+4 ADD

Op Code

Control Decode

Mem/ALU Result

]
Mem. Write Mem. Read

[ [

] ] ]

Register Block
Rs Rt Rd Write D t Read Data 1 Read Data 2

ADD Left Shift 2 ALU Srce. [ [ ] ] ALU ]

Branch dd [ [ [ ] ] ] [

Branch

P C

Instr. Address Instr. Bits

M[ U X
ALU Control

Data Read Address Data Write Data

M U X

Instruction Memory
IF/ID
Instr. Bits

Bits 0-15 Bits 16-20 Bits 11-15

Sign Extend

Fn. Code

[ ] [ [

[ [ ]

Data Memory
]

[ [

] ID/EX [

M ] U ] X
]

ALU Bypass
[ ] MEM/WB [ ]

Reg. Dist

EX/MEM

EE 2310, Homework #8

[0x

Problem 1
]

Branch Register Write

M U X
+4 ADD

Op Code

Control Decode

Mem/ALU

[ [0x ] ADD Left [0x ]

ALU Srce.

]
Mem. Write

[$ [$

] ]

Register Block
Rs Rt Rd Read Data 1

Shift

Branch dd [ ] ] [

Branch ]

Mem. Read

P C
[0x

Instr. Address Instr. Bits 0-31

[0x [0x ]

] ALU

Read Write Data 2 D t Sign Bits 0-15 Extend Bits 16-20

M [0x U X
ALU Control

Data Read Address Data Write Data

M U X

Instruction Memory
IF/ID
Instr. Bits 0-31

Fn. Code

[0x20]

Data Memory ALU Bypass

EX/MEM MEM/WB

Bits 11-15

M U X
ID/EX

ALU Op.

Reg. Dist

The branch is / is not

taken.

bgt $s0,$s1,return

EE 2310, Homework #8

Problem 2

Branch Register Write

M U X
+4 ADD

Op Code

Control Decode

Mem/ALU R l

[$ [$

] ] ]

Register Block
Rs Rt Rd Read Data 1

Left Shift 2 ALU Srce.

ADD

Mem. Write

Branch dd

Branch

Mem. Read

P C

Instr. Address Instr. Bits 0-31

[$

[0x [0x

Read Data 2 Write D t

M [0x U X
Fn. Code ALU Control

ALU ] [0x ]

Data Read Address Data Write Data

M U X

Instruction Memory
IF/ID
Instr. Bits 0-31

Sign Bits 0-15 Extend Bits 16-20 Bits 11-15

[0x [$ ]

Data Memory
]

[$

] ID/EX [

[$ 0x

M U ] X Reg. Dist
]

ALU Bypass
[$ ] [$ ] MEM/WB

EX/MEM

add $t2,$t0,$t1

EE 2310, Homework #8

[0x

Problem 3
]

Branch Register Write

M U X
+4 ADD

Op Code

Control Decode

Mem/ALU

[ [0x ]
Left [0x Shift

]
Mem. Write

lt

[$ ] [$ ]

Register Block
Rs Rt Rd Read Data 1

ADD ]

Branch dd [ ]

Branch ]

Mem. Read

[0x

ALU Srce.

P C
[0x

Instr. Address Instr. Bits 0-31

[0x ]

] ALU ]

Read [0x Write Data 2 D t Sign Extend

M [0x U X
Fn. Code ALU Control

Data Read Address Data Write Data

M U X

Instruction Memory
IF/ID
Instr. Bits 0-31

Bits 0-15

[0x

Data Memory ALU Bypass

EX/MEM MEM/WB

Bits 16-20 Bits 11-15

M U X
ID/EX

ALU Op.

Reg. Dist

The branch is / is not taken.

bne $t0,$t5,next

EE 2310, Homework #8

Problem 4.

Branch Register Write

M U X
+4 ADD

Op Code

Control Decode

Mem/ALU R l

[$ ] [$ ]

Register Block
Rs Rt Rd Read Data 1

Left Shift 2 ALU Srce.

ADD

Mem. Write

Branch dd

Branch

Mem. Read

P C

Instr. Address Instr. Bits 0-31

[$

[0x [0x

Read Data 2 Write D t

M [0x U X
Fn. Code

ALU ] [0x ]

Data Read Address Data Write Data

M U X

Instruction Memory
IF/ID
Instr. Bits 0-31

Bits 0-15 Bits 16-20 Bits 11-15

Sign Extend

ALU Control

[0x [$ ]

Data Memory

[ $

] ID/EX [0x

[$

M U ] X Reg. Dist
]

ALU Bypass
[$ ] MEM/WB [$ ]

EX/MEM

and $t9,$t8,$t7

EE 2310, Homework #8

Problem 5:

Branch Register Write

M U X
+4 ADD

Op Code

Control Decode

Mem/ALU Result

[$ [$

Rs

Register Block
Read Data 1 Read Data 2

P C

Instr. Address Instr. Bits

Rt

ADD Left Shift 2 ALU Srce. [0x ] ALU [0x

Mem. Write

Branch dd

Branch

Mem. Read

[0x
Data Read Address Data

[$

Rd Write D t

M [0x ]U X
ALU Control

[0x

]
Write Data

M U X

Instruction Memory
IF/ID
Instr. Bits

Bits 0-15 Bits 16-20 Bits 11-15

Sign Extend

Fn. Code

Data Memory
[$ ]

[$

] ID/EX

[$

M ] U X

ALU Bypass
[$ ] MEM/WB [$ ]

Reg. Dist

EX/MEM

[0x

lw $t0,16($t1)

EE 2310, Homework #8

Problem 6

In the forwarding unit above, if Read Data 1 is from $t0 and the data on the ALU bypass bus is from the instruction add $t0,$t1,$t2, show the data flow that results in the correct register data arriving at the upper ALU data input.

EE 2310, Homework #8

Problem 7

Assume you want to add a branch history unit to the pipeline to improve branch prediction. Draw it as a box affixed to the pipeline stage where it would go, and show a circuit connection to the stage where the branch history data is directed.