Refresher course in transistor

circuits
Dr N Harris
School of Electronics and Computer Science
(Based on notes by Dr Neil Ross for ELEC2012
And me for ELEC1005 if you want more detail)
Course Contents and Aims
Brief Revision of Bipolar Transistors
Brief Revision of Field Effect Transistors
Common configurations
Biasing
Small signal analysis
Useful analog techniques
Differential amplifer
Current mirrors
Active loads
Op Amps (whats in them)
Multipliers
Assignment
Aim: To refresh your understanding of transistors and basic uses,
and how to simulate circuits
The aim is to understand things like this
You will require Spice to do the
assignment
Spice is a circuit simulation package
Available from many different sources
A good free one is available from Linear
Technology
Its called LTSpice
Get it from here
http://www.linear.com/designtools/software/
Other Spice is available on departmental computers eg
Orcad/Cadence
Bipolar transistors
C
B
E
C
B
E
n
p
n
p
n
p
Familiar?
But what is really happening inside?
Lets try and find out!
Notice that the construction of the
transistor looks like 2 diodes back to
back.
Its made of n and p doped silicon.
We start by looking at a pn diode:-
Ideal PN Diode
Defined by the diode equation
|
|

\
|
= 1
kT
V
q
S
e I I
Is is called the saturation current of the diode.
V is the applied voltage
q is the charge on an electron - 1.6 x10
-19
C
k is the Boltzmann constant 1.38 x 10
-23
J/K
T is the absolute temperature
|
|

\
|
= 1
kT
V
q
S
e I I
kT/q = 25.3mV @ 20 degrees C
= 25.8mV @ 27 degrees C
Often a value of 25mV is assumed for
numerical convenience
I
s
itself is very temperature dependant
A typical value for I
s
is 10
-14
A at room temperature.
Diode Curve
1mA
2mA
0.64V
50mV
10
-14
A
I
V
|
|

\
|
= 1
kT
V
q
S
e I I
The slope at any point represents a conductance,
(1/R). As the slope varies, we term this a dynamic
conductance. The inverse of this is a dynamic resistance
A bit about Notation
Large Signal (DC)
Capital letters eg I
C
DC collector current
Small Signal (AC)
Lower case letters eg i
c
AC collector current
Instantaneous total signal
Combination eg I
c
Useful as transistor circuits are analysed in
2 chunks
Bipolar Transistors - definitions
N N P
i
E
i
B
i
C
Emitter
Collector
Base
P P N
i
E
i
B
i
C
Emitter
Collector
Base
B
C
E
v
BC
v
BE v
BE
i
C
i
B
i
B
i
E
v
BC
C
E
B
i
C
i
E
NPN
PNP
N N P
i
E
i
B
i
C
Emitter
Collector
Base
P P N
i
E
i
B
i
C
Emitter
Collector
Base
B
C
E
v
BC
v
BE v
BE
i
C
i
B
i
B
i
E
v
BC
C
E
B
i
C
i
E
NPN
PNP
Direction of
Conventional
Current (holes)
(Electrons go
The other way)
Bipolar Transistors - definitions
Main points to remember
The transistor can be thought
of a current source. The
collector current is
independent of
collector-base voltage
The emitter current is
controlled by the
base-emitter voltage
The emitter current and the
collector current are nearly the
same (base current small)
Collector current is therefore
controlled by the base-emitter
voltage
So what?
+
+
R
Add a load resistor
A small voltage change Vi between emitter and base causes a current change
I
E
. If all this current passes to the collector, then the output voltage changes
by I
E
.R. Basically it is controlled by R (within reason!)
Specifically, A=Vo/Vi=(R I
E)
/(r I
E
)=R/r where r is the dynamic resistance of the
base-emitter junction and is usually low (1000s of ohms), but sadly, as its dynamic,
changes its value with applied voltage (so not linear)
E
B
C
P
N
P
Transistor
This is the basis of transistor action.
Power gain has been achieved as the
voltage is increased although the current
hasnt changed much.(VI is bigger)
Current in the low resistance input circuit
has been transferred to the high
resistance output circuit.
Transistor= transfer resistor

However, not all the current gets from the

emitter to the collector. Some is lost in the base due to
recombination. is the fraction of the emitter current reaching the
collector. Usually quite close to 1
I
E
I
C
I
B
+
+
EB junction CB junction
Reverse bias Forward bias

Conventional current

relates to the fraction that is lost.

can be a large number and is very useful
I
E
I
C
I
B
+
+
EB junction CB junction
Reverse bias Forward bias

P
P
N
What about a NPN device?
Best considered with Electron Current (go the other way to conventional current - holes)
I
E
I
C
I
B
+ +
BE junction CB junction
Reverse bias Forward bias

N
P
N
The bias potentials are the other way round, and the flow shows the
majority carriers (in this case electrons)
What about a NPN device?
Now considered with Conventional Current (holes)
I
E
I
C
I
B
+ +
BE junction CB junction
Reverse bias Forward bias

N
P
N
Can be considered that I
C
and I
B
go in and add up to I
E
Can be thought of as a current controlled
valve
Base current can be used to program a
collector current
The fraction of the emitter current flowing
in the collector is called the alpha () of
the transistor
is called the common base current gain
< 1, but 1- <<1 eg =0.99
E C
i i =

C
E
i
i =
A bit more on Beta
from Kirchoff
C
C
C E C B
E C B
i
i
i i i i
i i i

\
|

=
+ = =
= + +

1
0
Therefore

=
1
B
C
i
i
Which is sometimes called h
fe
Beta (cont)
Note also that

+
=
1
Beta is called the common emitter current gain
It is one of the main manifestations of gain in the transistor.
Eg if =0.99, beta=0.99/(1-0.99)=99
For every microamp of base current,
we get 99 microamps of collector current
It is a current amplifier
i
C
=i
B
Very Important!
Common Emitter cct-Base circuit
I
B
V
BE
(A)
10
20
30
0.5 1
V
CE
>1V
B
E
v
BE
i
C
i
B
i
E
C
V
BE
V
CE
R
L
Lets wire up a transistor and have a look.
We have an input circuit (base) and an output circuit (collector)
with a common emitter. The input looks like a diode (as expected)
Emitter circuit
I
C
1
2
3
4
1 2 3 4 5
V
CE
mA
i
B
=10A
i
B
=20A
i
B
=30A
i
B
=40A
Active Region
Saturation Region
B
E
v
BE
i
C
i
B
i
E
C
V
BE
V
CE
R
L
The output looks like a
constant current source,
but dependent on ib
(Remember transistor action)
Current gain (or
F
)
Maximum value of is at 10-20 mA for discrete transistors
and 0.05-0.5 mA for IC transistors
I
C
1
2
3
4
1 2 3 4 5
V
CE
mA
i
B
=10A
i
B
=20A
i
B
=30A
i
B
=40A
Active Region
Saturation Region
The Early voltage
V
ea
Collector voltage has a small effect on collector
current. Width of Base reduces, collector current
increases (V
ea
~70V).
Transistor characteristics
Notice non-linearity with input voltage
Generic FET operation
The generic FET can be considered to be a semiconducting material
with a connection at either end (Drain and Source), with its
resistance modulated by the electric field applied perpendicularly at
the gate.
It can also be considered as a long PN junction, with lateral
conduction, so the depletion zone increases as you cross the device
N
S D
Field
P
V
Depletion Zone
Types of Field Effect Transistors
Junction Field Effect transistor (JFET)
Important in historical development
Not used much these days
Metal Oxide Semiconductor FET (MOSFET)
Mostly used for logic circuits
Also used for power circuits (Power MOSFET)
Increasingly used for Analogue IC design in
CMOS processes along with Digital IC
FET operation
In both the JFET and MOSFET, the
operation is basically the same.
The number of carriers in a conducting
channel is controlled by a lateral gate
The details of operation are quite different
in both cases but they are both
operating effectively as variable resistors
MOSFET structure
Consider an n-channel device:
N+ N+
P
Polysilicon
Oxide
B
S
G
D
Channel
D
S
G
B
D
S
G
B
D
S
G
B
D
S
G
B
N depletion
N enhancement
P depletion P enhancement
MOSFET Schematic Symbols
Notes on MOSFETs
The MOSFET is a 4 terminal device, not
three.
For discrete devices, the substrate (B) is
normally connected to the source to
effectively give a three terminal device
MOSFETs can be of two forms:
depletion : conducting when VGS=0
enhancement : non-conducting when VGS=0
I
D
V
DS
Region 1
Region 2
V
GS
increasing
V
T
+1
V
T
+2
V
T
+3
V
T
+4
DC characteristics of FETs
Fortunately, we can use the same basic
model for both types of device.
n-channel device
Note: for depletion device: V
T
< 0
for enhancement device: V
T
> 0
Saturation region
Linear region
I
C
1
2
3
4
1 2 3 4 5
V
CE
mA
i
B
=10A
i
B
=20A
i
B
=30A
i
B
=40A
Active Region
Saturation Region
Compare with bipolar
I
D
V
GS
Region 2
i.e. V
DS
large
V
TD
V
TE
Depletion Device
JFET or MOSFET
Enhancement MOST
only
VT is the threshold voltage.
The voltage at which the device
starts to conduct
FET Input Curves they are quadratic, not exponential
I
C
V
CE
I
B
increasing
I
C
V
BE
V
CE
large
Compare with bipolar
DC Characteristics of FETS
Region (1) is much smaller in bipolar
device (<0.3V)
Usual parameter is IB in bipolar, VGS on
FETS, but note that it could equally be VBE
on bipolar (rough equivalence)
Bipolar IC vs VBE characteristic is
exponential and very steep. FET is quadratic
and much less steep. This means that the
gain of the FET is MUCH less than bipolar
DC Characteristics of FETS
Bipolar is an enhancement type device (in
FET terms)
Negligible gate current flows for FETS
Note different terminology for saturation
for the two types of device
Mathematical Description
In region (2), beyond pinchoff,
This is only valid for V
GS
-V
T
0 ie V
GS
V
T
Also only valid for V
DS
V
GS
-V
T
ie region 2
Notice that we have two parameters to
describe the FET, K and V
T
.
( )
2
2
T GS D
V V
K
I =
V
DS
Region 1
Region 2
V
GS
increasing
V
T
+1
V
T
+2
V
T
+3
V
T
+4
V
DS
Region 1
Region 2
V
GS
increasing
V
T
+1
V
T
+2
V
T
+3
V
T
+4
Mathematical Description
V
T
is called the threshold voltage
K has the dimensions A/V
2
and is called
the device constant or beta of the device.
For the MOSFET the parameter is called KP
For a JFET the parameter is called BETA
We avoid using the term beta in this
context to remove the possibility of
confusion with bipolar.
Mathematical Description
In region (1), we have a different
equation
K and V
T
are the same as before.
We still have the restriction V
GS
-V
T
0
This time the restriction on V
DS
is 0 V
DS
V
GS
-V
T
( )
|

\
|
=
2
.
DS
T GS DS D
V
V V V K I
V
DS
Region 1
Region 2
V
GS
increasing
V
T
+1
V
T
+2
V
T
+3
V
T
+4
V
DS
Region 1
Region 2
V
GS
increasing
V
T
+1
V
T
+2
V
T
+3
V
T
+4
Basic transistor circuits
Emitter is common to
input and output
Basic transistor circuits
Collector is common
to input and output
Basic transistor circuits
Base is common to
input and output
Consider the Common Emitter configuration -
Transfer Function for DC
v
BE
i
C
i
B
V
CE
=Vout
R
L
v
S
R
S
V
CC
v
out
v
in
v
B
0.6V
S
R
L
R
Slope =
Example using Pspice
So how do we use this as an amplifier?
The Problem
We want to amplify a small signal
We cannot apply it direct to our amplifier
Why?
R
L
v
in
R
S
v
out
v
out
v
in
v
B
Applying an AC signal results in different outputs
Depending on bias (or offset)
Input signals
Output signals
Basic Biassing
For AC we can couple through a capacitor
R
L
v
in
v
out
R
B
C
L C CC OUT
B C
B
BE CC
B
R I V V
I I
R
V V
I
=
=

Let V
in
= 0
Now apply V
in
Transistor is already in the active region
A small bias current always flows through RB
Simple bias circuit more detail
Assume V
BE
= 0.6 V
B
C
B
C
CC out
C
B
CC
CC C CQ CC out
BQ CQ
B
CC
BQ
B B CC
R
R
R
R
V V
R
R
V
V R I V V
I I
R
V
I
R I V

6 . 0 1
6 . 0
6 . 0
6 . 0
+
|
|

\
|
=
|
|

\
|

= =
=

=
+ =
Q-point depends on the value of - not very good!
R
L
v
in
v
out
R
B
C
Simple bias circuit
=100 =50
Traditional Preferred Bias Technique
(Emitter biasing)
R
1
and R
2
form a potential divider providing a fixed V
B
V
B
becomes V
BE
+I
E
R
E
R
E
provides a form of negative feedback. As I
E
increases, I
E
R
E
increases,
and V
BE
falls, which results in I
E
R
E
falling as well
DC Analysis (Quiescent Point)
1) Replace R
1
and R
2
by the Thevenin equivalent
R
L
C
C2
V
CC
R
E
R
TH
V
TH
V
OUT
R
TH
=R
1
//R
2
And V
TH
=V
CC
R
2
/(R
1
+R
2
)
TH
B TH
B
R
V V
I

=
We also make the assumption
( )
( ) ( )
( )
( )
( )
E
BE TH
E TH
BE TH
B C
E TH
BE TH
B
BE TH E TH B
E B B TH TH BE
TH B TH B
R
V V
R R
V V
I I
R R
V V
I
V V R R I
R I I R V V
R I V V

+ +

= =
+ +

=
= + +
+ =
=

1
1
1
1
TH
B TH
B
R
V V
I

=
From
BE E B
V V V = From
Small compared with
Hence I
C
is largely independent of
|
|

\
|

=
B
CC
C
R
V
I
6 . 0

Compared to simple method

Improved bias circuit
Improved bias circuit
=100 =50
Small signal Models
Having biased the transistor, we need to know the gain for our signals
of interest.
Small signal model is used. It only works for small signals, as the
small signal model assumes a straight line fit to the transistor curves
i.e it is linearised around the operating point.
Small signal analysis is very important, particularly for designing and
understanding IC design techniques.
Its all about trying to make a non-linear expression linear.
This makes analysing it much easier as we can use the common and
well known techniques of network theory, such as superposition, and
Norton and Thevenin theorems.
Transistor Curves (What is the gain for a small signal?)
v
BE
i
B
V
BE
Slope=
1/r
v
BE
i
C
V
BE
Slope=g
m
Base
Collector
B C
I I =
Remember
We assume a straight line at
the Q point, as shown.
The output current looks like
as shown in the second graph
We can see why there is no gain for low iB. A large variation in VBE
produces very little variation in iC.
kT
qv
S C
BE
e I i =
BE
C
dv
di
Now
And the slope is given by
v
BE
i
C
V
BE
Slope=g
m
But we know that we are operating at the quiescent point
so we set the ac or small signal to zero as
c C C
i I i + =
and i
c
=0, therefore i
C
=I
C
Note that gm is different depending on where you are on the curve.
We need the slope at the operating point
Total current = DC + AC
And so the top equation applies
So
kT
qI
e I
kT
q
dv
e dI
dv
di
C
kT
qV
S
I i
BE
kT
qv
S
I i
BE
C
BE
C c
BE
C c
= = =
=
=
Because
kT
qV
S C
BE
e I I =
This is the slope at the Q point and is therefore the mutual conductance
m
C
g
kT
qI
=
Basically the diode equation
This is the definition of DC current
Note only dependent on DC conditions
Refer back to the base
B C
I I =
Remembering Therefore the input slope is
r
g
kT
qI
slope
m C
1 1
= = =

v
BE
i
B
V
BE
Slope=
1/r
Giving the input resistance r as

r
g
r
m
= =
Basic Hybrid PI Model
b
c
g
m
v
be
e
r
p
m
C
m
g
r
q
kT
I
g

=
=
Basis of small signal analysis ignores the DC conditions
Note that small in this case means less than 25mV
It is the same as this -

b
c
h
fe
i
b
e
r
p
i
b
b b m be m
be b
i i r g v g
v r i

=

fe
h
The difference is that in this case,
the output makes use of a current
dependent generator rather than a
voltage dependent one.
Small Signal FET model
In region (2), FETS behave like a voltage
controlled current source, just like a bipolar.
Therefore we can use the same small signal
equivalent circuit:
g
m
v
gs
v
g
g
d
s
Note that because there is no gate
Current, r

disappears
Gm is much lower in FETs
High frequency Hybrid model
R
x
is the spreading resistance (~150)
The capacitances lead to non-ideal performance (high frequency
limitations)
Application of the Small signal model
Consider our simple common emitter cct with
simple biasing
What is the small signal gain?
V
CC
=5
R
B
=820Kohm
R
C
=2.2Kohm
=200
V
BE
=0.6V
Common Emitter Amplifier
Determine the DC bias condition
( )
V
R
V V R
V
R I V V
mA
R
V V
I
A
R
V V
I
B
BE CC C
CC
C B CC C
B
BE CC
C
B
BE CC
B
64 . 2
36 . 2 5
07 . 1
36 . 5
=
=

=
=
=
|
|

\
|

=
=

V
CC
=5
R
B
=820Kohm
R
C
=2.2Kohm
=200
V
BE
=0.6V
Calculate the components in the
hybrid pi model
k
g
r
mS
q
kT
I
g
m
C
m
65 . 4
43
25
07 . 1
= =
= = =

Now draw small signal equivalent circuit

Power supplies s/c
at signal frequency.
We are performing a
superposition analysis
so suppress all sources
except the one we are
interested in. Voltage
sources go short circuit
Coupling Capacitor
Coupling Capacitor
Make it look better
Get rid of capacitors!
C s m
C be m o
R v g
R v g v
=
=
6 . 94 =
= =
C m
S
o
V
R g
v
v
A
( )
C L
L C
m
s
l
C L be m l
R R
R R
g
v
v
R R v g v
+
=
=
With R
L
disconnected, v
l
=-g
m
R
C
v
s
What happens if we add a load
Bias conditions unaffected
C s m
C be m o
R v g
R v g v
=
=
6 . 94 =
= =
C m
S
o
V
R g
v
v
A
Let R
L
be 10Kohm
R
L
L C s m
L C be m o
R R v g
R R v g v
=
=
77 =
= =
L C m
S
o
V
R R g
v
v
A
Gain is reduced.
Loading effects of amplifiers are important as we shall see
Summary
We know the importance of biassing the transistor
Having biased the transistor, we need to know the gain for our signals
of interest.
Small signal model is used. It only works for small signals, as the
small signal model assumes a straight line fit to the transistor curves
i.e it is linearised around the operating point
We have looked at small signals as applied to the basic biassing circuit
and we have seen that it becomes easy to calculate the gain for small
(<25mV) signals, even when extra loads are added.
All we need to know is the quiescent collector current (I
C
)
Then we can calculate r

and g
m
, and this is all we need for calculation
Trouble is, the basic biassing circuit is not very good.
We want a better biassing technique. This is emitter biassing
What effect does RE have on the gain? A small signal circuit should help us
analyse this circuit easily.
Small Signal Equivalent Circuit
m
C
m
g
r
q
kT
I
g

=
=
Power supply is grounded for signals
We can replace the bias resistors R
1
and R
2
with R
TH

C be m out
R v g v =
But we need to establish v
be
We can see instantly that
This is not so obvious as R
E
is in both the input and output
loop
We notice that the current through R
E
comprises
of an element from the input circuit (i
b
) and g
m
v
be
, and
that the input circuit current is equivalent of v
be
/r

Defining 1/r

as g

,we can see that

( )
( )
( )
( )
E m
in C m
out
E m
in
be
E m be be E be in
E E m be
R g g
v R g
v
R g g
v
v
R g g v v v v v
v R g g v

+ +

=
+ +
=
+ + = + =
= +
1
1
C be m out
R v g v =
As
E
C
in
out
m E m
R
R
v
v
then g g and R g

>> >>

1
But if
( )
E m
in C m
out
R g g
v R g
v

+ +

=
1
Hence we do not get the gain we want (-g
m
R
C
) but a much lower gain, -R
C
/R
E
Therefore
How can we get gain but use the
better biasing?
Separate the DC and the AC circuit
performance
Think of a way to eliminate the emitter
resistor at signal frequencies
Use a capacitor in parallel to the emitter
resistor!
Bypassed Emitter Resistor
Capacitor
Worked example
2k
C
C2
V
CC
=6
1k
40k
20k
C
C1
V
IN
V
OUT
C
E
=100
V
BE
=0.7
What is the voltage gain of this circuit, with and without C
E
First calculate I
Q
( )
mA 14 . 1
101 3 . 13
7 . 0 2 100
=
+

= =
k k
I I
C Q
( )
( )
E TH
BE TH
B C
R R
V V
I I

+ +

= =
1
2k
C
C2
V
CC
=6
1k
40k
20k
C
C1
V
IN
V
OUT
C
E
=100
V
BE
=0.7
For the input circuit, V
TH
=2V and R
TH
=40k//20k=13.3kohm
Therefore
From
( ) V k mA V
CQ
7 . 3 2 14 . 1 6 = =
Calculate g
m
and R
pi
k
g
r
mS
q
kT
I
g
m
C
m
2 . 2
10 46
100
46
10 25
10 14 . 1
3
3
3
=

= =
=

= =

( ) ( )
94 . 1
1 46 . 0 46 1
2 46
1
=
+ +

=
+ +

=
k mS mS
k mS
R g g
R g
v
v
E m
C m
in
out

With emitter resistor

(no capacitor)
Low gain
Include C
E
2k
C
C2
V
CC
=6
1k
40k
20k
C
C1
V
IN
V
OUT
C
E
=100
V
BE
=0.7
When we include C
E
, we can see that intuitively R
E
tends towards zero as the capacitor acts as a short circuit
92 = =
C m
in
out
R g
v
v
Therefore
Common emitter amplifier
C1 and C2 are for AC coupling (DC blocking)
C
E
decouples the emitter (i.e low impedance to
ground for AC signals)
The above are usually assumed to be open circuit
for DC analysis
Small signal analysis determines gain, bandwidth
etc.
So now we know what all the bits do!
Mid-band frequency response
In mid-band, gain is independent of frequency
Coupling capacitors have negligible impedance
Internal capacitances are not significant
1. Coupling and de-coupling capacitors become
short circuit
2. Internal capacitances are ignored
3. DC supplies replaced with short circuits
Input and output impedances
for a CE Amplifier
The input impedance, Rin, is the impedance seen looking into the input terminals
i.e. the ratio of input voltage to input current.
It is r

for a CE amplifier
The output impedance, Rout, is the Norton or Thevenin impedance of the output
circuit.
Using the hybrid model, the output circuit is a Norton equivalent (current source
in parallel with a resistance). In the simplified model the current source is treated as
ideal and so has infinite output impedance, thus R
L
is the only resistance seen.
It is R
L
for a CE amplifier
Now lets look at the Emitter follower, or
common collector
Circuit Small signal equivalent
i
Notice the introduction of r0,
the output impedance of the
transistor
Analysis of emitter follower
E b b b
E b b
i
o
m
b i E m b o b
R i i r i
R i i
V
V
r g
V r i V R V g i V r i V
) (
) (
) (
, ) ( ,

+ +
+
=
=
+ = + = =
E
E
i
o
R r
R
V
V
) 1 (
) 1 (

+ +
+
=
1
) 1 ( If

>> +
i
o
E
V
V
r R

Ro is neglected
Input and output impedances
b
E b b
b
i
in
i
R i r i
i
V
Z
) 1 (

+ +
= =
E in
R r Z ) 1 (

+ + =
2 1
2 1
'
'
'
'
' '
,
with parallel in is , impedance, input Actual
R R
R R
R
R Z
R Z
Z
R Z Z
in
in
in
in in
+
=
+
=
Input and output impedances
) 1 ( ) 1 (
) 1 (
) 1 (
) 1 (
gives g Rearrangin
) 1 ( ) 1 ( ,
) 1 (
) 1 (
circuit) short (Output
circuit) open (Output

+ +
+
=
+ +
+
=
|
|

\
|
+ = + =
+
= + =
= =
i E
E i
out
E
E i
oc
oc i
E E oc
i
sc
sc
oc
o
o
out
V
r
R r
R V
Z
R r
R V
V
r
V V
R iR V
r
V
i i
i
V
i
V
Z

+ +
=
1 ) 1 (
r
R r
r R
Z
E
E
out
Summary of emitter follower
Voltage gain equals 1 (if is large)
Current gain is
Input impedance is large
Output impedance is small
E
E
i
o
R r
R
V
V
) 1 (
) 1 (

+ +
+
=
E in
R r Z ) 1 (

+ + =

+ +
=
1 ) 1 (
r
R r
r R
Z
E
E
out
Comparison of CC with CE
Things to think about
Although the basic configurations give us
some useful amplifiers, they are not ideal
Major drawbacks include
Cannot accept DC signals due to coupling
capacitors
Biasing resistors lead to low input impedance
Necessary improvements
We would like to have a high gain amplifier that
can operate at DC
We would like a high input impedance to avoid
loading effects
We would like to integrate these features into a
single chip
Big resistors dont integrate well
Integrated transistors can be well matched (vital for
DC systems)
This leads us to the Op-Amp
What do we need for an Op-Amp
Very high input impedance (virtual earth)
Very low output resistance (no loading)
Very high voltage gain (so we can apply
feedback)
Very wide bandwidth, including DC
Vout = 0 when V1=V2 irrespective of the
magnitude of V1(flexible input conditions)
(Equivalent of saying Vout=0 when Vin=0)
So whats in an Op Amp
Differential input stage
Voltage gain stage
Output stage
All DC coupled
How to operate at DC
We cant have coupling capacitors
Direct coupling
We introduced these to allow biasing
resistors
However, direct connection will give us
biassing issues
Alternative way of biassing
We need to provide a finite I
C
We did this by pushing a known I
B
into the
transistor
We could just pull a known current through the
collector
By placing a current source in the emitter
Unfortunately this stops the transistor amplifying
as it now has a constant current flowing though
it
Transistor action requires the collector current to be
varied by the transistor now not possible!
Think about this a bit more
A ideal current source has infinite
resistance
A practical current source has a large, but
finite resistance
In terms of AC (small signal), a current
source will appear as this resistance
We could use this feature to make a
large resistor for AC
Therefore, care has to be taken in the
assumptions made when modelling.
Going back to our example
In terms of gain, the CE amplifier has a
value of -R
C
/R
E
In this case R
E
is infinite
Therefore the gain tends to zero
Even if we include a non-infinite
resistance, the gain is still nearly zero
If we swap R
C
and I over, the gain gets
very large in principle (more later)
Lets persevere with this
arrangement.as it has some advantages
We can solve this problem by introducing a
second transistor in a parallel arrangement to
the first
Now we have scope to allow the collector
currents to vary as when one goes down, the
other can go up to compensate, thus still
allowing a constant I
E
It is constrained by the fact that the two collector
currents must add up to the value of the emitter
current source
Long tailed pair (LTP)
Current source may
be replaced by a resistor
A very useful basic amplifier stage.
The gain block used in most
analogue ICs
When both inputs change levels
together common mode signal
Amplifies difference between input
levels
Transistors must be matched, i.e.
have the same parameter values,
etc.
Long tailed pair
The differential input voltage is given by
2 1 B B din
V V v =
The common mode input voltage is given by
( ) 2 /
2 1 B B cin
V V V + =
If the transistors are well matched
C C CC C
E C C C
R I V V
I I I I
=
= = =
and
2
2 1
This is the average offset voltage of the input.
From the diagram above
The effective DC input
is the V
BE
of each transistor
which is the average of the
total input.
Superimposed on top of
this is the differential input
Simulated response
I am sweeping V1 whilst holding V3 constant
This is the large signal response.
Notice the non-linearity.
Notice the input voltage range is low
Small signal analysis
r

g v
m 1
g v
m
2
R
C
R
C
R
E
v
b1
v
b2
v
c1
v
c2
v
e
v
v
1
2
Assume that the emitter current source has a dynamic
resistance of R
E
(could be a resistor of this value).
LTP analysis
2 2
2 1 2 1
2 1 2 1
c c
cout
b b
cin
c c dout b b din
v v
v
v v
v
v v v v v v
+
=
+
=
= =
For a pure differential signal, v
b1
= -v
b2
therefore v
e
=0 (half way between
the 2 input potentials)
For a pure differential signal, the increase in current in Q
1
equals the
decrease of current in Q
2
. Hence, there is no change in emitter voltage,
v
e
= 0 as no overall change in current
Thus the emitter point is at ground potential (for small signal
analysis) and the two halves of the amplifier can be
considered separately and R
E
can be ignored
r

g v
m 1
g v
m 2
R
C
R
C
R
E
v
b1
v
b2
v
c1
v
c2
v
e
v
v
1
2
LTP analysis
The gain of each transistor is just -g
m
R
C
and for a
pure differential signal:
din C m
b C m b C m
c c dout
v R g
v R g v R g
v v v
=
+ =
=
2 1
2 1
Thus the differential voltage gain is given by
C m
din
dout
d
R g
v
v
A = =
LTP common mode input
For pure common mode input v
b1
=v
b2
, and by symmetry v
c1
=v
c2
.
The two transistors are in parallel and can be considered as one device with
forward transconductance 2g
m
and input resistance r

( is unchanged),
with the collector resistor halved as they are in parallel.
If >>1, so g
m
>>g

E
C
C
R
R
A
2
1

With no loss of generality we can imagine the bases and collectors joined.
(No current will flow, they are at the same potential).
Hence, for pure common mode signal, the circuit behaves
like a CE stage with unbypassed emitter resistor R
E
.
( )
E m
C
m
C
in
out
R g g
R
g
A
v
v

2 2 1
2
2
+ +

= =
r

g v
m 1
g v
m 2
R
C
R
C
R
E
v
b1
v
b2
v
c1
v
c2
v
e
v
v
1
2
( )
amplifier CE for the
1
From
E m
in C m
out
R g g
v R g
v

+ +

=
Summary of the LTP
It provides a differential input (and output if required)
with a large differential gain and small common mode
gain.
If the transistors are well matched, changes in V
BE
due
to temperature appear as a common mode voltage.
Hence the amplification of thermally induced voltages is
small. This makes the LTP suitable as a DC amplifier.
Can be implemented in 2 ways..
Ones uses NPN and the other uses PNP.
Both give effectively the same result
Note the difference output
is the same
So how do we generate
our current source?
CURRENT MIRRORS
These are useful building block circuits. The idea is that a current is
supplied to the input of the mirror and an identical current flows in the output
circuit, irrespective of the secondary voltage.
In an extension of this concept current mirrors may be designed that provide
an output current which is a multiple of the input current.
Current mirrors are useful for biassing, and creating large dynamic
impedances.
The simple current mirror
in
i
o
i
Q
Q
1 2
Assume the transistors are
identical. Since the base emitter
voltages are the same
2 1 C C
I I =
hence,
in o
I I =
Current mirrors
Q1 is connected as a diode
Q1 and Q2 are matched ~ almost identical device
properties
is large

+
=
2
i
O
I
I
1 1
2

(2+)

i o
I I
Several transistors may be used to give several independent
current sources. Their values will be equal if the transistors are
identical.
Ratios other than unity may be obtained by varying the area of the
transistors.
It is the current density which is determined by V
BE
. Hence the
current in each transistor is proportional to its area
One current mirror may have several outputs with different current
ratios. Useful for setting bias currents.
in
i
o1
i
Q
Q
1
2
o2
i
3
Q
Improved current mirror
1
1

+
+ +
=
+
+ =
1
2
1
2
2
i
i
I
I
( )
1
2
1
2

+ +
+
=


i
o
I
I
(

+ 1
2
( )

+
=
+ =
1
2
1 2
b
b
i
i
Wilson current mirror
1 1

2+
(

+
+

1
2

+
+
=
|
|

\
|
+
+
+ =
1
2
1
2
2
o
i
I
I
2 2
2
2
2
+ +
+
=


i
o
I
I
Improved current ratio
Improved output impedance
Q2 (diode) adds feedback
The Active Load
The voltage gain of a simple CE amplifier depends on the g
m
of the
transistor and the collector load resistance.
To increase the gain it is necessary to increase g
m
(increase the current)
or increase R
C
. The maximum value of the product of the collector current
and the load resistance is clearly limited by the supply voltage.
One way to avoid the restriction is to use a current source, as we have
seen that these have large dynamic output impedance (R
C
).
When considering very high load resistances, we also need to remember
that the collector characteristics of a CE amplifier are also that of a
current source ie very high. Its value is related to the Early voltage ie the
slope of the I
C
/V
CE
characteristic in the active area
The gain is given by
The maximum gain is now limited by the
output resistance of the transistor.
( )
C o m V
R r g A // =
C
i
Q
Vcc
LTP with active load
A current mirror is often used to provide
an active load for a long tailed pair, and
convert the differential output to single
ended.
The active load
1) increases the single ended gain for
differential input
2) reduces the single ended output for
common mode input (improves CMRR)
Note this is the other way up
Compares to 741. Makes overall
biassing easier
The other side of the current mirror
is a diode. This has a low dynamic
impedance. We cannot just use current
sources because the collector current
on one side needs to vary. Decreasing the input to
Q1 results in a decrease in current through diode
Q3. This is mirrored in Q4. However Q2 is asking for
more current, and the excess is forced through the load.
Voltage gain is lower on the Q1/Q3
side, hence the singled sided operation.
Gain Stage Darlington connection
By connecting the emitter of one transistor directly to
the base of the next, a very high gain amplifier is
created
Can be considered as 2 cascaded emitter followers with
infinite emitter resistance in the first stage
1

1+
(1+)
(1+)(1+)
Current gain is effectively
2
Output stage
We want to minimise quiescent current
We want low output resistance
We need to drive useful current
Complementary emitter follower
(Class B output stage)
Emitter follower (common collector)
has a low output impedance.
Also has a voltage gain of 1
ie no gain, but has a high current
gain.
This is fine as the previous 2 stages
have given us high voltage gain.
Cross-over distortion
V
i
must exceed +0.6V for Q
1
to turn on,or
be less than -0.6V for Q
2
to turn on.
If an offset voltage is applied at the
input, linearity is greatly improved.
The maximum efficiency of a class B amplifier with sine wave drive
is 78.6%.
Practical class B circuit (actually class AB)
The classic circuit
Vin
Vee
RL
I1
D2
Q2
Q1
D1
Vcc
Q3
The diodes D1 and D2
provide the offset
together with the
current in Q3. The
diodes may be diode
connected transistors.
Q3 can be the gain stage.
Once again as Vin is increased,
the current tries to increase. I1
resists this and so V
CE
has to rise.
The diode voltage doesnt alter,
allowing low distortion operation.
741 op-amp
Simplified op-amp schematic
Net result:
Operation down to DC
Extremely high gain (100,000 or more)
Resistance to common mode signals
Makes it insensitive to temperature
0 v in gives 0 v out
High input impedance, low output impedance
Ideal for feedback
Feedback allows amplifier characteristics to be
ignored!
Analogue Multiplier (2 quadrant)
One use of the LTP is as a multiplier
g
m
is defined by the bias current and is
linear
If we can modulate the bias current we
can vary the gain!
The LTP again
din C m
b C m b C m
c c dout
v R g
v R g v R g
v v v
=
+ =
=
2 1
2 1
T
C C
m
V
I
kT
qI
g = =
Let 2I
C
=I
E
(ie biassed equally)
C din
T
E
out
E
C
C din
T
C
out
R V
V
I
V
I
I
R V
V
I
V
2 2
Now = =
=
So V
out
is proportional to I
E
x V
din
(a current multiplied by a voltage)
The LTP again
R
V V
I
BE i
E

=
2
R
V
I
i
E
2
=
So lets put a voltage to current converter
in the tail. We can use a current mirror.
R
V
i2
-V
EE
As it will be the current through R if
the mirror is perfect.
We can imagine a set of conditions
where V
i2
>>V
BE
and so
din i out
C din
T
i
out
C din
T
E
out
V V V
R V
R V
V
V
R V
V
I
V
2
2
So
2
So
2
Now

=
=
Another use
Notice that if we drive V
i2
from a variable
DC source we can make a voltage
controlled amplifier
Can also be used as a modulator (but only
for positive signals!)
Limitations
V
din
has to be small due to small signal model use
V
i2
can only be positive, as bias current always has to
flow
This is called a 2 quadrant multiplier:-
V
i2
V
din
LTspice implementation
Varying V4 and V5.
The slope gives the gain.
Note the change in gain for
changing V5 (Tail current)
The gain is the slope of the
lines below.
Also note differential
symmetry, but that the V5
voltage needs to be
positive to keep the tail
current positive
Also note non-linearity!
One potential use - modulator
V4 is a high frequency sine wave (Carrier)
V5 is a low frequency sine wave (Modulation)
The multiplier allows the low frequency
to be superimposed upon a carrier.
Amplitude modulation
V5 is changing the
gain of the amplifier
sinusoidally
Revisit the LTP
Remember one of its limitations is that it
is only linear for small signals.
It is well known that feedback can
improve linearity (Remember CE
biassing?)
Can we apply feedback to our LTP to
improve its linear range?
Emitter degeneration
If we add a resistor in the emitter of our LTP we can
improves things
In this example we set the tail current to 1mA
By changing the value of {Res} we can see we reduce
the gain but we increase the linear range
How does this work?
For the LTP, a Large signal analysis shows
that (part of the assignment)
Where V
ID
=V
BE2
-V
BE1
Which is only linear when V
ID
/2V
T
<<1
We can in principle change what's inside
the bracket
Add a resistor
By adding a resistor we reduce the value of V
BE
for a given input
voltage
V
BE2
V
BE1
IR
IR
IR V V
IR V V
IR IR V V V
DIN ID
ID DIN
BE BE DIN
=
+ =
+ + =
2
2
1 2
|
|

\
|

=
|
|

\
|
=
T
DIN
T
ID
C
V
IR V
I
V
V
I I
2
2
tanh 2
2
tanh 2
0 0
R I V
V IR if IR V
IR V V
V IR V
V
IR V
V
IR V
I
V
IR V
I I
MAX DIN
T DIN
T DIN
T DIN
T
DIN
T
DIN
T
DIN
C
0 ) (
0 0
2 2 2
2 2
2 2 ie
1
2
2
if
2
2
2
2
2
tanh 2

=
|
|

\
|

=
>
Which is easy to make true
(For the case of a pure
differential mode signal we
need only consider differential
changes in V
BE
and IR)
To show this, notice
I=2I
C
and substitute in
above
Maximum I occurs when
I = I
0
so max V
DIN
= I
0
R
As I
0
R is usually bigger than 2V
T
I
0
So for our circuit
If we have a maximum I of +/-0.5 mA (Half the tail current), and a
resistor of 1K then V
IN
can now be +/-1V for a linear response (to a
first approximation)
1K
+/-1V
General Assignment (Bipolar
design)
Analyse a 4 quadrant bipolar multiplier
which is linear, giving +/-10V outputs for
+/-5V inputs.
The coursework is in stages
You will need access to LTSpice or another
circuit simulator.
Deliverables
A short report (<6 pages) summarising the
findings. This should contain the following
Analysis of specific tasks (see next slides)
Large signal analysis of LTP
Comparison with the small signal model
Removal of 2 quadrant limitation
Verification of 4 quadrant multiplication by large signal analysis
Linearisation of the upper differential input
Linearisation of the lower differential inputs by degeneration
Demonstrate it works as a linear multiplier
Design to meet the specification
Some critical discussion of the circuit
Specific Tasks to be done
Perform a large signal analysis of the long
tail pair and verify that
|
|

\
|
=
T
ID
C
V
V
I I
2
tanh
0
Relate this to the small signal analysis done in these notes and discuss the limitations
of the small signal performance ie what is the maximum signal that can be input for
the system to be linear
Enter and simulate the given
circuit
You will have to enter a suitable simulation command, and identify the
inputs and outputs
Analyse this and show that it is
now a 4 quadrant multiplier
Verify, (and show working) that this circuit
has a response of
|
|

\
|
|
|

\
|
=
T
ID
T
ID
C
V
V
V
V
I I
2
tanh
2
tanh
2 1
0
And explain how this has removed the 2 quadrant problem.
Also say what the linear range of inputs are for this circuit.
You need now to extend the
linear range
Show this linearises the top input by simulation
Include emitter degeneration in
the bottom LTP
This should allow you to linearise the
lower differential input across a range of
your choice
Now adjust if necessary to meet
the spec
Simulate this and calculate/choose values for voltages/currents/resistors that
show the linear response for inputs of +/-5V with an output of +/- 10V.
There are extra marks for calculating these values instead of just trying values out
Now write a couple of paragraphs that critically evaluate the circuit
Assignment submission details
Deadline is 8
th
January (first Tuesday back)
Hand it in before you go if you are going to be
late back
4:00 pm at the latest.
ECS Coursework office.
Report detailing your findings, showing the
points described in previous slides.
Limit yourself to 6 pages
Web page has a summary of the assignment