r059210203 Switching Theory Logic Design

Code No: R059210203 Set No.
1
II B.Tech I Semester Supplementary Examinations, February 2007
SWITCHING THEORY & LOGIC DESIGN
( Common to Electrical & Electronic Engineering, Electronics &
Instrumentation Engineering, Bio-Medical Engineering, Electronics &
Control Engineering, Electronics & Computer Engineering and
Instrumentation & Control Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. (a) Perform the following using BCD arithmetic. Verify the result. [2 × 4 = 8]
i. 127310 + 958710
ii. 776210 + 383810
(b) Convert the following. [4 × 2 = 8]
i. 97710 = ( )16
ii. 65710 = ( )8
iii. 75410 = ( )2
iv. 100116 = ( )10
2. (a) Draw the NAND logic diagram that implements the complement of the fol-
lowing function. [8]
F(A,B,C,D) = Σ (0,1,2,3,4,8,9,12)
(b) Obtain the complement of the following Boolean expressions.
i. AB+A(B+C)+B’(B+D)
ii. A+B+A’B’C [4]
(c) Obtain the dual of the following Boolean expressions.
i. A’B+A’BC’+A’BCD+A’BC’D’E
ii. ABEF+ABE’F’+A’B’EF [4]
3. (a) Reduce the following function

Q using K- map and implement it in AOI logic as
well as NOR logic F= M(0, 1, 2, 3, 4, 7) [10]
(b) What do you mean by K-map? Name its advantages and disadvantages [6]
4. (a) Implement thePfollowing Boolean function using 8:1 multiplexer.

f (ABCD) = P m(0, 2, 4, 6, 8, 10, 12, 14)
f (ABCD) = m(2, 4, 5, 7, 10, 14)
(b) Explain how to use decoder as a demultiplexer. [6+6+4]
5. Write a brief note on:
(a) Architecture of PLDs

(b) Capabilation and the limitations of threshold gates. [8+8]
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Code No: R059210203 Set No. 1
6. (a) Find a modulo-6 gray code using k-Map & design the corresponding counter.
(b) Compare synchronous & Asynchronous. [10+6]
7. A clocked sequential circuit is provided with a single input x and single output Z.
Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of the
sequence it produce an output Z = 1 and overlapping is also allowed.
(a) Obtain State - Diagram.

(b) Also obtain state - Table.
(c) Find equivalence classes using partition method & design the circuit using D
- flip-flops. [4+4+8]
8. (a) Draw the ASM chart for the following state transistion, start from the initial
state T1 , then if xy=00 go to T2 , if xy=01 go to T3 , if xy=10 go to T1 , other
wise go to T3 .
(b) Show the exit paths in an ASM block for all binary combinations of control
variables x, y and z, starting from an initial state. [8+8]
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1. (a) Explain, How error occurred in a data transmission can be detected using
parity bit. [6]
(b) Perform the subtraction with the following unsigned binary numbers by taking
the 2’s complement of the subtrahend. [5 × 2 = 10]
i. 111011 - 111000
ii. 1110 - 110110
iii. 10010 - 1101
iv. 110 - 10100
v. 11011 - 10000
2. (a) Reduce the following Boolean expressions. [8]

i. AB’(C+BD)+A’B’
ii. A’B’C+(A+B+C’)’+A’B’C’D
iii. ABCD+AB(CD)’+(AB)’CD
iv. (A+A’)(AB+ABC’)
(b) Obtain the complement of the following Boolean expressions. [8]
i. ABC+A’B+ABC’
ii. (BC’+A’D)(AB’+CD’)
iii. x’yz+xz
iv. xy+x(wz+wz’)
3. (a) Write short note on prime implicant chart.

(b) Minimize followingPfunction using Tabular minimization.
F (A, B, C, D) = m(6, 7, 8, 9) + d(10, 11, 12, 13, 14, 15). [4+12]
4. (a) Realize Full Adder Using two half adders and logic gates.
(b) Draw the block diagram of BCD adder using two 4-bit parallel binary adders
and logic gates. [4+12]
5. Write a brief note on:
(a) Architecture of PLDs
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(b) Capabilation and the limitations of threshold gates. [8+8]
6. (a) Find a modulo-6 gray code using k-Map & design the corresponding counter.
(b) Compare synchronous & Asynchronous. [10+6]

wise go to T3 .
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1. (a) Perform the following using BCD arithmetic. Verify the result. [2 × 4 = 8]
i. 748410 + 366810
ii. 825410 + 827710
(b) Convert the following. [4 × 2 = 8]
i. A616 = ( )10
ii. 12668 = ( )10
iii. 101000112 = ( )10
iv. 37210 =( )16
2. (a) Reduce the following Boolean expressions. [8]

i. ((AB)’+A’+AB)’
ii. AB+(AC)’+AB’+C(AB+C)
iii. ((AB’+ABC)’+ A(B+AB’))’
iv. AB+A(B+C)+B(B+C)
(b) Obtain the Dual of the following Boolean expressions. [8]
i. x’y’+xy+x’y
ii. xy’+y’z’+x’z’
iii. x’+xy+xz’+xy’z’
iv. (x+y)(x+y’)
3. (a) Write short note on prime implicant chart.

(b) Minimize followingPfunction using Tabular minimization.
F (A, B, C, D) = m(6, 7, 8, 9) + d(10, 11, 12, 13, 14, 15). [4+12]
4. (a) Design a Excess-3 adder using 4-bit parallel binary adder and logic gates.
(b) Draw the logic diagram of a single bit comparator. [12+6]
5. (a) Derive the PLA programming table for the combinational circuit that squares
a 3 bit number.
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(b) For the given 3-input, 4-output truth table of a combinations circuit,tabulate
the PAL programming table for the circuit. [8+8]
Inputs Output
x y z A B C D
0 0 0 0 1 0 0
0 0 1 1 1 1 1
0 1 0 1 0 1 1
0 1 1 0 1 0 1
1 0 0 1 0 1 0
1 0 1 0 0 0 1
1 1 0 1 1 1 0
1 1 1 0 1 1 1
6. (a) Compare synchronous & Asynchronous circuits

(b) Design a Mod-6 synchronous counter using J-K flip flops. [6+10]

8. (a) For the given ASM chart obtain its equivalent state diagram 1.
(b) Design the circuit using multiplexers.
(c) Also design the circuit using D-Flip-flop per state. [4+8+6]
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Figure 1:
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1. Convert the following to Decimal and then to Binary.
(a) 123416
(b) ABCD16
(c) 11228
(d) 17268
(e) 99710
(f) 65410 [3+3+3+3+2+2]
2. (a) Draw the logic diagram corresponding to following expressions without sim-
plifying them. [8]
i. (A+B) (C+D) (A’+B+D)
ii. (AB+A’B’)(CD’+C’D)
(b) Obtain the complement of the following Boolean expressions. [8]
i. x’yz+x’yz’+ xy’z’+xy’z
ii. x’yz+xy’z’+xyz+xyz’
iii. x’z+x’y+xy’z+yz
iv. x’y’z’+x’yz’+xy’z’+xy’z+xyz’
3. (a) What do you mean by dont care combinations? [4]

(b) What you mean by min terms and max terms of Boolean expressions. [4]
P
(c) Simplify the Boolean function using K-map F= m(0, 1, 3, 4, 5, 6, 7, 8, 9) +
d(10, 11, 12, 13, 14, 15) [8]
4. Design a BCD(B0 , B1 , B2 , B3 , B4 ) to Binary(A,B,C,D,E) converter using logic

gates. [16]
5. (a) Given a 32 x 8 Rom chip with an enable input, show the external connection
necessary to construct a 128 × 8 Rom with four chips and a decoder.
(b) Tabulate the PLA programming table for the four Boolean functions listed
below
A(x,y,z) = ε(1, 2, 4, 6)
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B(x,y,z) = ε(0, 1, 6, 7)
C(x,y,z) = ε(2,6)
D(x,y,z) = ε(1, 2, 3, 5, 7). [8+8]
6. (a) Compare synchronous & Asynchronous circuits

(b) Design a Mod-6 synchronous counter using J-K flip flops. [6+10]

wise go to T3 .
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Code No: R059210203 Set No.

3. (a) Reduce the following function

4. (a) Implement thePfollowing Boolean function using 8:1 multiplexer.

5. Write a brief note on:

(a) Architecture of PLDs

(a) Obtain State - Diagram.

2. (a) Reduce the following Boolean expressions. [8]

3. (a) Write short note on prime implicant chart.

5. Write a brief note on:

(a) Architecture of PLDs

(a) Obtain State - Diagram.

2. (a) Reduce the following Boolean expressions. [8]

3. (a) Write short note on prime implicant chart.

6. (a) Compare synchronous & Asynchronous circuits

(a) Obtain State - Diagram.

1. Convert the following to Decimal and then to Binary.

3. (a) What do you mean by dont care combinations? [4]

4. Design a BCD(B0 , B1 , B2 , B3 , B4 ) to Binary(A,B,C,D,E) converter using logic

6. (a) Compare synchronous & Asynchronous circuits

(a) Obtain State - Diagram.

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