MDLOGIC SOLUTIONS - #4 Arcot Road, Kodambakkam, Chenna !4 "!

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Ab(tract0 Automation in every design is expected in all domains, to face the challenges in manual functioning,. Design automation techniques are a key challenge in the widespread application of timing-robust asynchronous circuit styles. In the presented paper, a new methodology for mapping multi rail logic expressions to is !"" convention logic # $"% gate library is proposed. &he new methodology then compared to another recently designed mapping approach,

demonstrating that the new methodology can further reduce the area and improve the delay of $" circuits. Also, in contrast to the original approach, $" gate library for mapping. In which only targets area reduction, the new methodology can target any arbitrary cost function or use any subset of the order to automate the new methodology and compare it with the original one, both methodologies were implemented in the 'erl programming language and compared in terms of mapping performance and runtime. &he results show that, depending on the test circuit, the new methodology can offer up to ()* improvement in area, and +,* improvement in delay. 12 (t n' S.(tem0 In the existing design a new methodology for mapping multi rail logic expressions to !"" convention logic # $"% gate library is proposed. &he new methodology is then compared to another recently designed mapping

MDLOGIC SOLUTIONS - #4 Arcot Road, Kodambakkam, Chenna !4 "!##$##"4# % #4444##"4# md&o' c(o&)t on(*'ma &+com

approach, demonstrating that the new methodology can further reduce the area and improve the delay of $" circuits.

3ro,o(ed S.(tem0 In the proposed design the mapping automation is clearly designed with low power logic latches and flip flops, all the combinational circuit tend to depend upon the one of the clock source which is routed in to the circuit. &he convention logic is implemented with the proposed gate library. ull

D (ad/anta'e( n e2 (t n' (.(tem &he hardware is fully reali-ed by combinational circuits, so chances are there in generating switching delays. Ad/anta'e( n ,ro,o(ed (.(tem $ircuit is integrated with stable clock inside the system hence all combinational circuits depends upon the clock, here less delays. So-t4are Re5) rement(0 Design .nvironment/ 0I"I 0 I1. "anguage/ 23D" 1imulation/ 45D."1I4 6 0I"I 0 I1. 1imulator 6ard4are Re5) rment(0

MDLOGIC SOLUTIONS - #4 Arcot Road, Kodambakkam, Chenna !4 "!##$##"4# % #4444##"4# md&o' c(o&)t on(*'ma &+com

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