SHANMUGHA

ARTS, SCIENCE, TECHNOLOGY AND RESEARCH ACADEMY

(SASTRA University)
TIRUMALAISAMUDRAM THANJAVUR !" #$%&

COURSE CODE COURSE NAME

' (ECCEC )$* ' HDL +ROGRAMMING LA(

(RANCH' ELECTRONICS AND COMMUNICATION ENGINEERING SEMESTER' VII

CONTENTS

VHDL AND ITS STRUCTURE AN APPROACH TO FPGA IMPLEMENTATION WITH QUARTUS II SOFTWARE LIST OF EXPERIMENTS

VHDL Coding (With s it!"#$ %$h!&io'!#( D!t! )#o*( !nd St' +t '!# D$s+'i,tions- )o'.
Basic gates 1. Half Adder and Half Subtractor 2. Full Adder and Full Subtractor 3. 8:1 Multiplexer 4. 4:1 !ecoder ". Four bit co#parator using single bit co#parator . 8:3 $riorit% encoder &. Four bit adders 8. Signed and 'nsigned #ultiplier (. Master sla)e flip*flop+! t%pe and ,*- t%pe. 1/. Four bit 0ipple counter and 'p*do1n counter 11. 'ni)ersal s2ift register 12. State #ac2ine #odelling of Meela% #ac2ine and Moore #ac2ine.

VHDL AND ITS STRUCTURE

INTRODUCTION
VHDL is an acron%# for Ver% 2ig2 speed integrated circuit (VHSICHard1are Description Language 12ic2 is a progra##ing language t2at describes a logic circuit b% function3 data flo1 be2a)ior3 and4or structure. 52is 2ard1are description is used to configure a progra##able logic de)ice +PLD.3 suc2 as a field progra##able gate arra% + FPGA.3 1it2 a custo# logic design. 52e general for#at of a 6H!7 progra# is built around t2e concept of %LOC/S 12ic2 are t2e basic building units of a 6H!7 design. 8it2in t2ese design bloc9s a logic circuit of function can be easil% described. A 6H!7 design begins 1it2 an ENTIT0 bloc9 t2at describes t2e interface for t2e design. 52e interface defines t2e input and output 1ogic signals of t2e circuit being designed. 52e ARCHITECTURE bloc9 describes t2e internal operation of t2e design. 8it2in t2ese bloc9s are nu#erous ot2er functional bloc9s used to build t2e design ele#ents of t2e logic circuit being created. After t2e design is created3 it can be si#ulated and s%nt2esi:ed to c2ec9 its logical operation. SIMULATION is a bare bones t%pe of test to see if t2e basic logic 1or9s according to design and concept. S0NTHESIS allo1s ti#ing factors and ot2er influences of actual field progra##able gate arra% +FPGA. de)ices to effect t2e si#ulation t2ereb% doing a #ore t2oroug2 t%pe of c2ec9 before t2e design is co##itted to t2e FPGA or si#ilar de)ice. Man% soft1are pac9ages used for 6H!7 design also support sc2e#atic capture 12ic2 ta9es a logic sc2e#atic or state diagra# and translates it into 6H!7 code. 52is3 in turn3 #a9es t2e design process a lot easier.

12 DATA T0PES
6H!7 is a )er% st'ong#3 t%ped language. ;t is not per#issible to <oin t1o signals if t2e% do not 2a)e t2e sa#e data t%pe. ;n order to #a9e 6H!7 an effecti)e platfor# and si#ulator independent standard3 ;=== defined data t%pes 1ere introduced> std?logic and std?ulogic. 52ese data t%pes 2a)e beco#e an industr% standard for design. Std*logic and std?ulogic can assu#e t2e sa#e )alues3 t2e difference being t2at std?logic is a resol)ed subt%pe of std?ulogic. Std?ulogic is a t%pe 12ic2 is declared in t2e ;=== pac9age std?logic?11 4. Std?ulogic @ std?logic is a nine )alue logic s%ste# 12ic2 can assu#e t2e follo1ing )alues: 4U5 66 Uniniti!#i7$d 4X566 Fo'+ing Un8no*n 49566 Fo'+ing 9 4:5 66 Fo'+ing : 4;5 66 High I<,$d!n+$ 4W 66 W$!8 Un8no*n 4L5 66 W$!8 9 4H5 66 W$!8 : 465 66 Don5t +!'$ 52e difference bet1een std?ulogic and std?logic is std?logic is resol)ed subt%pe of std?ulogic. Std?logic is resol)ed #eans t2at 3 if a signal is dri)en b% se)eral dri)ers3 a predefined resolution function is called up 12ic2 resol)es t2e conflict and decides 12ic2 )alue t2e signal 1ill be gi)en.

52e different t%pes of data t2at can be used 1it2 6H!7 include bits3 buses3 boolean3 strings3 real and integer nu#ber t%pes3 p2%sical3 and user defined enu#erated t%pes. D$)ining Sign!#s 52ere are t1o data t%pes used for defining interfacing and interconnecting signals * "its and "it=&$+to's. 52e bit t%pe defines a single binar% bit t%pe of signal li9e RESET or ENA%LE. ;t is used to define a single control or data line. For #ultiple bus signals3 suc2 as data or address buses3 an arra% called a bit?)ector is used. Bit?)ectors reAuire a range of bits to be defined and 2as t2e s%ntax: bit?)ector+range.52e range for a bit?)ector is defined fro# t2e least significant bit +LS%. to t2e #ost significant bit +MS%. and can be set to go fro# one to t2e ot2er in ascending or descending order b% using: 7SB to MSB or MSB do*nto 7SB. Here are so#e exa#ples of bit?)ector for#s: !dd'$ss" s(9 to >-? d!t!" s(:@ do*nto 9-? 52e first defines an 8*bit address bus fro# addressbus+/. to addressbus+&.. 52e second3 a data bus fro# databus+1". do1nto databus+/.. 52e IEEE STD=LOGIC=::AB standard includes additional definitions for 6H!7 data t%pes. For t2e bit t%pe3 t2e ;=== t%pe is STD=LOGIC and for a bit?)ector it is STD=LOGIC=VECTOR. 52e use of t2e ;=== standard t%pes assures t2at our 6H!7 code 1ill be ,o't!"#$. Th$ %oo#$!n T3,$ 52e boolean t%pe 2as onl% t1o )alues: TRUE (:- and FALSE (9- and is usuall% used to 2old t2e results of a co#parison or t2e basis for conditional state#ent results. N <$'i+!# T3,$s

Bu#ber t%pes t2at are usable in 6H!7 code are INTEGERS and REALS. ;ntegers are signed nu#bers and reals are used for floating point )alues. 52e range of )alues for bot2 nu#ber t%pes depends on t2e soft1are application being used. S "t3,ing 6H!7 pro)ides a #et2od to create a )ersion of an existing t%pe 1it2 a specified range of )alues b% using t2e SU%T0PE declaration. A t%pical exa#ple of t2e use and s%ntax of t2is operation is: s "t3,$ SHORTINT is int$g$' '!ng$ 9 to 1@@? 12ic2 creates an integer t%pe3 SHORTINT 1it2 a specified range of )alues fro# / to 2"".

En <$'!t$d o' Us$' D!t! T3,$ An enu#erated data t%pe pro)ides a #eans for creating and defining user t%pes. 52e% are declared using t2e T0PE operator 1it2 a s%ntax of: T0PE t3,$=n!<$ (t3,$ &!# $s-? Cnce t2e data t%pe 2as been declared3 t2en it can be used in a )ariable declaration +discussed later.. For exa#ple3 2ere is a declaration for a data t%pe called MONTHS: T0PE MONTHS (CAN( FE%( MAR( APR( MA0( CUN( CUL( AUG( SEP( OCT( NOV( DEC-? A )ariable declared to be of t%pe MONTHS can 2a)e an%one of t2e t1el)e )alues indicated in t2e parent2esis. 52is T3,$ o,$'!to' can also be used for designing a 7oo9 up table for certain applications. For exa#ple if 1e 1ant to use predefined ten 8bit

)alues for a specific application3 t2en t2e t%pe operator can be used as follo1s. 5%pe data?7'5 is arra%+( do1nto /. of std?logic?)ector+& do1nto /.> Signal ne1data : data?7'5:D +E1/1/11//F3F//11//11F3F1111////F3 E1/1/1/1/F3F11//11//F3F////11//F3 E1111//11F3F111//111F3F1/11///1F3F11111111F.> ;n t2e abo)e exa#ple3 ne1data is t2e 7'5 12ic2 is of t%pe data?7'5 and it 2as ten 8bit )alues. Oth$' D!t! T3,$s 6H!7 specifications include additional data t%pes t2at are used in t2e be2a)ioral description of a circuit design. 52ese t%pes are: A. Arra%s are single or #ultidi#ensional enu#erated arra% t%pes and t2e std?logic?)ector t%pe. B. An access t%pe acts li9e a pointer t%pe and 2as li#ited use. G. A file t%pe is used to access a file. !. A p2%sical t%pe is used to specif% finite Auantities suc2 as ti#e3 )oltage3 etc. 52is t%pe includes units of #easure suc2 as #illiseconds +#s. and )olts. =. 5i#e units used 1it2 t2e p2%sical t%pe are:

pri#ar% unit is fs................fe#tosecond ps D 13/// fs.................. ..picosecond ns D 13/// ps................. ..nanosecond us D 13/// ns................ ...#icrosecond

#s D 13/// us............... ...#illisecond sec D 13/// #s............. ...second #in D / sec................ ....#inute 2our D / #in............... ....2our

F. 52e line t%pe is an ASG;; string of c2aracters. H. A record contains a collection of #ultiple data t%pes. 52ese are t2e )arious data t%pes used b% 6H!7.

D2 ENTIT0 %LOC/
An $ntit3 "#o+8 is t2e basic building bloc9 of a 6H!7 design. =ac2 design 2as onl% one entit% bloc9 12ic2 describes t2e interface signals in to and out of t2e design unit. 52e s%ntax for an entit% declaration is: $ntit3 $ntit3=n!<$ is ,o't (sign!#=n!<$(sign!#=n!<$ . <od$ t3,$? sign!#=n!<$(sign!#=n!<$ . <od$ t3,$-? $nd $ntit3=n!<$? An entit% bloc9 starts 1it2 t2e reser)e 1ord $ntit3 follo1ed b% t2e entit%?na#e. Ba#es and identifiers can contain letters3 nu#bers3 and t2e under score c2aracter3 but #ust begin 1it2 an alp2a c2aracter. Bext is t2e reser)ed 1ord is and t2en t2e ,o't declarations. A single PORT declaration is used to declare t2e interface signals for t2e entit% and to assign MODE and data T0PE to t2e#. ;f #ore t2an one signal of t2e sa#e t%pe is declared3 eac2 identifier na#e is separated b% a +o<<!. ;dentifiers are follo1ed b% a +o#on (.-3 #ode and data t%pe selections. ;n general3 t2ere are fi)e t%pes of #odes.

1. 2. 3. 4. ".

In* co#ponent onl% read t2e signal O t*Go#ponent 1rite to t2e signal Ino t*co#ponent read or 1rite to t2e signal +Bidirectional signal. % ))$'*Go#ponent 1rite and read bac9 t2e signal Lin8!g$*used onl% in t2e docu#entation purposes.

52e port diagra#s for )arious #odes are s2o1n in t2e fig.

In VHDL( ALL STATEMENTS !'$ t$'<in!t$d "3 ! s$<i+o#on2 52e entit% declaration is co#pleted b% using an $nd operator and t2e entit%?na#e. Here is an exa#ple of an entit% declaration for a set4reset + SR. latc2: entit% latc2 is port +s3r : in std?logic> A3nA : out std?logic.> end latc2> 52e set4reset latc2 2as input control bits s and ' 12ic2 are defined as single input bits and output bits E and nE. A design circuitIs operation 1ill be defined in t2e arc2itecture bloc9.

A #it$'!# +onst!nt can be defined 1it2in an entit% 1it2 t2e g$n$'i+ declaration3 12ic2 is placed before t2e port declaration 1it2in t2e entit% bloc9. Heneric literals can be used in port and ot2er declarations. 52is #a9es it easier to #odif% or update designs. For instance if %ou declare a nu#ber of bit?)ector bus signals3 eac2 eig2t bits in lengt23 and at so#e future ti#e %ou 1ant to c2ange t2e# all to 1 *bits3 %ou 1ould 2a)e to c2ange eac2 of t2e bit?)ector range. B% using a generic to define t2e range )alue3 1e 2a)e to <ust c2ange t2e genericIs )alue and t2e c2ange 1ill be reflected in eac2 of t2e bit?)ectors defined b% t2at generic. 52e s%ntax to define a generic is: g$n$'i+ (n!<$ . t3,$ .F &!# $-? 52e reser)ed 1ord g$n$'i+ defines t2e declaration state#ent. 52is is follo1ed b% an identifier na#e for t2e generic and a colon. Bext is t2e data t%pe and a literal assign#ent )alue for t2e identifier. .F is t2e assign#ent operator t2at allo1s a literal )alue to be assigned to t2e generic identifier na#e. For exa#ple3 2ere is t2e code to define a bus 1idt2 si:e using a generic literal. $ntit3 <3 ,'o+$sso' is g$n$'i+ (" sWidth . int$g$' .F >-? $resentl%3 bus8idt2 2as t2e literal )alue of &. 52is #a9es t2e docu#entation #ore descripti)e for a )ector t%pe in a port declaration: ,o't( d!t!=" s . in std=#ogi+=&$+to' (" sWidth do*nto 9-? E6o t . o t std=#ogi+=&$+to' (" sWidth do*nto 9--? ;n t2is exa#ple3 data?bus and A?out 2a)e a 1idt2 of eig2t +8. bits + > do*n to 9.. 12en t2e design is updated to a larger bus si:e of sixteen +1 . bits3 t2e onl% c2ange is to t2e literal assign#ent in t2e generic declaration fro# > to :@2

B2 ARCHITECTURE %LOC/

52e !'+hit$+t '$ "#o+8 defines 2o1 t2e entit% operates. 52is #a% be described in #an% 1a%s3 t1o of 12ic2 are #ost pre)alent: STRUCTURAL and DATA FLOW o' %EHAVIORAL for#ats. 52e %EHAVIORAL approac2 describes t2e actual logic be2a)ior of t2e circuit. 52is is generall% in t2e for# of a Boolean expression or process. 52e STRUCTURAL approac2 defines 2o1 t2e entit% is structured * 12at logic de)ices #a9e up t2e circuit or design. 52e general s%ntax for t2e arc2itecture bloc9 is: !'+hit$+t '$ !'+h=n!<$ o) $ntit3=n!<$ is d$+#!'!tions? "$gin st!t$<$nts d$)ining o,$'!tion? $nd !'+h=n!<$? For our first exa#ple3 1e 1ill use t2e set4reset BC0 latc2 of figure 1. ;n 6H!7 code listings3 ** +double das2. indicates a co##ent line used for docu#entation and ignored b% t2e co#piler.

librar% ieee> use ieee.std?logic?11 4.all> ** entit% bloc9 entit% latc2 is ** interface signal declarations port +s3r : in std?logic>

A3nA : out std?logic.> end latc2> ** arc2itecture bloc9 arc2itecture flipflop of latc2 is begin ** assign#ent state#ents A JD r nor nA> nA JD s nor A> end flipflop> 52e first t1o lines i#ports t2e ;=== standard logic librar% std=#ogi+=::AB 12ic2 contains predefined logic functions and data t%pes suc2 as std?logic and std?logic?)ector. 52e use state#ent deter#ines 12ic2 portions of a librar% file to use. ;n t2is exa#ple 1e are selecting all of t2e ite#s in t2e 11 4 librar%. 52e next bloc9 is t2e entit% bloc9 12ic2 declares t2e latc2Is interface inputs3 r and s and /outputs A and nA. 52is is follo1ed b% t2e arc2itecture bloc9 12ic2 begins b% identif%ing itself 1it2 t2e na#e flipflop as a description of entit% latc2. 8it2in t2e arc2itecture bloc9Is bod% +designated b% t2e "$gin reser)ed 1ord. are t1o assign#ent state#ents. Signal assign#ent state#ents follo1 t2e general s%ntax of: sign!#=id$nti)i$'=n!<$ GF $H,'$ssion? 52e GF s%#bol is t2e assign#ent operator for assigning a )alue to a signal. 52is differs fro# t2e .F +)ariable assign#ent. operator used to assign an initial literal )alue to generic identifier used earlier. ;n our latc2 exa#ple3 t2e state of t2e signal E is assigned t2e logic result of t2e nor function using input signals ' and nE. 52e nor operator is defined in t2e ;=== std?logic?11 4 librar% as a standard 6H!7 function to perfor# t2e nor logic operation. 52roug2 t2e use of Boolean expressions3 t2e

operation of t2e BC0 latc2Is be2a)ior is described and translated b% a 6H!7 co#piler into t2e 2ard1are function appearing in figure 1. Ti<$ D$#!3s !ataflo1 or be2a)ioral arc2itectures can also include ti#ing influences b% adding propagation dela% )alues using t2e after operator and a ti#e p2%sical data t%pe. An exa#ple of adding a one nanosecond inertial dela% to nor gate operation appears as: E GF ' no' nE !)t$' :ns?

52is 1ould cause output E to go 2ig2 : ns after t2e application of t2e ' input. 52e inertial for# reAuires t2at ' sta% acti)e3 as ho#d ti<$3 for a #ini#u# ti#e eAual to t2e dela% ti#e +: ns in t2is exa#ple.. ;f %ou 1ant to allo1 E to c2ange for r pulses t2at are s2orter t2an 1 ns3 %ou need to use t2e t'!ns,o't d$#!3 for# 12ic2 reAuires t2e t'!ns,o't operator to be included preceding t2e logic state#ent: E GF t'!ns,o't ' no' nE !)t$' :ns?

Again3 t2e difference bet1een t2e t1o ti#e dela%s is t2at 1it2out t2e transport operator3 t2e input 2as to be present for t2e entire dela% ti#e 12ile 1it2 t2e transport operator3 t2e input does not need to be applied for a period eAual to t2e full dela% ti#e period. Using V$+to' T3,$s in th$ A'+hit$+t '!# %#o+8 A bit?)ector or std?logic?)ector t%pe is an !''!3 o) "its. 52e range designates t2e si:e of t2e arra% and t2e index )alues to be used b% t2e arra%. =le#ents of t2e arra% are accessed b% using t2e arra% na#e and an index )alue in t2e for# of: !''!3=n!<$(ind$H-. 52e best 1a% to see 2o1 )alues are assigned to an arra% is to do an exa#ple. librar% ieee> use ieee.std?logic?11 4.all> entit% de#ux is port + e : in std?logic?)ector +3 do1nto /.> s : in std?logic?)ector +1 do1nto /.> d : out std?logic?)ector +3 do1nto /..> end de#ux>

arc2itecture rtl of de#ux is signal t : std?logic?)ector +3 do1nto /.> begin t+3. JD s+1. and s+/.> t+2. JD s+1. and not s+/.> t+1. JD not s+1. and s+/.> t+/. JD not s+1. and not s+/.> d JD e and t> end rtl> Before 1e loo9 at t2is exa#ple line b% line3 1e need an introduction to a ne1 declaration3 SIGNAL. 52is declaration is used to define an int$'n!# sign!# for our design. ;n t2e entit% bloc9 1e defined interfacing or external signals t2at ta9e infor#ation in and return data out. ;nternal signals are t2ose used to perfor# so#e internal connections or function bet1een logic entities. A signal declaration 2as t2e s%ntax: sign!# sign!#=id$nti)i$' . t3,$? ;t is si#ilar to a port signal declaration except for t2e lac9 of a #ode indication. ;n t2e de#ux exa#ple3 t2e entit% 2as t2ree arra% declarations3 t1o are 4*bits +$ and d. and one is 2*bits +s.. 8it2in t2e arc2itecture bloc93 a local signal is declared as a 4*bit arra% +t.. 52e )alues for t are assigned in descending order directed b% t2e four state co#binations of s(:- and s(9-. Botice 2o1 eac2 ele#ent is accessed using t2e arra% na#e and an index )alue. t(D- is assigned t2e results of anding s(:- and s(9-. 52is is a single bit #anipulation and assign#ent of one bit fro# eac2 arra%3 bits t(D-( s(:-3 and s(9-. 52e last line s2o1s 2o1 arra% )alues can be assigned for t2e entire arra% at one ti#e. 52e reAuire#ent is t2at all arra%s in t2e assign#ent state#ent 2a)e t2e sa#e si:e. ;f t2at is t2e case3 t2an eac2 ele#ent of eac2 arra% is acted upon indi)iduall%. ie:

d(D- GF $(D- !nd t(D- etc. Since )ectors can be assigned using to as 1ell as do1nto3 care #ust be ta9en in t2e assign#ent. ;f3 in t2e pre)ious exa#ple3 d 1as declared as d . o t std=#ogi+=&$+to'( 9 to D-? t2an t2e assign#ent d GF $ !nd t? 1ould assign to d(9- t2e result of $(D- and t(D- 12ic2 #a% not be 12at %ou intended.

@2 PROCESS
State#ents 1it2in arc2itecture bloc9s3 to t2is point3 are executed

+on+ ''$nt#3 * t2at is at t2e sa#e ti#e. Also3 t2ere is no 1a% to s%nc2roni:e t2eir execution 1it2 cloc9ing or an% ot2er 9ind of signals. 5o incorporate seAuential state#ent execution and so#e #anner of s%nc2roni:ation3 1e need to use a PROCESS bloc9 12ose general s%ntax for# is: ,'o+$ss=n!<$ . ,'o+$ss (s$nsiti&it3 #ist&!'i!"#$ &!'i!"#$=n!<$s . &!'i!"#$=t3,$? "$gin st!t$<$nts? $nd ,'o+$ss? $rocess state#ents are placed in t2e !'+hit$+t '$ "#o+8 of %our design. 52e process?na#e and )ariable declarations are optional. V!'i!"#$ declarations are used to define a )ariable local to and used b% t2e process. 6ariable declarations are added in t2e declaration area preceding t2e bod% of t2e process bloc9. ;n contrast to a signal3 )ariable declarations define #e#or% locations3 identified b% )ariable identifier na#es3 used to store results of expressions. Signals3 b% t2eir nature3 cannot be used to perfor# arit2#etic #anipulations suc2 as incre#enting or decre#enting t2eir )alue 12ile )ariables can be operated on #at2e#aticall%. 52e )ariable assign#ent operator is .F 12ic2 is t2e sa#e one used for assigning initial literal )alues. 52e s%ntax for a )ariable assign#ent is:

&!'i!"#$=id$nti)i$' .F $H,'$ssion? 5o e)aluate expressions used in a )ariable declaration or process bloc93 %ou #ust beco#e fa#iliar 1it2 t2e operators used b% 6H!7. ;n order of t2eir precedence3 t2e% are: High$st

+. * parent2esis KK * exponential abs * absolute unsigned #agnitude nu#bers not * in)ersion

N$Ht

K * #ultiplication 4 * di)ision #od * #odulo or Auotient fro# di)ision re# * re#ainder result of di)ision

N$Ht

L * identit% * * negation

N$Ht

L * addition * * subtraction @ * concatenation

N$Ht

sll * s2ift left logical srl * s2ift rig2t logical

sla * s2ift left arit2#etic sra * s2ift rig2t arit2#etic rol * rotate left ror * rotate rig2t

N$Ht

D * eAualit% 4D * not eAual J * less t2an M * greater t2an JD * less t2an or eAual MD * greater t2an or eAual

LOWEST

and * logic and or * logic or nand * logic nand nor * logic nor xor * logic exclusi)e or xnor * logic exclusi)e nor

Bo1 an exa#ple of a )ariable assign#ent: +nt .F +nt I :? As 1it2 an% ot2er language3 t2e expression on t2e rig2t is e)aluated first. ;n t2is case one is added to t2e )ariable cnt. 52e results are t2an stored bac9 into t2e cnt )ariable indicated on t2e left side of t2e assign#ent state#ent. 52is one si#pl% incre#ents cnt b% 1. 5o set t2is )ariable state#ent into a process bloc93 t2e code 1ould loo9 li9e:

+o nt . ,'o+$ss(H&!'i!"#$ +nt . int$g$' .F 6:? "$gin +nt .F +nt I :? $nd ,'o+$ss? 52e first line of t2e process s%ntax is its declaration and contains an optional para#eter list3 9no1n as t2e s$nsiti&it3 #ist. A process executes once at t2e beginning of a si#ulation and an% ti#e t2at an e)ent occurs on an ite# in t2e sensiti)it% list. An EVENT is an% c2ange of state of a signal. A c2ange of state on signal H 1ill cause t2is process to execute once. 52e next line is a )ariable declaration t2at is si#ilar to a port +signal. declaration. Since it is a )ariable and not a port3 t2ere is no #ode selection. Also3 )ariables can be assigned an initial )alue using an assign#ent operator as s2o1n in t2e exa#ple. 8e 1ant +nt to start at /3 but since t2e process executes once upon starting si#ulation +1it2out an e)ent occurring on H.3 1e need to initiali:e +nt to *1. 52e initial execution of t2e process due to t2e start of a si#ulation 1ill set +nt to / b% incre#enting it once. After t2at3 eac2 ti#e an e)ent occurs on H( +nt 1ill be incre#ented once3 t2us 9eeping trac9 of 2o1 #an% ti#es H c2anges state. 52e state#ents to be executed b% t2e process bod% follo1 t2e "$gin reser)ed 1ord. Finall%3 t2e process declaration is co#pleted using an end process state#ent. D$+#!'!tions 1it2in t2e process bloc9 and preceding t2e process bod% are executed onl% once * 12en si#ulation is initiated. 52ereafter3 12en t2e process is run due to an e)ent on one of t2e signals on t2e sensiti)it% list3 onl% t2e bod% of t2e process is executed. 52is pre)ents )ariables fro# being re*initiali:ed eac2 ti#e t2e process is run. All state#ents in a process execute seAuentiall%. Here are a couple of exa#ples of process state#ents 1it2 an anal%sis of eac2:

,'o+$ss ( 0 &!'i!"#$ X( ; . std=#ogi+? "$gin X .F 0? ; .F not X? $nd ,'o+$ss? 52is is a fairl% eas% appearing exa#ple3 but letIs ta9e so#e ti#e exploring 12at 2appens to #a9e sure %ou full% grasp t2e difference bet1een concurrent and seAuential operation. 0 is included in t2e sensiti)it% list3 so it #ust 2a)e been declared in t2e design before t2e process state#ent. 6ariables X and ; are declared in t2e process bloc9 forcing t2ese )ariables to be local to t2e process and not accessible outside of it. 5o follo1 12at 2appens 12en t2e process is executed3 letIs assu#e so#e initial )alues for our t2ree )ariables: ND1 OD1 PD/

;nitial )alues for )ariables can be set in t2e )ariable declaration state#ents using t2e :D assign#ent operator in t2is #anner: &!'i!"#$ X . std=#ogi+ .F :? &!'i!"#$ ; . std=#ogi+ .F 9? Cf course3 signal 0 1ould 2a)e to be initiali:ed before t2e process state#ent to gi)e it a beginning state. ;n t2is case3 %ou 1ould probabl% use an assign#ent state#ent: 0 GF J:J?

Since 0 2as been defined as an interface signal in an entit%3 t2e GF assign#ent operator is reAuired 2ere. Assigning a literal logic state3 1 or /3 to a signal reAuires a sing#$ E ot$ around t2e 1 or /. 52is causes t2e soft1are to con)ert t2e ASG;; 1 or / to a logic state and assign it to t2e signal. Assigning a string of logic bit literals to a )ector reAuires double Auotes so t2at t2e ASG;; string can be con)erted to logic states for eac2 bit of t2e )ector. Bu#erical literals 1ill not use t2e Auotes around it. 52e sa#ple states 1ere not selected as rando#l% as %ou #ig2t t2in9. ; c2ose t2e# to illustrate t2e point of s$E $nti!# operation 1it2in t2e process. 82en 0 c2anges to a / t2roug2 so#e outside influence3 an e)ent occurs and t2e process is initiated. ;f t2e state#ents 1it2in t2e process 1ere executed +on+ ''$nt#3( t2e% 1ould use t2e initial )alues to produce results for all outputs. 52e c2ange in 0 fro# 1 to / causes X to c2ange to a / because of t2e state#ent X .F 0? Because X 2ad a )alue of 1 initiall%3 t2is )alue is used for t2e second state#ent in concurrent execution. 52is forces ; to beco#e 1 fro# t2e state#ent ; .F not X2 Ho1e)er3 t2e state#ents in t2e process are executed s$E $nti!##3 rat2er t2an concurrentl%. 82at actuall% occurs in t2e process is X beco#es / 12en 0 c2anges to / as it did for a concurrent execution. Ho1e)er3 t2is ti#e3 ; 1ould beco#e 1 since t2e second state#ent in a seAuential execution 1ould use t2e ne1 )alue of X instead of XIs initial )alue. Bo1 to a #ore practical exa#ple use of a process 12ic2 1ill also include a #et2od to pre)ent state#ents 1it2in t2e process bod% fro# executing 12en si#ulation is first begun and an e)ent 2as not %et occurred: librar% ieee> use ieee.std?logic?11 4.all> entit% !FF is ** Signals are initiali:ed to / b% default. ** 5o #a9e QB a 13 it 2as to be initiali:ed port + !3 G7- : in std?logic>

Q : out std?logic> QB : out std?logic :D I1I.> end !FF> arc2itecture data?flip of !FF is begin process + G7- . begin if +G7- D I1I and G7-Ie)ent . t2en Q JD ! after 1/ns> QB JD not ! after 1/ns> end if> end process> end data?flip> 52e entit% bloc9 is co)ered b% t2e +o<<$nt #in$s 12ic2 are al1a%s preceded b% a do "#$ d!sh (66-. ;dentifiers of all 9inds are usuall% initiali:ed b% #ost co#pilers 12en t2e% are declared3 to / or null. 5o set QN to t2e opposite state of Q initiall%3 1e 2ad to assign it an initiall% )alue of 1 b% using .F J:J follo1ing its port declaration. 52e rest of t2e entit% bloc9 is straig2t for1ard. ;n t2e arc2itecture bloc9 1e did not reAuire an% local )ariables or signals so none are declared. 52e process bloc9 contains one signal in t2e sensiti)it% list3 CL/. 52e onl% state#ent in t2e process bod% is an i)22th$n22$#s$ state#ent. 52e if..t2en..else state#ent 12ic2 is explored in #ore detail later3 2as a standard for#at of: i) +ondition th$n st!t$<$nts? $#s$ st!t$<$nts? $nd i)?

52e $#s$ "#o+8 is optional and is used 12en t2ere are state#ents to be executed 12en t2e conditional test returns a )!#s$ '$s #t2 52e th$n state#ents are executed 12en t2e condition rings t' $. 52e i)22th$n22$#s$ state#ent in t2e exa#ple 2as t1o conditions and bot2 2a)e to be #et to execute t2e state#ents 1it2in t2e t2en bloc9. 52e first condition reAuires t2e state of CL/ to be high. 52e and operator in t2e condition field forces a second condition to also be true. 52is condition is CL/J$&$nt 12ic2 sa%s t2at an event #ust 2a)e occurred on CL/ to be true. ;f t2e e)ent occurred3 CL/J$&$nt returns t' $. ;f no e)ent occurred3 it returns a )!#s$ )alue. 52e inclusion of t2is condition eli#inates t2e execution of t2e state#ents 1it2in t2e if bloc9 12en si#ulation first begins since t2e lac9 of a CL/ e)ent causes CL/J$&$nt to be )!#s$. 52e onl% ti#e t2e if condition 1ill be satisfied is 12en an e)ent on CL/ occurred. Additionall%3 CL/ 2as to be 2ig23 so t2is co#bination causes t2e t2en state#ents to be executed onl% on a positive transition (edge) of t2e CL/ signal. 52e .F operator is used to assign initial )alues in a )ariable state#ent. Botice t2at for signals3 sing#$ E ot$s are reAuired around t2e initial )alue +I/I. 12ile none are used for an integer +/.. 52is is because signal )alues are logic states and integer )alues are nu#erical. Bu#erical )alues do not reAuire Auotes. Also notice t2e difference 12en integer )ariables are assigned a )alue fro# an expression co#pared to a signal assign#ent. ;n a pre)ious exa#ple 1e used 0 GF A !nd %? to assign to 0 t2e results of A and %. ;n t2is #ost recent exa#ple3 1e did a arit2#etic operation on an integer )alue and assigned t2e results to it: +nt .F +nt I :?

. GCB!;5;CBA7 S5A5=M=B5S

i)22th$n22$#s$ 52e pri#ar% conditional test function is t2e i)22th$n22$#s$ construct t2at 1or9s t2e sa#e as it does in an% progra##ing language. 52e s%ntax for t2is function is: i) +ondition!#=t$st th$n st!t$<$nts? $#s$ st!t$<$nts? $nd i)? 52e state#ents follo1ing th$n are executed if t2e condition is true. 52e $#s$ bloc9 is optional and used onl% if t2ere is an !#t$'n!t$ process reAuired to be done if t2e conditional result is false. ;f state#ents can be nested using an $#si) bloc9. ;n t2at case3 t2e s%ntax is: i) +ondition!# t$st th$n st!t$<$nts? $#si) +ondition!# t$st th$n st!t$<$nts? $#s$ st!t$<$nts? $nd i)? ;f a co#pound conditional is desired t2en parent2esis #a% be used to encase t2e entire conditional test section. Here is an exa#ple if..t2en..else application: +o nt . ,'o+$ss(H&!'i!"#$ +nt . int$g$' .F 9? "$gin i) (H F J:J !nd HJ#!st=&!# $ F J9J- th$n

+nt .F +nt I :? $#s$ +nt .F +nt 6 :? $nd i)? 52is code section is processed 12ene)er an e)ent occurs on H. 52e if state#ent c2ec9s to see if H is no1 1 and 1as pre)iousl% a / + HJ#!st=&!# $ F J9J.. ;f t2is is true +nt is incre#ented once. ;f t2is is false, 12ic2 #eans t2at H c2anged fro# a 1 to a /3 t2en +nt is decre#ented once. 52e final result 1ill tell t2e user 12at t2e last change 1as +a +nt )alue of 1 indicates a c2ange fro# / to 1 and a / +nt )alue indicates t2e last c2ange 1as fro# 1 to /.. Other Conditional Statements S3nt!H. (i- WHEN ELSE st!t$<$nt. id$nti)i$' GF $H,'$ssion=t' $ WHEN +ondition ELSE $H,'$ssion=)!#s$? =xa#ple: N JD A and B 8H=B S D I/I =7S= A or B> (iiid$nti)i$' GF $H,'$ssion: WHEN +ondition : ELSE $H,'$ssion1 WHEN +ondition1 ELSE $H,'$ssionD WHEN +onditionD ELSE $H,'$ssionN WHEN OTHERS?

Id$nti)i$' is !ssign$d th$ $H,'$ssion )o' th$ WHEN +ondition th!t is t' $2 =xa#ple: print1 JD user1 8H=B +en D I1I and sel D I/I. =7S= user2 8H=B +en D I1I and sel D I1I. =7S= user3 8H=B C5H=0S> CASE St!t$<$nt Syntax CASE t$st=&!' IS WHEN t$st=&!#: FK id$nti)i$' GF $H,'$ssion:? WHEN t$st=&!#1 FK id$nti)i$' GF $H,'$ssion1? WHEN t$st=&!#D FK id$nti)i$' GF $H,'$ssionD? WHEN t$st=&!#B FK id$nti)i$' GF $H,'$ssionB? WHEN t$st=&!#@ FK id$nti)i$' GF $H,'$ssion@? WHEN OTHERS FK n ##? .F <!3 "$ s$d inst$!d o) GF Condition!# t$st is don$ on !## &!# $s +on+ ''$nt#32 Assign<$nt is <!d$ )o' t' $ WHEN +ondition2 =xa#ple: 5N$= op ;S +A!!3 S'B3 M'73 !;6.> S;HBA7 op?code : op> $0CG=SS +op?code3 A3 B. B=H;B GAS= op?code ;S 8H=B A!! DM N :D A L B>

8H=B S'B DM N :D A * B> 8H=B M'7 D M N :D A K B> 8H=B !;6 DM N :D A K B> 8H=B C5H=0S DM N :D N> =B! GAS=> =B! $0CG=SS> Syntax WITH SELECT st!t$<$nt WITH t$st=&!'i!"#$ SELECT id$nti)i$' GF $H,'$ssion: WHEN t$st=&!#:( $H,'$ssion1 WHEN t$st=&!#1( $H,'$ssionD WHEN t$st=&!#D( $H,'$ssionB WHEN OTHERS? Example 8;5H S=7 S=7=G5 N JD A 8H=B R//R3 B 8H=B R/1R3 G 8H=B R1/R3 ! 8H=B R11R3 IPS 8H=B C5H=0S>

&. 7CC$S
Th$ Fo' Loo, 52e )o' #oo, is used to repeat t2e execution of a section of code for a gi)en nu#ber of ti#es. 52e general s%ntax for a for loop is:

)o' &!'i!"#$ in '!ng$ #oo, st!t$<$nts? $nd #oo,? 52e range 2as t2e sa#e for#at as t2e range used in a bit?)ector assign#ent except3 in a for state#ent3 it also defines t2e direction for t2e )alue of t2e )ariable for eac2 iteration of t2e loop +to incre#ents and do1nto decre#ents.. Here is an exa#ple: signal x : bit?)ector +& do1nto /.> 2 2 process+x. )ariable p : std?logic> begin p :D I/I> for i in & do1nto / loop p :D p xor x+i.> end loop> end process> 52e first line is a signal assign#ent not enclosed in an entit%. A local )ariable +,. is assigned 1it2in t2e process and it is initiali:ed to / 12en t2e process is begun in response to an e)ent on H. 52e eig2t bits of H are exclusi)el% C0ed 1it2 eac2 ot2er to produce t2e e)en parit% for t2e 1ord in H. 82en entering t2e loop3 i is initiali:ed to t2e first )alue in t2e range +&.. ;n t2e first iteration of t2e loop3 H(>- is OC0ed 1it2 , (9-3 t2e result is returned to ,3 and i is decre#ented. ;n t2e second iteration3 H(A- is OC0ed 1it2 , again and t2e result3 once #ore3 is returned to , and i is decre#ented again. 52is seAuence repeats until i F 92 52e last iteration3 OC0s H(9- 1it2 t2e accu#ulated result in , and exits t2e loop. 82en t2e loop is finis2ed3 , 1ill 2old t2e e)en parit% state for 1ord H.

L2

STRUCTURAL DESIGN
52e arc2itecture bloc9 defines 2o1 t2e entit% operates and can be described in #an% 1a%s3 t1o of 12ic2 are #ost pre)alent: structural and be2a)ioral +data flo1.. 8e 2a)e alread% loo9ed at t2e be2a)ior t%pe of arc2itecture. 52is section explores t2e st' +t '!# !,,'o!+h 12ic2 defines 2o1 t2e entit% is constructed * 12at logic de)ices #a9e up t2e design. 52e general for#at for t2e structural arc2itecture is: !'+hit$+t '$ !'+hit$+t '$=n!<$ o) $ntit3=n!<$ is int$'n!# int$'+onn$+ting sign!# d$+#!'!tions? +o<,on$nt (o"M$+t- d$+#!'!tions? "$gin it$'!tions (+o,i$s- o) +o<,on$nts? $nd !'+hit$+t '$=n!<$?

N2 COMPONENTS
A +o<,on$nt is created fro# an% pre)iousl% designed entit%. ;t can be declared on t2e sa#e page as t2e current design or i#ported fro# a librar%. A co#ponent defines t2e design (o"M$+t- 12ic2 can be inst!nti!t$d o' +o,i$d. As suc23 t2ere are so#e definite procedures to follo1 12en using co#ponents. 52e general s%ntax for a co#ponent declaration is: +o<,on$nt $ntit3=N!<$ ,o't (n!<$s. <od$ t3,$-? $nd +o<,on$nt? Go#ponents are related to t2e entit% t2roug2 t2e use of t2e sa#e na#e and port list. $ort signal declarations #ust be in t2e sa#e order as t2e entit% port declarations and #ust 2a)e t2e sa#e na#e3 #ode and t%pe * after all3 a co#ponent is going to be not2ing #ore t2an a reference for a copy of an entit% design. 52e content of a co#ponent bloc9 #ust #atc2 t2e content of

t2e source entit% bloc9 exactl%. Cnce t2e co#ponent is declared3 it #a% be inst!nti!t$d (+o,i$d- and reused an% nu#ber of ti#es 1it2in t2e design b% t2e use of t2is code: ,!'t=n!<$ . +o<,on$nt=n!<$ ,o't <!, (sign!#s in $H!+t o'd$'-? For an exa#ple3 1e 1ill use t2e follo1ing BC0 latc2 12ic2 is si#ilar to one in figure.

And 2ere is t2e entit% and arc2itecture bloc9s of t2e structural design: librar% ;===> use ;===.std?logic?11 4.all> ** BC0 gate entit% design entit% nor?gate is port +a3b : in std?logic> c : out std?logic.> end nor?gate> arc2itecture #%?nor of nor?gate is begin c JD a nor b>

end #%?nor> ** begin latc2 design entit% latc2 is port +s3r : in std?logic> A3nA : out std?logic.> end latc2> arc2itecture flipflop of latc2 is ** BC0 gate co#ponent declaration co#ponent nor?gate port +a3b : in std?logic> c out std?logic.> end co#ponent> begin ** instantiation of t1o BC0 gates n1 : nor?gate port #ap +r3 nA3 A.> n2 : nor?gate port #ap +s3 A3 nA.> end flipflop> A nu#ber of concepts are illustrated b% t2is exa#ple. First3 1e 2a)e t2e co#ponent declaration placed in t2e arc2itecture bloc9 preceding t2e arc2itecture bod%. ;t starts 1it2 t2e reser)e 1ord +o<,on$nt follo1ed b% t2e co#ponentIs na#e3 in t2is case * nor?gate. As 1it2 an entit%3 signals for t2e co#ponent are declared using t2e ,o't function. ;n t2is exa#ple 1e 2a)e t1o inputs3 ! and " and one output3 +. An end co#ponent state#ent co#pletes t2e declaration. 52is creates a co#ponent O%CECT. Botice t2at t2e nor?gate

co#ponent and its corresponding entit% declarations are identical except for t2e co#ponent and entit% reser)ed 1ords. 52e i#portance of t2is3 is t2at 1e 1ill declare t1o instances of t2is ob<ect3 eac2 of 12ic2 1ill inh$'it th$ ,'o,$'ti$s of t2e nor?gate co#ponent ob<ect. 52e first instance is n: and notice t2at its declaration is placed in t2e bod% of t2e arc2itecture bloc9. 52is #eans t2at t2e arc2itecture 1ants to use t2is instance for t2e latc2. ;n order to inherit nor?gate properties3 t2e signals used b% t2e instance #ust be MAPPED fro# t2e nor?gate ob<ect. 52is is acco#plis2ed using t2e ,o't <!, state#ent. 52e signals #apped #ust be in t2e sa#e order as t2e co#ponent ob<ect. ;n t2is case ' and nE in2erit t2e input function fro# ! and " of t2e nor?gate ob<ect. E gets t2e output function fro# + in t2e nor?gate co#ponent. ;n t2is si#ple exa#ple3 t2ere are no extra interconnecting signals. All connections are establis2ed using signals of t2e BC0 gate co#ponents. Here is a little different design t2at incorporates interconnecting signals bet1een co#ponents.

:92 SIGNALS.

Before 1e code t2is one3 letIs ta9e a close loo9 at t2e circuit. 52ere are four parts: t1o AB!3 one C03 and one ;B6=05=0 gate. Man% of t2e co#ponent signals are connected to external signals: Sel connected to O1 * A and O3 * A Ain to O1 * B Bin to O2 * A !out to O4 * N 52ere are also internal signal connections bet1een co#ponents 12ic2 2a)e t2e follo1ing labels: BotS * connects output of in)erter to O2 * B S1 * connects O1 * N to O4 * A S/ * connects O2 * N to O4 * B ;n a structural design3 t2e internal signals are declared using t2e SIGNAL declaration 12ic2 2as t2e s%ntax: SIGNAL . T0PE? Botice t2e lac9 of a #ode designation in t2e signal declaration. 52is is because3 t2ese are interconnecting signals bet1een co#ponents. 52is #eans t2at t2e% are connecting an output fro# one co#ponent to t2e input of anot2er. 52at alone 1ould #a9e it difficult to declare a #ode for t2e#. Secondl%3 t2e% are internal interconnecting signals. !irection is deter#ined b% existing port interface declarations of t2e entities of t2e co#ponents being connected.

For a structural design3 %ou are onl% stating 2o1 parts are connected toget2er. 52e design depends on pre)iousl% defined be2a)ior of t2e indi)idual parts 12ic2 deter#ine 2o1 t2e design 1ill 1or9. 8it2 all of t2is3 letIs code t2e design in structural description. librar% ;===> use ;===.std?logic?11 4.all> ** !efine t2ree logic co#ponents ** AB! Hate entit% #%?and is port + A3 B : in std?logic> N : out std?logic .> end #%?and> arc2itecture and?gate of #%?and is begin N JD A and B> end and?gate> ** C0 gate entit% #%?or is port + A3 B : in std?logic> N : out std?logic .> end #%?or> arc2itecture or?gate of #%?or is begin N JD A or B> end or?gate> ** ;n)erter gate

entit% #%?in) is port + A : in std?logic> N : out std?logic .> end #%?in)> arc2itecture in)?gate of #%?in) is begin N JD not A> end in)?gate> ** Start 2*bit #ultiplexor entit% #%?#ux is port + Sel3 Ain3 Bin : in std?logic> !out : std?logic .> end #%?#ux> arc2itecture #ux?c9t of #%?#ux is ** signal declarations signal S/3 S13 BotS : std?logic> ** co#ponent declarations co#ponent #%?and is port + A3 B : in std?logic> N : out std?logic .> end co#ponent> co#ponent #%?or is port + A3 B : in std?logic> N : out std?logic .> end co#ponent>

co#ponent #%?in) is port + A : in std?logic> N : out std?logic .> end co#ponent> ** structural design bod% begin O1 : #%?and port #ap + Sel3 Ain3 S1 .> O2 : #%?and port #ap + Bin3 BotS3 S/ .> O3 : #%?in) port #ap + Sel3 BotS .> O4 : #%?or port #ap + S13 S/3 !out .> end #ux?c9t> 52e design begins b% defining t2ree logic gates3 #%?and3 #%?or3 and #%?in) for AB!3 C03 and ;B6=05=0 gates. All t2ree of t2ese gates could also 2a)e been i#ported fro# a librar% file. 52is design includes t2e t2ree entit% designs for t2e logic gates. =ac2 arc2itecture of t2e gate designs is in be2a)ior or data flo1 for#. 52at is t2e be2a)ior of t2e gate is described for eac2. ;n t2e arc2itecture bloc9 t2ere are se)eral declarations #ade before t2e beginning of t2e bod% portion. 52e first declares t2e internal signals used in t2e design. Since 6H!7 is 2ierarc2ical in nature3 t2ese signal declarations 2a)e to #ade before t2e co#ponent instantiations t2at use t2e#. 52e re#aining declarations define t2e co#ponents used b% t2e

arc2itecture.After t2eir declarations starts t2e bod% of t2e arc2itecture bloc9 designated b% t2e begin reser)e 1ord. 7oo9 at t2e si#plicit% of t2is part of t2e design. ;ts onl% a list of co#ponents and 2o1 signals are connected to t2e#. X: and X1 are copies of #%?and3 XD of #%?in)3 and XB of #%?or. Botice t2at t2e port #ap signals are in t2e sa#e order as t2e co#ponent and entit% port declarations. Suppose %ou do not 9no1 t2e order. 52ere is a 1a% around t2at

9no1n as DIRECT ASSOCIATION 12ic2 does reAuire3 #ini#all%3 t2at %ou 9no1 t2e port signal na#es and t2eir intended use. Here is an alternate 1a% of instantiating X: as #%?and: X: . <3=!nd ,o't <!, (A FK S$#( 0 FK S:(% FK Ain -? 52e order of t2e port #ap list no longer #atters since eac2 indi)idual signal relations2ip is defined indi)iduall%.

::2 MODULAR DESIGN

Bo1 t2at #%?#ux is co#pleted3 it can be used as a co#ponent or MODULE in a larger design3 sa% an 8*bit #ultiplexor.

Basicall%3 <ust continue 1it2 t2e #ux design b% adding a ne1 entit%: entit% eig2t?#ux is port + Ain3 Bin : in std?logic?)ector +& do1nto / .>

!out : out std?logic?)ector + & do1nto / .> Sel : in std?logic .> end eig2t?#ux> arc2itecture #ultiplex of eig2t?#ux is ** declare #%?#ux co#ponent co#ponent #%?#ux is port #ap + Ain3 Bin3 Sel : in std?logic> !out : out std?logic .> end co#ponent> ** instantiate #%?#ux co#ponent eig2t ti#es begin M& : #%?#ux port #ap + Ain+&.3 Bin+&.3 Sel3 !out+&. .> M : #%?#ux port #ap + Ain+ .3 Bin+ .3 Sel3 !out+ . .> M" : #%?#ux port #ap + Ain+".3 Bin+".3 Sel3 !out+". .> M4 : #%?#ux port #ap + Ain+4.3 Bin+4.3 Sel3 !out+4. .> M3 : #%?#ux port #ap + Ain+3.3 Bin+3.3 Sel3 !out+3. .> M2 : #%?#ux port #ap + Ain+2.3 Bin+2.3 Sel3 !out+2. .> M1 : #%?#ux port #ap + Ain+1.3 Bin+1.3 Sel3 !out+1. .> M/ : #%?#ux port #ap + Ain+/.3 Bin+/.3 Sel3 !out+/. .> end eig2t?#ux>

AN APPROACH TO FPGA IMPLEMENTATION WITH QUARTUS II SOFTWARE

52e follo1ing steps 1ill 2elp to use Quartus ;; soft1are for )arious issues related to F$HA ;#ple#entation. Step 1: As soon as t2e Quartus ;; soft1are is opened after necessar% license file ;nstallations3 a Be1 $ro<ect 2as to be created. Step 2: 52e Be1 $ro<ect can be created fro# Fi#$ 6K N$* P'oM$+t Wi7!'d. A 1indo1 1ill be opened after selcting Be1 $ro<ect 1i:ard. ;n t2is 1indo13 8or9ing director% of t2e $ro<ect and $ro<ect Ba#e 2a)e to be #entioned. 52e target de)ice also 2as to be selected at t2is stage. ;n t2e present lab3 A#t$'! C3+#on$ II FPGA EP1C19FBLBC> 1ill be used for 2ard1are i#ple#entation. So t2is F$HA can be selected as 52is F$HA is present in !e)elop#ent @ =ducation +!=1. Board. Step 3: 52e !esign =ntr%4S%nt2esis3 Si#ulation and 5i#ing Anal%sis =!A tools 2a)e to be specified in t2e =!A tools settings page of Be1 $ro<ect 8i:ard. Step 4:: A ne1 6H!7 file 2as to be created fro# Fi#$ 6K N$* 6KVHDL )i#$. After creating a ne1 6H!7 file and upon co#pleting t2e coding 3 it 2as to be sa)ed. Ma9e sure t2at t2e entit% na#e of t2e file and filena#e are sa#e. Bo1 t2e file 1ould be present in t2e Files section of t2e $ro<ect Ba)igator 1indo1. Step ": 0ig2tclic9 t2e file and select t2e Set as top le)el entit% option fro# t2e list of options. Bo1 1e can see t2e file in t2e #ain page of t2e $ro<ect Ba)igator 1indo1. Step " : After co#pleting t2e 6H!7 coding3 t2e file 2as to be s%nt2esi:ed. S%nt2esis is t2e process of con)erting one for# of 2ard1are description to t2e ot2er. 52e result of a s%nt2esis process is Hard1are Betlist. 52e s%nt2esis can be perfor#ed b% c2oosing t2e option fro# P'o+$ssing 6K st!'t 6K St!'t An!#3sis O S3nth$sis.

Step : After correcting errors if an%3 t2e ;4C pins 2a)e to be specified fro# $in $lanner 12ic2 is a)ailable in Assign#ents toolbar. As soon as t2e s%nt2esis process is o)er3 t2e pin planner 1ill contain t2e list of all pins present in t2e entit% of t2e design. Step &: 52e design 2as to be Go#piled. 52is can be perfor#ed b% c2oosing t2e option Start Go#pilation fro# $rocessing toolbar +ie. P'o+$ssing 6K St!'t Co<,i#!tion2 Step 8: After successful co#pilation3 t2e design is no1 read% for 2ard1are i#ple#entation. 'SB Blaster is used for F$HA progra##ing. 52e !=1 board does not reAuire additional po1er source for progra##ing. ;t can ta9e t2e po1er fro# 'SB cable itself. 52e Altera 'SB Blaster 2as to be installed during t2e first ti#e of progra##ing t2e de)ice. ;n subseAuent de)ice progra##ing3 t2e Altera 'SB Blaster 1ill be auto#aticall% recogni:ed b% t2e s%ste# +$G.. 52e progra##ing #ode is ,5AH. 52e progra##er can be selected fro# 5ools toolbar +ie. Too#s 6K P'og'!<<$'2 Step (: A .sof file +S0AM Cb<ect File. 1ould be auto#aticall% created after Successful co#pilation of t2e design. ;t is better to ensure t2at t2e 2ard1are setup contains 'SB Blaster +'SB */.. Start Button can be pressed for progra##ing t2e deisgn into F$HA. ;f a ne1 .sof file 2as to be progra##ed3 Add file option can be used. Step1/: Bo1 t2e design in F$HA is read% for c2ec9ing TTTT Not$. For $in !etails3 refer !=1 'ser Manual.

LIST OF EXPERIMENTS

VHDL Coding (With suitable Behavioral Data !lo" and Stru#tural Des#riptions$ !or%
Basic gates 1. Half Adder and Half Subtractor 2. Full Adder and Full Subtractor 3. 8:1 Multiplexer 4. 4:1 !ecoder ". Four bit co#parator using single bit co#parator . 8:3 $riorit% encoder &. Four bit adders 8. Signed and 'nsigned #ultiplier (. Master sla)e flip*flop+! t%pe and ,*- t%pe. 1/. Four bit 0ipple counter and 'p*do1n counter 11. 'ni)ersal s2ift register 12. State #ac2ine #odelling of Meela% #ac2ine and Moore #ac2ine.

PRELIMINAR0 EXPERIMENT %ASIC LOGIC GATES D!t$. AIM. 5o 1rite 6H!7 progra#s to i#ple#ent t2e follo1ing logic gates. +a. BC5 +b. 2 input C0 +c. 2 input BC0 +d. 2 input AB! +e. 2 input BAB! +f. 2 input OC0 +g. 2 input OBC0. ALGORITHM. 1. 2. 3. 4. ". . &. 8. (. Start t2e progra#. ;nclude t2e ;=== librar% and t2e std?logic?11 4.all pac9age. !eclare t2e entit% of t2e gate. !efine t2e input and t2e output ports =nd t2e entit%. !eclare t2e arc2itecture of t2e gate. !efine t2e functionalit% of t2e gate at be2a)ioral le)el . =nd t2e arc2itecture. 7oad t2e design3 si#ulate t2e 1a)efor#3 and )erif% t2e trut2*table.

LOGIC DIAGRAMS AND TRUTH TA%LES OF %ASIC GATES

PORT DIAGRAM

a. ;n)erter

b.2 ;nput logic gates

PROGRAMS. !2 In&$'t$' librar% ieee> use ieee.std?logic?11 4.all> entit% in) is port+x: in std?logic> F: out std?logic.> end in)>

arc2itecture in)?be2 of in) is begin F JD not x> end in)?be2>

"2 1 In, t OR g!t$ librar% ieee> use ieee.std?logic?11 4.all> entit% C0?ent is port+x: in std?logic> %: in std?logic> F: out std?logic.> end C0?ent> arc2itecture C0?be2 of C0?ent is begin F JD x or %> end C0?be2> +2 1 In, t NOR g!t$ librar% ieee> use ieee.std?logic?11 4.all> entit% BC0?ent is port+x: in std?logic> %: in std?logic> F: out std?logic.> end BC0?ent> arc2itecture be2)2 of BC0?ent is begin

F JD x nor %> end be2)2> d21 In, t AND g!t$ librar% ieee> use ieee.std?logic?11 4.all> entit% AB!?ent is port+x: in std?logic> %: in std?logic> F: out std?logic.> end AB!?ent> arc2itecture be2a)2 of AB!?ent is begin F JD x and %> end be2a)2> $21 In, t NAND g!t$ librar% ieee> use ieee.std?logic?11 4.all> entit% BAB!?ent is port+x: in std?logic> %: in std?logic> F: out std?logic.> end BAB!?ent> arc2itecture be2)2 of BAB!?ent is begin F JD x nand %> end be2)2> )21 In, t XOR g!t$

librar% ieee> use ieee.std?logic?11 4.all> entit% OC0?ent is port+x: in std?logic> %: in std?logic> F: out std?logic.> end OC0?ent> arc2itecture be2)2 of OC0?ent is begin F JD x xor %> end be2)2> g21 In, t XNOR g!t$ librar% ieee> use ieee.std?logic?11 4.all> entit% OBC0?ent is port+x: in std?logic> %: in std?logic> F: out std?logic.> end OBC0?ent> arc2itecture be2)2 of OBC0?ent is begin F JD x xnor %> end be2)2> W!&$)o'<s. In&$'t$'

1 In, t OR g!t$

1 In, t NOR g!t$

1 In, t AND g!t$

1 In, t NAND g!t$

1 In, t XOR

1 In, t XNOR g!t$

RESULT. 52e basic logic gates 1ere si#ulated in MODELSIM and t2e corresponding trut2 tables )erified. NOTE. 0ecord boo9 s2ould be #aintained in t2e follo1ing for#at. a. =xperi#ent Bu#ber b. !ate c. Ai# of t2e experi#ent d. Algorit2# e. 7ogic diagra# f. 5rut2 table g. $ort diagra# 2. 7isting of t2e progra# i. <. 8a)efor#s 0esult

52e abo)e #entioned for#at s2ould be strictl% follo1ed for all t2e experi#ents. +see preli#inar% experi#ent for reference.

52e students are expected to co#plete t2e acti)ities #entioned.

HALF ADDER AND HALF SU%TRACTOR EH,$'i<$nt No. : D!t$. AIM. 5o 1rite 6H!7 progra#s to i#ple#ent t2e h!#) !dd$' at be2a)ioral le)el using i)6 $#s$ and *ith s$#$+t state#ents3 and h!#) s "t'!+to' using *h$n6$#s$ and +!s$6 *h$n state#ents. ALGORITHM. 1. 2. 3. 4. Start t2e progra# ;nclude t2e ;=== librar% and t2e std?logic?11 4.all pac9age. !eclare t2e entit% for t2e 2alf adder42alf subtractor . !efine t2e input and t2e output ports

". . &.

=nd t2e entit% . !eclare t2e arc2itecture of 2alf adder42alf subtractor. !efine t2e functionalit% of 2alf adder and 2alf subtractor at be2a)ioral le)el using if*else3 1it2*select and case*12en3 12en*else state#ents respecti)el%.

8. (.

=nd t2e arc2itecture. 7oad t2e design3 si#ulate t2e 1a)efor#3 and )erif% t2e trut2*table.

PROGRAMS. !- H!#) !dd$' sing i)6th$n. entit% 2alfadder is port+ a:in std?logic?)ector+1 do1nto /.>su#3carr%: out std?logic.> end 2alfadder> arc2itecture 2alfadder?arc2 of 2alfadder is signal s:std?logic?)ector+1 do1nto /.> begin process+a. begin if aDF//F t2en sJDF//F> elsif aDF/1F t2en sJDF1/F> elsif aDF1/F t2en sJDF1/F> else sJDF/1F> end if> end process> carr%JDs+/.> su#JDs+1.> end> "- H!#) !dd$' sing *ith s$#$+t st!t$<$nt.

entit% 2alfadder1 is port+ a:in std?logic?)ector+1 do1nto /.>su#3carr%: out std?logic.> end 2alfadder1> arc2itecture 2alfadder?arc2 of 2alfadder1 is signal s:std?logic?)ector+1 do1nto /.> begin 1it2 a select sJD E//F 12en E//F3 E1/F 12en E/1F3 E1/F 12en E1/F3 E/1F 12en E11F> carr%JDs+/.> su#JDs+1.> end> !- H!#) S "t'!+to' sing +!s$ *h$n st!t$<$nts. entit% 2alfsub is port+ a:in std?logic?)ector+1 do1nto /.>d3b: out std?logic.> end 2alfsub> arc2itecture 2alfsub?arc2 of 2alfsub is signal s:std?logic?)ector+1 do1nto /.> begin process+a. begin case a is 12en E//FDMsJDF//F> 12en E/1FDMsJDF11F> 12en E1/FDMsJDF1/F> 12en E11FDMsJDF//F> 12en ot2ersDMnull>

end case> end process> bJDs+/.> dJDs+1.> end> "- H!#) S "t'!+to' sing *h$n $#s$ st!t$<$nts. entit% 2alfsub1 is port+ a:in std?logic?)ector+1 do1nto /.>d3b: out std?logic.> end 2alfsub1> arc2itecture 2alfsub?arc2 of 2alfsub1 is signal s:std?logic?)ector+1 do1nto /.> begin sJDF//F 12en aDF//F else E11F 12en aDF/1F else E1/F 12en aDF1/F else E//F> bJDs+/.> dJDs+1.> end>

RESULT.

ACTIVIT0 . 1. 8rite t2e 6H!7 coding for reali:ing t2e function of 2alf adder using 2 input BAB! gates and )erif% t2e result. 2. 8rite t2e 6H!7 coding for reali:ing t2e function of 2alf adder using 2 input BC0 gates and )erif% t2e result. 3. 8rite a 6H!7 coding for coding for 2alf subtractor using 2 input BAB! gates and )erif% t2e result. 'se #ini#u# nu#ber of BAB! gates. 4. 8rite a 6H!7 coding for coding for 2alf subtractor using 2 input BAB! gates and )erif% t2e result. 'se #ini#u# nu#ber of BC0 gates.

FULL ADDER !nd FULL SU%TRACTOR EH,$'i<$nt No. 1 D!t$. AIM. 5o 1rite 6H!7 progra#s to i#ple#ent t2e ) ## !dd$' and ) ## s "t'!+to' at be2a)ioral le)el using i)6$#s$( *ith s$#$+t state#ents. ALGORITHM. 1. 2. 3. 4. Start t2e progra#. ;nclude t2e ;=== librar% and t2e std?logic?11 4.all pac9age. !eclare t2e entit% for t2e full adder. !efine t2e input and t2e output ports for t2e full adder.

". . &. 8. (. 1/. 11 12. 13. 14. 1".

=nd t2e entit%. !eclare t2e arc2itecture of full adder. !efine t2e functionalit% of full adder at be2a)ioral le)el using if*else3 1it2*select state#ents. =nd t2e arc2itecture. !eclare t2e entit% for t2e full subtractor. !efine t2e input and t2e output ports for t2e full subtractor. =nd t2e entit%. !eclare t2e arc2itecture of full subtractor. !efine t2e functionalit% of full subtractor at be2a)ioral le)el using if* else3 1it2*select state#ents. =nd t2e arc2itecture. 7oad t2e designs3 si#ulate t2e 1a)efor#s3 and )erif% t2e trut2*tables.

PROGRAMS . !- F ## !dd$' sing i) th$n $#s$. entit% fulladder is port+ a:in std?logic?)ector+2 do1nto /.>su#3carr%: out std?logic.> end fulladder> arc2itecture fulladder?arc2 of fulladder is signal s:std?logic?)ector+1 do1nto /.> begin process+a. begin if aDF///F t2en sJDF//F> elsif aDF//1F t2en sJDF1/F> elsif aDF/1/F t2en sJDF1/F> elsif aDF/11F t2en sJDF/1F>

elsif aDF1//F t2en sJDF1/F> elsif aDF1/1F t2en sJDF/1F> elsif aDF11/F t2en sJDF/1F> else sJDF11F> end if> end process> carr%JDs+/.> su#JDs+1.> end> "- F ## Add$' sing *ith s$#$+t st!t$<$nt. entit% fulladder1 is port+ a:in std?logic?)ector+2 do1nto /.>su#3 carr%: out std?logic.> end fulladder1> arc2itecture fulladder?arc2 of fulladder1 is signal s:std?logic?)ector+1 do1nto /.> begin 1it2 a select sJD E//F 12en E///F3 E1/F 12en E//1F3 E1/F 12en E/1/F3 E/1F 12en E/11F3 E1/F 12en E1//F3 E/1F 12en E1/1F3 E/1F 12en E11/F3 E11F 12en E111F> carr%JDs+/.> su#JDs+1.> end>

+- F ## S "t'!+to' sing i) th$n $#s$.

entit% fullsub is port+ a:in std?logic?)ector+2 do1nto /.>d3b: out std?logic.> end fullsub> arc2itecture fullsub?arc2 of fullsub is signal s:std?logic?)ector+1 do1nto /.> begin process+a. begin if aDF///F t2en sJDF//F> elsif aDF//1F t2en sJDF11F> elsif aDF/1/F t2en sJDF11F> elsif aDF/11F t2en sJDF/1F> elsif aDF1//F t2en sJDF1/F> elsif aDF1/1F t2en sJDF//F> elsif aDF11/F t2en sJDF//F> else sJDF11F> end if> end process> bJDs+/.> dJDs+1.> end>

d- F ## S "t'!+to' sing *ith s$#$+t. entit% fullsub1 is port+ a:in std?logic?)ector+2 do1nto /.>d3b: out std?logic.> end fullsub1> arc2itecture fullsub?arc2 of fullsub1 is signal s:std?logic?)ector+1 do1nto /.>

begin 1it2 a select sJD E//F 12en E///F3 E11F 12en E//1F3 E11F 12en E/1/F3 E/1F 12en E/11F3 E1/F 12en E1//F3 E//F 12en E1/1F3 E//F 12en E11/F3 E11F 12en E111F> bJDs+/.> dJDs+1.> end>

RESULT.

ACTIVIT0. 1. 8rite t2e 6H!7 coding for reali:ing t2e function of full adder using 2 input BAB! gates and )erif% t2e result. 2. 8rite t2e 6H!7 coding for reali:ing t2e function of full adder using 2 input BC0 gates and )erif% t2e result. 3. 8rite a 6H!7 coding for a single bit full adder using 2 2alf adders and )erif% t2e result. 'se structural le)el of #odeling. 4. 8rite t2e 6H!7 coding for reali:ing t2e function of full subtractor using 2 input BAB! gates and )erif% t2e result. ". 8rite t2e 6H!7 coding for reali:ing t2e function of full subtractor using 2 input BC0 gates and )erif% t2e result.

. 8rite t2e 6H!7 coding in structural #odel to design t2e follo1ing co#binational circuits. Also tabulate t2e trut2 table for all co#binations of inputs. Gircuit 1:

Gircuit 2:

Gircuit 3:

L.: MULTIPLEXER EH,$'i<$nt No. D D!t$. AIM. 5o 1rite a 6H!7 progra# to i#ple#ent a L.: < #ti,#$H$' at t2e be2a)ioral le)el using +!s$ *h$n state#ent. ALGORITHM. 1. 2. 3. 4. ". Start t2e progra#. ;nclude t2e ;=== librar% and t2e std?logic?11 4.all pac9age. !eclare t2e entit% for t2e 8:1 #ultiplexer . !efine t2e input and t2e output ports. =nd t2e entit%.

. &. 8. (. PROGRAM.

!eclare t2e arc2itecture of. 8:1 #ultiplexer. !efine t2e functionalit% of 8:1 #ultiplexer at be2a)ioral le)el . =nd t2e arc2itecture. 7oad t2e design3 si#ulate t2e 1a)efor#3 and )erif% t2e trut2*table.

librar% ieee> use ieee.std?logic?11 4.all> entit% Mux is port+;: in std?logic?)ector+& do1nto /.> Sel:in std?logic?)ector+2 do1nto /.> C:out std?logic.> end Mux> arc2itecture be2)1 of Mux is begin process+;3Sel. begin case Sel is 12en R///R DM C JD ;+/.> 12en R//1R DM C JD ;+1.> 12en R/1/R DM C JD ;+2.> 12en R/11R DM C JD ;+3.> 12en R1//R DM C JD ;+4.> 12en R1/1R DM C JD ;+".> 12en R11/R DM C JD ;+ .> 12en R111R DM C JD ;+&.> 12en ot2ers DM C JD UPS> end case> end process> end be2)1>

RESULT.

ACTIVIT0. 1. 8rite a 6H!7 coding for 8:1 Multiplexer using +i.1it2 select +ii. 12en else state#ents. ;#ple#ent 1 :1 Multiplexer using 8:1 Multiplexer 2. 8rite a 6H!7 coding for reali:ing F+x3%3:.D + t2e result. 3. 8rite a 6H!7 coding for reali:ing t2e function of 2alf adder using 2:1 #ultiplexer and )erif% t2e result. 4. 8rite a 6H!7 coding for reali:ing t2e function of 2alf subtractor using 2:1 #ultiplexer. ". 8rite a 6H!7 coding to reali:e full adder using 4:1 Multiplexer. . 8rite a 6H!7 coding for reali:ing F+A3B3G3!.D V+ 1333431131231331431" . using 4:1 M'O and )erif% t2e result . B.:A DECODER EH,$'i<$nt No. B D!t$. AIM. 5o 1rite 6H!7 progra# to i#ple#ent a B.:A d$+od$' at t2e be2a)ioral le)el using +!s$ *h$n state#ent . .using 4:1 M'O and )erif%

ALGORITHM. 1. 2. 3. 4. Start t2e progra#. ;nclude t2e ;=== librar% and t2e std?logic?11 4.all pac9age. !eclare t2e entit% for t2e decoder. !efine t2e input and t2e output ports.

". . &. 8. (.

=nd t2e entit%. !eclare t2e arc2itecture of decoder. !efine t2e functionalit% of decoder at be2a)ioral le)el. =nd t2e arc2itecture. 7oad t2e design3 si#ulate t2e 1a)efor#3 and )erif% t2e trut2*table.

PROGRAMS. !- Using +!s$P*h$n st!t$<$nt o'din!'3 <$thod. librar% ieee> use ieee.std?logic?11 4.all> entit% decoder is port+;:in std?logic?)ector+3 do1nto /.> C:out std?logic?)ector+1" do1nto /..> end decoder> arc2itecture be2) of decoder is begin process +;. begin case ; is 12en R////R DM C JD R///////////////1R> 12en R///1R DM C JD R//////////////1/R> 12en R//1/R DM C JD R/////////////1//R> 12en R//11R DM C JD R////////////1///R> 12en R/1//R DM C JD R///////////1////R> 12en R/1/1R DM C JD R//////////1/////R> 12en R/11/R DM C JD R/////////1//////R> 12en R/111R DM C JD R////////1///////R> 12en R1///R DM C JD R///////1////////R> 12en R1//1R DM C JD R//////1/////////R>

12en R1/1/R DM C JD R/////1//////////R> 12en R1/11R DM C JD R////1///////////R> 12en R11//R DM C JD R///1////////////R> 12en R11/1R DM C JD R//1/////////////R> 12en R111/R DM C JD R/1//////////////R> 12en R1111R DM C JD R1///////////////R> 12en ot2ers DMnull> end case> end process> end be2)> "- Loo8 , t!"#$ A,,'o!+h. librar% ieee> use ieee.std?logic?11 4.all> use ieee.std?logic?arit2.all> entit% decoder4x1 is port+din : in std?logic?)ector+3 do1nto /.> dout : out std?logic?)ector+1" do1nto /..> end decoder4x1 > arc2itecture be2a)ioral of decoder4x1 is t%pe arra%?t%pe is arra%+1" do1nto /. of std?logic?)ector+1" do1nto /.> signal decodeout : arra%?t%pe :D +R1///////////////R3 R/1//////////////R3 R//1/////////////R3 R///1////////////R3 R////1///////////R3 R/////1//////////R3R//////1/////////R3 R///////1////////R3 R////////1///////R3R/////////1//////R3R/////////1//////R3 R///////////1////R3R////////////1///R3R/////////////1//R3 R//////////////1/R3R///////////////1R. > **52e order of arrange#ent of output )alues in 7'5 is )er% i#portant. begin process+din. begin

case din is 12en R////R DM dout JD decodeout+/.> 12en R///1R DM dout JD decodeout+1.> 12en R//1/R DM dout JD decodeout+2.> 12en R//11R DM dout JD decodeout+3.> 12en R/1//R DM dout JD decodeout+4.> 12en R/1/1R DM dout JD decodeout+".> 12en R/11/R DM dout JD decodeout+ .> 12en R/111R DM dout JD decodeout+&.> 12en R1///R DM dout JD decodeout+8.> 12en R1//1R DM dout JD decodeout+(.> 12en R1/1/R DM dout JD decodeout+1/.> 12en R1/11R DM dout JD decodeout+11.> 12en R11//R DM dout JD decodeout+12.> 12en R11/1R DM dout JD decodeout+13.> 12en R111/R DM dout JD decodeout+14.> 12en R1111R DM dout JD decodeout+1".> 12en ot2ers DM dout JD +ot2ers DMI/I.> end case> end process> end be2a)ioral>

RESULT.

ACTIVIT0. 1. 8rite a 6H!7 coding for 3:8 decoder using +i.;f else +ii. 12en else state#ents. Also i#ple#ent 4:1 decoder using 3:8 decoder. 2. 8rite a 6H!7 coding for 2:4 decoder using case 12en state#ent. Also i#ple#ent 4:1 decoder using 2:4 decoder. 3. 8rite 6H!7 codings for 2:4 decoder and 3:8 decoder using loo9up table #et2od. Fo ' "it +o<,!'!to' sing Sing#$ "it +o<,!'!to' EH,$'i<$nt No. @ D!t$. AIM. 5o 1rite 6H!7 progra# to i#ple#ent a )o ' "it +o<,!'!to' at t2e be2a)ioral le)el using i)6$#s$ state#ents. ALGORITHM. 1. 2. 3. 4. ". . Start t2e progra#. ;nclude t2e ;=== librar% and t2e std?logic?11 4.all pac9age. !eclare t2e entit% for t2e co#parator. !efine t2e input and t2e output ports. =nd t2e entit%. !eclare t2e arc2itecture of co#parator.

&. 8. (.

!efine t2e functionalit% of co#parator at be2a)ioral le)el using if*else state#ents. =nd t2e arc2itecture. 7oad t2e design3 si#ulate t2e 1a)efor#3 and )erif% t2e trut2*table.

PROGRAM. librar% ieee> use ieee.std?logic?11 4.all> entit% co#parator is generic+n: natural :D4.> port+A:in std?logic?)ector+n*1 do1nto /.> B:in std?logic?)ector+n*1 do1nto /.> less:out std?logic> eAual:out std?logic> greater:out std?logic.> end co#parator> arc2itecture be2) of Go#parator is begin process+A3B. begin if +AJB. t2en less JD I1I> eAual JD I/I> greater JD I/I> elsif +ADB. t2en less JD I/I> eAual JD I1I> greater JD I/I> else less JD I/I> eAual JD I/I>

greater JD I1I> end if> end process> end be2)> RESULT.

ACTIVIT0. 1.8rite a 6H!7 coding for reali:ing 1 bit co#parator using BAB! gates and )erif% t2e result. Also i#ple#ent 4 bit co#parator fro# t2e lo1 le)el design. 'se For generate s%ntax for reali:ing t2e top le)el progra#. 2.8rite a 6H!7 coding for reali:ing 1 bit co#parator using BC0 gates and )erif% t2e result. Also i#ple#ent 4 bit co#parator fro# t2e lo1 le)el design. 'se ;F generate s%ntax for reali:ing t2e top le)el progra#. L.D PRIORIT0 ENCODER EH,$'i<$nt No. A D!t$. AIM. 5o 1rite a 6H!7 progra# to i#ple#ent a L.D ,'io'it3 $n+od$' at t2e be2a)ioral le)el. ALGORITHM. 1. 2. 3. 4. Start t2e progra#. ;nclude t2e ;=== librar% and t2e std?logic?11 4.all pac9age. !eclare t2e entit% for t2e priorit% encoder . !efine t2e input and t2e output ports.

". . &. 8. (.

=nd t2e entit%. !eclare t2e arc2itecture of priorit% encoder. !efine t2e functionalit% of priorit% encoder at be2a)ioral le)el. =nd t2e arc2itecture. 7oad t2e design3 si#ulate t2e 1a)efor#3 and )erif% t2e trut2*table.

PROGRAM: librar% ieee> use ieee.std?logic?11 4.all> entit% priorit% is port + 1 : ;n std?logic?)ector+& do1nto /.> % : Cut std?logic?)ector+2 do1nto /..> end priorit%> arc2itecture be2a)ior of priorit% is begin % JDR111R 12en 1+&. D I1I else R11/R 12en 1+ . D I1I else R1/1R 12en 1+". D I1I else R1//R 12en 1+4. D I1I else R/11R 12en 1+3. D I1I else R/1/R 12en 1+2. D I1I else R//1R 12en 1+1. D I1I else R///R> end be2a)ior>

RESULT.

ACTIVIT0. 1. 8rite a 6H!7 coding for 8:3 priorit% encoder. Hi)e priorit% to ????? bit. 2. 8rite a 6H!7 code for i#ple#enting 4:2 encoder using i.case..12en and ii. if..t2en..else state#ents 3. 8rite a 6H!7 code for i#ple#enting 8:3 encoder using structural #odel. FOUR %IT ADDER EH,$'i<$nt No. > D!t$. AIM. 5o 1rite a 6H!7 progra# to i#ple#ent a )o ' "it 'i,,#$ +!''3 !dd$' using single bit full adder. ALGORITHM. 1. 2. 3. 4. ". . Start t2e progra#. ;nclude t2e ;=== librar% and t2e std?logic?11 4.all pac9age. !eclare t2e entit% for t2e lo1er le)el +single bit full adder. . !efine t2e input and t2e output ports. =nd t2e entit% for t2e lo1er le)el. !eclare t2e arc2itecture of. lo1er le)el.

&. 8. (. 1/. 11. 12. 13. 14. 1". PROGRAMS.

!efine t2e functionalit% of lo1er le)el at be2a)ioral le)el . =nd t2e arc2itecture for t2e lo1er le)el. !eclare t2e entit% for t2e four bit ripple carr% adder . !efine t2e input and t2e output ports for t2e four bit ripple carr% adder. =nd t2e entit%. !eclare t2e arc2itecture of t2e four bit ripple carr% adder !efine t2e functionalit% of t2e four bit ripple carr% adder at a structural le)el using t2e lo1er le)el single bit full adder. =nd t2e arc2itecture. 7oad t2e design3 si#ulate t2e 1a)efor#3 and )erif% t2e trut2*table.

!-Sing#$ "it ) ## !dd$'. entit% fulladd is port+ a:in std?logic?)ector+2 do1nto /.>su#3carr%: out std?logic.> end fulladd> arc2itecture fulladder?arc2 of fulladd is signal s:std?logic?)ector+1 do1nto /.> begin process+a. begin if aDF///F t2en sJDF//F> elsif aDF//1F t2en sJDF1/F> elsif aDF/1/F t2en sJDF1/F> elsif aDF/11F t2en sJDF/1F> elsif aDF1//F t2en sJDF1/F> elsif aDF1/1F t2en sJDF/1F> elsif aDF11/F t2en sJDF/1F> else sJDF11F> end if> end process>

carr%JDs+/.> su#JDs+1.> end> "- Fo ' "it 'i,,#$ +!''3 !dd$' sing i)6g$n$'!t$. librar% ieee > use ieee.std?logic?11 4.all > entit% adder4 is port + x3 % : in std?logic?)ector+3 do1nto /. > cin : in std?logic > s : out std?logic?)ector+3 do1nto /. >cout : out std?logic . > end adder4 > arc2itecture structure of adder4 is signal c : std?logic?)ector+/ to 4. > begin c+/. JD cin > g1:for i in / to 3 generate stages: fulladder port #ap +x+i.3 %+i.3 c+i.3 s+i.3 c+iL1.. > end generate> cout JD c+4. > end structure > +- Fo ' "it !dd$' sing st' +t '!# <od$#. librar% ieee > use ieee.std?logic?11 4.all > entit% adder4 is port + x3 % : in std?logic?)ector+3 do1nto /. > cin : in std?logic > s : out std?logic?)ector+3 do1nto /. > cout : out std?logic . > end adder4 > arc2itecture structure of adder4 is signal c : std?logic?)ector+1 to 3. >

begin stage/: fulladd port #ap + x+/.3 %+/.3 cin3 s+/.3 c+1. . > stage1: fulladd port #ap + x+1.3 %+1.3 c+1.3s+1.3 c+2. . > stage2: fulladd port #ap + x+2.3 %+2.3 c+2.3s+2.3 c+3. . > stage3: fulladd port #ap + x+3.3 %+3.3 c+3.3s+3.3 cout . > end structure > RESULT.

ACTIVIT0. 1. 8rite a 6H!7 coding for BG! adder circuit and )erif% t2e result . 2. 8rite a 6H!7 coding for carr% propagate adder circuit and )erif% t2e result . 3. 8rite a 6H!7 coding for 8 bit adder using 8 single bit full adder. 'se For generate s%ntax for t2e top le)el design. ;#ple#ent full adder using ????????state#ent. SIGNED AND UNSIGNED MULTIPLIERS EH,$'i<$nt No. L D!t$. AIM. 5o 1rite a 6H!7 progra# to i#ple#ent a T*o "it "in!'3 < #ti,#i$' at t2e be2a)ioral le)el.

ALGORITHM. 1. 2. Start t2e progra#. ;nclude t2e ;=== librar% and t2e std?logic?11 4.all3 std?logic?arit2.all3 std?logic?unsigned.all pac9ages.

3. 4. ". . &. 8. (. PROGRAM.

!eclare t2e entit% for t2e t1o bit binar% #ultiplier . !efine t2e input and t2e output ports. =nd t2e entit%. !eclare t2e arc2itecture for t2e t1o bit binar% #ultiplier. !efine t2e functionalit% for t2e t1o bit binar% #ultiplier. =nd t2e arc2itecture. 7oad t2e design3 si#ulate t2e 1a)efor#3 and )erif% t2e trut2*table.

librar% ieee> use ieee.std?logic?11 4.all> use ieee.std?logic?arit2.all> use ieee.std?logic?unsigned.all> entit% #ultiplier is port+nu#13 nu#2:in std?logic?)ector+1 do1nto /.> product: out std?logic?)ector+3 do1nto /..> end #ultiplier> arc2itecture be2) of #ultiplier is begin process+nu#13 nu#2. )ariable nu#1?reg: std?logic?)ector+2 do1nto /.> )ariable product?reg: std?logic?)ector+" do1nto /.> begin nu#1?reg :D I/I @ nu#1> product?reg :D R////R @ nu#2> ** algorit2# is to repeat s2ifting4adding for i in 1 to 3 loop if product?reg+/.DI1I t2en product?reg+" do1nto 3. :D product?reg+" do1nto 3. L nu#1?reg+2 do1nto /.> end if>

product?reg+" do1nto /. :D I/I @ product?reg+" do1nto 1.> end loop> ** assign t2e result of co#putation bac9 to output signal product JD product?reg+3 do1nto /.> end process> end be2)> RESULT.

ACTIVIT0. 1. 8rite a 6H!7 coding for a 4 bit binar% arra% #ultiplier and )erif% t2e result. 2. 8rite a 6H!7 coding for 4bit O 3 bit binar% #ultiplier and )erif% t2e result. 3. 8rite a 6H!7 coding for 4 bit Baug2 1oole% #ultiplier and )erif% t2e result. 4. 8rite a 6H!7 coding for 4bit Braun #ultiplier and )erif% t2e result. MASTER SLAVE FLIP FLOPS (D T0PE AND C6/ T0PEEH,$'i<$nt No. N D!t$. AIM. 5o 1rite a 6H!7 progra# to i#ple#ent a D )#i, )#o, 1it2 s3n+h'ono s and !s3n+h'ono s '$s$t at t2e be2a)ioral le)el. ALGORITHM. 1. 2. 3. 4. ". Start t2e progra#. ;nclude t2e ;=== librar% and t2e std?logic?11 4.all pac9age. !eclare t2e entit% for t2e ! flip flop . !efine t2e input and t2e output ports. =nd t2e entit%.

. &. 8. (.

!eclare t2e arc2itecture of ! flip flop . !efine t2e functionalit% of ! flip flop at be2a)ioral le)el . =nd t2e arc2itecture. 7oad t2e design3 si#ulate t2e 1a)efor#3 and )erif% t2e trut2*table.

PROGRAMS. F#i, )#o, *ith !s3n+h'ono s '$s$t. librar% ieee> use ieee.std?logic?11 4.all> entit% dff is port+data?in:in std?logic> cloc9:in std?logic> reset: in std?logic> data?out:out std?logic.> end dff> arc2itecture be2) of dff is begin process+cloc93reset. begin if resetDS/S t2en data?out JD U/S> elsif +cloc9Ie)ent and cloc9DI1I. t2en data?out JD data?in> end if> end process> end be2)> F#i, )#o, *ith s3n+h'ono s '$s$t. librar% ieee>

use ieee.std?logic?11 4.all> port+data?in:in std?logic> cloc9:in std?logic> reset: in std?logic> data?out:out std?logic.> end dff> arc2itecture be2) of dff is begin process+cloc9. begin if +cloc9Ie)ent and cloc9DI1I. t2en if resetDS/S t2en data?out JD U/S> else data?out JD data?in> end if> end if> end process> end be2)>

RESULT.

ACTIVIT0. :2 8rite a 6H!7 coding for reali:ing cloc9ed ,- flip flop using BAB! gates along 1it2 preset and clear action. 12 8rite a 6H!7 coding for reali:ing #aster sla)e ! flip flop and )erif% t2e result. D2 8rite a 6H!7 coding for reali:ing #aster sla)e ,*- flip flop and )erif% t2e result.

FOUR %IT RIPPLE COUNTER AND UP Q DOWN COUNTER EH,$'i<$nt N <"$'. :9 D!t$. AIM. 5o 1rite a 6H!7 progra# to i#ple#ent a D "it UPRDOWN +o nt$' at t2e be2a)ioral le)el and to )erif% t2e result. ALGORITHM. 1. 2. 3. Start t2e progra#. ;nclude t2e ;=== librar% and t2e std?logic?11 4.all 3 sd?logic?unsigned.all pac9ages. !eclare t2e entit% for t2e 3 bit '$4!C8B counter.

4. ". . &. 8. (. PROGRAM.

!efine t2e input and t2e output ports. =nd t2e entit%. !eclare t2e arc2itecture of t2e 3 bit '$4!C8B counter. !efine t2e functionalit% of 3 bit '$4!C8B counter at be2a)ioral le)el. =nd t2e arc2itecture. 7oad t2e design3 si#ulate t2e 1a)efor#3 and )erif% t2e trut2*table.

librar% ieee> use ieee.std?logic?11 4.all> use ieee.std?logic?unsigned.all> entit% updo1n is port+cl93reset: in std?logic> counten3up:in std?logic> su#:out std?logic?)ector+2 do1nto /.> cout:out std?logic.> end> arc2itecture rtl of updo1n is signal count: std?logic?)ector+2 do1nto /.> begin process+cl93reset. begin if resetDS/S t2en countJD+ot2ersDMS/S.> elsif cl9Se)ent and cl9DS1S t2en if countenDS1S t2en case up is 12en U1S DMGountDcountL1> 12en ot2ers DMGountDcount*1> end case> end if>

end if> end process> su#JDcount> coutJDS1S 12en countenDS1S and ++upDS1S and countD&. or +upDS/S and countDS/S. elseS/S> end> RESULT.

ACTIVIT0. 1. 8rite a 6H!7 coding for 4 bit 0ipple counter using ! flip*flop and )erif% t2e result. 2. 8rite a 6H!7 coding for 4 bit '$4!C8B counter using 5 flip flop and )erif% t2e result. UNIVERSAL SHIFT REGISTER EH,$'i<$nt No. :: D!t$. AIM. 5o 1rite a 6H!7 progra# to i#ple#ent a D "it shi)t '$gist$' at t2e be2a)ioral le)el. ALGORITHM. 1. 2. 3. 4. ". Start t2e progra#. ;nclude t2e ;=== librar% and t2e std?logic?11 4.all pac9age. !eclare t2e entit% for t2e 3 bit s2ift register . !efine t2e input and t2e output ports. =nd t2e entit%.

. &. 8. (.

!eclare t2e arc2itecture of s2ift register. !efine t2e functionalit% of s2ift register at be2a)ioral le)el . =nd t2e arc2itecture. 7oad t2e design3 si#ulate t2e 1a)efor#3 and )erif% t2e trut2*table.

PROGRAM. librar% ieee > use ieee.std?logic?11 4.all> entit% s2ift?reg is port+;:in std?logic> cloc9:in std?logic> s2ift:in std?logic> Q:out std?logic.> end s2ift?reg> arc2itecture be2) of s2ift?reg is signal S: std?logic?)ector+2 do1nto /.:DR111R> begin process+;3 cloc93 s2ift3 S. begin ** e)er%t2ing 2appens upon t2e cloc9 c2anging if cloc9Ie)ent and cloc9DI1I t2en if s2ift D I1I t2en S JD ; @ S+2 do1nto 1.> end if> end if> end process> ** concurrent assign#ent Q JD S+/.> end be2)>

RESULT.

ACTIVIT0. 1. 8rite 6H!7 progra# for four bit +i.S;SC +ii.S;$C +iii.$;$C +i).$;SC s2ift registers using structural #odel and )erif% t2e result. 2. 8rite a 6H!7 progra# for uni)ersal s2ift register and )erif% t2e result.

STATE MACHINE MODELLING OF MEAL0 MACHINE AND MOORE MACHINE

EH,$'i<$nt No. :1 D!t$.

AIM. 5o 1rite a 6H!7 progra# to i#ple#ent a Moore state #ac2ine at be2a)ioral le)el.

ALGORITHM.

1. 2. 3. 4. ". . &. 8. (. 1/.

Start t2e progra#. ;nclude t2e ;=== librar% and t2e std?logic?11 4.all pac9age. !eclare t2e entit% for t2e gi)en #oore state #ac2ine . !efine t2e input and t2e output ports. =nd t2e entit%. !eclare t2e arc2itecture of #oore state #ac2ine. ;nitialise all t2e states of t2e finite state #ac2ine. !efine t2e functionalit% of #oore state #ac2ine at be2a)ioral le)el . =nd t2e arc2itecture. 7oad t2e design3 si#ulate t2e 1a)efor#3 and )erif% t2e trut2*table.

MOORE STATE MACHINE.

PROGRAM. librar% ieee> use ieee.std?logic?11 4.all> entit% #oorefs# is port+le)el3cl9 :in std?logic> tic9 :out std?logic.> end #oorefs#> arc2itecture ar of #oorefs# is t%pe state?t%pe is +:ero3edg3one.> signal state:state?t%pe>

begin process+cl93le)el3state. begin if cl9Ie)ent and cl9 D I1I t2en case state is 12en :ero DM tic9 JD I/I> if le)el D I1I t2en state JD edg> else state JD :ero> end if> 12en edg DM tic9 JD I1I> if le)el D I1I t2en state JD one> else state JD :ero> end if> 12en one DM tic9 JD I/I> if le)el D I1I t2en state JD one> else state JD :ero> end if> end case> end if> end process>

end>

RESULT.

ACTIVIT0. 1. 8rite a 6H!7 code to design a Moore state #ac2ine 12ic2 2as t2e states s/3s13s2 @ s3. 2. 8rite a 6H!7 code to design a Meal% state #ac2ine 1it2 t2ree states na#el% one3t1o3t2ree.

FREQUENC0 DIVIDER

AIM. 5o 1rite a 6H!7 coding to generate a cloc9 of freAuenc% 4/-H: and dut%c%cle "/4"/ fro# a gi)en cloc9 freAuenc% "/MH:. ALGORITHM. 1. Start t2e progra#. 2. ;nclude t2e ;=== librar% and t2e std?logic?11 4.all pac9age. 3. !eclare t2e input and output ports in t2e entit%. 4. !eclare t2e arc2itecture of cloc9 di)ider. ". Galculate t2e nu#ber of ti#es3 t2e input cloc9 2as to be counted to get t2e desired cloc9 freAuenc% and start counting t2e input cloc9 signal. . Bo1 depending on t2e dut%c%cle3 di)ide t2e calculated count )alue3 for exa#ple if t2e dut%c%cle is 2"4&"3 t2en t2e output cloc9 2as to be #ade CB for 2"W of t2e count and t2e sa#e 2as to be #ade CFF for t2e re#aining &"W of t2e count. &. 82en t2e count )alue reac2es t2e #axi#u#3 #a9e it to one and count t2e input cloc9 signal again. 8. 0epeat t2e procedure. (. =nd of arc2itecture.

MODEL CALCULATION. ;nput Gloc9 freAuenc% D "/ MH: Cutput Gloc9 freAuenc% D 4/ -H: Gount )alue D ;nput cloc9 freAuenc% 4 Cutput cloc9 freAuenc% D +"/ x 1/ .4+4/ x 1/3. D 12"/ Hi)en dut% c%cle D "/ 4"/ C4p cloc9 CB ti#e count D C4p cloc9 CFF ti#e count D PROGRAM . 2" 2"

librar% ieee> use ieee.std?logic?11 4.all> use ieee.std?logic?arit2.all> entit% cloc9di)ider1 is port+cl9in3reset : in std?logic> ** cl9in force )alue D 2/ns+for an i4p cloc9 freAuenc% of ** "/MH:. cl9out : out std?logic.> end cloc9di)ider1> arc2itecture be2a)ioral of cloc9di)ider1 is signal count :integer range / to 2///:D/> begin process+cl9in3reset. begin if reset D I1I t2en ** as%nc2ronous reset cl9out JD I/I> count JD /> elsif cl9inIe)ent and cl9in D I1I t2en count JD count L 1> if count JD 24 t2en cl9out JD I1I> elsif count M 24 and count J 12"/ t2en cl9out JD I/I> else count JD 1> cl9out JD I1I> end if> end if> end process> end be2a)ioral>

RESULT.

ACTIVIT0. 1. Henerate a cloc9 signal 1it2 freAuenc% 1 /-H: and dut% c%cle 2"4&". Assu#e t2e input cloc9 c%cle period as 2"ns. 2. Henerate a cloc9 signal 1it2 freAuenc% 12"-H: and dut% c%cle "/4"/. Assu#e t2e input cloc9 freAuenc% as /MH:.

QUESTIONS

Int'od +tion 1. 82at t%pe of language is 6H!7X 2. 82at is t2e basic building unit of a 6H!7 designX 3. 82at do all 6H!7 designs begin 1it2X 4. 82ic2 bloc9 describes a designIs interfaceX ". 82ic2 bloc9 describes a designIs be2a)iorX . 82at is t2e difference bet1een si#ulation and s%nt2esisX D!t! T3,$s &. 6H!7 is a ???????????? t%ped language. 8. 82ic2 data t%pe defines a single logic signalX (. 82ic2 data t%pe describes a busX 1/. 82at t1o 1a%s can a )ectorIs range be describedX 11. 82at are t2e ;=== S5!?7CH;G?11 4 data t%pes for single logic signals and busesX 12. 82% is it desirable to use ;=== S5!?7CH;G?11 4 data t%pingX 82at is t2e difference bet1een resol)ed and unresol)ed logicX 13. 82at are t2e onl% t1o )alues for a Boolean t%peX 14. 82at are t2e nu#erical data t%pesX 1". 82at is S'B5N$;BH used forX 1 . 82at t%pe is use to create a user data t%peX 1&. 82at reser)ed 1ord is used to declare a user data t%peX 18. Greate t2e use data t%pe DA0S and assign it t2e )alues: MON( TUE( WED( THU( FRI( SAT and SUN. 1(. 82ic2 data t%pe is used for a string of ASG;; c2aractersX 2/. 82ic2 data t%pe includes ti#e units as )aluesX Entit3

21. Greate t2e entit% bloc9 for a t2ree input OC0 gate. 22. 82ic2 s%#bol is used to end all 6H!7 state#entsX 23. 82at part of a port declaration defines a signals in or out directionX 24. 82ic2 6H!7 construct is used to define a literal constant in an entit% bloc9X 2". Greate t2e integer constant included in an entit% bloc93 called %US=SI;E and assign it a )alue of 32. 2 . 82ic2 s%#bols are used as an assign#ent operator to assign a literal to an identifier na#eX A'+hit$+t '$ %#o+8 2&. 82at are t2e t1o pri#ar% 1a%s to describe a logic circuits function 1it2in an arc2itecture bloc9X 28. Greate t2e arc2itecture bloc9 for t2e 3*input OC0 gate of Auestion 21. 2(. 82ic2 s%#bols are used to assign an expressionIs result to an output interface signalX 3/. 82at are t2e rules used to define an identifier na#eX 31. 82at s%#bols define a co##ent lineX 32. 8rite t2e state#ents t2at 1ill allo1 a design to access all t2e contents of t2e ;=== A0;5H librar%. 33. Add a 2" ns inertial dela% to t2e OC0 assign#ent state#ent of Auestion 28. 34. Ma9e t2e dela% in Auestion 33 transport rat2er t2an inertial. 3". Ho1 does a transport dela% differ fro# an inertial dela%X 3 . 82at is t2e purpose of a SIGNAL declarationX 3&. 82ere are SIGNAL declarations placed in t2e designX 38. 8rite an assign#ent state#ent t2at assigns t2e contents of s(@- to t(1-.

3(. 8rite an assign#ent state#ent t2at copies all t2e states of d!t!=" s to d!t!=in. 52e% are bot2 8*bit buses. P'o+$ss 4/. State#ents in an arc2itecture bloc9 are executed ???????????????? . 41. State#ents in a process bloc9 are executed ??????????????. 42. 82at is t2e purpose of a processI sensiti)it% listX 43. 'nder 12at conditions is a process runX 44. 82at is an EVENTX 4". 82at is t2e difference bet1een e)ent and non*e)ent dri)en process executionX 4 . 8rite a process bloc9 t2at 9eeps a running tall% of eac2 ti#e an interrupt +INT. signal is asserted 2ig2. 4&. 82ic2 s%#bols are used to differentiate bet1een a logic 1 and an integer 1X 48. 82ic2 s%#bols are used to differentiate bet1een a logic 1/11 and an integer 13/11X 4(. 82at are t2e results of using CL/J$&$nt as a condition in t2e i) state#ent of t2e DEF exa#pleX Condition!# St!t$<$nts "/. ;n an i)22th$n22$#s$ construct3 12ic2 state#ents are executed if t2e condition is TRUE and 12ic2 if it is FALSEX "1. 82at reser)ed 1ord is used to nest if..t2en..else state#entsX "2. 8rite t2e process bloc9 t2at separatel% tallies positi)e and negati)e transitions of t2e signal TIME=OUT. Loo,s

"3. 82at is t2e purpose of a )o' loopX "4. 82at are t2e reAuire#ents for a )o' loopX "". 8rite a process bloc9 t2at uses a )o' loop to set a :ero flag 2ig2 if all t2e bits in a sixteen +1 . bit 1ord are lo1 +:ero.. St' +t '!# D$sign "&. 82at is t2e basic building ele#ent of a structure designX "8. 8rite t2e co#ponent declaration for t2e OC0 gate in Auestion 21. "(. ;nstantiate t1o copies of t2e OC0 gate in Auestion "&. Hate X: 2as inputs Ain and %in and output I:. Hate X1 2as inputs Cin and I: and output XORD. /. 8rite t2e declaration for interconnecting signal I: in Auestion "8. 1. ;nstantiate OC0 gate X: in Auestion "8 using direct association. 2. 8rite is t2e general rule for co#ponent declarationsX 3. 82at is #eant b% instantiating a co#ponentX Sign!#s 4. Ho1 do signal declarations differ fro# port interface declarationsX ". 82at is t2e pri#e use of signalsX

Mod #!' D$sign

. 82at is a #oduleX &. 82ere do #odules get t2eir functions and interface signalsX