FUJITSU SEMICONDUCTOR DATA SHEET

DS04-27401-8E

ASSP
BIPOLAR

Power Supply Monitor with Watch-Dog Timer

MB3773
DESCRIPTION
MB3773 generates the reset signal to protect an arbitrary system when the power-supply voltage momentarily is intercepted or decreased. It is IC for the power-supply voltage watch and Power on reset is generated at the normal return of the power supply. MB3773 sends the microprocessor the reset signal when decreasing more than the voltage, which the power supply of the system specified, and the computer data is protected from an accidental deletion. In addition, the watch-dog timer for the operation diagnosis of the system is built into, and various microprocessor systems can provide the fail-safe function. If MB3773 does not receive the clock pulse from the processor for a specified period, MB3773 generates the reset signal.

FEATURES
Precision voltage detection (VS = 4.2 V 2.5 %) Detection threshold voltage has hysteresis function Low voltage output for reset signal (VCC = 0.8 V Typ) Precision reference voltage output (VR = 1.245 V 1.5%) With built-in watch-dog timer of edge trigger input. External parts are few.(1 piece in capacity) The reset signal outputs the positive and negative both theories reason. One type of package (SOP-8pin : 1 type)

APPLICATION
Industrial Equipment Arcade Amusement etc.

Copyright2003-2006 FUJITSU LIMITED All rights reserved

MB3773
PIN ASSIGNMENT

(TOP VIEW)

CT RESET CK GND

1 2 3 4

8 7 6 5

RESET VS V REF V CC

(FPT-8P-M01)

MB3773
BLOCK DIAGRAM
VCC
5

Reference AMP = : 1.24 V

Reference Voltage Generator

= : 1.24 V = : 10 A

+ _ 6

= : 100
k +

= : 1.2 A

VREF

COMP.O
+ _

= : 10 A

COMP.S
+

VS

_ S

= : 40 k
Inhibit

CK

WatchDog Timer

P.G
4 1 8 2

GND

CT

RESET

RESET

MB3773
FUNCTIONAL DESCRIPTIONS
Comp.S is comparator including hysteresis. it compare the reference voltage and the voltage of Vs, so that when the voltage of Vs terminal falls below approximately 1.23 V, reset signal outputs. Instantaneous breaks or drops in the power can be detected as abnormal conditions by the MB3773 within a 2 s interval. However because momentary breaks or drops of this duration do not cause problems in actual systems in some cases, a delayed trigger function can be created by connecting capacitors to the Vs terminal. Comp.O is comparator for turning on/off the output and, compare the voltage of the CT terminal and the threshold voltage. Because the RESET/RESET outputs have built-in pull-up circuit, there is no need to connect to external pull-up resistor when connected to a high impedance load such as CMOS logic IC. (It corresponds to 500 k at Vcc = 5 V.) when the voltage of the CK terminal changes from the high level into the Low level, pulse generator is sent to the watch-dog timer by generating the pulse momentarily at the time of drop from the threshold level. When power-supply voltages fall more than detecting voltages, the watch-dog timer becomes an interdiction. The Reference amplifier is an op-amp to output the reference voltage. If the comparator is put up outside, two or more power-supply voltage monitor and overvoltage monitor can be done. If it uses a comparator of the open-collector output, and the output of the comparator is connected with the Vs terminal of MB3773 without the pull-up resistor, it is possible to voltage monitor with reset-hold time.

MB3773
MB3773 Basic Operation

VCC VCC CT RESET RESET CK GND

Logic Circuit

RESET RESET CK

TPR (ms) = : 1000 CT (F) TWD (ms) = : 100 CT (F) TWR (ms) = : 20 CT (F) Example : CT = 0.1 F TRR (ms) = : 100 (ms) TWD (ms) = : 10 (ms) TWR (ms) = : 2 (ms)

VCC
VSH VSL 0.8 V

CK

TCK

CT

RESET

TPR

TWD TWR

TPR

(1) (2)

(3)(4)(5)

(5)

(6) (7)

(8)(9)

(10)

(11) (12)

MB3773
OPERATION SEQUENCE
(1) When Vcc rises to about 0.8 V, RESET goes Low and RESET goes High. The pull-up current of approximately 1 A (Vcc = 0.8 V) is output from RESET. (2) When Vcc rises to VSH ( = : 4.3V) , the charge with CT starts. At this time, the output is being reset. (3) When CT begins charging, RESET goes High and RESET goes Low. After TPR reset of the output is released. Reset hold time: TPR (ms) = : 1000 CT (F) After releasing reset, the discharge of CT starts, and watch-dog timer operation starts. TPR is not influenced by the CK input. (4) C changes from the discharge into the charge if the clock (Negative edge) is input to the CK terminal while discharging CT. (5) C changes from the charge into the discharge when the voltage of CT reaches a constant threshold ( = : 1.4 V) . (4) and (5) are repeated while a normal clock is input by the logic system. (6) When the clock is cut off, gets, and the voltage of CT falls on threshold ( = : 0.4 V) of reset on, RESET goes Low and RESET goes High. Discharge time of CT until reset is output: TWD is watch-dog timer monitoring time. TWD (ms) = : 100 CT (F) Because the charging time of CT is added at accurate time from stop of the clock and getting to the output of reset of the clock, TWD becomes maximum TWD + TWR by minimum TWD. (7) Reset time in operating watch-dog timer:TWR is charging time where the voltage of CT goes up to off threshold ( = : 1.4 V) for reset. TWR (ms) = : 20 CT (F) Reset of the output is released after CT reaches an off threshold for reset, and CT starts the discharge, after that if the clock is normally input, operation repeats (4) and (5) , when the clock is cut off, operation repeats (6) and (7) . (8) When Vcc falls on VSL ( = : 4.2 V) , reset is output. CT is rapidly discharged of at the same time. (9) When Vcc goes up to VSH, the charge with CT is started. When Vcc is momentarily low, After falling VSL or less Vcc, the time to going up is the standard value of the Vcc input pulse width in VSH or more. After the charge of CT is discharged, the charge is started if it is TPI or more. (10) Reset of the output is released after TPR, after Vcc becomes VSH or more, and the watch-dog timer starts. After that, when Vcc becomes VSL or less, (8) to (10) is repeated. (11) While power supply is off, when Vcc becomes VSL or less, reset is output. (12) The reset output is maintained until Vcc becomes 0.8 V when Vcc falls on 0 V.

MB3773
ABSOLUTE MAXIMUM RATINGS
Rating Parameter Supply voltage Input voltage VCK RESET, RESET Supply voltage Power dissipation (Ta +85 C) Storage temperature VOH PD TSTG Symbol Min VCC VS 0.3 0.3 0.3 0.3 55 Max + 18 VCC + 0.3 ( +18) + 18 VCC + 0.3 ( +18) 200 + 125 V V V V mW C Unit

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

RECOMMENDED OPERATING CONDITIONS

Value Parameter Supply voltage RESET, RESET sink current VREF output current Watch clock setting time CK Rising/falling time Terminal capacitance Operating ambient temperature Symbol Min VCC IOL IOUT tWD tFC, tRC CT Ta + 3.5 0 200 0.1 0.001 40 Max + 16 20 +5 1000 100 10 + 85 V mA A ms s F C Unit

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the devices electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.

MB3773
ELECTORICAL CHARACTERISTICS
(1) DC Characteristics (VCC = 5 V, Ta = + 25 C) Value Parameter Supply current Symbol ICC VSL Detection voltage VSH Hysteresis width Reference voltage Reference voltage change rate Reference voltage output loading change rate CK threshold voltage CK input current IIL CT discharge current ICTD VOH1 High level output voltage VOH2 VOL1 VOL2 Output saturation voltage VOL3 VOL4 IOL1 Output sink current IOL2 CT charge current Min supply voltage for RESET ICTU VCCL1 VHYS VREF VREF1 VREF2 VTH IIH Condition Min Watch-dog timer operating
VCC

Typ 600 4.20 4.20 4.30 4.30 100 1.245 1.245 3 1.25 0 0.1 10 4.9 4.9 0.2 0.3 0.2 0.3 60 60 1.2 0.8

Max 900 4.30 4.35

Unit A

4.10 4.05 4.20 4.15 50

Ta = 40 C to + 85 C
VCC

V 4.40 4.45 150 1.263 V 1.215 5 0.8 1.0 7 4.5 4.5 20 20 0.5 1.275 10
+5

Ta = 40 C to + 85 C
VCC

mV

Ta = 40 C to + 85 C
VCC = 3.5 V to 16 V

1.227

mV mV V A A V

IOUT = 200 A to + 5 A Ta = 40 C to + 85 C VCK = 5.0 V VCK = 0.0 V Watch-dog timer operating VCT = 1.0 V VS open, IRESET = 5 A VS = 0 V, IRESET = 5 A VS = 0 V, IRESET = 3 mA VS = 0 V, IRESET = 10 mA VS open, IRESET = 3 mA VS open, IRESET = 10 mA VS = 0 V, VRESET = 1.0 V VS open, VRESET = 1.0 V Power on reset operating VCT = 1.0 V VRESET = 0.4 V, IRESET = 0.2 mA VRESET = VCC 0.1 V, RL (between pin 2 and GND) = 1 M

2.0 1.0 14 0.4 0.5

V 0.4 0.5 2.5 1.2 mA A V

Min supply voltage for RESET

VCCL2

0.8

1.2

MB3773
(2)AC Characteristics Parameter VCC input pulse width CK input pulse width CK input frequency Watch-dog timer watching time Watch-dog timer reset time Rising reset hold time Symbol TPI TCKW TCK TWD TWR TPR TPD1 TPD2 tR tF CT = 0.1 F CT = 0.1 F CT = 0.1 F, VCC RESET, RL = 2.2 k, CL = 100 pF RESET, RL = 2.2 k, CL = 100 pF RL = 2.2 k, CL = 100 pF RL = 2.2 k, CL = 100 pF
5V

Condition

(VCC = 5 V, Ta = + 25 C) Value Unit Min Typ Max 8.0 10 2 100 2 3 1.0 0.1 15 3 150 10 s 10 1.5 s 0.5 s s s ms ms ms

VCC CK

4V

or

3.0 20 5 1 50

Output propagation delay time from VCC

Output rising time* Output falling time*

* : Output rising/falling time are measured at 10 % to 90 % of voltage.

MB3773
TYPICAL CHARACTERISTIC CURVES
Supply current vs. Supply voltage
0.75
Ta = + 25 C Ta = + 85 C

Output voltage vs. Supply voltage

(RESET terminal)
6.0

Supply current ICC (mA)

0.65 0.55 0.45 0.35 0.25 0.15

Ta = 40 C Ta = + 25 C Ta = + 85 C Ta = 40 C CT = 0.1 F

Output voltage VRESET (V)

Pull up 2.2 k
Ta = 40 C, + 25 C, + 85 C

5.0 4.0 3.0 2.0 1.0

2.0

4.0

6.0

8.0 10.0 12.0 14.0 16.0 18.0 20.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

Supply voltage VCC (V) Output voltage vs. Supply voltage

(RESET terminal)
6.0 4.50 4.44 4.30 4.20 4.10 4.00

Supply voltage VCC (V) Detection voltage (VSH, VSL) vs. Operating ambient temperature
(RESET, RESET terminal)

Output voltage VRESET (V)

Pull up 2.2 k

Detection voltage VSH, VSL (V)

5.0 4.0 3.0 2.0 1.0 Ta = + 85 C Ta = + 25 C Ta = 40 C 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0

VSH

VSL

40

20

+20

+40

+60

+80 +100

Supply voltage VCC (V) Output saturation voltage vs. Output sink current
Output saturation voltage VOL2 (mV) Output saturation voltage VOL2 (mV) (RESET terminal)
Ta = 40 C 400 CT = 0.1F

Operating ambient temperature Ta ( C) Output saturation voltage vs. Output sink current
(RESET terminal)
500 Ta = 40 C CT = 0.1F

400

300

Ta = + 25 C Ta = + 85 C

300

200

Ta = +25 C Ta = +85 C

200

100

100

2.0

4.0

6.0 8.0 10.0 12.0 14.0 16.0 18.0

2.0 4.0

6.0

8.0 10.0 12.0 14.0 16.0 18.0

Output sink current IOL2 (mA)

Output sink current IOL8 (mA)

(Continued) 10

MB3773

High level output voltage vs. High level output current

High level output voltage VOH8 (V) High level output voltage VOH2 (V)
5.0

High level output voltage vs. High level output current

5.0

(RESET terminal)
CT = 0.1 F

(RESET terminal)
CT = 0.1 F

Ta = +25 C 4.5 Ta = 40 C Ta = +85 C

4.5

Ta = 40 C

Ta = +25 C Ta = +85 C

4.0

10

15

4.0

10

15

High level output current IOH2 (A)

High level output current IOH8 (A)

Reference voltage vs. Supply voltage

1.246
1.255

Reference voltage vs. Reference current

CT = 0.1 F

Reference voltage VREF (V)

Ta = +25 C Ta = +85 C Ta = 40 C CT = 0.1 F

1.242 1.240 1.238 1.236 1.234

Reference voltage VREF (V)

1.244

1.250 Ta = +25 C 1.245 Ta = +85 C Ta = 40 C 1.240

3.0 5.0 7.0 9.0 11.0 13.0 15.0 17.0 19.0 21.0

40

80

120

160

200

240

Supply voltage VCC (V)

Reference current IREF (A)

Reference voltage vs. Operating ambient temperature

1.27

Rising reset hold time vs. Operating ambient temperature

160 VCC = 5 V CT = 0.1 F

Reference voltage VREF (V)

Rising reset hold time TPR (ms)

1.26 1.25 1.24 1.23 1.22 1.21

140 120 100 80 60 40 0 40 20 0

Operating ambient temperature Ta ( C)

40 20

+20 +40 +60 +80 +100

+20 +40 +60 +80 +100

Operating ambient temperature Ta ( C)

(Continued) 11

MB3773
(Continued) Reset time vs. Operating ambient temperature
(At watch-dog timer)
3 VCC = 5 V CT = 0.1 F

Watch-dog timer watching time vs. Operating ambient temperature

16 14 VCC = 5 V CT = 0.1 F

Watch-dog timer watching time TWD (ms)

Reset time TWR (ms)

12 10 8 6 4 0 40 20

40

20

+20

+40 +60

+80 +100

+20 +40

+60

+80 +100

Operating ambient temperature Ta ( C)

Operating ambient temperature Ta ( C)

Watch-dog timer watching time vs. CT terminal capacitance

10 6

Reset time vs. CT terminal capacitance

(at watch-dog timer)

Rising reset hold time vs. CT terminal capacitance

10 6

10 2

Rising reset hold time TPR (ms)

10 5

10 5 10 4 10 3 10 2 10 1 10 0 10 1 10 2 10 3 10 3 10 2 10 1 10 0 10 1 10 2 Ta = 40 C Ta = +25 C, +85 C

Watch-dog timer watching time TWD (ms)

10 4

Reset time TWR (ms)

10 1 Ta = +25 C, +85 C

10 3 10 2 10 1 10 0 10 1 10 2 10 3

Ta = 40 C Ta = +25 C, +85 C

10 0 Ta = 40 C

10 1

10 2

10 3 10 3 10 2 10 1 10 0 10 1 10 2

10 3 10 2 10 1 10 0 10 1 10 2

CT terminal capacitance CT (F)

CT terminal capacitance CT (F)

CT terminal capacitance CT (F)

12

MB3773
APPLICATION CIRCUIT
EXAMPLE 1: Monitoring 5V Supply Voltage and Watch-dog Timer
VCC (5V)

MB3773 1 2 3 4 8 7 6 5

Logic circuit RESET RESET CK GND

CT

Notes : Supply voltage is monitored using VS. Detection voltage are VSH and VSL.

EXAMPLE 2: 5V Supply Voltage Monitoring (external fine-tuning type)

VCC (5V)

MB3773 1 2 3 4 8 7 6 5

R1

Logic circuit RESET RESET CK GND

CT

R2

Notes : Vs detection voltage can be adjusted externally. Based on selecting R1 and R2 values that are sufficiently lower than the resistance of the ICs internal voltage divider, the detection voltage can be set according to the resistance ratio of R1 and R2 (Refer to the table below.) R1 (k) 10 9.1 R2 (k) 3.9 3.9 Detection voltage: VSL (V) 4.4 4.1 Detection voltage: VSH (V) 4.5 4.2

13

MB3773

EXAMPLE 3: With Forced Reset (with reset hold)

(a) VCC MB3773 1 2 3 4 8 7 6 5 Logic circuit RESET RESET CK GND

CT

SW

Note : Grounding pin 7 at the time of SW ON sets RESET (pin 8) to Low and RESET (pin 2) to High.

(b) VCC MB3773 1 2 3 4 8 7 6 5 Tr Logic circuit RESET RESET CK GND

10 k 10 k

Cr

RESIN

Note : Feeding the signal to terminal RESIN and turning on Tr sets the RESET terminal to Low and the RESET terminal to High.

14

MB3773

EXAMPLE 4: Monitoring Two Supply Voltages (with hysteresis, reset output and NMI) VCC2(12 V) VCC1 (5 V)

MB3773 1 2 3 4 8 7 6 5

Logic circuit RESET RESET CK NMI or port GND

CT

30 k R3 180 k R4
+ _ + _

10 k R6

1.2 k R1 5.1 k R2 4.7 k R5

Comp. 1 Comp. 2

Example : Comp. 1, Comp. 2 : MB4204, MB47393 Notes : The 5 V supply voltage is monitored by the MB3773. The 12 V supply voltage is monitored by the external circuit. Its output is connected to the NMI terminal and, when voltage drops, Comp. 2 interrupts the logic circuit. Use VCC1 ( = 5 V) to power the comparators (Comp. 1 and Comp. 2) in the external circuit shown above. The detection voltage of the VCC2 ( = 12 V) supply voltage is approximately 9.2 V/9.4 V and has a hysteresis width of approximately 0.2 V. VCC2 detection voltage and hysteresis width can be found using the following formulas: Detection voltage V2H = V2L = Hysteresis width R3 + (R4 // R5) R4 // R5 R3 + R5 R5 VREF

(Approximately 9.4 V in the above illustration) (Approximately 9.2 V in the above illustration)

VREF

VHYS = V2H V2L

15

MB3773

EXAMPLE 5: Monitoring Two Supply Voltages (with hysteresis and reset output)

VCC2 (12 V) VCC1 (5 V)

MB3773 1 2 3 4 8 7 6 5

20 k R6

Logic circuit

CT

30 k R3 180 k R4
+ _

Diode

RESET RESET CK GND

+ _

1.2 k R1 5.1 k R2 4.7 k R5

Comp. 1 Comp. 2

Example : Comp. 1, Comp. 2 : MB4204, MB47393 Notes : When either 5 V or 12 V supply voltage decreases below its detection voltage (VSL), the MB3773 RESET terminal is set to High and the MB3773 RESET terminal is set to Low. Use VCC1 ( = 5 V) to power the comparators (Comp. 1 and Comp. 2) in the external circuit shown above. The detection voltage of the VCC2 ( = 12 V) supply voltage is approximately 9.2 V/9.4 V and has a hysteresis width of approximately 0.2 V. For the formulas for finding hysteresis width and detection voltage, refer to section 4.

16

MB3773

EXAMPLE 6: Monitoring Low voltage and Overvoltage Monitoring (with hysteresis)

VCC (5 V)

MB3773 1 2 3 4 8 7 6 5

20 k R6

Logic circuit RESET RESET CK GND

CT

30 k R3 180 k R4
+

Diode

_ _ +

1.2 k R1 5.6 k R6

Comp. 1

Comp. 2

4.7 k R5

Example : Comp. 1, Comp. 2 : MB4204, MB47393 RESET

V1L V1H

V2L V2H

VCC

Notes : Comp. 1 and Comp. 2 are used to monitor for overvoltage while the MB3773 is used to monitor for low voltage. Detection voltages V1L/V1H at the time of low voltage are approximately 4.2 V/4.3 V. Detection voltages V2L/V2H at the time of overvoltage are approximately 6.0 V/6.1 V. For the formulas for finding hysteresis width and detection voltage, see EXAMPLE 4. Use VCC ( = 5 V) to power the comparators (Comp. 1 and Comp. 2) in the external circuit shown above.

17

MB3773

EXAMPLE 7: Monitoring Supply Voltage Using Delayed Trigger

VCC 5V 4V

VCC

MB3773 1 2 3 4 8 7 6 5

Logic circuit RESET RESET CK GND

CT

C1

Note : Adding voltage such as shown in the figure to VCC increases the minimum input pulse width by 50 s (C1 = 1000 pF).

18

MB3773
EXAMPLE 8: Stopping Watch-dog Timer (Monitoring only supply voltage) These are example application circuits in which the MB3773 monitors supply voltage alone without resetting the microprocessor even if the latter, used in standby mode, stops sending the clock pulse to the MB3773. The watch-dog timer is inhibited by clamping the CT terminal voltage to VREF. The supply voltage is constantly monitored even while the watch-dog timer is inhibited. For this reason, a reset signal is output at the occurrence of either instantaneous disruption or a sudden drop to low voltage. Note that in application examples (a) and (b), the hold signal is inactive when the watch-dog timer is inhibited at the time of resetting. If the hold signal is active when tie microprocessor is reset, the solution is to add a gate, as in examples (c) and (d). (a) Using NPN transistor
VCC(5 V)

MB3773 1 2 3 4 8 7 6 5 R2=1 k CT R1=1 M

Logic circuit RESET RESET CK HALT GND

(b) Using PNP transistor

VCC (5 V)

MB3773
1 2 3 4 8 7 6 5

Logic circuit RESET RESET CK HALT GND R1=51 k

R2=1 k CT

(Continued) 19

MB3773
(Continued)

(c) Using NPN transistor

VCC (5 V)

MB3773 1 2 3 4 8 7 6 5 R2=1 k CT

Logic circuit RESET RESET CK HALT GND

R1=1 M

(d) Using PNP transistor

VCC (5 V)

MB3773 1 2 3 4 8 7 6 5 R2=1 k CT

Logic circuit RESET RESET CK HALT GND

R1=51 k

20

MB3773

VCC( = 5 V)

EXAMPLE 9: Reducing Reset Hold Time VCC ( = 5 V)

MB3773 1 2 3 4 8 7 6 5

Logic circuit RESET RESET CK GND

MB3773 1 2 3 4 8 7 6 5

Logic circuit

CT

CT

RESET RESET CK GND

(a) TPR reduction method

(b) Standard usage

Notes : RESET is the only output that can be used. Standard TPR, TWD and TWR value can be found using the following formulas. Formulas: TPR (ms) = : 100 CT (F) TWD (ms) = : 100 CT (F) TWR (ms) = : 16 CT (F) The above formulas become standard values in determining TPR, TWD and TWR. Reset hold time is compared below between the reduction circuit and the standard circuit.

CT = 0.1 F TPR reduction circuit TPR = : TWD = : TWR = : 10 ms 10 ms 1.6 ms Standard circuit 100 ms 10 ms 2.0 ms

21

MB3773
EXAMPLE 10: Circuit for Monitoring Multiple Microprocessor

VCC ( = 5 V)

FF1 S D1 Q1 CK1 Q1 R

FF2 S D2 Q2 CK2 Q2 R

FF3 S D3 Q3 CK3 Q3 R R2 R1

*
RESET RESET

*
RESET RESET

*
RESET RESET

CK GND

CK GND

CK GND

1 2 CT *: Microprocessor 3 4

8 7 6 5 Figure 1

MB3773

Notes : connects from FF1 and FF2 outputs Q1 and Q2 to the NOR input. Depending on timing, these connections may not be necessary. Example : R1 = R2 = 2.2 k CT = 0.1 F CK1 Q1 CK2 Q2 CK3 Q3
NOR Output

Figure 2

22

MB3773
Description of Application Circuits Using one MB3773, this application circuit monitors multiple microprocessor in one system. Signals from each microprocessor are sent to FF1, FF2 and FF3 clock inputs. Figure 2 shows these timings. Each flip-flop operates using signals sent from microprocessor as its clock pulse. When even one signal stops, the relevant receiving flip-flop stops operating. As a result, cyclical pulses are not generated at output Q3. Since the clock pulse stops arriving at the CK terminal of the MB3773, the MB3773 generates a reset signal. Note that output Q3 frequency f will be in the following range, where the clock frequencies of CK1, CK2 and CK3 are f1, f2 and f3 respectively. 1 1 1 1 1 --- -- --- + --- + --f0 f f1 f2 f3 where f0 is the lowest frequency among f1, f2 and f3.

23

MB3773

EXAMPLE 11: Circuit for Limiting Upper Clock Input Frequency

VCC (5 V)

R2 1 2 3 4 8 7 6 5
RESET

RESET R1=10 k CK Tr1 C2 GND

CT

Notes : This is an example application to limit upper frequency fH of clock pulses sent from the microprocessor. If the CK cycle sent from the microprocessor exceeds fH, the circuit generates a reset signal. (The lower frequency has already been set using CT.) When a clock pulse such as shown below is sent to terminal CK, a short T2 prevents C2 voltage from reaching the CK input threshold level ( = : 1.25 V), and will cause a reset signal to be output. The T1 value can be found using the following formula : T1 = : 0.3 C2R2 where VCC = 5 V, T3 3.0 s, T2 20 s T2

CK waveform

T3

C2 voltage

T1 Example : Setting C and R allow the upper T1 value to be set (Refer to the table below). C 0.01 F 0.1 F R 10 k 10 k T1 30 s 300 s

24

MB3773
NOTES ON USE
Take account of common impedance when designing the earth line on a printed wiring board. Take measures against static electricity. - For semiconductors, use antistatic or conductive containers. - When storing or carrying a printed circuit board after chip mounting, put it in a conductive bag or container. - The work table, tools and measuring instruments must be grounded. - The worker must put on a grounding device containing 250 k to 1 M resistors in series. Do not apply a negative voltage - Applying a negative voltage of 0.3 V or less to an LSI may generate a parasitic transistor, resulting in malfunction.

ORDERING INFORMATION
Part number MB3773PF- MB3773PF-E1 Package 8-pin plastic SOP (FPT-8P-M01) 8-pin plastic SOP (FPT-8P-M01) Remarks Conventional version Lead Free version

RoHS Compliance Information of Lead (Pb) Free version

The LSI products of Fujitsu with E1 are compliant with RoHS Directive , and has observed the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB) , and polybrominated diphenyl ethers (PBDE) . The product that conforms to this standard is added E1 at the end of the part number.

MARKING FORMAT (Lead Free version)

Lead-Free version

3773 E1XXXX
XXX

INDEX

25

MB3773
LABELING SAMPLE (Lead free version)
lead-free mark JEITA logo JEDEC logo

MB123456P - 789 - GE1

(3N) 1MB123456P-789-GE1 1000

Pb

(3N)2 1561190005 107210

QC PASS

PCS 1,000 MB123456P - 789 - GE1

2006/03/01

ASSEMBLED IN JAPAN
1/1

MB123456P - 789 - GE1

0605 - Z01A 1000
1561190005

Lead-Free version

26

MB3773
MB3773PF-E1 RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL
Item Mounting Method Mounting times Before opening Storage period From opening to the 2nd reflow When the storage period after opening was exceeded Storage conditions Condition IR (infrared reflow) , Manual soldering (partial heating method) 2 times Please use it within two years after Manufacture. Less than 8 days Please processes within 8 days after baking (125 C, 24h)

5 C to 30 C, 70%RH or less (the lowest possible humidity)

[Temperature Profile for FJ Standard IR Reflow] (1) IR (infrared reflow)

260 C 255 C

H rank : 260 C Max.

170 C to 190 C

RT

(b)

(c)

(d)

(e)

(a)

(d')

(a) Temperature Increase gradient (b) Preliminary heating (c) Temperature Increase gradient (d) Actual heating (d)

: Average 1 C/s to 4 C/s : Temperature 170 C to 190 C, 60s to 180s : Average 1 C/s to 4 C/s : Temperature 260 C MAX; 255 C or more, 10s or less : Temperature 230 C or more, 40s or less or Temperature 225 C or more, 60s or less or Temperature 220 C or more, 80s or less : Natural cooling or forced cooling

(e) Cooling

Note : Temperature : the top of the package body (2) Manual soldering (partial heating method) Conditions : Temperature 400 C MAX Times : 5 s max/pin 27

MB3773
PACKAGE DIMENSION
8-pin plastic SOP Lead pitch Package width package length Lead shape Sealing method Mounting height Weight 1.27 mm 5.3 6.35 mm Gullwing Plastic mold 2.25 mm MAX 0.10 g P-SOP8-5.36.35-1.27

(FPT-8P-M01)

Code (Reference)

8-pin plastic SOP (FPT-8P-M01)

*1 6.35 0.20 .250 .008
8
+0.25 +.010

Note 1) *1 : These dimensions include resin protrusion. Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder.
0.17 0.04 .007 .002
+0.03 +.001

INDEX

*2 5.300.30 7.800.40 (.209.012) (.307.016)

Details of "A" part 2.00 0.15

+0.25 +.010

.079 .006
1 4

(Mounting height)

"A" 0.13(.005)

0.25(.010) 0~8

1.27(.050)

0.470.08 (.019.003)

0.500.20 (.020.008) 0.600.15 (.024.006)

0.10 0.05

+0.10 +.004

.004 .002 (Stand off)

0.10(.004)

2002 FUJITSU LIMITED F08002S-c-6-7

Dimensions in mm (inches). Note: The values in parentheses are reference values.

28

MB3773

FUJITSU LIMITED
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