PROJECT STAGE 1

ELEC 5509 DESIGN PROJECT

Name : Kapil Bharadwaj Jonnavithula

Student ID : 100917744
Carleton University

Hand Calculations :
A1)
Given,
Burried Oxide thickness of 1000nm and Silicon film Thickness of 200nm.

A2)
Given,
nMos device has an n+ Poly Gate and a very lightly doped Si film.
There is no electric field in the gate oxide at threshold.
Surface electron concentration of 1016 cm-3.
Threshold voltage Vtn= ?

A3)

A4)
Suppose the silicon film is doped with concentration NA and fully depleted.
Silicon film doping NA = ?

At NA = 1.44* 1016 cm-3 , according to the calculation, Vtn =-Vtp.

This shift applies to both nMOS and pMOS transistors.
We can get the values using the Minimos too.
Using a p+ polygate for the pMOS device gives us the useful values of Vtn and Vtp..

MINIMOS Simulations:
B1)
By running the SOI Minimos example files, we get the Vtn and Vtp for a lightly doped Si film.
SOI example for nMOS to get Vtn.
* Carleton SOI CMOS, NMOS device, lightly doped Si film
DEVICE CHANNEL=N GATE=NPOLY TINS=50E-7 BULK=1E-4 KBULK=3.9 FILM=0.2e-4
W=1.0E-4 L=5.0E-4
* source/drain diffusion
PROFILE NS=3E20 TEMP=1080 TIME=600 NB=0.245E16
* Compute VT, defined as value of VG giving ID=1E-7A
OPTION MODEL=THRESH PHYSCHK=NO CU=1E-7
BIAS UD=0.1 UG=0
OUTPUT PSI=N ETRAN=N ELAT=N MIN=N DC=Y AVAL=N
END ERR=0.001 BIN=Y

By running it in the minimos, we get threshold voltage value.

Vtn = 0.414(v)
SOI example for pMOS :
DEVICE CHANNEL=P GATE=NPOLY TINS=50E-7 BULK=1E-4 KBULK=3.9 FILM=0.2e-4
W=1.0E-4 L=5E-4
OPTION MODEL=THRESH PHYSCHK=NO CU=1E-7
* source/drain implant
PROFILE ELEM=B DOSE=3E15 AKEV=50 TEMP=1000 TIME=600 NB=1E11 SUBS=P
* dummy implant to create an n-type region at Si film surface
IMPLANT ELEM=AS DOSE=8E10 AKEV=50 TEMP=900 TIME=60
BIAS UD=-0.1 UG=0.0
OUTPUT PSI=N ETRAN=N ELAT=N MIN=N DC=Y AVAL=N
END ERR=0.001 BIN=Y

Vtp = -1.159 ( V)
The Threshold voltages of nMOS and pMOS i.e. Vtn and Vtp have a huge contrast as the NA value is
different in both the cases.
When the NA value is high, we can see the positive values in the threshold voltages.
B2)
Here we need to find the Si film doping that is required to give Vtn = -Vtp.
when NA =1016( from the hand calculations) ,
for nMOS, Vtn= 0.414(V)
for pMOS , Vtp= -0.530(V)
When NA= 1.1*1016 ,
for nMOS , Vtn= 0.464(V)
for pMOS , Vtp= -0.462(V)
At this NA value, Vtn = =Vtp
Vtp for pMOS,

Vtn for nMOS,

For the following simulations, we will be using NA = 1.1E16.

B3) We can calculate the Subthreshold swing ( S) based on the drain current and VGS values.
Let us consider a nMOS device,
DEVICE CHANNEL=N GATE=NPOLY TOX=50E-7 W=1.0E-4 L=5.0E-4
PROFILE NS=3E20 TEMP=1080 TIME=600 NB=1.1E16
OPTION MODEL=THRESH PHYSCHK=NO CU=1E-9
BIAS UD=0.1 UG=0 UB=-1
OUTPUT PSI=N ETRAN=N ELAT=N MIN=N DC=N AVAL=N
END ERR=0.001 BIN=Y
By changing the CU to 1E-9 , we get one VGS value.
From minimos : ID= 1nA , Vgs = 0.912(V)
ID=10nA, Vgs = 0.006(V)

Subthreshold swing S = 85mV/decade ( this is a bulk CMOS )

For pMOS device,
From minimos :
ID= 1nA, Vgs=-0.009
ID=10nA, Vgs=0.058

Subthreshold Swing, S= 67mV/decade ( Almost equal to the theoritical minimum of 60mV/decade).

B4)
Let us consider nMOS device,
DEVICE CHANNEL=N GATE=NPOLY TOX=50E-7 W=1.0E-4 L=2.0E-4
PROFILE NS=3E20 TEMP=1080 TIME=600 NB=1.1E16
OPTION MODEL=THRESH PHYSCHK=NO CU=1E-7
BIAS UD=0.1 UG=0 UB=-1
OUTPUT PSI=N ETRAN=N ELAT=N MIN=N DC=N AVAL=N
END ERR=0.001 BIN=Y
When L=5m, Vt = 1.172( V)
Reducing the value to L=2m, Vt = 0.971V
This shows that there are short channel effects in the nMOS device.
The following graph gives the drain induced barrier lowering in the nMOS device.

Let us consider a pMOS device,

DEVICE CHANNEL=P GATE=NPOLY TINS=50E-7 BULK=1E-4 KBULK=3.9 FILM=0.2e-4
W=1.0E-4 L=2.0E-4
OPTION MODEL=THRESH PHYSCHK=NO CU=1E-7
PROFILE ELEM=B DOSE=3E15 AKEV=50 TEMP=1000 TIME=600 NB=1.1E16 SUBS=P
IMPLANT ELEM=AS DOSE=8E10 AKEV=50 TEMP=900 TIME=60
BIAS UD=-0.1 UG=0.0
OUTPUT PSI=N ETRAN=N ELAT=N MIN=N DC=Y AVAL=N
END ERR=0.001 BIN=Y
When L=5m, Vt= -0.462V
Reducing th value to L=2m, Vt= -0.194(V)
This device does not suffer significant short channel effects.

The following graph gives the drain induced barrier lowering for the pMOS device.

B5)
Given,
L=2m
From the following simulation in the postmini console, we can get the peak generation rate.

Peak Generation rate for nMOS

The hole current injected into the well can be determined by the following simulation model on
postmini.

Hole current ( current injected into the well)

Hot carrier effects are significant in heavily doped devices. Since our device is lightly doped, the effect
of hot carriers cannot be seen much. Hot carrier effects are worse in the nMOS device than the
analogous pMOS device.
B6)
To find the smallest channel length ( L) that provides acceptable short channel and hot carrier
behaviour for both nMOS and pMOS,
We need to plot a graph between the lengths and the threshold voltages( Vt) after we simulate the
values using different lengths in Minimos.
For a nMOS device,
L

Vt
0.9
1
1.5
2
3
5
7
9
10

-1.323
-0.559
0.19
0.307
0.389
0.464
0.52
0.569
0.594

0.5

0
0
-0.5

-1

-1.5

10

12

Vt

For a pMOS device

L

Vt
0.9
1
1.5
2
3
5
7
9
10

0.143
0.057
-0.119
-0.194
-0.3
-0.462
-0.587
-0.715
-0.77

0.4
0.2
0
0

10

12

-0.2
-0.4

Vt

-0.6
-0.8
-1

As the threshold voltage decreases, the short channel effect decreases and the hot carrier effects
increase and as the threshold voltage increase, the short channel effects increase and the hot carrier
effects decrease. Thus reducing the threshold voltage by decreasing the channel length gives us short
channel effect. Both the short channel and hot carrier behaviour are dependent on channel Length(L).