This application note provides detailed information on how 3rd party FPGA development boards can be used with Altium Designer.
When developing an FPGA design using Altium Designer, the full, feature-rich Live Design environment becomes available with the presence of a NanoBoard and, when wishing to use the available processor cores, an appropriate licensing option for the software. Many Engineers and Designers already possess 3rd party FPGA development boards or their own custom/production boards. Altium Designer provides support for interfacing to such boards.
development board. Connect the JTAG Soft Device chain signals to the relevant general purpose I/O header, which has four device IO pins available. If the parallel cable does not end in fly leads, you will need to 'tap-off' the soft signals from the parallel port cable and wire them to the relevant general purpose header. Whichever method of connection you decide upon and especially if you wish to wire up the JTAG Soft chain from the parallel port, care must be taken to ensure that the voltage levels of the JTAG signals sent to a physical device are at safe levels for that device. For example, if the physical device has a supply voltage of 2.5V, sending JTAG signals direct from the parallel port (with voltages of 5V) would be too high. In such cases, voltage translation (or shifting) would be required to step the voltage down to required (and safe) operating levels for the FPGA device (see the section entitled Voltage Shifting).
FPGA
Hard Soft
MCU Virtual Inst
Figure 1. Accessing information for Hard and Soft Devices chains over the parallel port cable
To simplify the process of wiring between the parallel port on the PC and the development board, the software supports reprogramming which pins on the parallel port are used to implement the two JTAG chains.
The mappings used in the [HardChannel] section of both the Altera.JTGBRD and Xilinx.JTGBRD files have been set to use the parallel port pins designated by that Vendor. Although not typically supported, mappings in the [SoftChannel] section of the Xilinx.JTGBRD file have been defined ready, as an example. These should be modified according to design requirements. JTAG Board File The content of a JTAG Board file is divided into various sections. The following two sections are common to all files: [FileVersion] the version of the JTAG Board file [BoardDetails] includes the name of the board as well as any board ID(s). The latter are currently only supported for the NanoBoard and defined in the Nanoboard.JTGBRD file.
Following these are sections that detail mapping of the supported communication chains from the parallel port to the actual rd routing on the board named in the [BoardDetails] section. For 3 party boards, two sections can be declared: [HardChannel] mapping for the JTAG Hard Device chain [SoftChannel] mapping for the JTAG Soft Device chain.
Figure 2 shows an example of a JTAG Board file, in this case the file required to map the JTAG chains to a Xilinx development board Xilinx.JTGBRD.
Figure 2. Mapping JTAG device chains to a Xilinx development board using a JTAG Board file
JTAG Channel Mapping The mappings themselves use bit masks. Table 1 summarizes each of the mask values that can be used and how these values relate to the pins of the parallel port.
Table 1. Parallel Port Mapping mask values
Mask Value
2 3 4 5
10h 20h 40h 80h 0800h 1000h 2000h 4000h 8000h 010000h 020000h 040000h 080000h
6 7 8 9 15 13 12 10 11 1 14 16 17
The mapping is true for any standard IEEE 1284 parallel port cable used (e.g. the parallel port ribbon cable that comes with a NanoBoard, Parallel Cable III and IV or MultiPRO Desktop Tool for Xilinx and the ByteBlaster II for Altera). Using Table 1 in conjunction with any of the predefined JTAG Board files, the designated pins of the parallel port used for the JTAG channels can be easily determined. Consider for example, the Xilinx.JTGBRD file illustrated in Figure 2. Using Table 1, the pins of the parallel port used for the JTAG Hard Device chain can be determined as follows: [HardChannel] Mask_TCK = 000002 ..maps to pin 3 of the port Mask_TMS = 000004...maps to pin 4 of the port Mask_TDO = 001000...maps to pin 13 of the port Mask_TDI = 000001...maps to pin 2 of the port Similarly, the pins of the port that are used for the JTAG Soft Device chain can be decoded as: [SoftChannel] Mask_TCK = 000080 ..maps to pin 9 of the port Mask_TMS = 080000...maps to pin 17 of the port Mask_TDO = 004000...maps to pin 10 of the port Mask_TDI = 000020...maps to pin 7 of the port Note: Although the predefined Xilinx.JTGBRD file defines mapping for the JTAG Soft Device chain, support for these channels may not be present, depending on the development board you are connecting. Conversely, if you are creating a new JTAG Board file for your own custom board, or modifying an existing one, use Table 1 to determine the mask values to use for each JTAG channel, depending on the pins of the parallel port you wish to use. When choosing the pins of the port to use, the pins electrical type (input or output) must correspond to that of the JTAG signal: TCK, TMS and TDI must be mapped to output pins TDO must be mapped to an input pin.
Accessing unused Data pins of the Parallel Port Communication over both Hard and Soft JTAG chains simultaneously is not supported. Where use of both channels has been defined in the associated JTAG Board file a channel needs to be initialized (prior to using it) and then finalized (after communications over the channel have ceased). This initialization and finalization is handled by the Software using the Data Bus of the PC's parallel port. Any pins of the Data Bus that are not assigned to JTAG communications may freely be accessed and used for other purposes. For example, you may want to make available an additional signal that indicates which channel is currently in use. To provide access to unused pins of the Data Bus, the following additional parameters are definable in a JTAG Board file:
DataBackground the value assigned to this parameter is used to initialize the current channel. This value is output on the Data Bus of the parallel port (D7..D0). Any pins of this bus assigned for JTAG must be set (High). In the predefined Xilinx.JTGBRD file, the value used for this parameter is F7h. This value sets all lines of the Data Bus High, with the exception of D3 (i.e. 11110111). Lines D0, D1, D2, D5 and D7 have been assigned for JTAG and are therefore set high accordingly. D3 is, as an example, being used as a status signal to show whether a channel is in use. At channel initialization it is set Low.
DataFinal, Mask_DataFinal together, these two parameters are used to finalize use of the present channel. The value of each bit in DataFinal is written onto the data bus ONLY if the value of the corresponding bit in Mask_DataFinal is set. Again, any pins of this bus assigned for JTAG must be set (High). Continuing to look at the predefined Xilinx.JTGBRD file, the value 08h is defined for the DataFinal parameter and the value used for the mask (Mask_DataFinal parameter) is set to 08h also. With these values defined, use of the current communications channel will be finalized and the value xxxx1xxx written onto the data bus (D7..D0). D3, which in this example is being used to provide channel communications status, is taken High.
NanoBoard
JTAG Header
rd
The User Board A and B connectors facilitate the connection of two development boards. Both headers give access to the JTAG Hard and Soft Device chains eight signals in total. The pinout is identical for both headers. The pinout for the User Board A header can be seen in Figure 4.
If you just want to connect the JTAG Hard Device chain, simply connect from the designated JTAG header of the development board to the desired User Board header on the NanoBoard. Pin 10 of the User Board header must be connected to ground in order for the NanoBoard's Controller to detect that a board is connected to the header. The Controller will then reroute the Hard and Soft JTAG chains via the header accordingly. If you wish to also enable communications to Nexus-enabled devices within a design, the JTAG Soft Device chain signals must be wired from the User Board header of the NanoBoard to four accessible FPGA I/O pins (as discussed earlier in the section Software to Development Board Communications). If you do not intend to use the soft chain, pin 5 of the header should be connected to pin 6. To only detect device(s) on the 3rd party board, ensure that any Daughter Board currently plugged into the NanoBoard is removed. If a Daughter Board remains present it must be programmed with a design, otherwise the JTAG Soft Device chain will not be routed correctly through the Daughter Board and on to the User Board header. As such, the chain will be broken and you will not see soft devices within the design running on your development board. The voltage level present at each User Board header is 3.3V the voltage already having been translated on-board from the 5V level supplied by the parallel port. For the majority of FPGA devices, this voltage will be that expected by the device. In such cases connection of the JTAG channels is straightforward. If the voltage of the device is lower than 3.3V, further shifting-down of the voltage is required (see the section entitled Voltage Shifting).
JTAG link
Hard
FPGA
Soft
MCU
Virtual Inst
User Board A
User Board B
Figure 5. Accessing information for the multiplexed JTAG chains over a single JTAG link
Voltage Shifting
When connecting a development board directly to the PC via the parallel port, the voltage level of the JTAG signals from the port are at a level of 5V. This level exceeds the safe operating voltage level for signals connected to FPGA devices. The voltage
level of the JTAG channel signals must therefore be shifted / translated into a smaller, safer level, prior to being delivered to the pins of the physical FPGA device. For a 3rd party development board, voltage shifting with respect to the JTAG Hard Device chain signals is normally provided either on the board itself or in the connector of the dedicated parallel port cable. For a custom-made board, you will need to add the required voltage shifting circuitry yourself. Similarly for JTAG Soft Device chain signals, the majority of development boards will not have provision for such signals and therefore, when wiring up the signals yourself, they will still be at the voltage level defined by the parallel port interface 5V. The voltage level will therefore need to be shifted down. The required voltage shifting of the Soft JTAG signals could be easily done by creating an additional interfacing board and adding the relevant voltage shifting circuitry to it. The 74LVC244A octal buffer/line driver with 5V tolerant I/O is particularly well suited to such a job. For example, you could create your own additional interface board that takes the parallel port cable into a header, then routes the individual JTAG chain signals to individual headers for output to the development board. The JTAG Hard Device chain signals will of course be wired directly between input and output headers. The JTAG Soft Device chain signals will run through the required voltage shifting stage, prior to arriving at the output header. Figure 6 illustrates how such a board could be used to connect the development board to the PC
To PC
V Shift Circuitry
Figure 6. Example voltage shifting of Soft JTAG signals via a purpose-built interface board
This approach of separating the design source files (schematics & HDL) from the implementation details (constraint files) lets you easily map one design to different device + PCB combinations. Since the FPGA project can have multiple constraint files targeting different implementations, you need some way of configuring when the different constraint files are used. This is done by defining a unique configuration for each target implementation for each configuration you specify which constraint file(s) to use. For an overview of using Altium Designer to develop an FPGA design, see An Introduction to Embedded Intelligence. For detailed information on how to create an FPGA project, add source schematic and/or HDL documents, place and wire components and implement the design in an FPGA, see the Getting Started with FPGA Design tutorial.
Available (and supported) devices will have a pin number value entered in the main device availability grid as well as information made available in the Selected Device region of the dialog. Devices that do not exist are represented by a hyphen character '-'. Use the dialog to locate and select the required device and click OK. A corresponding record will be added to the constraint file, targeting the chosen device. The entry will appear in the form: ;..................................................................... Record=Constraint | TargetKind=Part | TargetId=XC2S300E-6PQ208C ;.....................................................................
These devices can be found in the FPGA NB2DSK01 Port-Plugin (FPGA NB2DSK01 Port-Plugin.IntLib) and FPGA Generic (FPGA Generic.IntLib) integrated libraries respectively, both of which are located in the \Library\Fpga folder of the installation. These signals must then be mapped to physical pins of the FPGA device the same four pins that are brought out from the device to the general purpose I/O header to which you have wired the physical connections for the soft JTAG chain from the parallel port of the PC. This mapping is carried out in the constraint file, as described in the next section.
For a clock signal, you may prefer to instruct the place and route tools which ports are to be assigned to clock pins, then let the place and route tool choose from the available clock pins on the target device. For example, to constrain the soft JTAG clock signal (JTAG_NEXUS_TCK) to an FPGA clock resource, you would use the following entry in the constraint file:
Record=Constraint|TargetKind=Port|TargetId=JTAG_NEXUS_TCK|FPGA_CLOCK=TRUE
Taking this constraint one step further, you could define the frequency to be assigned to this signal, for example:
Record=Constraint|TargetKind=Port|TargetId=JTAG_NEXUS_TCK|FPGA_CLOCK_FREQUENCY=1 Mhz
If you have left pin assignment for the place and route tools, when the place and route process is complete the pin assignments can be imported into the constraint file using the Import Pin File command, from the Constraint Editor's Design menu.
Creating a Configuration
Once the device has been specified and the nets mapped to pins there is one last step before you can process and download the design to the target FPGA, that is to define a configuration. Think of a configuration as board + device implementation information. To do this, right-click on the FPGA project name in the Projects panel and select Configuration Manager. The Configuration Manager dialog will appear (Figure 10).
After creating a new configuration, click the appropriate check box(es) to specify which constraint files, currently defined for the project, are to be included. For a detailed description of configurations and constraint files, see the Design Portability, Configurations and Constraints article.
AP0119 (v2.0) May 15, 2008
For details about creating your own constraint file and getting to synthesis, see the Re-targeting the design to the Production Board application note. For detailed information on constraint syntax, see the Constraint File Reference.
Figure 11. Successful detection of the physical device on a 3rd party development board
The Soft Devices chain should contain an entry for each Nexus-enabled device used in the design that is currently targeted to the physical device displayed in the Hard Devices chain. Figure 12 illustrates this using the example NiosStratixTest project. In this case, the design includes one processor and three virtual instruments. Remember that to use processor cores in a design, you will need to purchase the appropriate licensing option for your Altium Designer software.
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Note: The Soft Devices chain only becomes populated with the Nexus-enabled devices for a design, once that design has been compiled either from the Project or by running the Compile stage of the Process Flow associated with the physical device in question. To test correct operation of both the Hard and Soft JTAG chains, simply process and download the design to the physical device on the board. As the programming file is downloaded to the device, the progress will be shown in the Status bar. Once successfully downloaded, the text underneath the icon for the device will change from Reset to Programmed. You can, if desired, specify a specific user code ID for the device, by entering a dedicated hex code in the User ID Code for FPGA field, in the Options tab of the Options for FPGA Project dialog. By default, the entry in this field will be oxFFFFFFFF, which will yield Programmed in the Devices view when the device is successfully programmed. This is especially useful when your board has multiple FPGA devices of the same type and you want to easily distinguish which device is which from within the Devices view. When a specific ID code is defined, upon successful programming of a device the text underneath the device's icon will change from Reset to User-Code: n (Error! Reference source not found.), where n is the corresponding ID defined for that device.
Figure 13. Successful programming of the physical FPGA device
If the JTAG Soft Device chain is working correctly, any Nexus-enabled devices on the Soft Devices chain (in the Devices view) will be displayed as Running (Figure 14).
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The devices listed in the dialog will be those that appear on the Hard Devices chain in the Devices view.
The devices listed in the dialog will be those that appear on the Soft Devices chain in the Devices view.
Example Designs
A selection of example designs targeting 3rd party boards can be found in the /Examples/FPGA Third Party Boards rd folder of the installation. Table 2 lists the various 3 party boards included as examples and the specific devices targeted by the associated constraint file(s).
Table 2. 3 party development boards and devices featured as example designs
rd
Physical Device APA075-FPQ208 APA150-FPQ208 APA300-FPQ208 APA450-FPQ208 APA600-FPQ208 APA750-FPQ208 APA1000-FPQ208 EP1C20F400C7 EP1S10F780C6ES XC2S200-5PQ208C XC2S300E-6PQ208C XC2S300E-6FT256C XC2S200E-6PQ208C XC3S200-4FT256C
AP0119 (v2.0) May 15, 2008
Altera Cyclone20 Nios Development Board Altera Stratix10 Nios Development Board Burch B5-X200 Development Board Burch B5-X300 Development Board Digilent DigiLab 2FT Development Board Digilent DigiLab IIE Development Board Digilent Spartan 3 Development Board
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Memec CoolRunner XPLA3 Demo Board Memec CPLD95XL Demo Board Memec Spartan2E System Board (Rev.1) Memec Spartan3 SxLC (Rev.1) Memec Spartan II Demo Board (Rev.3) Memec Virtex2 V2MB1000 Dev Kit (Rev.3) Memec Virtex-II Pro Development Board Memec Virtex4 LX25 LC Development Board (Rev.1) Memec XC9500XV Demo Board NuHorizons CoolRunner2 Development Board (Rev.2) NuHorizons Spartan3 Development Board Parallax Stratix 672 SmartPack Xilinx Spartan3 Starter Kit
Note: In some design examples only constraint files may exist which target specific devices (and no schematic sheets). This is actually the simplest method of testing connection between the Software and a 3rd party development board to see that the physical device is detected and appears correctly in the Hard Devices chain of the Devices view.
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Figure 15. Multiple IP files are supported. For better management, there are options for copying to a project directory or zipping up core files together.
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Figure 16. Advanced and custom build stage options give you full control over every build stage. The ability to insert custom command lines is also available.
Revision History
Date 25-Jun-2004 23-Mar-2005 18-Jul-2005 12-Dec-2005 12-Apr-2007 15-May-2008 Version No. 1.0 1.1 1.2 1.3 1.4 2.0 Revision Initial Release Document renamed. Table 2 updated. Updated for Altium Designer SP4 Path references updated for Altium Designer 6 Updated for Altium Designer 6.7 Updated for Altium Designer Summer 08
Software, hardware, documentation and related materials: Copyright 2008 Altium Limited. All Rights Reserved. The material provided with this notice is subject to various forms of national and international intellectual property protection, including but not limited to copyright protection. You have been granted a non-exclusive license to use such material for the purposes stated in the end-user license agreement governing its use. In no event shall you reverse engineer, decompile, duplicate, distribute, create derivative works from or in any way exploit the material licensed to you except as expressly permitted by the governing agreement. Failure to abide by such restrictions may result in severe civil and criminal penalties, including but not limited to fines and imprisonment. Provided, however, that you are permitted to make one archival copy of said materials for back up purposes only, which archival copy may be accessed and used only in the event that the original copy of the materials is inoperable. Altium, Altium Designer, Board Insight, DXP, Innovation Station, LiveDesign, NanoBoard, NanoTalk, OpenBus, P-CAD, SimCode, Situs, TASKING, and Topological Autorouting and their respective logos are trademarks or registered trademarks of Altium Limited or its subsidiaries. All other registered or unregistered trademarks referenced herein are the property of their respective owners and no trademark rights to the same are claimed. v8.0 31/3/08.
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