Rectangular pulses generated with AT89S52. (Range 3rd Exercises) Assignment 1.

Create a rectangular signal generator alternating with 1:1 (1s) duty with AT89S52 and displays the result at the oscilloscope and at the !"s without interruption and with interruption o# counters $ ti%ers. The!r" Circuits work with bus &ay can 'e called circuits that operate with %ultiple inputs and outputs( and each is su')ect to the sa%e operation. *t is the dri+ers and %ultiple #lip,#lops ". This is actually a eight " #lip, #lops whose cloc- respecti+ely control inputs are co%'ined into a single outlet and controlled 'y edge or le+el. .or a large nu%'er o# inputs and outputs (8 inputs / 8 outputs / control signal) these circuits usually contain only one control input. *t is designed to control the output o# deli%iter as is the case with circuits 01 S502( 01 S501( 01 S202 and 01 S201 or reset (01 S202 circuit). .unction is easily understanda'le #ro% sche%atic (see .igure 1).

Fig. 1. Inputs and outputs of 74LS244, 74LS274, 74LS373 and 74LS374 circuits.

74LS244 - 4-bit unidirectional bus driver 01 S211 is a 1'it circuit with a pair o# one,way 'us dri+ers. 3oth dri+ers are %utually independent. *nputs A4 to A2 ha+e per#or%ance, enhanced e5citers and they ha+e ad)usted signals connected to the outputs 64 to 62. &hile tri,state outputs are controlled and acti+ated 7 entry in the log. 4 (#or 7 8 4 outputs are acti+ated( otherwise in a state o# high i%pedance). 74LS245 - 8-bit bidirectional bus driver 01 S215 is an 8,'it circuit with 'idirectional 'us dri+er. *nput 7 (acti+e in the log. 4) is used to control three,status dri+er. "*9 input deter%ines the direction o# trans%ission ("*9 8 1 #or %o+ing data in the direction A to 3( "*9 8 4 in the direction 3 to A). :ins A4 to A0 and 34 to 30( wor-ing either as inputs or outputs (that is deter%ined 'y the a'o+e,%entioned signal "*9). 74LS373 - 8-bit D flip-flop driven by three-status level of output These circuits include 8 inputs ("4 to "0) and 8 outputs (;4 to ;0) " #lip,#lops. .lip,#lops are controlled 'y le+els. *# is on input 7 log. 1( the latch is opened. .or 7 8 4 the latch is closed( the circuit <re%e%'ers< the pre+ious state. Access =C is acti+e in the log. 4 and is used to control the output deli%iter. &hen the =C 8 4 are outputs ;4 to ;0 acti+ated.

=therwise( you are in a state o# high i%pedance 'ut it is still controlled 'y sensor o# input 7. Thus only can 'e output in the high i%pedance state while we write to circuit. 74LS374 - 8-bit D flip-flop driven by leading edge of three-status output These circuits include 8 inputs ("4 to "0) and 8 outputs (;4 to ;0) " #lip,#lops. .lip,#lops are controlled 'y rising edge o# signal C >. =therwise si%ilar rules apply as #or circuit 01 S202. Interrupt *nterruption o# the progra% is a reaction to e5ternal e+ents. 9unning o# progra% is locally interrupted and 'egins run the progra%%ed routine. A#ter is progra%%ed routine at the end the progra% continues its wor- in the place where it was interrupted. AT89S52 %icrocontroller uses a total o# 8 interrupt sources. !ach interrupt source ha+e assigned a #i5ed address (see Ta'le 1)( to which the processor is trans#erred in the interruption. 9egister *: :?4 :T4 :?1 :T1 :S :T2 9egister *! !?4 !T4 !?1 !T1 !S !T2

address 4442h 4443h 4412h 4413h 4422h 4423h

Source interruption e5ternal interrupt 4 (input *@T4) counter $ ti%er 4 e5ternal interrupt 1 (input *@T1) counter $ ti%er 1 serial channel (recei+e $ 'roadcast character) counter $ ti%er 2 or e5ternal interrupt T2!?

Tab. 1 Registry and address of the interrupt sources Interrupts enable - the I A#ter a reset o# %icrocontroller AT89S52 is the inco%e o# any interruption prohi'ited. &e %ust the interruption ena'led #irst. 3it !A 8 4 disa'les all interrupts. To allow %ust 'e set !A 8 1 and set the corresponding 'it desired interruption. To set the recei+e interrupt #ro% the input %ust 'e allowed *@T= interrupt !A 8 1 and set !?4 8 1. *ndi+idual 'its o# *! register are 'it,addressa'le( so we can ena'le and disa'le each interrupt independently.

Register IE !ounter " ti#ers Counter is a circuit that counts pulses o# the e5ternal signal( such as rising or #alling edge o# the e5ternal signal #ro% the inducti+e or photoelectric sensors. The ti%er co%prises #i5ed #reAuency which is deri+ed #ro% the %icrocontroller cloc- signal. The AT89S52

%icrocontroller has counter $ ti%er with 1B'it length. 3oth counters and ti%ers wor- as ascending( i.e. contents o# %e%ory location to %anage( always incre%ents. Their content is accessi'le +ia %e%ory,%apped registers TC4( T 4 and TC1( T 1 which deter%ine the higher and lower sylla'le (8 'its) o# the counters. The cloc- synchroniDation signal to the counters can 'e deri+ed #ro% the oscillator processor or #ro% an e5ternal source at pins T4 and T1. *# internal oscillator is a source o# signal( then the counter is in the ti%er #unction. *n the #unction counter o# e5ternal e+ents( the content o# the counter (register) is increased 'y one when the signal Tn changed #ro% 1 to 4. *nputs T4 and T1 are 'eing tested at the state o# each %achine cycle. =ne %icroprocessor %achine cycle consists o# si5 states( ti%e (cloccycles , states) designated S1 to SB( each state is di+ided into two phases :1 and :2. Eachine cycle is thus %ade up a total o# 12 stages( which indicates S1:1( S1:2( S2:1( S2:2( and SB:2. !ach stage has a length o# one period stro-ing signal. "uration o# state: T= "uration o# the %achine cycle: T = B T = 12 G !" F f #S$ 2 f #S$ G !" F

achine cyc%e &here is in one cycle log. 1 (high +oltage) and in the ne5t log. 4 (low +oltage)( the contents o# the counter is incre%ented. The new counter +alue is set during the ne5t cycle. 3ecause input change detection Tn ta-es 2 %achine cycles (21 oscillator periods)( the %a5i%u% counting #reAuency o# the e5ternal signal 1 $ 21 oscillator #reAuency %icroco%puters. ogic le+el o# signal %ust always re%ain unchanged at least #ull one %achine cycle. Con#iguration o# counters$ti%ers 4 and 1 we can set at the register TE=". Start( stop or reset 'its o# custo% counters we can set in the Trn at the TC=@ register. $!%& 'egister - #anage#ent !ounter " ti#ers ($i#er " !ounter !ontrol) TC=@ register is 'it addressa'le( 'it register used to progra% startup or indication ti%er o+er#low.

Registr T$#& T.4( T.1 , indicate o+er#low o# counter$ti%er 1( the o+er#low is auto%atically set a#ter the entry into interruption ser+ice is auto%atically reset T94( T91 , allow counting pulse #or counter$ti%er 1 and 4 *!4( *!1 , Adoption o# the e5ternal interrupt. 9esponsi'le 'it is set #or #alling edge or le+el log.4 input e5ternal interrupt *@Tn depending on the state o# the con#iguration 'it *T@. A#ter the transition o# the processor ser+ice to the interrupt su'routine( 'it is auto%atically reset. *T4( *T1 , Con#iguration to acti+ate an e5ternal interrupt. *# *T@ 8 1( the application is acti+ated on the e5ternal interrupt (#alling edge) signal input *@Tn. *# *T@ 8 4( the application is acti+ated le+els log.4 input *@Tn. 'egister $*%D - #ode selection counter " ti#ers TE=" , Ti%er %ode register $ counter (Ti%er $ Counter %ode control) is not 'it,addressa'le( allowing the two %odes to choose counters $ ti%ers. *t is di+ided into two hal+es 'y 1 'its. The lower 1 'its control the counter $ ti%er 4 and the upper 1 'its control the counter $ ti%er 1.

Registr T #' 7AT! (7) %anages the control gate counters 7AT! 8 1 counter $ ti%er is controlled 'y a progra%%ed 'it T9@ and input *@Tn 7AT! 8 4 counter $ ti%er is controlled 'y a progra%%ed 'it T9@ C $ T (Counter $ Ti%er) choose whether counter $ ti%er will wor- as a counter or ti%er C $ T 8 4 wor-s as a ti%er cloc- signal is created #ro% the internal %icroprocessor cloc- sync signal deri+ed as 1 $ 12 cloc- signal C $ T 8 1 wor-s as a counter( cloc- input is Tn. The %a5i%u% #reAuency is 1 $ 21 cloc- signal E4( E1 (Eode) The co%'ination o# these 'its are chosen one o# #our %odes counters $ ti%ers. Eode 4 , the two counter $ ti%ers are 12'its TC@ has 8 'its and 5 'its T @. 3oth counted up( a#ter the o+er#low is set TC=@ register in the T.@ Eode 1 , the two counter $ ti%ers are 1B,'it and TC@( T @ has 8 'its. 3oth counted up( a#ter the o+er#low is set TC=@ register in the T.@

Eode 2 , the two counter $ ti%ers are 8,'it #unction with 9! =A"( this %eans that the o+er#low is returned to its original +alue. Eode 2 , *n this %ode the counter $ ti%er 4 is di+ided into two separate 8'it counter T 4 and Th4. Counter T 4 is controlled 'y 'it Counter $ Ti%er 4 uses the standard signal C $ T( 7AT!( T94( *@T4( and T.4. Th4 counter is controlled 'y 'it counter $ ti%er 1 is do%inated 'y only control 'it T91. =+er#low sets T.1 #lag. &or-s to counter $ ti%er 4 in %ode 2( then the counter $ ti%er 1 can only generate a 'aud rate #or serial channel or %ay 'e used when we use the 'rea-. 3ecause T91 'it is used #or %anaging counter$ti%er 4 is stopping or running counter$ti%er 1 controlled set,up %ode to %ode 2 or cancellation 2rd Schematic diagram of connection of the eight LEDs

Sche%atic diagra% o# the eight !"s includes an integrated circuit *=1 01CCT215 co%%only -nown as a power dri+er (power 'us). *nputs are A1 to A8( 31 to 38 outputs are in+ol+ed !". 3ecause non,in+erting dri+er 01CCT215 and !" diodes are connected to the anode supply +oltage( !" lights up when the input #or one o# A1 to A8 introduced log. 4. &hen connecting the product to the de+elop%ental -it to port :2( o## !" connected to 'its :1.5( :1.B and :1.0 these 'its are used #or the serial download.