Ee2258 Lab Manual New

EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY
Ex. No.:1 Date: AIM:
STUDY OF BASIC DIGITAL ICS.
To verify the truth table of basic digital ICs of AND, OR, NOT, NAND, NOR, EX-OR gates, J !!, R" !!, D!!# A ARATUS RE!UIRED: S".No $# '# ,# )# -# .# (# +# T.EORY: AND /ate: A% AND gate is the 1hysical reali2atio% of logical 3ulti1licatio% o1eratio%# It is a% electro%ic circuit /hich ge%erates a% out1ut sig%al of 4$5 o%ly if all the i%1ut sig%als are 4$5# OR /ate: A% OR gate is the 1hysical reali2atio% of the logical additio% o1eratio%# It is a% electro%ic circuit /hich ge%erates a% out1ut sig%al of 4$5 if a%y of the i%1ut sig%al is 4$5# NOT /ate: A NOT gate is the 1hysical reali2atio% of the co31le3e%tatio% o1eratio%# It is a% electro%ic circuit /hich ge%erates a% out1ut sig%al /hich is the reverse of the i%1ut sig%al# A NOT gate is also &%o/% as a% i%verter because it i%verts the i%1ut# NAND /ate: A NAND gate is a co31le3e%ted AND gate# The out1ut of the NAND gate /ill be 4*5 if all the i%1ut sig%als are 4$5 a%d /ill be 4$5 if a%y o%e of the i%1ut sig%al is 4*5# AND GATE LOGIC DIAGRAM:
CA6E IN"TIT7TE O! TEC8NO9O:; 6age $
Na#e o$ t%e A&&a'at() Digital IC trai%er &it AND gate OR gate NOT gate NAND gate NOR gate EX-OR gate Co%%ecti%g /ires
S&e*+$+*at+o, IC ()*+ IC (),' IC ()*) IC ()** IC ()*' IC ()+.
!(a,t+t$ $ $ $ $ $ $ As re0uired
A Y0A.B B IN DIAGRAM OF IC 1238 :
CIRCUIT DIAGRAM:
TRUT. TABLE: S".No

$# '# ,# )# IN UT A * * $ $ B * $ * $ OUT UT Y0A.B * * * $
NOR /ate: A NOR gate is a co31le3e%ted OR gate# The out1ut of the OR gate /ill be 4$5 if all the i%1uts are 4*5 a%d /ill be 4*5 if a%y o%e of the i%1ut sig%al is 4$5#
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E45OR /ate: A% E<-OR gate 1erfor3s the follo/i%g =oolea% fu%ctio%, A B 0 6 A . B 7 8 6 A . B 7 It is si3ilar to OR gate but e<cludes the co3bi%atio% of both A a%d = bei%g e0ual to o%e# The e<clusive OR is a fu%ctio% that give a% out1ut sig%al 4*5 /he% the t/o i%1ut sig%als are e0ual either 4*5 or 4$5# FLI FLO A !li1 !lo1 is a se0ue%tial device that sa31les its i%1ut sig%als a%d cha%ges its out1ut states o%ly at ti3es deter3i%ed by cloc&i%g sig%al# !li1 !lo1s 3ay vary i% the %u3ber of i%1uts they 1ossess a%d the 3a%%er i% /hich the i%1uts affect the bi%ary states# RS FLI FLO : The cloc&ed R" fli1 flo1 co%sists of NAND gates a%d the out1ut cha%ges its state /ith res1ect to the i%1ut o% a11licatio% of cloc& 1ulse# >he% the cloc& 1ulse is high the " a%d R i%1uts reach the seco%d level NAND gates i% their co31le3e%tary for3# The !li1 !lo1 is reset /he% the R i%1ut high a%d " i%1ut is lo/# The !li1 !lo1 is set /he% the " i%1ut is high a%d R i%1ut is lo/# >he% both the i%1uts are high the out1ut is i% a% i%deter3i%ate state# D FLI FLO : To eli3i%ate the u%desirable co%ditio% of i%deter3i%ate state i% the "R !li1 !lo1 /he% both i%1uts are high at the sa3e ti3e, i% the D !li1 !lo1 the i%1uts are %ever 3ade e0ual at the sa3e ti3e# This is obtai%ed by 3a&i%g the t/o i%1uts co31le3e%t of each other# 9: FLI FLO : The i%deter3i%ate state i% the "R !li1-!lo1 is defi%ed i% the J !li1 !lo1# J i%1uts behave li&e " a%d R i%1uts to set a%d reset the !li1 !lo1# The out1ut ? is ANDed /ith i%1ut a%d the cloc& 1ulse, si3ilarly the out1ut ?5 is ANDed /ith J i%1ut a%d the Cloc& 1ulse# >he% the cloc& 1ulse is 2ero both the AND gates are disabled a%d the ? a%d ?5 out1ut retai% their 1revious values# >he% the cloc& 1ulse is high, the J a%d i%1uts reach the NOR gates# >he% both the i%1uts are high the out1ut toggles co%ti%uously# This is called Race arou%d co%ditio% a%d this 3ust be avoided# T FLI FLO : This is a 3odificatio% of J !li1 !lo1, obtai%ed by co%%ecti%g both i%1uts J a%d together# T !li1 !lo1 is also called Toggle !li1 !lo1# OR GATE LOGIC DIAGRAM:
i%1uts
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IN DIAGRAM OF IC 12;2 :
CIRCUIT DIAGRAM:
TRUT. TABLE: S".No

A $# '# ,# )# * * $ $ IN UT B * $ * $ OUT UT Y0A8B * $ $ $
ROCEDURE:
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LOGIC GATES: $# Co%%ectio%s are give% as 1er the circuit diagra3 '# !or all the ICs (th 1i% is grou%ded a%d $)th 1i% is give% @- A su11ly# ,# A11ly the i%1uts a%d verify the truth table for all gates# FLI FLO S: 1. Give connections as per the circuit diagram. 2. Inputs are given to the circuit making high 1 i.e. +5 V or + Vcc supply and for lo trainer kit. &. 'he (inary input !!$ !1$ 1!$ 11 are given and the outputs are o(served. ). *epeat the same procedure for +,$ #$ and ' -lip.-lops and verify the truth ta(le. ! i.e. G"#$ clock input is given from the I%
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NOT GATE LOGIC DIAGRAM: AAA Y0A
IN DIAGRAM OF IC 1232 :
CIRCUIT DIAGRAM:
TRUT. TABLE:
S".No
IN UT A
OUT UT Y0A $
$#
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'#
<I<A5<OICE: $# >hat is I%tegrated CircuitB '# >hat is a 9ogic gateB ,# >hat are the basic digital logic gatesB )# >hat are the gates called u%iversal gatesB -# >hy NAND a%d NOR gates are called u%iversal gatesB .# >hat are the 1ro1erties of EX-NOR gateB (# >hat is !li1 flo1B +# >hat are the characteristics of a cloc&ed R-" fli1 flo1B C# >hat is the differe%ce bet/ee% 9atch a%d !li1 flo1B $*# 8o/ ca% you co%vert "R fli1 flo1 to J fli1 flo1B
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NAND GATE LOGIC DIAGRAM: A Y0A.B B IN DIAGRAM OF IC 1233 :
CIRCUIT DIAGRAM:
TRUT. TABLE: S".No

A $# CA6E IN"TIT7TE O! TEC8NO9O:; * IN UT B * OUT UT Y06A.B7 $ 6age +
'# ,# )#
* $ $
$ * $
$ $ *
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NOR GATE LOGIC DIAGRAM:
IN DIAGRAM OF IC 1232 :
CIRCUIT DIAGRAM:
TRUT. TABLE:
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S".No
A $# '# ,# )# * * $ $
IN UT B * $ * $
OUT UT Y06A8B7 $ * * *
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E45OR GATE LOGIC DIAGRAM:
IN DIAGRAM OF IC 128= :
C IRCUIT DIAGRAM:
TRUT. TABLE:
S".No
IN UT
OUT UT
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A $# '# ,# )# * * $ $
B * $ * $
Y0A 8 B * $ $ *
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RS FLI FLO LOGIC SYMBOL:
CIRCUIT DIAGRAM:
C.ARACTERISTIC TABLE:
CLOC: ULSE 1 2 ; 2 5 = 1 8 IN UT S 3 3 3 3 1 1 1 1 R 3 3 1 1 3 3 1 1 RESENT STATE 6!7 3 1 3 1 3 1 3 1 NE4T STATE6!817 3 1 3 3 1 1 4 4 STATUS No *%a,/e No *%a,/e Re)et Re)et Set Set U,>ete'#+,e>
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TRUTH TABLE: R 3 3 1 1 S 3 1 3 1 ! 3 1 3 1 ! 1 3 1 1
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D FLI FLO LOGIC SYMBOL:
CIRCUIT DIAGRAM:
C.ARACTERISTIC TABLE: CLOC: ULSE 1 2 IN UT D 3 3 RESENT STATE 6!7 3 1 NE4T STATE6!817 3 3

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; 2
1 1
3 1
1 1
TRUTH TABLE:
D 1 3 !6 'e)e,t State7 1 3 !816Next Seate7 3 1
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9: FLI FLO LOGIC SYMBOL: CIRCUIT DIAGRAM:
C.ARACTERISTIC TABLE: CLOC: IN UT ULSE 9 1 3 2 3 ; 3 2 3 5 1 = 1 1 1

: 3 3 1 1 3 3 1
RESENT STATE 6!7 3 1 3 1 3 1 3
NE4T STATE6!817 3 1 3 3 1 1 1
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TRUTH TABLE: 9 3 3 1 1 : 3 1 3 1 ! 1 1 3 1 ! 3 3 1 1
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T FLI FLO LOGIC SYMBOL:
CIRCUIT DIAGRAM:
C.ARACTERISTIC TABLE: CLOC: IN UT ULSE T 1 2 ; 2 3 3 1 1
RESENT STATE 6!7 3 1 3 1
NE4T STATE6!817 3 3 1 3
TRUTH TABLE:
T
!
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3 1
1 3
1 1
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RESULT: Thus the truth table of all the basic digital ICs a%d the fli1 flo1s are verified# .ALF ADDER TRUT. TABLE: S.No 1. 2. ;. 2. IN UT A 3 3 1 1 B 3 1 3 1 S 3 1 1 3 OUT UT C 3 3 3 1
DESIGN: !ro3 the truth table the e<1ressio% for su3 a%d carry bits of the out1ut ca% be obtai%ed as, S(#? S 0 A B
Ca''-? C 0 A . B CIRCUIT DIAGRAM:
-Da1 for "7DE

-Da1 for CARR;E

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SUM 0 AB 8 AB Ex. No.: 2 Date: AIM:
CARRY 0 AB
DESIGN OF ADDER AND SUBTRACTOR
To desig% a%d verify the truth table of the 8alf Adder, 8alf "ubtractor, !ull Adder F !ull "ubtractor circuits. A ARATUS RE!UIRED: S".No $# '# ,# )# -# .# T.EORY: ADDER: The 3ost basic arith3etic o1eratio% is the a>>+t+o, of t/o bi%ary digits# There are four 1ossible ele3e%tary o1eratio%s, %a3ely, *@*G* *@$G$ $@*G$ $ @ $ G $*' Na#e o$ t%e A&&a'at() Digital IC trai%er &it AND gate OR gate NOT gate EX-OR gate Co%%ecti%g /ires IC ()*+ IC (),' IC ()*) IC ()+. S&e*+$+*at+o, !(a,t+t$ $ $ $ $ As re0uired
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The first three o1eratio%s 1roduce a su3 of /hose le%gth is o%e digit, but /he% the last o1eratio% is 1erfor3ed the su3 is t/o digits# The higher sig%ifica%t bit of this result is called a carry a%d lo/er sig%ifica%t bit is called the su3# .ALF ADDER: A co3bi%atio%al circuit /hich 1erfor3s the additio% of t/o bits is called half adder# The i%1ut variables desig%ate the auge%d a%d the adde%d bit, /hereas the out1ut variables 1roduce the su3 a%d carry bits# FULL ADDER TRUT. TABLE: S.No 1. 2. ;. 2. 5. =. 1. 8. IN UT A 3 3 3 3 1 1 1 1 B 3 3 1 1 3 3 1 1 C 3 1 3 1 3 1 3 1 OUT UT SUM 3 1 1 3 1 3 3 1 CARRY 3 3 3 1 3 1 1 1
DESIGN: !ro3 the truth table the e<1ressio% for su3 a%d carry bits of the out1ut ca% be obtai%ed as, SUM 0 ABC 8 ABC 8 ABC 8 ABC CARRY 0 ABC 8 ABC 8 ABC 8ABC 7si%g ar%augh 3a1s the reduced e<1ressio% for the out1ut bits ca% be obtai%ed as, SUM
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SUM 0 ABC 8 ABC 8 ABC 8 ABC 0 A FULL ADDER:
A co3bi%atio%al circuit /hich 1erfor3s the arith3etic su3 of three i%1ut bits is called full adder# The three i%1ut bits i%clude t/o sig%ifica%t bits a%d a 1revious carry bit# A full adder circuit ca% be i31le3e%ted /ith t/o half adders a%d o%e OR gate# SUBTRACTOR The arith3etic o1eratio%, subtractio% of t/o bi%ary digits has four 1ossible ele3e%tary o1eratio%s, %a3ely, *-*G* * - $ G $ /ith $ borro/ $-*G$ $-$G* I% all o1eratio%s, each subtrahe%d bit is subtracted fro3 the 3i%ue%d bit# I% case of the seco%d o1eratio% the 3i%ue%d bit is s3aller tha% the subtrahe%d bit, he%ce $ is borro/ed# .ALF SUBTRACTOR: A co3bi%atio%al circuit /hich 1erfor3s the subtractio% of t/o bits is called half subtractor# The i%1ut variables desig%ate the 3i%ue%d a%d the subtrahe%d bit, /hereas the out1ut variables 1roduce the differe%ce a%d borro/ bits# FULL SUBTRACTOR:
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A co3bi%atio%al circuit /hich 1erfor3s the subtractio% of three i%1ut bits is called full subtractor# The three i%1ut bits i%clude t/o sig%ifica%t bits a%d a 1revious borro/ bit# A full subtractor circuit ca% be i31le3e%ted /ith t/o half subtractors a%d o%e OR gate#
CARRY
CARRY 0 AB 8 AC 8 BC CIRCUIT DIAGRAM:
.ALF SUBTRACTOR TRUT. TABLE: S.No 1. 2. IN UT A 3 3 B 3 1 OUT UT DIFF BORR 3 3 1 1

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;. 2. DESIGN:
1 1
3 1
1 3
3 3
!ro3 the truth table the e<1ressio% for differe%ce a%d borro/ bits of the out1ut ca% be obtai%ed as, D+$$e'e,*e? DIFF 0 A B
Bo''o@? BORR 0 A . B ROCEDURE: $# Co%%ect the circuit as 1er the circuit diagra3 2. -or all the I%s /th pin is grounded and 1)th pin is given +5 V supply. ,# !or various i%1uts, %ote the corres1o%di%g out1ut# )# Aerify the truth table#
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CIRCUIT DIAGRAM:
-Da1 for DI!!ERENCEE
-Da1 for =ORRO>E
DIFFERENCE 0 AB 8 AB
BORROA 0 AB
FULL SUBTRACTOR TRUT. TABLE: S.No 1. IN UT A 3 B 3 C 3 OUT UT DIFF 3 BORR 3
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2. ;. 2. 5. =. 1. 8.
3 3 3 1 1 1 1
3 1 1 3 3 1 1
1 3 1 3 1 3 1
1 1 3 1 3 3 1
1 1 1 3 3 3 1
<I<A5<OICE: $# >hat is co3bi%atio%al circuitB '# >hat is differe%t bet/ee% co3bi%atio%al a%d se0ue%tial circuitB ,# >hat are the gates i%volved for bi%ary adderB )# 9ist the 1ro1erties of E<-Nor gateB -# >hat is e<1ressio% for su3 a%d carryB .# >hat is half adderB (# >hat is full adderB +# >hat are half subtractor a%d full subtractorB
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DESIGN: !ro3 the truth table the e<1ressio% for differe%ce a%d borro/ bits of the out1ut ca% be obtai%ed as, D+$$e'e,*e? DIFF0 ABC 8 ABC 8 ABC 8 ABC Bo''o@? BORR 0 ABC 8 ABC 8 ABC 8ABC 7si%g ar%augh 3a1s the reduced e<1ressio% for the out1ut bits ca% be obtai%ed as, DIFFERENCE
DIFF 0 ABC 8 ABC 8 ABC 8 ABC 0 A BORROA
BORR 0 AB 8 AC 8 BC
CA6E IN"TIT7TE O! TEC8NO9O:; 6age ,*
CIRCUIT DIAGRAM:
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RESULT: Thus the desig% of the half adder, half subtractor, full adder F full subtractor circuits /as do%e a%d their truth tables /ere verified# BINARY TO GRAY: LOGIC DIAGRAM:
TRUT. TABLE:
B; 3 3 3 3 3 3 IN UTS6BINARY CODE7 B2 B1 3 3 3 3 3 1 3 1 1 3 1 3 B3 3 1 3 1 3 1 G; 3 3 3 3 3 3 OUT UTS6GRAY CODE7 G2 G1 3 3 3 3 3 1 3 1 1 1 1 1 G3 3 1 1 3 3 1
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3 3 1 1 1 1 1 1 1 1
1 1 3 3 3 3 1 1 1 1
1 1 3 3 1 1 3 3 1 1
3 1 3 1 3 1 3 1 3 1
3 3 1 1 1 1 1 1 1 1
1 1 1 1 1 1 3 3 3 3
3 3 3 3 1 1 1 1 3 3
1 3 3 1 1 3 3 1 1 3
Ex. No.:; Date: AIM:
DESIGN AND IM LEMENTATION OF CODE CON<ERTERS
To desig% a%d verify the truth table of =i%ary to :ray code, :ray to =i%ary Code, =CD to E<cess-, code co%verter circuits# ARATUS RE!UIRED: S".No $# '# ,# )# -# .# Na#e o$ t%e A&&a'at() Digital IC trai%er &it AND gate OR gate NOT gate EX-OR gate Co%%ecti%g /ires IC ()*+ IC (),' IC ()*) IC ()+. S&e*+$+*at+o, !(a,t+t$ $ $ $ $ As re0uired
T.EORY: Code co%verter is a circuit that 3a&es t/o syste3s co31atible eve% though each uses differe%t bi%ary codes# There is a /ide variety of bi%ary codes used i% digital syste3s# "o3e of these codes are =i%ary Coded Deci3al, :ray code, E<cess- , code , A"CII code, etc# BINARY TO GRAY: The D"= of the bi%ary code alo%e re3ai%s u%cha%ged i% the :ray code# The re3ai%i%g bits i% the gray are obtai%ed by EX-OR i%g the corres1o%di%g gray code bit a%d 1revious bit i%
CA6E IN"TIT7TE O! TEC8NO9O:; 6age ,,
the bi%ary code# The gray code is ofte% used i% digital syste3s because it has the adva%tage that o%ly o%e bit i% the %u3erical re1rese%tatio% cha%ges bet/ee% successive %u3bers# GRAY TO BINARY: The D"= of the :ray code re3ai%s u%cha%ged i% the bi%ary code the re3ai%i%g bits are obtai%ed by EX H OR i%g the corres1o%di%g gray code bit a%d the 1revious out1ut bi%ary bit# BCD TO E4CESS ;: Code co%verter is a co3bi%atio%al circuit that tra%slates the i%1ut code /ord i%to a %e/corres1o%di%g /ord# The e<cess-, code digit is obtai%ed by addi%g three to the corres1o%di%g=CD digit# To Co%struct a =CD-to-e<cess-,-code co%verter /ith a )-bit adder feed =CD-code to the )-bit adder as the first o1era%d a%d the% feed co%sta%t , as the seco%d o1era%d#The out1ut is the corres1o%di%g e<cess-, code#
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GRAY TO BINARY LOGIC DIAGRAM:
TRUT. TABLE:
G; 3 3 3 3 3 3 3 IN UTS6GRAY CODE7 G2 G1 3 3 3 3 3 1 3 1 1 1 1 1 1 3 G3 3 1 1 3 3 1 1 OUT UTS6BINARY CODE7 B; B2 B1 B3 3 3 3 3 3 3 3 1 3 3 1 3 3 3 1 1 3 1 3 3 3 1 3 1 3 1 1 3
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3 1 1 1 1 1 1 1 1
1 1 1 1 1 3 3 3 3
3 3 3 1 1 1 1 3 3
3 3 1 1 3 3 1 1 3
3 1 1 1 1 1 1 1 1
1 3 3 3 3 1 1 1 1
1 3 3 1 1 3 3 1 1
1 3 1 3 1 3 1 3 1
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BCD TO E4CESS ; LOGIC DIAGRAM:
TRUT. TABLE:
IN UTS6BCD CODE7 A 3 3 3 3 3 B 3 3 3 3 1 C 3 3 1 1 3 D 3 1 3 1 3 B 3 3 3 3 3 OUT UTS6E4CESS ; CODE7 Y 3 1 1 1 1 4 1 3 3 1 1 A 1 3 1 3 1
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3 3 3 1
1 1 1 3
3 1 1 3
1 3 1 3
1 1 1 1
3 3 3 3
3 3 1 1
3 1 3 1
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E4CESS ; TO BCD CODE CON<ERTER:
TRUT. TABLE: Ex*e)) ; +,&(t E, E' E$ E*

! ! ! ! ! 1 1 1 1 1 1 ! 1 1 1 1 ! ! ! ! 1 1 1 ! ! 1 1 ! ! 1 1 ! ! 1 ! 1 ! 1 ! 1 ! 1 ! 1
BCD O(t&(t =, =' =$

! ! ! ! ! ! ! ! 1 1 1 ! ! ! ! 1 1 1 1 ! ! ! ! ! 1 1 ! ! 1 1 ! ! 1
=*
! 1 ! 1 ! 1 ! 1 ! 1 !
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<I<A5<OICE: $# 9ist the 1rocedures to co%vert gray code i%to bi%aryB '# >hy /eighted code is called as reflective codesB ,# >hat is a se0ue%tial codeB )# >hat is error deducti%g codeB -# >hat is A"CII codeB
RESULT: Thus the ) bit bi%ary to gray co%verter, gray to bi%ary co%verter a%d =CD to E<cess , co%verter /ere desig%ed a%d i31le3e%ted#
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ODD/E<EN ARITY GENERATOR TRUT. TABLE: IN UT S".No $# '# ,# )# -# .# (# +# A * * * * $ $ $ $ B * * $ $ * * $ $ C * $ * $ * $ * $ OUT UT 6ODD ARITY7 $ * * $ * $ $ * OUT UT 6E<EN ARITY7 * $ $ * $ * * $
!ro3 the truth table the e<1ressio% for the out1ut 1arity bit is, 6I A, =, CJ G K I*, ,, -, .J Also /ritte% as, 6 G A5=5C5 @ A5=C @ A=5C @ A=C5 G IA CIRCUIT DIAGRAM:
ODD ARITY GENERATOR
CJ 4
E<EN ARITY GENERATOR
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ARITY GENERATOR AND C.EC:ER
To desig% a%d verify the truth table of a three bit OddLEve% 6arity ge%erator a%d chec&er# A ARATUS RE!UIRED: S".No $# '# ,# )# T.EORY: A 1arity bit is used for the 1ur1ose of detecti%g errors duri%g tra%s3issio% of bi%ary i%for3atio%# A 1arity bit is a% e<tra bit i%cluded /ith a bi%ary 3essage to 3a&e the %u3ber of $5s either odd or eve%# The 3essage i%cludi%g the 1arity bit is tra%s3itted a%d the% chec&ed at the receivi%g e%d for errors# A% error is detected if the chec&ed 1arity does %ot corres1o%d /ith the o%e tra%s3itted# The circuit that ge%erates the 1arity bit i% the tra%s3itter is called a 1arity ge%erator a%d the circuit that chec&s the 1arity i% the receiver is called a 1arity chec&er# I% eve% 1arity the added 1arity bit /ill 3a&e the total %u3ber of $5s a% eve% a3ou%t a%d i% odd 1arity the added 1arity bit /ill 3a&e the total %u3ber of $5s a% odd a3ou%t# I% a three bit odd 1arity ge%erator the three bits i% the 3essage together /ith the 1arity bit are tra%s3itted to their desti%atio%, /here they are a11lied to the 1arity chec&er circuit# The 1arity chec&er circuit chec&s for 1ossible errors i% the tra%s3issio%# "i%ce the i%for3atio% /as tra%s3itted /ith odd 1arity the four bits received 3ust have a% odd %u3ber of $5s# A% error occurs duri%g the tra%s3issio% if the four bits received have a% eve% %u3ber of $5s, i%dicati%g that o%e bit has cha%ged duri%g tra%s3issio%# The out1ut of the 1arity chec&er is de%oted by 6EC I1arity error chec&J a%d it /ill be e0ual to $ if a% error occurs, i#e#, if the four bits received has a% eve% %u3ber of $5s# Na#e o$ t%e A&&a'at() Digital IC trai%er &it NOT gate EX-OR gate Co%%ecti%g /ires IC ()*) IC ()+. S&e*+$+*at+o, !(a,t+t$ $ $ As re0uired
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ARITY C.EC:ER: ODD ARITY C.EC:ER:
TRUT. TABLE:
IN UT S.No A 1. 2. ;. 2. 5. =. 1. 8. F. 13. 11. 12. 1;. 12. 15. 1=. 3 3 3 3 3 3 3 3 1 1 1 1 1 1 1 1 6 $o(' C+t #e))a/e Re*e+De> 7 B 3 3 3 3 1 1 1 1 3 3 3 3 1 1 1 1 C 3 3 1 1 3 3 1 1 3 3 1 1 3 3 1 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 OUT UT 6 a'+t- e''o' *%e*E7 4 1 3 3 1 3 1 1 3 3 1 1 3 1 3 3 1 6age ))
!ro3 the truth table the e<1ressio% for the out1ut 1arity chec&er bit is, X IA, =, C, 6J G K I*, ,, -, ., C, $*, $', $-J The above e<1ressio% is reduced as, X G IA = C 6J 4
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ROCEDURE:
CA6E IN"TIT7TE O! TEC8NO9O:; 6age ).
$# Co%%ectio%s are give% as 1er the circuit diagra3s# '# !or all the ICs (th 1i% is grou%ded a%d $)th 1i% is give% @- A su11ly# ,# A11ly the i%1uts a%d verify the truth table for the 6arity ge%erator a%d chec&er#
RESULT: The desig% of the three bit odd 6arity ge%erator a%d chec&er circuits /as do%e a%d their truth tables /ere verified# IN DIAGRAM FOR IC 1225:
CA6E IN"TIT7TE O! TEC8NO9O:; 6age )(
BCD TO DECIMAL DECODER:
PIN DIAGRAM FOR IC 74147:
LOGIC DIAGRAM FOR ENCODER:
Ex. No.:5
ENCODER AND DECODER

6age )+
Date: AIM: To desig% a%d i31le3e%t e%coder a%d decoder usi%g logic gates a%d study of IC ())- a%d IC ()$)(# A ARATUS RE!UIRED: S".No $# '# ,# )# -# T.EORY: ENCODER: A% e%coder is a digital circuit that 1erfor3s i%verse o1eratio% of a decoder# A% e%coder has '% i%1ut li%es a%d % out1ut li%es# I% e%coder the out1ut li%es ge%erates the bi%ary code corres1o%di%g to the i%1ut value# I% octal to bi%ary e%coder it has eight i%1uts, o%e for each octal digit a%d three out1ut that ge%erate the corres1o%di%g bi%ary code# I% e%coder it is assu3ed that o%ly o%e i%1ut has a value of o%e at a%y give% ti3e other/ise the circuit is 3ea%i%gless# It has a% a3biguity that /he% all i%1uts are 2ero the out1uts are 2ero# The 2ero out1uts ca% also be ge%erated /he% D* G $# DECODER: A decoder is a 3ulti1le i%1ut 3ulti1le out1ut logic circuits /hich co%verts coded i%1ut i%to coded out1ut /here i%1ut a%d out1ut codes are differe%t# The i%1ut code ge%erally has fe/er bits tha% the out1ut code# Each i%1ut code /ord 1roduces a differe%t out1ut code /ord i#e there is o%e to o%e 3a11i%g ca% be e<1ressed i% truth table# I% the bloc& diagra3 of decoder circuit the e%coded i%for3atio% is 1rese%t as % i%1ut 1roduci%g '% 1ossible out1uts# '% out1ut values are fro3 * through out '% H $# TRUTH TABLE: IN UT
Na#e o$ t%e A&&a'at() Digital IC trai%er &it & I01 "2"# G2'3 4* G2'3 "4' G2'3 Co%%ecti%g /ires
S&e*+$+*at+o,
!(a,t+t$
I% /)1! I% /)&2 I% /)!)
' , $ As re0uired
OUT UT
6age )C
YI 1 3 3 3 3 3 3
Y2 3 1 3 3 3 3 3
Y; 3 3 1 3 3 3 3
Y2 3 3 3 1 3 3 3
Y5 3 3 3 3 1 3 3
Y= 3 3 3 3 3 1 3
Y1 3 3 3 3 3 3 1
A 3 3 3 1 1 1 1
B 3 1 1 3 3 1 1
C 1 3 1 3 1 3 1
LOGIC DIAGRAM FOR DECODER:
TRUTH TABLE: E 1 3 3 3 3 IN UT A 3 3 3 1 1 B 3 3 1 3 1 D3 1 3 1 1 1 OUT UT D1 D2 1 1 1 1 3 1 1 3 1 1 D; 1 1 1 1 3
ROCEDURE:
CA6E IN"TIT7TE O! TEC8NO9O:; 6age -*
IiJ IiiJ IiiiJ <I<A5<OICE:
Co%%ectio%s are give% as 1er circuit diagra3# 9ogical i%1uts are give% as 1er circuit diagra3# Observe the out1ut a%d verify the truth table#
$# 8o/ the out1ut li%e /ill be activated i% decoder circuitB '# >hat are the %ecessary ste1s for i31le3e%ti%g higher order decodersB ,# >hat is the use of code co%vertersB )# 8o/ to co%vert =CD to Deci3al decoderB -# >hat is seve% seg3e%t dis1laysB .# >hat is the other %a3e of e%coderB (# >hat is e%codi%gB +# >hat are the a11licatio%s of e%coderB C# >hat is =CD e%coderB
RESULT: Thus the e%coder a%d decoder circuits /ere desig%ed a%d i31le3e%ted#
6age -$
CIRCUIT DIAGRAM: A)-,*%'o,o() R+&&"e *o(,te'
TRUT. TABLE: A * * * * * * * * $ $ $ $ $ $ $ $ B * * * * $ $ $ $ * * * * $ $ $ $ C * * $ $ * * $ $ * * $ $ * * $ $ D * $ * $ * $ * $ * $ * $ * $ * $
6age -'
Ex. No.:= Date: AIM:
COUNTER
To co%struct a )-bit asy%chro%ous a%d sy%chro%ous cou%ters# A ARATUS RE!UIRED: S".No $# '# Na#e o$ t%e A&&a'at() Digital IC trai%er &it Co%%ecti%g /ires S&e*+$+*at+o, !(a,t+t$ As re0uired
T.EORY: Asy%chro%ous cou%ter are those i% /hich cloc& 1ulse is give% to the first fli1-flo1 a%d the fli1flo1 out1ut tra%sitio% serves as a source for triggeri%g other fli1-flo1s# The fli1-flo1s cha%ges o%e at a ti3e i% ra1id successio%, a%d the sig%al 1ro1agates through the cou%ter i% a ri11le fashio%# Asy%chro%ous decade cou%ter is also called as ri11le cou%ter# I% a ri11le cou%ter the fli1 flo1 out1ut tra%sitio% serves as a source for triggeri%g other fli1 flo1s# I% other /ords the cloc& 1ulse i%1uts of all the fli1 flo1s are triggered %ot by the i%co3i%g 1ulses but rather by the tra%sitio% that occurs i% other fli1 flo1s# The ter3 asy%chro%ous refers to the eve%ts that do %ot occur at the sa3e ti3e# >ith res1ect to the cou%ter o1eratio%, asy%chro%ous 3ea%s that the fli1 flo1 /ithi% the cou%ter are %ot 3ade to cha%ge states at e<actly the sa3e ti3e, they do %ot because the cloc& 1ulses are %ot co%%ected directly to the cloc& i%1ut of each fli1 flo1 i% the cou%ter# "y%chro%ous cou%ters are those i% /hich si3ulta%eous cloc& 1ulses are give% to all the fli1-flo1s#
6age -,
S-,*%'o,o() R+&&"e *o(,te':
TRUT. TABLE: A * * * * * * * * $ $ $ $ $ $ $ $ B * * * * $ $ $ $ * * * * $ $ $ $ C * * $ $ * * $ $ * * $ $ * * $ $ D * $ * $ * $ * $ * $ * $ * $ * $
6age -)
ROCEDURE: $# Co%%ect the circuit as 1er the circuit diagra3# '# Note the out1ut a%d verify the cou%ter o1eratio%# <I<A5<OICE:
$# 8o/ 3a%y fli1-flo1s are re0uired to co%struct a decade cou%terB '# >hat is DOD cou%terB ,# 8o/ 3a%y differe%t states does a ,-bit asy%chro%ous cou%ter haveB )# "tate so3e a11licatio%s of cou%ters# -# >hat are Cou%ters a%d /hat are its ty1esB .# >hat are Ri11le cou%tersB (# >hat are sy%chro%ous cou%tersB +# "tate the adva%tage of sy%chro%ous cou%ter over asy%chro%ous cou%tersB
RESULT: Thus Asy%chro%ous a%d sy%chro%ous cou%ters /ere desig%ed a%d truth table verified#
6age --
SISO CIRCUIT DIAGRAM:
TRUT. TABLE: SISO Data i%1ut G $$** C"o*E * ) + $' $. Se'+a" I,&(t * $ $ * * I O CIRCIT DIAGRAM: Se'+a" O(t&(t * $ $ * *
6age -.
S.IFT REGISTERS
To i31le3e%t the follo/i%g shift register usi%g fli1 flo1 I# II# III# IA# A "I6O "I"O 6I"O 6I6O
ARATUS RE!UIRED: S".No $# '# ,# Na#e o$ t%e A&&a'at() Digital IC trai%er &it IC Co%%ecti%g /ires ()() S&e*+$+*at+o, !(a,t+t$ $ As re0uired
T.EORY: A register is used to 3ove digital data# A shift register is a 3e3ory i% /hich i%for3atio% is shifted fro3 o%e 1ositio% i% to a%other 1ositio% at a li%e /he% o%e cloc& 1ulse is a11lied# The data ca% be shifted either left or right directio% to/ards right or to/ards left# A shift register ca% be used i% four /ays de1e%di%g u1o% the i%1ut i% /hich the data are e%tered i% to a%d ta&es out of it# The four co%figuratio% are give% as "erial i%1ut H "erial out1ut 6arallel i%1ut H "erial out1ut "erial i%1ut H 6arallel out1ut 6arallel i%1ut H 6arallel out1ut fli1 flo1 are used to co%struct shift register have D fli1 flo1 is used for co%structi%g
R" or J
shift register#
TRUT. TABLE:
CA6E IN"TIT7TE O! TEC8NO9O:; 6age -(
C"o*E A 3 1 3 1
a'a""e" I,&(t B 3 1 C 3 3 D 3 1 !A 3 1
a'a""e" O(t&(t !B 3 1 !C 3 3 !D 3 1
SI O CIRCUIT DIAGRAM:
TRUT. TABLE: Le$t S%+$t No. o$ *"E &(")e * $ ' , ) . ( +
Se'+a" +,&(t D+, * $ $ * $ * * * *
!; * * * * $ $ * $ *
a'a""e" O(t&(t !2 !1 * * * * * $ $ $ $ * * $ $ * * * * *
!3 * $ $ * $ * * * *
6age -+
R+/%t S%+$t: No. o$ *"E Se'+a" +,&(t D+, a'a""e" O(t&(t
6age -C
&(")e * $ ' , ) . ( + * $ $ * $ * * * *
!; * $ * $ $ * * * *
!2 * * $ * $ $ * * *
!1 * * * $ * $ $ * *
!3 * * * * $ * $ $ *
ISO CIRCUIT DIAGRAM:
ROCEDURE: $# :ive the co%%ectio%s as 1er the circuit '# "et or Reset at the 1i% ' /hich it5s the D"= of serial data# ,# A11ly a si%gle cloc& "et or Reset seco%d digital i%1ut at 1i% '# )# Re1eat ste1 ' u%til all )-bit data are ta&e% a/ay# <I<A5<OICE:
CA6E IN"TIT7TE O! TEC8NO9O:; 6age .*
$# >hat is registerB '# >hat are the 3odes of shift registerB ,# 8o/ ri%g cou%ter is i31le3e%ted usi%g shift registersB )# Co31are 1arallel a%d serial sub registersB -# Defi%e se0ue%ce ge%eratorB .# >hat are the ty1es of shift registerB (# Defi%e shift registers#
RESULT: Thus the "I"O, "I6O, 6I"O, 6I6O shift registers /ere desig%ed a%d i31le3e%ted# 2 4 1 MULTI LE4ER LOGIC SYMBOL:
6age .$
TRUTH TABLE: S".No $# '# ,# )# SELECTION IN UT S1 * * $ $ S2 * $ * $ OUT UT Y I* I$ I' I,
PIN DIAGRAM OF IC 7411:
Ex. No.:8
MULTI LE4ER G DEMULTI LE4ER

6age .'
Date: AIM: To desig% a%d verify the truth table of a )X$ Dulti1le<er F $X) De3ulti1le<er# A ARATUS RE!UIRED: S".No $# '# ,# )# -# T.EORY: Dulti1le<er is a digital s/itch /hich allo/s digital i%for3atio% fro3 several sources to be routed o%to a si%gle out1ut li%e# The basic 3ulti1le<er has several data i%1ut li%es a%d a si%gle out1ut li%e# The selectio% of a 1articular i%1ut li%e is co%trolled by a set of selectio% li%es# Nor3ally, there are '% i%1ut li%es a%d % selector li%es /hose bit co3bi%atio%s deter3i%e /hich i%1ut is selected# Therefore, 3ulti1le<er is 43a%y i%to o%e5 a%d it 1rovides the digital e0uivale%t of a% a%alog selector s/itch# A De3ulti1le<er is a circuit that receives i%for3atio% o% a si%gle li%e a%d tra%s3its this i%for3atio% o% o%e of '% 1ossible out1ut li%es# The selectio% of s1ecific out1ut li%e is co%trolled by the values of % selectio% li%es# Na#e o$ t%e A&&a'at() Digital IC trai%er &it 4* gate "4' gate 2"# gate 5 three input 6 Co%%ecti%g /ires I% /)&2 I% /)!) I% /)11 As re0uired S&e*+$+*at+o, !(a,t+t$
CIRCUIT DIAGRAM:
6age .,
DEMULTI LE4ER LOGIC SYMBOL:
6age .)
6age .-
TRUT. TABLE: S".No $# '# ,# )# -# .# (# +# CIRCUIT DIAGRAM: IN UT S1 S2 D+, * * * * * $ * $ * * $ $ $ * * $ * $ $ $ * $ $ $ Y3 * $ * * * * * * OUT UT Y1 Y2 * * * * * * $ * * * * $ * * * * Y; * * * * * * * $
6age ..
ROCEDURE: $# Co%%ectio%s are give% as 1er the circuit diagra3s# '# !or all the ICs (th 1i% is grou%ded a%d $)th 1i% is give% @- A su11ly# ,# A11ly the i%1uts a%d verify the truth table for the 3ulti1le<er F de3ulti1le<er# <I<A5<OICE: $# >hat is a 3ulti1le<erB '# >hat is de3ulti1le<erB ,# "tate so3e a11licatio%s of 3ulti1le<er a%d de3u<# )# Dulti1le<er is also called data selector# -# De3ulti1le<er is also called data distributor# .# >hat is the differe%ce bet/ee% de3ulti1le<er a%d decoderB (# >hat is the use of select li%esB +# 8o/ to e%able the 3ulti1le<erB C# =uild a )E$ 3u< usi%g o%ly 'E$ 3u<B $*# 8o/ to i31le3e%t a Daster "lave fli1 flo1 usi%g a ' to $ 3u<B
RESULTE The desig% of the )<$ Dulti1le<er a%d $<) De3ulti1le<er circuits /as do%e a%d their truth tables /ere verified# IN DIAGRAM:
CA6E IN"TIT7TE O! TEC8NO9O:; 6age .(
CIRCUIT DIAGRAM OF ASTABLE MULTI<IBRATOR:
6age .+
Ex. No.:F Date: AIM:
ASTABLE MULTIVIBRATOR
To study the a11licatio% of IC--- as a% astable 3ultivibrator# A ARATUS RE!UIRED: S".No $# '# ,# )# -# .# (# +# T.EORY: A% astable 3ultivibrator, ofte% called a free-ru%%i%g 3ultivibrator, is a recta%gular-/ave ge%erati%g circuit# This circuit do %ot re0uire a% e<ter%al trigger to cha%ge the state of the out1ut# The O6-AD6 has threshold a%d co%trol i%1uts# >he%ever the threshold voltage e<ceeds the co%trol voltage, the high out1ut fro3 the O6 HAD6 /ill set the fli1-flo1# The collector of discharge tra%sistor goes to 1i% (# >he% this 1i% is co%%ected to a% e<ter%al tri33i%g ca1acitor, a high ? out1ut fro3 the fli1 flo1 /ill saturate the tra%sistor a%d discharge the ca1acitor# >he% ? is lo/ the tra%sistor o1e%s a%d the ca1acitor charges# The co31le3e%tary sig%al out of the fli1-flo1 goes to 1i% , a%d out1ut# >he% e<ter%al reset 1i% is grou%ded it i%hibits the device# The o% H off feature is useful i% 3a%y a11licatio%# The lo/er O6- AD6 i%verti%g ter3i%al i%1ut is called the trigger because of the voltage divider# The %o%-i%verti%g i%1ut has a voltage of @AccL,, the O6-A31 out1ut goes high a%d resets the fli1 flo1# The ti3e duri%g /hich the out1ut is either high or lo/ is deter3i%ed by t/o resistors a%d a ca1acitor, /hich are co%%ected e<ter%ally to the --- ti3er# The ti3e duri%g /hich the ca1acitor charges fro3 $L, Acc to 'L, Acc is e0ual to the ti3e the out1ut is high a%d is give% by, t* 0 3.=F 6R1 8 R27 C
CA6E IN"TIT7TE O! TEC8NO9O:; 6age .C
Na#e o$ t%e A&&a'at() !u%ctio% :e%erator CRO Dual R6" Ti3er IC =read =oard Resistors Ca1acitors Co%%ecti%g /ires
S&e*+$+*at+o, , D82 ,* D82 * H ,* A IC ---
!(a,t+t$ $ $ $
As re0uired
DESIGN: :ive% fG ) 82, Therefore, Total ti3e 1eriod, T G $Lf G MMMMMMMMMMMM >e &%o/, duty cycle G tc L T Therefore, tc G -----------------------a%d td G MMMMMMMMMMMM >e also &%o/ for a% astable 3ultivibrator td G *#.C IR'J C Therefore, R' G MMMMMMMMMMMMM tc G *#.C IR$ @ R'J C Therefore, R$ G MMMMMMMMMMMMM OBSER<ATIONS: A#&"+t(>e S.No AaDe$o'#) 6 No. o$ >+D x <o"t) &e' >+D 7 T+#e &e'+o> 6 No. o$ >+D x T+#e &e' >+D 7 t* t>
1.
O(t&(t <o"ta/e ? <o
2.
Ca&a*+to' Do"ta/e ? <*
6age (*
"i3ilarly the ti3e duri%g /hich the ca1acitor discharges fro3 'L, A cc to $L, Acc is e0ual to the ti3e the out1ut is lo/ a%d is give% by, t> 0 3.=F 6R27 C Thus the total ti3e 1eriod of the out1ut /avefor3 is, T 0 t* 8 t> 0 3.=F 6R1 8 2 R27 C The ter3 duty cycle is ofte% used i% co%Nu%ctio% /ith the astable 3ultivibrator# The duty cycle is the ratio of the ti3e tc duri%g /hich the out1ut is high to the total ti3e 1eriod T# It is ge%erally e<1ressed i% 1erce%tage# I% e0uatio% for3, H >(t- *-*"e 0 I6R1 8 R27 / 6R1 8 2 R27J x 133 ROCEDURE: $# Co%%ectio%s are give% as 1er the circuit diagra3# '# @ -A su11ly is give% to the @ Acc ter3i%al of the ti3er IC# ,# At 1i% , the out1ut /avefor3 is observed /ith the hel1 of a CRO )# At 1i% . the ca1acitor voltage is obtai%ed i% the CRO a%d the A * a%d Ac voltage /avefor3s are 1lotted i% a gra1h sheet#
6age ($
MODEL GRA .:
<I<A5<OICE:
CA6E IN"TIT7TE O! TEC8NO9O:; 6age ('
$# >hat is 3ultivibratorB '# >hat are the various 3odes of o1eratio% of 3ultivibratorB E<1lai% ,# 9ist the basic bloc&s of IC --- ti3erB )# >hat is o%e-shot 3ultivibratorB -# >hat is 0uasi stable stateB .# :ive the a11licatio%s of ----ti3er Astable 3ultivibrator# (# >hat is the adva%tage of --- IC over o1 a31B +# 9ist the a11licatio%s of 3o%ostable 3ode of --- ti3er# C# Defi%e Offset voltage# $*# Defi%e duty cycle# $$# De%tio% the a11licatio%s of IC---# $'# :ive the 3ethods for obtai%i%g sy33etrical s0uare /ave# $,# >hat is the other %a3e for 3o%ostable 3ultivibratorB $)# E<1lai% the o1eratio% of IC--- i% astable 3ode## $-# >hy %egative 1ulse is used as triggerB
RESULT: The desig% of the Astable 3ultivibrator circuit /as do%e a%d the out1ut voltage a%d ca1acitor voltage /avefor3s /ere obtai%ed#
IN DIAGRAM:
CA6E IN"TIT7TE O! TEC8NO9O:; 6age (,
CIRCUIT DIAGRAM OF MONOSTABLE MULTI<IBRATOR:
DESIGN: O To desig% a 3o%ostable 3ultivibrator /ith t1 G *#.$. 3s , assu3e C G *#*$ P! Q :ive% t1 G *#.$. 3s G $#$ R$ C Therefore, R$ G MMMMMMMMMMMMM
Ex. No.:13
MONOSTABLE MULTIVIBRATOR
6age ()
Date: AIM: To desig% the 3o%ostable 3ultivibrator usi%g the IC---# A ARATUS RE!UIRED: S".No $# '# ,# )# -# .# (# +# T.EORY: A 3o%ostable 3ultivibrator ofte% called a o%e-shot 3ultivibrator is a 1ulse ge%erati%g circuit i% /hich the duratio% of the 1ulse is deter3i%ed by the RC %et/or& co%%ected e<ter%ally to the --- ti3er# I% a stable or sta%d-by state the out1ut of the circuit is a11ro<i3ately 2ero or at logic lo/ level# >he% a% e<ter%al trigger 1ulse is a11lied, the out1ut is forced to go high Ia11ro<# AccJ# The ti3e duri%g /hich the out1ut re3ai%s high is give% by, t& 0 1.1 R1 C At the e%d of the ti3i%g i%terval, the out1ut auto3atically reverts bac& to its logic lo/ state# The out1ut stays lo/ u%til a trigger 1ulse is a11lied agai%# The% the cycle re1eats# Thus the 3o%ostable state has o%ly o%e stable state he%ce the %a3e 3o%ostable# Na#e o$ t%e A&&a'at() !u%ctio% :e%erator CRO Dual R6" Ti3er IC =read =oard Resistors Ca1acitors Co%%ecti%g /ires As re0uired S&e*+$+*at+o, , D82 ,* D82 * H ,* A IC --!(a,t+t$ $ $ $ $
OBSER<ATIONS:
6age (-
S.No
A#&"+t(>e 6 No. o$ >+D x <o"t) &e' >+D 7
T+#e &e'+o> 6 No. o$ >+D x T+#e &e' >+D 7 to, to$$
1. 2. ;.
T'+//e' +,&(t O(t&(t <o"ta/e ? <o Ca&a*+to' Do"ta/e ? <*
MODEL GRA .:
ROCEDURE:
CA6E IN"TIT7TE O! TEC8NO9O:; 6age (.
$# Co%%ectio%s are give% as 1er the circuit diagra3# '# @ -A su11ly is give% to the @ Acc ter3i%al of the ti3er IC# ,# A %egative trigger 1ulse of -A, ' 82 is a11lied to 1i% ' of the --- IC )# At 1i% , the out1ut /avefor3 is observed /ith the hel1 of a CRO -# At 1i% . the ca1acitor voltage is obtai%ed i% the CRO a%d the A * a%d Ac voltage /avefor3s are 1lotted i% a gra1h sheet# <I<A5<OICE: $# E<1lai% the o1eratio% of IC--- i% 3o%ostable 3ode# '# >hat is the chargi%g ti3e for ca1acitor i% 3o%ostable 3odeB ,# >hat are the 3odes of o1eratio% of --- ti3ersB )# :ive the co31ariso% bet/ee% co3bi%atio%al circuits a%d se0ue%tial circuits# -# >hat do you 3ea% by 1rese%t stateB .# :ive the a11licatio%s of --- ti3ers IC#
RESULTE The desig% of the Do%ostable 3ultivibrator circuit /as do%e a%d the i%1ut a%d out1ut /avefor3s /ere obtai%ed# IN DIAGRAM:
CA6E IN"TIT7TE O! TEC8NO9O:; 6age ((
CIRCUIT DIAGRAM: To 3easure i%1ut offset voltage
To 3easure i%1ut bias curre%t
6age (+
C.ARACTERISTICS OF O 5AM
To 3easure the follo/i%g 1ara3eters of o1-a31 $# I%1ut bias curre%t '# I%1ut offset curre%t ,# I%1ut offset voltage )# "le/ rate A ARATUS RE!UIRED: S".No $# '# ,# )# -# .# (# +# T.EORY: I,&(t C+a) *(''e,tE The i%verti%g a%d %o%i%verti%g ter3i%als of a% o1-a31 are actually t/o base ter3i%als of tra%sistors of a differe%tial a31lifier# I% a% ideal o1-a31 it is su11orted that %o curre%t flo/s through these ter3i%als# 8o/ever, 1ractically a s3all a3ou%t of curre%t flo/s through these ter3i%als /hich is o% the order of %A Ity1ical a%d 3a<i3u3 values are +* a%d $-**%AJ i% bi1olar o1-a31s a%d 1A for !ET o1-a31s# I%1ut bias curre%t is defi%ed as the average of the curre%ts e%teri%g i%to the i%verti%g a%d %o%i%verti%g ter3i%als of a% o1-a31# To co31e%sate for bias curre%ts a co31e%sati%g resistor Rco31 is used# Aalue of Rco31 is 1arallel co3bi%atio% of the resistors co%%ected to the i%verti%g ter3i%al# I%1ut bias curre%t I=GII=$@I='JL', /here I=$ a%d I=' are the base bias curre%ts of the o1-a31# I,&(t o$$)et *(''e,t: The bias curre%ts I=$ a%d I=' /ill %ot be e0ual i% a% o1-a31# I%1ut offset curre%t is defi%ed as the algebraic differe%ce bet/ee% the curre%ts i%to the i%verti%g a%d %o%Na#e o$ t%e A&&a'at() !u%ctio% :e%erator CRO Dual R6" O6-AD6 =read =oard Resistors Ca1acitors Co%%ecti%g /ires S&e*+$+*at+o, , D82 ,* D82 * H ,* A IC ()$
)#( , $** , $D *#*$P!
!(a,t+t$ $ $ $ $ $ $ As re0uired
6age (C
i%verti%g ter3i%als# IO"GI=$-I=' ,Ty1ical a%d 3a<i3u3 values of i%1ut offset curre%t are '*%A a%d '**%A# To 3easure i%1ut offset curre%t
To 3easure sle/ rate
TY ICAL <ALUES OF ELECTRICAL C.ARACTERISTICS OF 121: I%1ut bias curre%t G +*--**%A I%1ut offset curre%t G '*-'**%A
CA6E IN"TIT7TE O! TEC8NO9O:; 6age +*
I%1ut offset voltage G $--3A "le/ rate G R*#- ALSs I,&(t o$$)et Do"ta/e: Eve% if the i%1ut voltage is 2ero, out1ut voltage 3ay %ot be 2ero# This is because of the circuit i3bala%ces i%side the o1-a31# I% order to co31e%sate this, a s3all voltage should be a11lied bet/ee% the i%1ut ter3i%als# I%1ut offset voltage is defi%ed as the voltage that 3ust be a11lied bet/ee% the i%1ut ter3i%als of a% o1-a31 to %ullify the out1ut voltage# Ty1ical a%d 3a<i3u3 values of i%1ut offset voltage are '3A a%d .3A# S"e@ 'ate: "le/ rate is the rate of rise of out1ut voltage# It is the 3easure of fast%ess of o1-a31# It is e<1ressed i% ALPsec# If the slo1e re0uire3e%ts of the out1ut voltage of the o1-a31 are greater tha% the sle/ rate, distortio% occurs# "le/ rate is 3easured by a11lyi%g a ste1 i%1ut voltage# ROCEDURE: a7 I,&(t B+a) C(''e,t $# Co%%ect the circuit as sho/% i% !ig#$#$# '# Deasure the out1ut voltage fro3 /hich the i%verti%g i%1ut bias curre%t ca% be calculated as I=- G AoLRf# ,# Co%%ect the circuit as sho/% i% !ig#$#'# )# Deasure the out1ut voltage fro3 /hich the %o%-i%verti%g i%1ut bias curre%t ca% be calculated as I=@ G AoLRf# -# Average of 3ag%itude of both I=- a%d I=@ gives the i%1ut bias curre%t# C7 I,&(t O$$)et C(''e,t $# Co%%ect the circuit as sho/% i% !ig#$#,# '# Deasure the out1ut voltage usi%g 3ulti3eter# ,# Calculate the offset curre%t as Ios G AoLRf# *7 I,&(t O$$)et <o"ta/e $# Co%%ect the circuit as sho/% i% !ig#$#)# '# Deasure the out1ut voltage usi%g 3ulti3eter ,# Calculate offset voltage as Aos G Ao L I$@ Rf L R$J# >7 S"e@ Rate $# Co%%ect the circuit as sho/% i% !ig#$#-# '# :ive s0uare /ave i%1ut fro3 the sig%al ge%erator so that the out1ut is a s0uare /ave at $&82#
CA6E IN"TIT7TE O! TEC8NO9O:; 6age +$
,# I%crease the fre0ue%cy slo/ly u%til the out1ut is Nust barely a tria%gular /ave# )# Calculate sle/ rate as "R G I AL tJ#
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<I<A5<OICE: $# >hat is i%1ut bias curre%tB '# >hy do /e use Rco31 resistorB ,# >hat is ther3al driftB )# >hy is IC()$ o1-a31 %ot used for high fre0ue%cy a11licatio%sB -# "tate the ideal characteristics of O1-a31# .# >hat is u%ity gai% circuitB
RESULT: The i%1ut bias curre%t, i%1ut offset curre%t, i%1ut offset voltage a%d sle/ rate of the o1-a31 /ere deter3i%ed# I%1ut offset voltage G TT##3A I%1ut bias curre%t G TT##A
CA6E IN"TIT7TE O! TEC8NO9O:; 6age +,
I%1ut offset curre%t G ###T###A "le/ rate G TT##ALPs# IN DIAGRAM:
IN<ERTING AM LIFIER: CIRCUIT DIAGRAM OF IN<ERTING AM LIFIER:
DESIGN: >e &%o/ for a% i%verti%g A31lifier AC9 G R! L R$ Assu3e R$ Ia11ro<# $* UJ a%d fi%d Rf 8e%ce AoItheoreticalJ G - AC9 Ai
6age +)
IN<ERTING AND NON IN<ERTING O 5AM
To desig% a% I%verti%g a%d No% I%verti%g A31lifier for the give% s1ecificatio%s usi%g O1-A31 IC ()$#
ARATUS RE!UIRED: S".No $# '# ,# )# -# .# (# Na#e o$ t%e A&&a'at() !u%ctio% :e%erator CRO Dual R6" O6-AD6 =read =oard Resistors Co%%ecti%g /ires S&e*+$+*at+o, , D82 ,* D82 * H ,* A IC ()$ !(a,t+t$ $ $ $ $ $ As re0uired
T.EORY: IN<ERTING AM LIFIER: The i%1ut sig%al Ai is a11lied to the i%verti%g i%1ut ter3i%al through R$ a%d the %o%-i%verti%g i%1ut ter3i%al of the o1-a31 is grou%ded# The out1ut voltage A o is fed bac& to the i%verti%g i%1ut ter3i%al through the Rf - R$ %et/or&, /here Rf voltage is give% as, Ao G - AC9 Ai 8ere the %egative sig% i%dicates that the out1ut voltage is $+** out of 1hase /ith the i%1ut sig%al# NON5IN<ERTING AM LIFIER: is the feedbac& resistor# The out1ut
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The i%1ut sig%al Ai is a11lied to the %o% - i%verti%g i%1ut ter3i%al of the o1-a31# This circuit a31lifies the sig%al /ithout i%verti%g the i%1ut sig%al# It is also called %egative feedbac& syste3 si%ce the out1ut is feedbac& to the i%verti%g i%1ut ter3i%als#
OBSER<ATIONS: A#&"+t(>e S.No. 6 No. o$ >+D x <o"t) &e' >+D 7 I,&(t O(t&(t Theoretical 6ractical 6 No. o$ >+D x T+#e &e' >+D 7 T+#e &e'+o>
MODEL GRA .:
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The differe%tial voltage Ad at the i%verti%g i%1ut ter3i%al of the o1-a31 is 2ero ideally a%d the out1ut voltage is give% as, Ao G AC9 Ai 8ere the out1ut voltage is i% 1hase /ith the i%1ut sig%al# RECAUTIONS: $# Out1ut voltage /ill be saturated if it e<ceeds V $-A# ROCEDURE: $# Co%%ectio%s are give% as 1er the circuit diagra3# '# @ Acc a%d - Acc su11ly is give% to the 1o/er su11ly ter3i%al of the O1-A31 IC# ,# =y adNusti%g the a31litude a%d fre0ue%cy &%obs of the fu%ctio% ge%erator, a11ro1riate i%1ut voltage is a11lied to the i%verti%g i%1ut a%d No% I%verti%g ter3i%al of the O1A31# )# The out1ut voltage is obtai%ed i% the CRO a%d the i%1ut a%d out1ut voltage /avefor3s are 1lotted i% a gra1h sheet#
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NON5IN<ERTING AM LIFIER: CIRCUIT DIAGRAM OF NON IN<ERITNG AM LIFIER:
DESIGN: >e &%o/ for a No%-i%verti%g A31lifier AC9 G $ @ IR! L R$J Assu3e R$ I a11ro<# $* U J a%d fi%d Rf 8e%ce Ao G AC9 Ai OBSER<ATIONS: A#&"+t(>e S.No. 6 No. o$ >+D x <o"t) &e' >+D 7 I,&(t O(t&(t Theoretical 6 No. o$ >+D x T+#e &e' >+D 7 T+#e &e'+o>
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6ractical -
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MODEL GRA .:
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<I<A5<OICE: $# >hat do you 3ea% by li%ear circuitsB '# Defi%e a% ICB ,# >hat is a% i%verti%g a31lifierB )# >hat is the ty1e of feedbac& e31loyed i% the i%verti%g o1-a31 -# >hat is a voltage follo/erB .# Defi%e a %o%-i%verti%g a31lifierB (# :ive the closed loo1 gai% of a% i%verti%g a31lifierB +# >hat is the gai% of a %o%-i%verti%g a31lifierB
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RESULT: The desig% a%d testi%g of the No%-i%verti%g a31lifier is do%e a%d the i%1ut a%d out1ut /avefor3s /ere dra/%# IN DIAGRAM:
CIRCUIT DIAGRAM: S(##+,/ A#&"+$+e':
S.NO $# '# S(Ct'a*to':
<1 $*
<2 ,#) $*
T.EORETICAL <ALUE <O0<18<2 +#) '*
RACTICAL <ALUE <O +#'$#+
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Ex. No.:1; Date: AIM:
LICATIONS OF O 5AM
To de3o%strate the use of o1-a31 as I$J su33i%g a31lifier I'J subtractor I,J 2ero crossi%g detector a%d I)J voltage co31arator#
ARATUS RE!UIRED: S".No $# '# ,# )# -# .# (# Na#e o$ t%e A&&a'at() !u%ctio% :e%erator CRO Dual R6" O6-AD6 =read =oard Resistors Co%%ecti%g /ires S&e*+$+*at+o, , D82 ,* D82 * H ,* A IC ()$
$ , $*
!(a,t+t$ $ $ $ $ $ As re0uired
T.EORY: S(##+,/ A#&"+$+e': O1-a31 3ay be used to 1erfor3 su33i%g o1eratio% of several i%1ut sig%als i% i%verti%g i% i%verti%g a%d %o%-i%verti%g 3ode# The i%1ut sig%als to be su33ed u1 are
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give% to i%verti%g ter3i%al or %o%-i%verti%g ter3i%al through the i%1ut resista%ce to 1erfor3 i%verti%g a%d %o%-i%verti%g su33i%g o1eratio%s res1ectively# S(Ct'a*to': The basic differe%ce a31lifier ca% be used as a subtractor# The sig%als to be subtracted are co%%ected to o11osite 1olarity i%1uts i#e# i% i%verti%g or %o%-i%verti%g ter3i%als of the o1-a31# <o"ta/e Co#&a'ato': A co31arator is a circuit /hich co31ares a sig%al voltage a11lied at o%e i%1ut of a% o1-a31 /ith out1ut V Asat G IAccJ# If the sig%al is a11lied to the i%verti%g ter3i%al of the o1-a31 it is called i%verti%g co31arator a%d if the sig%al is a11lied to %o%-i%verti%g ter3i%al of the o1-a31 it is called %o%-i%verti%g co31arator# I% a% i%verti%g co31arator if i%1ut sig%al is less tha% refere%ce voltage, out1ut /ill be @Asat# >he% i%1ut sig%al voltage is greater
tha% refere%ce voltage out1ut /ill be HAsat# The vice-versa ta&es 1lace i% %o%-i%verti%g co31arator# TABULATION:
T.EORETICAL <ALUE S.NO $# '# <1 $* $* <2 <O0<15<2 ( $' , -'
RACTICAL <ALUE <O ,#**, -'#*$
<o"ta/e Co#&a'ato':
MODEL GRA .:
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Be'o C'o))+,/ Dete*to': Wero crossi%g co31arator IWCDJ is a% a11licatio% of voltage co31arator# It co%verts a%y ti3e varyi%g sig%al to s0uare of sa3e ti3e 1eriod /ith a31litude V Asat# The refere%ce voltage is set as 2ero volts# >he% the 1olarity of the i%1ut sig%al cha%ges, out1ut s0uare /ave cha%ges 1olarity# I,te/'ato': I%tegrator is used to i%tegrate the iL1 /avefor3# i#eX AO G YAi% dt# 8ere i% the i%verti%g a31lifier co%figuratio%, the feedbac& resistor Rf is re1laced by ca1acitor Cf# I%tegrators are co33o%ly used i% /ave sha1i%g %L/s, sig%al ge%erators etc# !or 1ro1er /ave i%tegratio%, T ZZ RC# :ai% a%d li%earity of the oL1 are t/o adva%tages of o1-a31 i%tegrators# 9i%earity is due to li%ear chargi%g of ca1acitor# Its li3itatio% is for Ai%G* a%d for lo/ fre0ue%cies, XCf G[ or the ca1acitor Cf acts as a% o1e% circuit# Therefore the o1-a31 i%tegrator /or&s as a% o1e% loo1 a31lifier a%d the gai% beco3es i%fi%ity or very high# D+$$e'e,t+ato': 8ere the out1ut /avefor3 is the derivative of the iL1 /avefor3# I% a basic i%verti%g a31lifier, if R$ is re1laced by C$, /e get the differe%tiator# =ut at high fre0ue%cies, the gai% of the circuit IRfLXC$J i%creases /ith i%crease i% fre0ue%cy at the rate of '*d=Ldecade# This 3a&es the circuit u%stable# Also XC$ decreases /he% fre0ue%cy i%creases#
ROCEDURE: a7 I,De't+,/ )(##+,/ a#&"+$+e': $# Co%%ect the circuit as sho/% i% figure
'# Co%%ect batteries for voltage A$, A'#

CA6E IN"TIT7TE O! TEC8NO9O:; 6age C-
,# Deasure a%d %ote the out1ut voltage a%d co31are it /ith theoretical value Ao G -IR f L RiJ
IA$@A'J C7 S(Ct'a*to': )# Co%%ect the circuit as sho/% i% figure -# Deasure a%d %ote the out1ut voltage a%d co31are it /ith theoretical value# *7 <o"ta/e *o#&a'ato': .# Co%%ect the circuit as sho/% i% the figure (# Co%%ect a% alter%ati%g /avefor3 to the %o%-i%verti%g i%1ut of the o1-a31 +# Co%%ect a refere%ce voltage source to i%verti%g i%1ut of the o1-a31 C# 6lot the i%1ut a%d out1ut /avefor3# >7 Be'o *'o))+,/ >ete*to': $*# Co%%ect the circuit as sho/% i% figure
Be'o C'o))+,/ Dete*to':
TABULATION: IN67T AO9TA:EIAJ TIDEIONJ AO9TA:EIAJ O7T67T TIDEIO!!J
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$$# Co%%ect the i%1ut to a sig%al ge%erator ge%erati%g a si% /ave /ith o%e volt 1ea& to 1ea& at $&82# $'# Co%%ect the i%1ut a%d out1ut to dual cha%%el CRO a%d co31are the i%1ut a%d out1ut# $,# 6lot the i%1ut a%d out1ut /avefor3 i% a gra1h#
e7 I,te/'ato' G D+$$e'e,t+ato': $)# $# Co%%ectio%s are 3ade as 1er the diagra3# $-# '# A11ly a% iL1 voltage of $-'A11 /ith $&82 fre0ue%cy a%d chec& the /avefor3 o% the CRO# $.# ,# Deasure the value of AO by varyi%g the fre0ue%cy of the iL1 sig%al# $(# )# Calculate gai% usi%g the for3ulae '* log IAO LAIN J#
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I,te/'ato':
TABULATION:
IN UT <OLTAGE6<7 TIME6ON7
OUT UT <OLTAGE6<7 TIME6OFF7
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6age CC
D+$$e'e,t+ato':
TABULATION: IN67T AO9TA:EIAJ TIDEIONJ AO9TA:EIAJ O7T67T TIDEIO!!J
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RESULT: Thus, the use of o1-a31 as su33i%g a31lifier, subtractor, voltage co31arator, 2ero crossi%g detector, i%tegrator, a%d differe%tiator /as studied#
25BIT BINARY ADDER: LOGIC DIAGRAM:
IN DIAGRAM OF IC 128;:
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DESIGN OF 25BIT ADDER AND SUBTRACTOR
To desig% a%d i31le3e%t a )-bit adder a%d subtractor usi%g IC()+,# A ARATUS RE!UIRED: S.No $# '# ,# )# IC EX-OR AND :ate OR :ate Co#&o,e,t) S&e*+$+*at+o,) IC ()+, IC ()+. IC ()*+ IC (),' !(a,t+t' $ $ $
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-# .#
IC Trai%er &it 6atch cards
$ !e/
T.EORY: A bi%ary adder is a digital circuit that 1roduces the arithe3atic su3 of ' bi%ary %u3bers# It ca% be co%structed /ith full adders co%%ected i% cascade /ith the out1ut carry fro3 each full adder co%%ected to the i%1ut carry of %e<t full adder i% chai%# The auge%ds bits of 4A5 a%d the adde%d bits of 4=5 are desig%ed by subscri1t %u3bers fro3 right to left, /ith subscri1t * de%oti%g the least sig%ifica%t bit# The carriers are co%%ected i% chai% through the full adder# The i%1ut carry to the adder is Co a%d it ri11les through the full adder to the i%1ut carry C)#
)-=IT =INAR; "7=TRACTORE
The circuit for subtracti%g )-bit co%sists of a% adder /ith i%verters , 1laced bet/ee% each data i%1utsI=J a%d the corres1o%di%g i%1ut of full adder# The i%1ut carry C* 3ust be e0ual to $ /he% 1erfor3i%g subtractio%#
LOGIC DIAGRAM OF 25BIT BINARY ADDER/SUBTRACTOR:
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)-=IT =INAR; ADDERL "7=TRACTORE
The additio% a%d subtractio% o1eratio% ca% be co3bi%ed i%to o%e circuit /ith o%e co33o% bi%ary adder# The 3ode i%1ut 3 co%trols the o1eratio%# >he% 3G*, the circuit is adder circuit# >he% 3G$, it beco3es subtractor#
)-=IT =CD ADDERE
Co%sider the arith3etic o1eratio% of t/o deci3al digits i% =CD, together /ith a% i%1ut carry fro3 a 1revious stage# "i%ce each i%1ut digit does %ot e<ceed C, the out1ut su3 ca%%ot be greater tha% $C, the $ i% the su3 bri%g a% i%1ut carry# The out1ut of t/o deci3al digits 3ust be re1rese%ted i% =CD a%d should a11ear i% the for3 listed i% the colu3%s# A =CD adder that adds ' =CD digits a%d 1roduce a su3 digit i% =CD# The t/o deci3al digits together /ith the i%1ut carry are first added i% the to1 )-bit adder to 1roduce the bi%ary su3#
ROCEDURE: $# Co%%ectio%s are 3ade as 1er the circuit diagra3# '# 9ogical i%1uts give% as 1er the truth table# ,# Observe the logical out1uts a%d verity /ith the truth table#
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TRUT. TABLE FOR 2 BIT BINARY ADDERS: B; * * * * * * * * $ $ $ $ $ B2 * * * * $ $ $ $ * * * * $ B1 * * $ $ * * $ $ * * $ $ * B3 * $ * $ * $ * $ * $ * $ * A; * * * * * * * * $ $ $ $ $ A2 * * * * $ $ $ $ * * * * $ A1 * * $ $ * * $ $ * * $ $ * A3 * $ * $ * $ * $ * $ * $ * S; * * * * $ $ $ $ * * * * $ S2 * * $ $ * * $ $ * * $ $ * S1 * $ * $ * $ * $ * $ * $ * S3 * * * * * * * * * * * * * COUT * * * * * * * * $ $ $ $ $

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$ $ $
$ $ $
* $ $
$ * $
$ $ $
$ $ $
* $ $
$ * $
$ $ $
* $ $
$ * $
* * *
$ $ $
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TRUT. TABLE 2 BIT BINARY ADDER/SUBTRACTOR: IN UT DATA A A2 $ $ * * $ $ $ A; * * * * * * * A2 * * $ * $ $ $ A1 * * * $ * * * B2 * $ $ * $ $ $ IN UT DATA B B; * * * $ * $ $ B2 $ * * $ $ $ * B1 * * * $ $ $ $ B $ $ * * * * * SUBTRACTION D2 * * $ $ $ $ $ D; $ * * * $ $ $ D2 $ * $ $ $ $ * D1 * * * * $ $ $
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BCD ADDER LOGIC DIAGRAM:
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TRUT. TABLE FOR BCD ADDER: BCD S(# S2 * * * * * * S; * * * * $ $ S2 * * $ $ * * S1 * $ * $ * $ Ca''C * * * * * *

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* * $ $ $ $ $ $ $ $
$ $ * * * * $ $ $ $
$ $ * * $ $ * * $ $
* $ * $ * $ * $ * $
* * $ $ $ $ $ $ $ $
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RESULT: Thus the )-=it adder a%d subtractor /ere desig%ed a%d i31le3e%ted usi%g IC ()+,#
CIRCUIT S.OAING A
LICATION OF A/D AND D/A CON<ERTER:
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FUNCTIONAL DIAGRAM OF ADC
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STUDY OF ANALOG TO DIGITAL CON<ERTER
Reali2atio% of circuit for digital co%versio%# T.EORY: The o1eratio% of a%y digital co33u%icatio% syste3 is based u1o% a%alog to digital a%d digital to a%alog co%versio% #The figure sho/s the ty1ical a11licatio% /ithi% A-ZD a%d D-ZA co%versio% is used #The a%alog sig%al obtai%ed fro3 the tra%sducer is ba%d li3ited by i%tialsi%g filter #The sig%al is the% sa31led at a fre0ue%cy rate 3ore tha% t/ice the 3a<i3u3 fre0ue%cy of the ba%d li3ited sig%al #The sa31led sig%al has to be held co%sta%t /hile co%versio% is ta&i%g 1lace i% ALD co%verter# This re0uires the ADC out1ut is a se0ue%ce i% bi%ary digit #The 3icro co31uter IorJ digital sig%al 1rocessor 1erfor3s# The %u3erical calculatio%s of the desired co%trols algorith3# The DLA co%vertor is usually o1erated at the sa3e fre0ue%cy as the ADC# The out1ut is 1assed through a s3oothi%g filter to reduce the effect of 0ua%ti2atio% %oise# =oth ADC a%d DAC are also &%o/% as data co%vertors a%d are available i% Ic for3# It 3ay be 3e%tio%ed here that for slo/ly varyi%g sig%al so3eti3es sa31le a%d hold circuit 3ay be avoided /ithout co%siderable error# The ALD co%versio% usually 3a&es use of a DLa co%vertors# "o /e shall first discuss DAC follo/ed by ADC# ALD CONAERTORE The =loc& sche3atic of ADC is sho/% i% figure# It 1rovides the fu%ctio% Nust o11osite to that of a DAC# It acce1ts a%alog i%1ut voltage Ao a%d 1roduces a% out1ut bi%ary /ords d$,d',T##d% of
$ ' n fu%ctio% value D$ so that D = d $ ' + d ' ' + ############## + d n '
>here the d$ is the 3ost sig%ifica%t bit a%d d% is the least sig%ifica%t bit# A% ADC usually has ' additio%al co%trol li%es# The start i%1ut to tell ADC /he% to start the co%versio% a%d the EOC out1ut to a%%ou%ce /he% the co%versio% is co31lete# De1e%di%g u1o% the ty1e of a11licatio%s ADC are desig%ed for 3icro1rocessor i%terfaci%g IorJ to directly drive 9CD IorJ 9ED dis1lays# ADC" co31ares a give% a%alog sig%al /ith the i%ter%ally ge%erated e0uivale%t sig%al# This grou1s i%cludes, !lash Ico31aratorJ ty1e co%vertor Cou%ter ty1e co%vert trac&i%g ty1e co%vertor
CA6E IN"TIT7TE O! TEC8NO9O:; 6age $$-
"uccessive a11ro<i3atio% ty1e co%vertor#
TRAC:ING A/D CON<ERTERE
FUNCTIONAL DIAGRAM OF SUCCESSI<E A
RO4IMATION ADC:
6age $$.
I%tegrati%g ty1e ADC" 1erfor3 co%versio% i% a% i%direct 3a%%er by first cha%gi%g the a%alog i%1ut sig%al to a li%ear fu%ctio% of ti3e or fre0ue%cy a%d the% to a digital code# The t/o 3ost /idly used i%tegrati%g ty1e co%vertors are $# Chargi%g bala%ci%g ADC '# Dual slo1e ADC The 3ost co33o%ly used ADC" are successive a11ro<i3atio% a%d the i%tegratio% ty1e# The successive a11ro<i3atio% a%d the i%tegratio% ADC" are used i% a11licatio% such as data loggers i%stru3e%tatio%s /ith co%versio% s1eed is i31orta%t# The successive a11ro<i3atio% a%d co31arator ty1e are faster but ge%erally less accurate tha% i%tegrati%g ty1e co%vertors# The flash ty1e is e<1e%sive for high degree of accuracy# The i%tegrati%g ty1e co%vertors are used to a11licatio%s such as digital 3eter, 1a%el 3eter a%d 3o%itori%g syste3 /ere the co%versio% accuracy is critical# S(**e))+De A&&'ox+#at+o, *o,De'to': The successive a11ro<i3atio% tech%i0ue used a very efficie%t code searh tech%ology strategy to co31lete i%-bit co%versio% i% Nust %-cloc& 1eriods# A% light but co%vertor /ould re0uire right cloc& 1ulses to obtai% a digital out1ut as sho/% i% figure# The circuit uses a successive a11ro<i3atio% register I"ARJ to fi%d the re0uired value of each bit by trail a%d error# The circuit o1erates as follo/s /ith the arrival of the state co33a%d, the "AR sets the D"=Gd$G$ /ith all other bits to 2ero that the DAC is greater tha% the DAC out1ut Ao the% $******* is less tha% the correct digital re1rese%tatio%# The D"= is left at 4$5 a%d the further IorJ %e<t lo/er sig%ifica%t bit is 3ade 4$5 a%d further tested# 8o/ever if va is less tha% DAc out1ut the $****** is greater tha% the curre%t correct digital re1rese%tatio%# "o reset D"= 4*5 a%d goto the %e<t lo/er sig%ifica%t bit# This 1rocedure is re1eated for all bits, o%e at a% ti3e u%til all bit 1ositio% has the% tested# >he%ever the DAC out1ut crosses Ao the co31arator cha%ges state a%d this ca% be ta&e% as the e%d of co%versio%IEOCJ co33a%d# The follo/i%g table sho/s the ty1ical co%versio% se0ue%ce# The figure sho/s the corres1o%di%g /avefor3s# It ca% be su3 that DLA out1ut voltage beco3es successively closer to the actual a%alog i%1ut voltage# It re0uires eight 1ulses to establish the accurate out1ut regardless of the value of the accurate out1ut regardless of the value of the a%alog i%1ut fro3 load the out1ut registers a%d rei%itiali2es the circuit#
6age $$(
6age $$+
Co''e*t >+/+t 'e&'e)e,tat+o,
S(**e))+De a&&'ox+#at+o, 'e/+)to' o(t&(t <> at >+$$e'e,t )ta/e) +, *o,De')+o, $******* $$****** $$$***** $$*$****
Co#&a'ato' o(t&(t
$Ii%itial oL1J $ * $ * $ * * *
$$*$*$**
$$*$$*** $$*$*$** $$*$*$$* $$*$*$$* $$*$*$*$ $$*$*$*$*
A co31ariso% of the %eed of a% + bit trac&i%g ADC a%d a% + bit successive a11ro<i3atio%# ADC is 3ade i% figure# :ive% the sa3e cloc& fre0ue%cy, /e see that the trac&i%g circuit is faster o%ly for s3all cha%ges i% the out1ut# I% ge%eral the successive a11ro<i3atio% tech%i0ue is 3ore versa late a%d su1erior to all other i%1ut circuits discussed so far, successive a11ro<i3atio% ADC" are available as self co%tai%ed ICs# The AD (-+' a '+ 1i% dual li%e cases 1ac&age is a ' bit ALD co%vertor usi%g successive a11ro<i3atio% tech%i0ue#
RESULT:
CA6E IN"TIT7TE O! TEC8NO9O:; 6age $$C
Thus the reali2atio% of circuit for co%versio% /as studied# BLOC: DIAGRAM OF LL:
IN DIAGRAM:
6age $'*
Ex. No.:1= Date: AIM:
STUDY OF LL
To study 699 IC a%d fre0ue%cy 3ulti1licatio% usi%g NEL"E -.- 699 IC# BASIC RINCI LES: The basic 1ri%ci1les of sche3atic diagra3 of the 699 is sho/% i% fig# This feedbac& syste3 co%sists of $# 6hase detector co31arator '# A lo/ 1ass filter ,# A% error a31lifier )# A voltage co%trol oscillatorO ACDQ A ACD is a free ru%%i%g 3ultivibrator a%d o1erates at a set fre0ue%cy !o# This fre0ue%cy is deter3i%ed by a% i%ter%al ti3i%g ca1acitor a%d e<ter%al series resistors# It ca% also the shifted to either side by a11lyi%g a dc voltage Ac to a% a11ro1riate ter3i%al of the IC# The fre0ue%cy deviatio% is directly 1ro1ortio%al to the co%trol voltage# If a% i%1ut sig%al As of fre0ue%cy is a11lied to 699, the 1hase detector co31ares the 1hase a%d fre0ue%cy of the i%co3i%g sig%al to that of the Out1ut Ao of the ACD#
If the t/o sig%al As of fre0ue%cy a%d 1hase a% error voltage is ge%erated# The 1hase detector is basically a 3ulti1lier a%d 1rocess the su3 O!o@!,Q a%d differe%ce O!s-!oQ co31o%e%ts at its
CA6E IN"TIT7TE O! TEC8NO9O:; 6age $'$
out1ut# The high fre0ue%cy co31o%e%ts O!s@!oQ is re3oved by the lo/ 1ass filter a%d differe%ce fre0ue%cy co31o%e%t is a31lified a%d the a11lied as co%trol voltage A c to Aco# The sig%al Ac shifts the Aco fre0ue%cy i% a directio% to reduce the fre0ue%cy differe%ce bet/ee% !, a%d fo# O%ce this actio% starts /e say that the sig%al is the ca1ture ra%ge# The circuit is said to be loc&ed# O%ce the loc&ed, the OL6 fre0ue%cy to of Aco is ide%tical to !, i%s1ect for a fi%ite 1hase differe%ce !# !ree Ru%%i%gE $# Ca1ture '# 9oc&ed IorJ trac&i%g The gra1h sho/s the ca1ture tra%sie%t as ca1ture starts s3all si%e /ave a11ears# This is due to the differe%ce fre0ue%cy bet/ee% the Aco a%d the IL6 sig%al# Each successive cycle causes the Aco fre0ue%cy beco3es s3aller a%d a large dc co31o%e%t is 1assed by the filter shifti%g the Aco loc&s o% to the sig%al a%d differe%ce fre0ue%cy is dc# The lo/ 1ass fiter co%trols the differe%ce ra%ge# If Aco fre0ue%cy is far a/ay the beat fre0ue%cy /ill be high to 1ass through the filter a%d the 699 /ill %ot res1o%d /e say thet the sig%al is %ot of the ca1ture ba%d# The Aco ca% tra%s, thus trac&i%g ra%ge# NE/SE 5=5 BLOC: DIAGRAM:
FRE!UENCY MULTI LIER USING IC LL:

CA6E IN"TIT7TE O! TEC8NO9O:; 6age $''
9OC IN RAN:EE O%ce the 699 is loc&ed it ca% trac& fre0ue%cy cha%ges i% the i%co3i%g sig%al# The ra%ge of fre0ue%cy /hich the 699 ca% 3ai%tai% loc& /ith the i%co3i%g sig%al is called loc& i% ra%ge or trac&i%g ra%ge# The loc& ra%ge is usually e<1ressed as a 1erce%tage of !o , the Aco !re0ue%cy#
CA6T7RE RAN:EE The ra%ge of fre0ue%cies over the 69l ca% ac0uire loc& /ith a% i%1ut sig%al is called the ca1ture ra%ge# This 1ara3eter is also e<1ressed as 1erce%tage of !o#
6799 IN TIDEE
CA6E IN"TIT7TE O! TEC8NO9O:; 6age $',
The total ti3e ta&e% by the 699 to establish the loc& is called 1ull i% ti3e# This de1e%ds o% the i%itial 1hase a%d fre0ue%cy differe%ce bet/ee% the t/o sig%als as /ell as o% the over all loo1 gai% loo1 filter characteristics#
IC LL 5=5: -.- is available as a $)-1i% di1 1ac&age as $*-1i% 3etal ca% 1ac&age# The 1i% co%figuratio% a%d the bloc& diagra3 are sho/% i% figure# The out1ut fre0ue%cy of the Aco is give% gy the e0uatio% !oG*#'-LRtCt 82, /here Rt a%d Ct are the e<ter%al resistor a%d ca1acitor co%%ected to + 1i% a%d 1i% +# The Aco free ru%%i%g fre0ue%cy is adNusted /ith Rt a%d Ct to be at the ce%tre of the i%1ut fre0ue%cy ra%ge# It 3ay be see% the i%1ut !re0ue%cy ra%ge# That 1hase loc&ed loo1 is i%ter%ally bro&e% bet/ee% the Aco out1ut a%d the 1hase co31arator so as the co31are fo /ith i%1ut sig%al !o A ca1acitor C is co%%ected bet/ee% 1i% ( a%d 1i% $* a%d 3ade a lo/ 1ass filter /ith the i%ter%al resista%ce of ,#.oh3#
LL A
LICATIONS:
The out1ut fro3 a 699 syste3 ca% be obtai%ed either as the voltage sig%al Ace corres1o%di%g to the error voltage i% the feedbac& loo1 IorJ as a fre0ue%cy sig%al to Aco out1ut ter3i%al# The voltage out1ut is used i% fre0ue%cy disse3i%atio% a11licatio% /hereas the fre0ue%cy out1ut is used i% sig%al co%ditio%i%g, fre0ue%cy sy%thesis IorJ cloc& recovery a11licatio%s#
!RE?7ENC; D79TI69ICATION DIAI"ION E The figure sho/s the bloc& diagra3 of a fre0ue%cy 3ulti1lier usi%g 699# A divided by N %et/or& is i%serted bet/ee% the Aco out1ut a%d the 1hase co31arator i%1ut fre0ue%cy !o is give% by !oG%fs#The 3ulti1licatio% factor ca% be obtai%ed by selecti%g a 1ro1er scali%g factor N of the cou%ter fre0ue%cy 3ulti1licatio% ca% also be obtai%ed by usi%g 699 i% its har3o%ic loc&i%g 3ode#If the i%1ut sig%al is such i% har3o%ic the% Aco ca% be directly loc&ed to the Nth har3o%ic of the i%1ut sig%al co%ditio%i%g /ithout a%y fre0ue%cy divider i% bet/ee% affi<ture loc&i%g 3ay %ot ta&e 1lace for high values of % Ty1ically % is &e1t less tha% $*#
6age $')
6age $'-
ROCEDURE: $# '# ,# Da&e the co%%ectio%s as 1er the circuit diagra3# "et the i%1ut sig%al at A11 s0uare /ave at -**82# Aary the Aco fre0ue%cy by adNusti%g the '* oh3s 1ote%tio3eter till the the 699 is
loc&ed# Deasure the out1ut fre0ue%cy# It should be five ti3es the i%1ut fre0ue%cy# )# Re1eat ste1 ',, for i%1ut fre0ue%cy of $ 8W a%d $#- 8W#
6age $'.
RESULT:
CA6E IN"TIT7TE O! TEC8NO9O:; 6age $'(
Thus the 699 IC a%d fre0ue%cy 3ulti1licatio% usi%g NEL"E -.- 699 IC /ere studied#
<OLTAGE CONTROLLED OSCILLATOR: 6IN CON!I:7RATIONE
BLOC: DIAGRAM:
6age $'+
STUDY OF <CO
To study ACO a%d voltage of fre0ue%cy characteristics of NEL"E -.. IC# T.EORY: <OLTAGE CONTROL OSCILLATOR: IC 5==: The co33o% ty1e of ACO available i% IC for3 is NEL"E -..# The 1i% co%figuratio% a%d bias bloc& diagra3 of -.. ACO are sho/% i% the figure referri%g to the figure ti3i%g ca1acitor# Ct is li%early charged or discharged by the co%sta%t curre%t source as i% # The a3ou%t of
CA6E IN"TIT7TE O! TEC8NO9O:; 6age $'C
curre%t AC a11lied at the 3odulati%g i%1ut IorJ by cha%gi%g the ti3i%g resistor Ri , e<ter%al to IC chi1# The voltage at 1i% . is held at the voltage as 1i% -# Thus if the 3odulati%g voltage at 1i% is i%creased, resulti%g i% lo/ voltage, across Rt a%d thereby decreasi%g the chargi%g curre%t# The voltage across the ca1acitor CT is a11lied to the i%verti%g i%1ut ter3i%al of the "ch3itt trigger# A' via after a31lified A$# The out1ut usi%g the "ch3itt trigger is desig%ed to A CC a%d *#-ACC# If Ra a%d Rb i% the 1ositive feedbac& loo1 the voltage s/i%gs fro3 *#-A cc to *#'-Acc# >he% the ca1acitor circuits e<ceeds *#-Acc duri%g chargi%g, the out1ut of "ch3itt trigger goes lo/# The ca1acitor %o/ discharges a%d /he% it is *#'- A cc the out1ut of "ch3itt trigger goes high# "i%ce the source a%d si%& curre%t are e0ual the ca1acitor charges a%d discharges for the sa3e a3ou%t of ti3e# This gives a tria%gular voltage /avefor3 across C T /hich is also available at 1i% )# The s0uare /ave out1ut of the "ch3itt trigger is i%verted by i%verter A, a%d is available at 1i% ,# The out1ut /avefor3 is sho/% i% figure# The out1ut fre0ue%cy is f o = '(VCC VC ) L ( C T RT VCC ) # AO9TA:E TO !RE?7ENC; CONAER"ION !ACTORE A 1ara3eter of i31orta%ce of ACO is voltage to fre0ue%cy co%versio% factor desig%ed as AGUf*$UAC#
A
a%d is
8ere AC is the 3odulatio% voltage re0uired to 1roduce the fre0ue%cy shift f *# !or a ACO if the origi%al fre0ue%cy shift is f* a%d %e/ fre0ue%cy is f$ the% Uf*Gf$-f* UAGf*CTRTAcoL' UACGUf*ACCLsf* OUT UT AA<EFORME
6age $,*
TY ICAL CONNECTION DIAGRAM:
6age $,$
RESULT: Thus the ACO a%d Aoltage of fre0ue%cy characteristics of NEL"E IC -.. /ere studied#
6age $,'

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EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

Ex. No.:1 Date: AIM:

STUDY OF BASIC DIGITAL ICS.

S&e*+$+*at+o, IC ()*+ IC (),' IC ()*) IC ()** IC ()*' IC ()+.

EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

A Y0A.B B IN DIAGRAM OF IC 1238 :

TRUT. TABLE: S".No

EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

CA6E IN"TIT7TE O! TEC8NO9O:;

EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

TRUT. TABLE: S".No

EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

CA6E IN"TIT7TE O! TEC8NO9O:;

EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

NOT GATE LOGIC DIAGRAM: AAA Y0A

CA6E IN"TIT7TE O! TEC8NO9O:;

EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

CA6E IN"TIT7TE O! TEC8NO9O:;

EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

NAND GATE LOGIC DIAGRAM: A Y0A.B B IN DIAGRAM OF IC 1233 :

TRUT. TABLE: S".No

EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

CA6E IN"TIT7TE O! TEC8NO9O:;

EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

NOR GATE LOGIC DIAGRAM:

CA6E IN"TIT7TE O! TEC8NO9O:;

EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

CA6E IN"TIT7TE O! TEC8NO9O:;

EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

E45OR GATE LOGIC DIAGRAM:

EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

CA6E IN"TIT7TE O! TEC8NO9O:;

EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

RS FLI FLO LOGIC SYMBOL:

CA6E IN"TIT7TE O! TEC8NO9O:;

EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

CA6E IN"TIT7TE O! TEC8NO9O:;

EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

D FLI FLO LOGIC SYMBOL:

C.ARACTERISTIC TABLE: CLOC: ULSE 1 2 IN UT D 3 3 RESENT STATE 6!7 3 1 NE4T STATE6!817 3 3

CA6E IN"TIT7TE O! TEC8NO9O:;

EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

CA6E IN"TIT7TE O! TEC8NO9O:;

EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

9: FLI FLO LOGIC SYMBOL: CIRCUIT DIAGRAM:

C.ARACTERISTIC TABLE: CLOC: IN UT ULSE 9 1 3 2 3 ; 3 2 3 5 1 = 1 1 1

RESENT STATE 6!7 3 1 3 1 3 1 3

EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

CA6E IN"TIT7TE O! TEC8NO9O:;

EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

T FLI FLO LOGIC SYMBOL:

C.ARACTERISTIC TABLE: CLOC: IN UT ULSE T 1 2 ; 2 3 3 1 1

RESENT STATE 6!7 3 1 3 1

EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

CA6E IN"TIT7TE O! TEC8NO9O:;

EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

Ca''-? C 0 A . B CIRCUIT DIAGRAM:

-Da1 for "7DE

-Da1 for CARR;E

EE2258/LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

SUM 0 AB 8 AB Ex. No.: 2 Date: AIM:

DESIGN OF ADDER AND SUBTRACTOR

CA6E IN"TIT7TE O! TEC8NO9O:;

S&e+$+at+o, IC ()+ IC (),' IC ()) IC ()** IC ()*' IC ()+.

TRUT. TABLE: Exe)) ; +,&(t E, E' E$ E