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Piezoelectric Micro-power Generation to Charge Supercapacitor with Optimized Duty Cycle

ZHOU ZHAO,* SHIRUI WANG AND CHAO YOU


Department of Electrical and Computer Engineering, North Dakota State University, Fargo, ND, 58102 USA ABSTRACT: Energy harvesting has been proved to be a novel solution to replace the batteries in remote power supply applications. Unfortunately, the limited capacity and low efficiency of output power constraint the practical applications of energy harvesting in daily life. After a systematic review of previous researches about energy harvesting in power management perspective, a circuit design, which focuses on low-frequency mechanical vibration, is introduced. With classical piezoelectric cantilever configuration, the maximum charging current of a supercapacitor can be obtained by optimizing the duty cycle of a buck regulator through software implemented pulse width modulation. The results of experiments prove the capacitive electric model of the piezo, the existence of maximum charging current of the supercapacitor, and the adaptive control of the designed circuits. With the duty cycle optimized to 2.17%, the maximum charging current of 17.36 mA is measured, which is approximately four times fold of previous researches in similar vibration conditions. An active RFID application is proposed to utilize the harvested power of 67.2 mW. Key Words: piezoelectric devices, energy storage, DCDC power convertors, capacitors, pulse width modulation.

INTRODUCTION materials can be fabricated as a generator to transform mechanical energy in ambient vibration into electrical energy, which can be stored and used to power some ultra low-power devices such as radio frequency identification (RFID) tags. Since most of the ultra low-power devices are wireless, it becomes essential to have their own independent power supplies. In tradition, the power supplies come from bulky batteries, which have environment unfriendly chemical ingredients. Most importantly, the batteries have limited life of 2001000 cycles compared to millions or more for most commercially available supercapacitors. With the development of wireless sensor network and microelectromechanical systems technologies, intelligent sensors are developed to be embedded in remote locations such as structural health monitoring sensors embedded in the bridges, medical sensors implanted in the human body, and global positioning system sensors attached to animals to track their behaviors in wildlife. Obtaining the sensors to replace the batteries could be very time-consuming and expensive. In the embedded case, the accessibility is even impossible and destructive. If a strain energy scavenging technology is realized, the life spans of those sensors could be extended

IEZOELECTRIC

significantly or even the batteries themselves could be replaced. There are many researches that successfully realize energy harvesting in the labs, but the total power efficiencies of the designed systems are constrained by the tradeoff among efficiencies of each subsystems. For instance, some researchers pay much attention to maximizing the output power of the piezoelectric source, but the useful power stored in the energy buffer is degraded by the significant power dissipation of the regulator. Based on systematic analysis of piezoelectric energy harvesting in power management perspective, the maximum charging current of a supercapacitor with optimized duty cycle is investigated. In the Background section, the previous researches are categorized along the power flow of energy harvesting. In the Theory section, the electrical model, output power of a piezo, and charging a supercapacitor are introduced. The circuit design and implementation are described in the Implementation section. The experiment setup and results are presented in the final section. BACKGROUND Sodano et al. (2004) presented a comprehensive review of piezoelectric energy harvesting, in which researches were summarized in categories including piezoelectric theoretical fundamentals, mechanical

*Author to whom correspondence should be addressed. E-mail: zhouzhao@usc.edu

JOURNAL

OF INTELLIGENT

MATERIAL SYSTEMS

AND

STRUCTURES, Vol. 21July 2010

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1045-389X/10/11 113110 $10.00/0 DOI: 10.1177/1045389X10376843 The Author(s), 2010. Reprints and permissions: http://www.sagepub.co.uk/journalsPermissions.nav

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Conversion efciency Transfer efciency Buffering efciency

Z. ZHAO ET AL.

Consumption efciency

Figure 1. Power flowchart of energy harvesting system.

vibration, power efficiency, storage circuitry, and wearable applications. Generally, the motivations of power management focus on efficiency improvement by reducing power dissipation of the whole system, which increases system stability, saves cost, and reduces impact on the environment. The methods to improve the efficiency of energy harvesting system can be categorized into four blocks along the energy harvesting power flow as shown in Figure 1. They include optimizations in conversion efficiency of energy source, transfer efficiency from the source to the load, buffering efficiency of the energy storage device, and consumption efficiency of the load. The techniques of designing the structures of piezoelectric material and ultra low-power applications are out of the scope of this article. The article focuses on transfer and buffering efficiency optimizations. Transfer Efficiency Due to the capacitive characteristic of the piezoelectric materials, a power regulator is needed in the subsystem of transfer efficiency. Many control mechanisms of the power regulator have been proposed to improve the transfer efficiency. Kasyap et al. (2002) designed a flyback converter whose input impedance did not depend on the load. With impedance match between the piezo and the converter, peak power efficiency of 20% was achieved with 80% flyback converter efficiency. Ottman et al. (2002) presented an adaptive control scheme using charging current versus duty cycle curve. The maximum charging current of 4.3 mA was available with optimal duty cycle of 3.18% at a rectifier voltage of 20.4 V, which approximated the half of the open circuit voltage of the piezoelectric source. With the highest mechanical excitation level of 95.31 V open circuit voltage, the harvested power increased from 16.43 to 70.42 mW with converter power loss of 18.87 mW. Hofmann et al. (2003) designed a stepdown converter operating in discontinuous conduction mode to reduce the power loss of the digital signal processor (DSP). With switch frequency of 1 kHz, the optimal duty cycle approached constant of 3.16%. The harvested power increased from 9.45 mW by direct charging to 30.66 mW with converter efficiency of 65%. Le et al. (2006) proposed a circuit to solve the problem that conventional diode rectifier did not provide efficient power conversion of piezo. Tan et al. (2008) presented a synchronous charge extraction circuits which increased the output power of piezo from 1.75 to 5.6 mW. Ramadass and Chandrakasan (2009)

demonstrated a bias-flip rectifier circuitry with a shared inductor to improve the power extraction from piezo up to 4.2 times compared with regular full-bridge rectifier. Unfortunately, most of these techniques did not consider the charging characteristics of the buffering subsystem, which is very important in optimizing the usable power for the load. In addition, strong strain with vibration frequency up to kHz is fully investigated. However, the strong vibration is limited in industry applications while most vibrations cannot be even sensed in daily life. Therefore, this article focuses on efficiently harvesting usable energy stored in the buffer from more popular low-frequency microvibrations. Buffering Efficiency Due to the low current output characteristic of the piezo, the harvested energy cannot be directly used by most electronics without accumulating a significant amount of charge in energy storage devices such as capacitors or rechargeable batteries. Umeda et al. (1997) investigated the impact of varying the size of capacitances on the efficiencies of the energy harvesting system. Sodano et al. (2003a) investigated the possible power output from the piezoelectric materials in cantilever configuration. They emphasized using capacitors as a method of energy storage for direct energy access. Sodano et al. (2003b) presented the results of charging various sized batteries using piezoelectric energy harvesting. The numerical equations between energy efficiency and vibration parameters were derived. Because of high power density, supercapacitors have been widely used in energy harvesting applications such as vehicle regenerative braking (Cerovsky and Mindl, 2005). Simjee and Chou (2006, 2008) designed a power regulator using a supercapacitor as an energy storage device, which proved that supercapacitor has better efficiency than battery to store the intermittent energy harvested from the piezo. THEORY This section investigates the theories about the output power of a piezo and supercapacitor charging technique. The piezo in cantilever vibration can be modeled as a sinusoid current source paralleled with parasitic capacitance as shown in Figure 2 (Ottman et al., 2002). The generated AC power needs to be converted to DC power before a load can use it. The output power of piezo is derived in the following section. Based on the equations in the following section, the derivations about maximized supercapacitor charging current are investigated in the section Charging Supercapacitor. Piezo Output Power The ideal current waveforms generated from the piezo ip(!t) and the rectified output current io(!t) are

Piezoelectric Micro-power Generation


io (t) D1 + ip (t) + Vp (t) D3 D2 io (t) + + Vrect Rl Vo

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by Equation (1) in one period:  io !t 0, for 0  !t  k; jip !tj, for k  !t  : 1a 1b

Cp

Crect

Piezelectric model

D4

The DC component of output current flowing through the resistive load hio(!t)i can be evaluated as: hio !ti 1  Z


Figure 2. Piezoelectric capacitive model with a full-wave rectifier and loads.

Ip sin!td !t
k

in which Ip is the amplitude of current ip(!t). Equation (2) can be reduced to:
ip (t) Ip o Vp (t) Vrect o Vrect io (t) io (t) o t IV k I II III 2 t k (k + 1) 2 t

hio !ti

Ip 1 cos k: 

In order to figure out the hio(!t)i, the cos k in Equation (3) can be evaluated by the current and voltage relationship across the Cp, which is: Cp dVp Ip sin !t: dt 4

(k + 1)

(k + 1)

Multiply dt with both sides of equation and integrate over the period from 0 to k: Z !
Vrect Vrect

Figure 3. Voltage and current waveforms of a full-wave rectifier.

Z Cp dVp
0

k

Ip sin !t d!t,

shown in Figure 3. The waveform of voltage across the piezoelectric electrode capacitor Vp(!t) can be divided into four operation periods. In the period of I, the voltage Vp(!t) is equal to the voltage Vrect and the current ip(!t) is positive. Therefore, the diodes D1 and D4 are conducting. When the current ip(!t) becomes negative at the point of , the Cp is discharged. Thus, the voltage Vp(!t) is decreased and all diodes are reversed-biased in the period of II. The insulation between the piezo and load continues until the voltage Vp(!t) is reverse charged to the voltage of Vrect at (k 1). Then, the diodes D2 and D3 are conducting and the voltage Vp(!t) are maintained constant of Vrect in the period of III. When the current ip(!t) becomes positive at 2, the voltage Vp(!t) is charged back to Vrect in period IV. When the magnitude of voltage Vp(!t) is smaller than Vrect, all diodes are reversed-biased and no current flows through the resistive load in periods II and IV. In periods I and III, output current flows through the rectifier capacitor Crect and the resistive load Rl. Assuming Crect  Cp, the majority of the generated current will be delivered to the resistive load instead of maintaining the voltage across the electrode capacitor Cp when the diodes are conducting. The output current io(!t) can be represented

which can be reduced to: cos k 1 2!Cp Vrect : Ip 6

Substitute cos k in Equation (3) with the Equation (6), the hio(!t)i can be represented as: hio !ti 2Ip 2Vrect !Cp :   7

The output power of the piezo can be shown to vary with the value of the Vrect as: P!t 2Vrect Ip Vrect !Cp :  8

Charging Supercapacitor There are three methods to charge a supercapacitor: constant current charging, constant power charging, and AC line charging. The constant current charging is the quickest form with controllable charging current. Since the power generated by the piezo has the characteristic of

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high voltage with low current, a buck regulator is usually an essential topology not only to regulate the output voltage to an applicable range but also strengthen the current driving capability of the piezo. In addition, continuous output current of the buck regulator overwhelms other switching mode regulators in the supercapacitor charging application (Maxwell, 2005). The electric model of a supercapacitor with a buck regulator and a piezoelectric model are shown in Figure 4, in which the equivalent parallel resistance of the supercapacitor is Rc. The regulated charging current ic can be represented in Equation (9) in the continuous conduction mode: ic hio !ti , k 9

which is equivalent to:  2 I2 2Vo !Cp Ip p x :  2Vo !Cp 2Vo !Cp

ic

14

The charging current of supercapacitor ic can be maxIp imized only when x is equal to 2Vo ! Cp , which means the optimized duty cycle can be represented by: 2Vo !Cp kopt , 15 Ip and the maximized charging current is: ic max I2 p : 2Vo !Cp 16

in which hio(!t)i and k are the DC component of piezo output current and duty cycle of the buck regulator, respectively. Since the relationship between input and output voltages of the buck regulator maintains: kVrect Vo : 10

IMPLEMENTATION The architecture of designed piezoelectric energy harvesting system is shown in Figure 5. A buck regulator is designed to regulate the power flow from the piezo to the load. A feedback control system is designed in obtaining the optimized duty cycle according to the charging current of the supercapacitor across a current sensitive resistor to make sure the charging current is maximized. The signal of charging current is amplified, digitized, and sent to a field programmable gate array (FPGA) for optimal duty cycle computations. In the following section, the elements used in the buck regulator are evaluated. The feedback control system is introduced in the later section. DCDC Buck Regulator

Using Equations (7), (9), and (10), the charging current of the supercapacitor can be represented as: ic 2Ip 2Vo !Cp : k k2 11

In addition, the voltage and current relationship across the supercapacitor maintains: dVo ic : dt Cs 12

Since the capacitance of the supercapacitor is so huge, the output voltage across the supercapacitor will be almost constant when the charging current is in limit range (Gualous et al., 2007). Therefore, if the charging current is maximized, the power supplied to the supercapacitor is maximized. Substituting k1 in Equation (11) with x yields: ic 2Ip 2Vo !Cp 2 x x ,   13

The classical circuit diagram of a buck regulator is shown in Figure 6 (Rashid, 2003). The maximum voltage drop between the source and drain of the power switch Q1 appears when Q1 is turned off and the input voltage is maximized. In addition, the peak current
Q1 L

Piezo

+ Crect

Dm Rs

+ Cs

Rl

Piezo electric Crect model

io (t) + Vrect

ic Buck Cs

0.15 + Vo Rc
Feedback control Driver system

Buffer Amplier

Supercapacitor electric model

Terminal

FPGA

ADC

Figure 4. Electric model of a supercapacitor with a piezo and a buck regulator.

Figure 5. Architecture of a piezoelectric energy harvesting system.

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flowing through the Q1 is equal to the maximum current flowing through the inductor L when the Q1 is conducting. According to the peak-to-peak ripple current of the inductor L, the peak current can be evaluated as: I2 Vo Vs Vo I1 , fLVs 17

in which the I1 and I2 are minimum and maximum of the inductor current, respectively, as shown in the Figure 7. In order to minimize the power dissipation of the conducting Dm, a low forward voltage drop zener diode is used. The zener diode has only 5 mA leakage current when reversed-biased at 29.7 V. In addition, it has 115 mA surge current, which is much higher than the calculated peak inductor current of 26.8 mA. The absolute maximum ratings of the Q1 are Vdss 200 V, Id 18 A with turn-on resistance of 0.15
, which decreases the power dissipation when the switch is conducting. Since the assumed highest open-circuit DC voltage of the piezo is about 20 V, a switching frequency of 1 kHz and a 33 mF, 35 V voltage rate electrolytic capacitor is adopted. Vc max Vo Vs Vo Vo : 8LCf 2 Vs 18

As shown in Figure 7, the waveform of the capacitor current ic can be divided into two periods. In period III, the ic is positive, which means the capacitor is charged. In period IV, when the ic becomes negative, the capacitor is discharged. The maximum output voltage across the capacitor can be evaluated by Equation (18). Since the expected maximum output voltage across the supercapacitor is less than 2.5 V, the design uses a 400 F, 2.5 V voltage rate supercapacitor as the energy buffer, which has 5.10 Wh/kg energy density and very low DC equivalent series resistance (ESR) of 3.2 m
. In order to maintain the continuous current flowing through the inductor, this design employs a 140 mH inductor.

Feedback Control System In order to use the charging current of the supercapacitor to control the duty cycle of the buck regulator, an analog-to-digital converter (ADC) is used to sample the voltage across a 0.15
current sensitive resistor as shown in Figure 5. Since there requires sufficient time to stabilize the charging current, the ADC samples the signal at 1 Hz with a 2-pole Sallen-Key filter. The sampled data is sent to the FPGA through serial peripheral interface (SPI). After the conversion, the ADC works in the shutdown mode to decrease power dissipation. Optimized Duty Cycle Computation: The flowchart of optimized duty cycle generation is showed in Figure 8. In system initialization, the output duty cycle is initialized to 100% and an 8-bit counter in FPGA is set to 255. Then, the duty cycle will decrease 0.39% per second, during which the sampled current is stored in on-chip memory. After 256 steps, the optimized duty cycle corresponding to maximized charging current is obtained among the 256 sampled data. The total process time to obtain the optimized duty cycle is about 4 min, which can be reconfigured according to different application requirements. If the mechanical vibration of the piezo is changed, the sampled instantaneous charging current is changed. The program will re-initialize to obtain the new optimized duty cycle to maximize the corresponding charging current. Software-defined PWM: The pulse width modulation (PWM) generation is implemented by using instructions executed by a PicoBlaze processor in the FPGA. The digital system design in the FPGA is shown in Figure 9. The software implementation indicates that the dynamics of the PWM are totally flexible by the instruction executions in the processor. The two key parameters of the PWM are the pulse repetition frequency (PRF) and the resolution of the duty cycle. This design has the PRF of 1 kHz and the

Q1 + is Vs + iL Dm L

A ic + Vc C

+ Rl Vo

io

Figure 6. Schematic of a classical DCDC buck converter.

iL I2 I1 o

II kT

I T (k + 1)T 2T

iC I2 IL I1 ILo VC

kT III IV

T (k + 1)T

2T

kT

T (k + 1)T

2T

Figure 7. Waveforms of a classical DCDC buck converter.

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resolution of 8-bits. Each step can be resolved at intervals of: 1 ms 3:90625 ms: 28 19

one instruction every 40 ns. The amount of instructions that can be executed within the 3.90625 ms step interval to support the PRF and duty cycle resolution is:   3:90625 ms 97: 20 40 ns Increasing the PRF or the duty cycle resolution will reduce the number of instructions, which can be executed during each step. In the end, there will only be enough instructions available to generate the PWM itself. Higher clock rates can be a solution only when the speed grade of FPGA permits. However, 97 instructions in this design are adequate to drive the PWM signal and still have approximately 50% of the processor resources available for the higher level control tasks such as dealing with the universal asynchronous receiver/ transmitter, processing the text commands from the terminal, and communicating with the ADC through the SPI interface as shown in Figure 9. EXPERIMENT

The PicoBlaze processor is a highly predictable processor requiring precise two clock cycles to execute one instruction. Although the PicoBlaze processor can be clocked faster in a higher speed grade of FPGA devices, this design makes direct use of a 50 MHz crystal oscillator on a development board. The PicoBlaze processor is able to execute 25 million instructions per second or

Initialize counter=255

Counter = 0? No Sample current

Yes

Find the maximized charging current

Output optimized PWM duty cycle

Store the sampled current in memory

Sample current

Decrease the duty cycle of PWM Decrease counter by1 ISR

Current change?

Yes

No

Figure 8. Algorithm of duty cycle computation in the processor.

The experiment setup is shown in Figure 10(d). The experiment uses piezo, QuickPack QP20W, from Mide Inc., which is shown in Figure 10(a). The bimorph piezo has two 10 mil depth piezoelectric materials stacked in one epoxy. The specifications of the piezo is shown in Table 1. The piezo equivalent capacitance is only 0.2 mF, which is much smaller than the 33 mF rectifier capacitor used in the design. Therefore, most of the power generated from the vibrating piezo will feed into the load during the conduction of the diodes. One edge of the piezo is fixed on a mechanical wave vibrator in horizontal cantilever configuration as shown in Figure 10(b). The mechanical wave vibrator has frequency response of 0.15 kHz with an amplitude

Address ROM 10 RXD 8


0 MUX1

Instruction 18 Output PicoBlaze 8 Processor


0 MUX2 1 Sel

TXD

ADC

Input 8

Sel

PWM

Port select Counter Decode at 195

8 Interrupt
CLR D Q1 CK Q Q D Q2 CK Q PR Q

Interrupt ack

CLK
Figure 9. Architecture of the digital system in a FPGA.

Piezoelectric Micro-power Generation

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displacement up to 7 mm at 1 Hz. The maximum vibration amplitude will decrease when the vibration frequency is increased, which can simulate the practical microvibration in daily life. Since the driving signal of the vibrator requires a function generator with minimum of 8 V, 0.5 A output, an accurate frequency adjustable signal generator with a power amplifier is used to drive the mechanical wave vibrator. In order to simulate the low frequency vibrations with acceptable output voltage level from piezo and not to break the fragile piezoelectric material, three experiments are conducted with frequency of 7 Hz with constant vibration amplitude. The variations of the vibration is beyond the scope of this article. The harvested energy from the piezo is rectified, regulated, fed to the supercapacitor through a designed printed circuit board (PCB) shown in Figure 10(c). The ADC module in Figure 10(d) samples the charging current of the supercapacitor and sends the information of charging current to the PicoBlaze processor in a Spartan-3E FPGA. The generated PWM signal from the FPGA general-purpose IO drives the power MOSFET in the buck regulator through a driver. Meanwhile, the information of the charging current and duty cycle is sent to a terminal through a serial communication. The piezo was measured with open circuit in the first experiment. The open circuit peak-to-peak voltage Voc (pk pk) generated from the piezo is about 87.0 V

and measured root mean square (RMS) value Voc (rms) is about 28.9 V. When the piezo is paralleled with a variable resistive load, the RMS value of output voltage across the resistive load is measured with different resistances as shown in the Figure 11(a). When the load are set to 100 k
and 1 M
, the RMS value of output voltage across the load are approximately 5 V and 22 V, respectively. The corresponding output power of the piezo are about 0.25 and 0.48 mW. When the resistive load is increased to above 2 M
, the resistive load behaves as an open circuit and the RMS value of output voltage approximates to open circuit voltage of 28.9 V, which shows the power generation capability of the piezo at 7 Hz vibration frequency. In the second experiment, the piezo is paralleled with a 100 mF capacitor without any resistive load. When the vibration frequency is 7 Hz, the capacitor can be charged up to 20.3 V. After the 100 mF capacitor is

Table 1. Specifications of piezo, QuickPack QP20W.


Specifications Device size (inch) Device weight (oz) Active elements Piezo wafer size (inch) Device capacitance (mF) Full scale voltage range (V) Value 2.00 1.50 0.03 0.28 1 stack of 2 piezos 1.81 1.31 0.01 0.20 200

(a) (b) (c)

3.69 inch

4.31 inch
(d)

Designed PCB

Supercapacitor

PWM output

Piezo

FPGA development board

ADC

Vibrator

Figure 10. Setup of experiment: (a) packaged piezo QP20W from Mide Inc., (b) cantilever configuration of the piezo on a vibrator, (c) PCB board of a buck regulator with interfaces, (d) experiment setup of the piezoelectric energy harvesting system.

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(a)
fc=7 HZ Voc(pk-pk)=87.0 V Voc(rms)=28.9 V

Z. ZHAO ET AL.
(b)
fc=7 HZ Voc(mean)=20.3V

Output rms voltage (V)

Output power (mW)

Piezo

Vo

Piezo

Vc

Vo

) fc=7 HZ Voc(rms)=28.9 V

( )

(c)

The charging current of supercapacitor (mA)

Piezo

+ Vc

Buck

Vo Rs

Feedback

( )
Figure 11. Results of experiment: (a) output voltage of piezo with a direct resistive load when Voc (rms) 28.9 V, (b) output power vs mean output voltage when Voc (mean) 20.3 V, (c) charging current of supercapacitor vs duty cycle when Voc (rms) 28.9 V.

paralleled with a variable resistive load, the stable voltage charged on the capacitor will depend upon the load resistances. When the resistance is increased, the charged voltage will increase, because the discharge current is decreased. The relationship between output power and the charged voltage is shown in Figure 11(b). As the resistive load is increased from 10 k
to 1 M
, the mean output voltage will increase from 420 mV to 10.12 V, and the output power will increase from 0.02 to 0.1 mW. Although, the mean output voltage keeps on increasing when the resistive load is increased, the output power is decreased after the mean output voltage reaches 10 V. The maximum output power of 0.1 mW is available when the mean output voltage is around 10 V, which is approximately the half of the open circuit voltage Voc (mean) of 20.3 V. This result proves the existence of the maximum output power of the piezo in 7 Hz vibration.

The input voltage of the buck regulator can be adjusted to around 10 V, when the vibration frequency of piezo is 7 Hz, the corresponding output voltage across the 93 k
resistive load is 2.5 V. The corresponding output power of buck converter is 0.067 mW. With the maximized piezo output power of 0.1 mW, the transfer efficiency of buck regulator is about 67.4%. In the third experiment, the designed feedback control system is used to test the performance of the designed circuit as shown in Figure 11(c). The relationship between the sampled charging current of the supercapacitor and duty cycle is provided. When the vibration level of the piezo is 7 Hz with Voc(rms) of 28.9 V, the measured charging current is very small until the duty cycle is decreased to 25%. The charging current increases significantly when duty cycle is decreased from 10% to 2%. However, duty cycle smaller than 1.4% degrades the charging current of the

Piezoelectric Micro-power Generation Table 2. Electrical specifications of different supercapacitors.


Specifications Capacitance (F) Voltage (V) DC ESR (m
) Operation temp ( C) Power density (W/kg) Energy density (Wh/kg) Leakage current (mA) PC-10 10 2.5 0.18 40 to 70 660 6.9 mAh 0.04 BCAP0025 25 2.7 42 40 to 65 2900 3.62 0.045 BCAP0050 50 2.7 20 40 to 65 3100 3.62 0.075 BCAP0150 150 2.7 14 40 to 65 1700 4.34 0.5 BCAP0310 310 2.5 2.2 40 to 65 5600 4.48 0.45 BCAP350 350 2.5 3.2 40 to 65 3900 5.1 1

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NESSCAP 400 2.7 4.2 40 to 60 5340 6.23 1

Table 3. Design performance benchmark.


Specifications Optimized duty cycle Maximized charging current (mA) Rectifier voltage (V) Open-circuit voltage (V) PWM frequency (kHz) Converter efficiency Setup time (s) Ottoman (2002) 3.18% or 3.16% 4.3 20.4 40 1 65% 360 Zhou 2.17% 17.36 20.3 28.9 1 67.4% 250

Table 4. Device resource utilization of Spartan-3E FPGA.


Specifications No. No. No. No. No. No. of of of of of of flip-flops occupied slices 4 input LUTs bonded IOBs RAMB16s BUFGMUXs Used 108 118 199 24 1 1 Available 9312 4656 9312 232 20 24 Utilization 1% 2% 2% 10% 5% 4%

Table 5. Specifications of ASIC design.

supercapacitor. The maximum charging current of 17.36 mA is measured when the duty cycle is optimized to 2.17%. As shown in Figure 11(b), the measured maximum output power of piezo is about 100 mW. Then, the estimated Ip is about 4.89 mA. Using Equation (15) with ! of 7 Hz and Cp of 0.2 mF, the estimated Vo will be about 6 mV. At this point, if the piezo is just connected with a 93 k
resistive load, the output voltage can stabilize at 2.5 V, which means the output power of piezo is about 67.2 mW. With the same input impedance in Figure 11(a), the Ip will be about 70.7 mA. Using Equation (16), the estimated ic is 15.08 mA, which is close to measured 17.36 mA. With different supercapacitors, the maximized charging current is increased when the ESR of supercapacitor is decreased, which is shown in Figure 11(c). However, there is also tradeoff of energy density in choosing proper supercapacitor. A variety of supercapacitors with different specifications are shown in Table 2 (Maxwell, 2009). As shown in the Table 3, the performance of the circuit design is compared with similar design in previous researches. The Ottomans research used similar piezo in size of 2.00 1.50 0.03 inch with vibration frequency of 53.8 Hz. Although the rectifier voltage and the efficiency of converter approximate to previous researches, the charging current of the supercapacitor is improved four times, because the supercapacitor can quickly soak up the power generated from piezo. In addition, only 69.4% of previous setting time is needed to scan the full scale of duty cycle. As shown in Table 4, only about 1 2% FPGA resource is used to adaptively optimize the duty cycle. According to the

Specifications Technology Cells Core area (mm2) Leakage power (nW) Dynamic power (nW) Total power (nW)

AMIS 0.5 mm 6574 2,690,703 812 165,216,621 165,217,434

IBM 7HP 180 nm 4917 38,204 0 5,615,867 5,615,867

TSMC 130 nm 4446 57,585 95 1,828,778 1,828,873

TSMC 90 nm 4579 28,362 244,173 612,870 857,044

Xilinx power analyzer, the total quiescent and dynamic power consumption of FPGA are about 81 and 3 mW, respectively. Based on the ultra high frequency RFID research (Karthaus and Fischer, 2003), the DC power of 16.7 mW extracted from RF signal is necessary to power tag internal logic. With the energy of 67.2 mW harvested from piezo, the front stage voltage multiplier of the tag can be eliminated. In addition, the reading distance of the active tag powered by a piezo can be further extended. In order to prove the feasibility of designing a standalone energy harvesting system, the digital design in FPGA is synthesized using different process technologies. The specifications of ASIC design with different process technologies are shown in Table 5. Both core area and power consumption are decreased with smaller process node. The power consumption of about 0.86 mW in 90 nm process is close to the harvested power of 0.1 mW. CONCLUSION Due to the high power density of the supercapacitor, the output voltage is almost constant. Therefore, the

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charging current of a supercapacitor is critical in evaluating the efficiency of energy storage in the supercapacitor. With the designed feedback control system, the charging current of the supercapacitor can be maximized by computing the optimized duty cycle of the buck regulator. The maximum charging current of 17.36 mA is obtained when the duty cycle is optimized to 2.17%. Future researches will focus on affect of vibrations on circuit performance and designing ultra-low power integrated circuits to make energy harvesting system stand-alone.

ACKNOWLEDGMENT This research was supported by the 3M Non-Tenured Faculty Award and NSF EPSCoR.

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