What are the steps required to solve setup and Hold violations in VLSI?

There are few steps that has to be performed to solved the setup and hold violations in VLSI. The steps are as follows: the optimization and restru turin! of the lo!i between the flops are arried wa". This wa" the lo!i s are ombined and it helps in solvin! this problem. There is wa" to modif" the flip#flops that offer lesser setup dela" and provide faster servi es to setup a devi e. $odif"in! the laun h#flop to have a better hold on the lo % pin& whi h provides '(#)* that ma%es the laun h#flop to be fast and helps in fi+in! the setup violations. The networ% of the lo % an be modified to redu e the dela" or slowin! down of the lo % that aptures the a tion of the flip#flop. There an be added dela",buffer that allows less dela" to the fun tion that is used. What are the different wa"s in whi h antenna violation an be prevented? -ntenna violation o urs durin! the pro ess of plasma et hin! in whi h the har!es !eneratin! from one metal strip to another !ets a umlated at a sin!le pla e. The lon!er the strip the more the har!es !ets a umulated. The prevention an be done b" followin! method: 'reatin! a .o!!in! the metal line& that onsists of atleas one metal above the prote ted la"er. There is a requirement to .o! the metal that is above the metal !ettin! the et hin! effe t. This is due to the fa t that if a metal !ets the et hin! then the other metal !ets dis onne ted if the prevention measures are not ta%en. There is a wa" to prevent it b" addin! the reverse /iodes at the !ates that are used in the ir uits. What is the fun iton of tie#hi!h and tie#low ells? Tie#hi!h and tie#low are used to onne t the transistors of the !ate b" usin! either the power or the !round. The !ates are onne ted usin! the power or !round then it an be turned off and on due to the power boun e from the !round. The ells are used to stop the boun in! and eas" from of the urrent from one ell to another. These ells are required Vdd that onne ts to the tie#hi!h ell as there is a power suppl" that is hi!h and tie# low !ets onne ted to Vss. This onne tion !ets established and the

transistors fun tion properl" without the need of an" !round boun e o urin! in an" ell. What is the main fun tion of metastabilit" in VS/L? $etastabilit" is an un%nown state that is !iven as neither one or zero. It is used in desi!nin! the s"stem that violates the setup or hole time requirements. The setup time requirement need the data to be stable before the lo %#ed!e and the hold time requires the data to be stable after the lo % ed!e has passed. There are potential violation that an lead to setup and hold violations as well. The data that is produ ed in this is totall" as"n hronous and lo %ed s"n hronous. This provide a wa" to setup the state throu!h whi h it an be %nown that the violations that are o urin! in the s"stem and a proper desi!n an be provided b" the use of several other fun tions. What are the steps involved in preventin! the metastabilit"? $etastabilit" is the un%nown state and it prevents the violations usin! the followin! steps: proper s"n hronizers are used that an be two sta!e or three sta!e whenever the data omes from the as"n hronous domain. This helps in re overin! the metastable state event. The s"n hronizers are used in between ross# lo %in! domains. This redu es the metastabilit" b" removin! the dela" that is aused b" the data element that are omin! and ta%in! time to !et removed from the surfa e of metal. 0se of faster flip#flops that allow the transa tion to be more faster and it removes the dela" time between the one omponent to another omponent. It uses a narrower metastable window that ma%es the dela" happen but faster flip#flops help in ma%in! the pro ess faster and redu e the time dela" as well. What are the different de!ins onstraints o ur in the S"nthesis phase? The steps that are involved in whi h the desi!n onstraint o urs are: first the reation of the lo % with the frequen " and the dut" " le !ets reated. This lo % helps in maintainin! the flow and s"n hronizin! various devi es that are used. /efine the transition time a ordin! the requirement on the input ports. The load values are spe ified for the output ports that are mapped with the input ports.

Settin! of the dela" values for both the input and output ports. The dela" in ludes the input and output dela". Spe if" the ase#settin!s to report the orre t time that are mat hed with the spe ifi paths. The lo % un ertainit" values are setup and hold to show the violations that are o urin!. What are the different t"pes of s%ews used in VLSI? There are three t"pes of s%ew that are used in VLSI. The s%ew are used in lo % to redu e the dela" or to understand the pro ess a ordin!l". The s%ew are as follows: Lo al s%ew: this ontain the differen e between the laun hin! flip#flop and the destination flip#flop. This defines a time path between the two. 1lobal s%ew: defines the differen e between the earliest omponent rea hin! the flip flow and the the latest arrivin! at the flip flow with the same lo % domain. In this dela"s are not measured and the lo % is provided the same. 0seful s%ew: defines the dela" in apturin! a flip flop paths that helps in settin! up the environment with spe ifi requirement for the laun h and apture of the timin! path. The hold requirement in this ase has to be met for the desi!n purpose. What are the han!es that are provided to meet desi!n power tar!ets? To meet the desi!n power tar!et there should be a pro ess to desi!n with $ulti#V// desi!ns& this area requires hi!h performan e& and also the hi!h V// that requires low#performan e. This is used to reate the volta!e !roup that allow the appropriate level#shifter to shift and pla ed in ross# volta!e domains. There is a desi!n with the multiple threshold volta!es that require hi!h perfoman e when the Vt be omes low. This have lots of urrent lea%a!e that ma%es the Vt ell to lower the performan e. The redu tion an be performed in the lea%a!e power as the lo % in this onsume more power& so pla in! of an optimal lo % ontrols the module and allow it to be !iven more power. 'lo % tree allow the swit hin! to ta%e pla e when the lo % buffers are used b" the lo % !atin! ells and redu e the swit hin! b" the power redu tion. What are the different measures that are required to a hieve the desi!n for better "ield?

To a hieve better "eild then there should be redu tion in maufa turabilit" flaws. The ir uit perfoman e has to be hi!h that redu es the parametri "ield. This redu tion is due to pro ess variations The measures that an be ta%en are: 'reation of powerful runset files that onsists of spa in! and shortin! rules. This also onsists of all the permissions that has to be !iven to the user. 'he % the areas where the desi!n is havin! litho!raphi issues& that onsists of sharp uts. 0se of redundant vias to redu e the brea%a!e of the urrent and the barrier. 2ptimal pla in! of the de# ouplin! apa itan es an be done so that there is a redu tion in power#sur!es. What is the differen e between the meal" and moore state ma hine? $oore model onsists of the ma hine that have an entr" a tion and the output depends onl" on the state of the ma hine& whereas meal" model onl" uses Input - tions and the output depends on the state and also on the previous inputs that are provided durin! the pro!ram. $oore models are used to desi!n the hardware s"stems& whereas both hardware and software s"stems an be desi!ned usin! the meal" model. $eal" ma hine3s output depend on the state and input& whereas the output of the moore ma hine depends onl" on the state as the pro!ram is written in the state onl". $eal" ma hine is havin! the output b" the ombination of both input and the state and the han!e the state of state variables also have some dela" when the han!e in the si!nal ta%es pla e& whereas in $oore ma hine doesn3t have !lit hes and its ouput is dependent onl" on states not on the input si!nal level. What is the differen e between S"n hronous and -s"n hronous reset.? S"n hronous reset is the lo!i that will s"nthesize to smaller flip#flops. In this the lo % wor%s as a filter providin! the small reset !lit hes but the !lit hes o ur on the a tive lo % ed!e& whereas the as"n hronous reset is also %nown as reset release or reset removal. The desi!ner is responsible of added the reset to the data paths. The s"n hronous reset is used for all the t"pes of desi!n that are used to filter the lo!i !lit hes provided between the lo %s. Whereas& the ir uit an be reset with or without the lo % present.

S"n hronous reset doesn3t allow the s"nthesis tool to be used easil" and it distin!uishes the reset si!nal from other data si!nal. The release of the reset an o ur onl" when the lo % is havin! its initial period. If the release happens near the lo % ed!e then the flip#flops an be metastable. What are the different desi!n te hniques required to reate a La"out for /i!ital 'ir uits? The different desi!n te hniques to reate the La"out for di!ital ir uits are as follows: /i!ital desi!n onsists of the standard ells and represent the hei!ht that is required for the la"out. The la"out depends on the size of the transistor. It also onsists of the spe ifi ation for Vdd and 14/ metal paths that has to be maintained uniforml". 0se of metal in one dire ton onl" to appl" the metal dire tl". The metal an be used and displa"ed in an" dire tion. 5la in! of the substrate that pla e where it shows all the empt" spa es of the la"out where there is resistan es. 0se of fin!ered transistors allows the desi!n to be more eas" and it is eas" to maintain a s"mmetr" as well. Write a pro!ram to e+plain the omparator? To ma%e a omparator there is a requirement to use multiple+er that is havin! one input and man" outputs. This allows the hoosin! of the ma+imum numbers that are required to desi!n the omparator. The implementation of the 6 bit omparator an be done usin! the law of ti!otom" that states that - ) 7& - 8 7& - 9 7 :Law of tri!otom";. The omparator an be implemented usin!: ombinational lo!i ir uits or multiple+ers that uses the H/L lan!ua!e to write the s hemati at <TL and !ate level. 7ehavioral model of omparator represented li%e: module omp= :">&"6&"?&a&b;@ input A>:=B a&b@ output ">&"6&"?@ wire ">&"6&"?@ assi!n ">9 :a )b;? >:=@ assi!n "69 :b )a;? >:=@ assi!n "?9 :a99b;? >:=@ endmodule

What is the fun tion of hain reorderin!? The optimization te hnique that is used ma%es it diffi ult for the hain orderin! s"stem to route due to the on!estion aused b" the pla ement of the ells. There are tool available that automate the reorderin! of the hain to redu e the on!estion that is produ ed at the first sta!e. It in reases the problem of the hain s"stem and this also allow the over omin! of the buffers that have to be inserted into the s an path. The in rease of the hold time in the hain reorderin! an ause !reat amount of dela". 'hain reorderin! allows the ell to be ome in the ordered format while usin! the different lo % domains. It is used to redu e the time dela" aused b" random !eneartion of the elment and the pla ement of it. What are the steps involved in desi!nin! an optimal pad rin!? To ma%e the desi!n for an optimal pad rin! there is a requirement for th orner#pads that omes a ross all the orners of the pad#rin!. It is used to !ive power ontinuit" and %eep the resistan e low. It requires the pad rin! that is to fullfill the power domains that is ommon for all the !round a ross all the domains. It requires the pad rin! to ontain simultaneous swit hin! noise s"stem that pla e the transfer ell pads in ross power domains for different pad len!th. /rive stren!th is been seen to he % the urrent requirements and the timin!s to ma%e the power pads. 'hoose a no# onne tion pad that is used to fill the pad#frame when there is no requirement for the inputs to be !iven. This onsumes less power when there is no input !iven at a parti ular time. 'he %in! of the os illators pads ta%e pla e that uses the s"n hronous ir uit
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What is the fun tion of enhan ement mode transistor? The enhan ement mode transistors are also alled as field effe t transistors as the" rel" on the ele tri filed to ontrol the shape and ondu tivit" of the hannel. This onsists of one t"pe of har!e arrier in a semi ondu tor material environment. This also uses the unipolar transistors to differentiate themselves with the sin!le# arrier t"pe operation transistors that onsists of the bipolar .un tion transistor. The uses of field effe t transistor is to ph"s ial implmementation of the semi ondu tor materials that is ompared with the bipolar transistors. It provides with the ma.orit" of the har!e arrier devi es. The devi es that onsists of a tive hannels to ma%e the har!e arriers pass throu!h. It onsists of the on ept of drain and the sour e. What is the purpose of havin! /epletion mode /evi e? /epletion modes are used in $2SCDT it is a devi e that remains 24 at zero !ate#sour e volta!e. This devi e onsists of load resistors that are used in the lo!i ir uits. This t"pes are used in 4#t"pe depletion#load devi es that allow the threshold volta!es to be ta%en and use of #? V to E?V is done. The drain is more positive in this omparison of 5$2S where the

polarities !ets reversed. The mode is usuall" determined b" the si!n of threshold volta!e for 4#t"pe hannel. /epletion mode is the positive one and used in man" te hnolo!ies to represent the a tual lo!i ir uit. It defines the lo!i famil" that is dependent on the sili on VLSI. This onsists of pull#down swit hes and loads for pull#ups. What is the differen e between 4$2S and 5$2S te hnolo!ies? 5$2S onsists of metal o+ide semi ondu tor that is made on the n#t"pe substrates and onsists of a tive areers named as holes. These holes are used for mi!ration purpose of the har!es between the p#t"pe and the drain. Whereas& 4$2S onsists of the metal o+ide semi ondu tor and the" are made on p#t"pe substrates. It onsists of ele trons as their arriers and mi!ration happens between the n#t"pe sour e and drain. 2n appl"in! the hi!h volta!e on the lo!i !ates 4$2S will be ondu ted and will !et a tivated& whereas 5$2S require low volta!e to be a tivated. 4$2S are faster than 5$2S as the arriers that 4$2S uses are ele trons that travels faster than holes. The speed is twi e as fast as holes. 5$2S are more immune to noi e than 4$2S. What is the differen e between '$2S and 7ipolar te hnolo!ies? '$2S te hnolo!" allows the power dissipation to be low and it !ives more power output& whereas bipolar ta%es lots of power to run the s"stem and the iri utar" require lots of power to !et a tivated. '$2S te hnolo!" provides hi!h input impedan e that is low drive urrent that allow more urrent to be flown in the iru it and %eep the ir uit in a !ood position& whereas it provides hi!h drive urrent means more input impedan e. '$2S te hnolo!" provides s alable threshold volta!e more in omparison to the 7ipolar te hnolo!" that provides low threshold volta!e. '$2S te hnolo!" provides hi!h noise mar!in& pa %in! densit" whereas 7ipolor" te hnolo!" allows to have low noise mar!in so that to redu e the hi!h volues and !ive low pa %in! densit" of the omponents. What are the different lassifi ation of the timin! ontrol? There are different lassifi ation in whi h the timin! ontrol data is divided and the" are: /ela" based timin! ontrol: this is based on timin! ontrol that allows to mana!e the omponent su h that the dela" an be notified and wherever it is required it an be !iven. The dela"s that are based on this are as:

<e!ular dela" ontrol: that ontrols the dela" on the re!ular basis. Intra#assi!nment dela" ontrol: that ontrols the internal dela"s. Fero dela" ontrol Dvents based timin! ontrol: this is based on the events that are performed when an event happens or a tri!!er is set on an event that ta%es pla e. It in ludes <e!ular event ontrol 4amed event ontrol Dvent 2< ontrol Level sensitive timin! ontrol: this is based on the levels that are !iven li%e = level or > level that is bein! !iven or shown and the data is bein! modified a ordin! the levels that are bein! set. When a level han!es the timin! ontrol also han!es.