VLSI Design Verification and Testing

Fault Modeling

Outline
Vocabulary: defects, errors and faults Functional vs. structural testing Fault models Single stuck-at fault Fault equivalence
equivalence collapsing

Fault dominance dditional fault models

!"ercise #roblems

Defects, errors and faults

Defect unintended difference bet$een t%e implemented %ard$are and its intended design
%ard$are, p%ysical level

Error $rong output signal produced by a defective system Fault representation of a defect at t%e abstracted function level
functional level
V((

&$o-input ' '( gate

, &.

Defect:

s%ort to ground

Fault: stuck-at logic ) Error: if *+ and ,*+ t%en -*+ correct output is -*)

&+ 1

fault model a collection of identical electrical be%aviors caused by various defects are gat%ered into a model t%at is used for simulation of large systems

Fault models
/eal defects 0and t%e variations t%ereof1 are too numerous and diverse, and still may differ in small respects, %o$ever preventing possible t%oroug% analysis ,ridge t%e gap bet$een a p%ysical cause and a functional effect
cause in t%e analog domain manifestation in t%e digital domain

&esting can not address any sort of defect, a subset of target fault must be derived. &%e testing algorit%ms $ill target to detecting t%is subset
generation and evaluation of test vectors

Fault models are independent of tec%nology

Fault models levels

layout level
increasing level of abstraction

geometric information accurately reflects reality, but too comple" circuit description modeled for analog circuit testing2 transistors, /, 3, - faults feasible for small circuits structural description 0netlist of gates1 stuck-at faults are t%e most popular models at t%is level bridging faults, delay faults also apply at t%is level be%avioral description faults at t%is level no longer %ave obvious correlation $it% manufacturing defects

transistor level

register-transfer level

be%avioral level

across levels

do not fit into any of t%e previous level e.g. quiescent current 04((51

Examples of defects in chips

bridged or missing metal contamination by particles missing contact $indo$ o"ide breakdo$n over etc%ing, or incomplete etc%ing mec%anical damage, or scratc%es defective mask defective p%otoresist incomplete removal of p%otoresist cracks, crystal imperfections defective connection on t%e bonding pads etc.

Scaling and complexity testing issue 6ur testing problem can be devised as depicted
8

$e kno$ t%e functionality, t%e topology 0netlist1 $e suspect some defects may disrupt correct circuit operation but 7 we can only access inputs (primary inputs) and outputs (primary outputs), i.e. no internal node

Functional vs structural testing

Functional test of a +)-input '( gate $ould demand testing for all input patterns, i.e. .+)
+ ) + ) + ) + ) + ) )

$%at can be concluded out of t%is test 8 7

an '( not a ' '( not an 6/ not a '6/

9ate under test is

test is and '(, and not any of t%e ot%ers. &%e number of ,oolean functions t%at can be generated $it% a +)-input gate equals .+).:

Functional vs structural testing !"#

Functional test of a +)-input '( gate $ould demand testing for all input patterns, i.e. .+)

+ ) + ) + ) + ) + )

These are the only valid conclusions that may e ta!en, since the output violates the truth ta le of "#"D and $%

$%at can be concluded out of t%is test 8 7

an '( not a ' '( not an 6/ not a '6/

9ate under test is

&%e full functional test must allo$ to conclude t%at t%e gate under test is and '(, and not any of t%e ot%ers. &%e number of ,oolean functions t%at can be generated $it% a +)-input gate equals .+).:
&%e full functional test of t%e ;<=)) =-bit microprocessor 0+>?@, .;AB, ?@ instructions, ?))) transistors1 $as estimated to take about 7 t$o million years C

 Structural test do not focus on t%e fonction implemented by a circuit, but on its structure
gates interconnects netlist
Function # out Function & in+ in. out

Functional vs Structural Testing !$#

basic assumption is t%at t%e design is correct

&%e focus on t%e structure, makes it possible to develop algorit%ms t%at are independent of t%e design. &%ese algorit%ms are based on fault models. Several $ill be presented in t%is course.

Single stuc%&at fault

Single stuck-at-DvalueE 0value*), or value*+1, represents a single line $%ic% is permanently tied to ) or +, i.e. 9'( or V((
most commonly applied fault model t$o possible faults may occur on a line, namely stuck-at-) and stuck-at+ representations:
s-a-), s-a-+ a), a+ line a s-a-), s-a-+ respectively S ), S +

#roperties of single stuck-at fault

6nly one line is faulty &%e logic state of a primary input, primary output or internal gate input or output is permanently stuck to logic + or logic )

Single stuc%&at fault !"#

e"ample: follo$ing ,oolean circuit %as > fault sites 0 1 and += single stuck-at faults
test vector

( ' (

'
g e

(
b

' (()
s-a-) B

'
f c %

( (') '

notice t%at t%e stem 0b1 and fanout branc%es 0e and f1 of a net are considered independently

Single stuc%&at fault model applied in a '('D gate

V((

preliminary remark: in t%e rest of t%is class, $e $ill apply stuck-at models one abstraction level %ig%er, i.e. /&3 or gate-level
G ,

Fe can observe t%e follo$ing:

controlling value some values $%ic% are present at one gate input determine on t%eir o$n t%e output value2 e.g. *) is a cont an input vector can detect a specific set of faults rolling value sensitized path some values $%ic% are present at one gate input, e.g. ,, let t%e value of t%e ot%er input, e.g. propagate to t%e output2 if a fault is present stucking , t%an it can be detected $it% an appropriate input vector2 t%e pat% is sensitiBed to t%e fault t%e minimum set of vectors needed to test t%e circuit is smaller t%en t%e e"austive number of input vectors

Single stuc%&at fault model applied in a '('D gate

V(( G ,

Fe can observe t%e follo$ing:

controlling value some values $%ic% are present at one gate input determine on t%eir o$n t%e output value2 e.g. *) is a controlling value ut vector can detect a specific set of faults sensitized path some values $%ic% are present at one gate input, e.g. ,, let t%e value of t%e ot%er input, e.g. propagate to t%e output2 if a fault is present stucking , t%an it can be detected $it% an appropriate input vector2 t%e pat% is sensitiBed to t%e fault t%e minimum set of vectors needed to test t%e circuit is smaller t%en t%e e"austive number of input vectors

Single stuc%&at fault model applied in a '('D gate

V((

' ( ,
G

Fe can observe t%e follo$ing:

controlling value some values $%ic% are present at one gate input determine on t%eir o$n t%e output value2 e.g. *) is a controlling value an input test vector can detect a specific set of faults sensitized path some values $%ic% are present at one gate input, e.g. ,, let t%e value of t%e ot%er input, e.g. propagate to t%e output2 if a fault is present stucking , t%an it can be detected $it% an appropriate input vector2 t%e pat% is sensitiBed to t%e fault t%e minimum set of vectors needed to test t%e circuit is smaller t%en t%e e"austive number of input vectors

Single stuc%&at fault model applied in a '('D gate

V(( G ,

s-a-)

Fe can observe t%e follo$ing:

controlling value some values $%ic% are present at one gate input determine on t%eir o$n t%e output value2 e.g. *) is a controlling value an input test vector can detect a specific set of faults sensitized path some values $%ic% are present at one gate input, e.g. , let t%e value of t%e ot%er input, e.g. , propagate to t%e output2 if a fault is present stucking ,, t%an it can be activated $it% an appropriate input vector, and propagate to t%e output2 t%e pat% is sensitiBed to t%e fault t%e minimum set of vectors needed to test t%e circuit is smaller t%en t%e e"austive number of input vectors

Single stuc%&at fault model applied in a '('D gate

V(( G ,

Fe can observe t%e follo$ing:

controlling value some values $%ic% are present at one gate input determine on t%eir o$n t%e output value2 e.g. *) is a controlling value an input test vector can detect a specific set of faults sensitized path some values $%ic% are present at one gate input, e.g. , let t%e value of t%e ot%er input, e.g. , propagate to t%e output2 if a fault is present stucking ,, t%an it can be activated $it% an appropriate input vector, and propagate to t%e output2 t%e pat% is sensitiBed to t%e fault t%e minimum set of vectors needed to test t%e circuit is smaller t%en t%e e"%austive number of input test vectors

Fault detection requires:

Single stuc%&at fault) fault detection

a test t t%at activates fault f t%e error t%at %as been activated must propagate to an observation point, a primary output or a latc% $%ere it is memoriBed in order to propagate to an observation point, all off-pat% gate inputs must be set to non-controlling values

) )
6nly vector ++ $ill activate t%e fault: +), )+, )) $ill not.

9+

e ) f s-a-) + 0)1 9H

&rue response Faulty response

+ 0)1

+ +

9.

circuit $it% n lines can %ave at most .n single-stuck-at faults

t%is circuit %as ? lines, and can be affected by +: single-stuck-at faults

Fault e*uivalence !+#

&%e number of fault sites in a ,oolean circuit is given as: I#4 J Igates J I 0fanout branc%es1
I: Knumber ofL #4: primary inputs

&%is number can gro$ to a significantly large value2 as $e $ill see in a later lecture, test vectors need to be found for every fault reducing t%e number of faults $ould be beneficial

Fault equivalence &$o faults f+ and f. are equivalent if all tests t%at detect f+ also detect f.

Fault e*uivalence !"#

-onsidering an n-bit input, single output, fault-free circuit $%ic% performs f, (V), $%ere V is an n-bit input ,oolean vector 4n t%e presence of t$o individual faults + and ., t%e circuit output function c%anges to f+ (V) and f" (V) respectively
i.e. V activates fault + and fault .

&%e t$o faulty functions are indistinguishable iff t%e faults %ave t%e same set of tests:

f1 (V ) f 2 (V ) = 0
--: M6/ for all .n V vectors

Fault e*uivalence) analysis of '('D

a b

sa) sa+ sa) sa+

' '( gate %as kJ+ s-a-) faulty inputs and output
sa) sa+ B

!ac% s-a-) transforms t%e ' '( gate output to a constant + value, regardless of t%e input test vector &%us,
)

, ,) and G+ are equivalent

E*uivalence rules

Fault collapsing
ll faults in a circuit are partitioned into disNoint equivalence sets. ll faults in an equivalence set are equivalent

Selecting one fault in eac% equivalence set is called fault collapsing

equivalence set fault equivalent collapsed set

fault collapsing

&%e set of selected faults is kno$n as equivalence collapsed set

 -ircuit must be leveliBed, i.e. t%e level to $%ic% eac% gate is participating must be defined, $%ic% s%ould guarantee t%at every gate inputs are defined before t%e gate output is processed all t%e gates belonging to one layer are processed at a time !quivalence collapsing rules are applied to eac% gate ,oolean gate %as several faults located at its inputs and output
only one of t%e faults determined to be equivalent is kept a fault located at t%e output of t%e gate is kept, if it is determined to be equivalent to faults located at any input of t%e gate

E*uivalence fault collapsing procedure

set of collapsed faults collapse ratio * set of all faults

Fault collapsing example

e)uivalence collapsing layer ': e)uivalence collapsing layer *: e)uivalence collapsing layer +:

sa' sa( a

sa' sa( d e sa' sa( sa' sa( g B % sa' sa(

sa( sa'

sa( sa' c sa' sa( f

sa' sa(

collapse ratio *

+) * ).@@@ +=

Fault dominance
ll tests of F.

F+ s-a-+

F. s-a-+

))+ ++) ))) +)+ +)) )++ )+) ll tests of F+ 0single1 also detects F.

F* dominates F'

(ominance fault collapsing:

if fault F. dominates fault F+, t%en F. can be removed from t%e list in t%e e"ample s%o$n above, F. s-a-+ is removed from t%e output t is sufficient to consider only t%e input faults of ,oolean gates

4f t$o faults dominate eac% ot%er t%en t%ey are equivalent

Fault dominance) analysis of '('D

list of vectors t%at detect

* O++P

list of vectors t%at detect ,) * O++P list of vectors t%at detect G+ * O++P list of vectors t%at detect
+

), ,), G+ are equivalent G) dominates

a b

* O)+P

list of vectors t%at detect ,+ * O+)P

, and ,+

list of vectors t%at detect G) * O)), )+, +)P

sa) sa+ B sa+

Fault dominance collapsing procedure t%e number of single stuck-at faults to be modeled for a ,oolean gate is equal
to nJ+, 4.e. number of inputs plus one t%e algorit%m proceeds from output t%roug% t%e netlist to t%e inputs +. receipt for collapsing t%e faults of a gate by dominance +. remove all faults from output .. for all inputs, keep one type: s-a-+ for '( and ' '(, s-a-) for 6/ and '6/ H. to any one of t%e inputs add one fault of t%e ot%er type 0s-a-) for '(, ' '(, s-a-+ for 6/, '6/1 +. '6&, buffer, $ire: remove output faults, keep bot% fault types on input .. no collapsing is possible for fanout
(ominance fault collapsing in a H-input '( gate

s-a-+ s-a-+

s-a-+ s-a-)

.hec%points
#rimary inputs and fanout branc%es of a combinational circuit are called c%eckpoints -%eckpoint t%eorem: test set t%at detects all single 0multiple1 stuck-at faults on all c%eckpoints of a combinational circuit, also detects all single 0multiple1 stuck-at faults in t%at circuit
a d e b B g

&otal fault sites * > -%eckpoints 0 1 * @

f c

&%us dominance fault collapsing reduces to:

only input faults are kept in t%e case of fanout-free circuit in t%e case of circuit $it% fanout, c%eckpoints are also included furt%er reduction by equivalence collapsing is possible

Dominance fault collapsing example !+# equivalence dominance dominance

collapsing layer +: collapsing layer .: collapsing layer H:

sa' sa( a

sa' sa( d e sa' sa( sa' sa( g B % sa' sa(

sa( sa'

sa( sa' c sa' sa( f

sa' sa(

Dominance fault collapsing example !"# dominance dominance dominance

collapsing layer +: collapsing layer .: collapsing layer H:

sa' sa( a

sa' sa( d e sa' sa( sa' sa( g B % sa' sa(

sa( sa'

sa( sa' c sa' sa( f

sa' sa(

collapse ratio *

> * ).@ +=

/ultiple stuc%&at faults

Multiple stuck-at fault many faults may occur simultaneously in a circuit, t%us multiple combinations of t%e lines being stuck-at logic + or logic ) are possible re usually not considered in practice, because
t%e number of multiple stuck-at faults becomes %uge, even for a reasonably small circuit, and t%us impractical to simulate tests for single stuck-at faults usually cover more t%an >>Q of multiple stuck-at faults

so, $%y bot%er 8

/ultiple stuc%&at faults !"#

;ultiple stuck-at faults may cause problems $%en considered in combination
s-a-+ F. s-a-+ FH

s-a-+ F+

G* ,

R* J,

all ot%er individual single stuck-at faults are detected by vectors )), )+ and +)

redundant faults do not propagate to t%e output vector ++ detects multiple stuck-at faults

multiple stuck-at faults 0F., FH1 and 0F+, F., FH1 are detected by vector ++, $%ic% is not in t%e initial vector list, t%us remain undetected

/ultiple stuc%&at faults !$#

functional masking introduced by multiple stuck-at faults prevents t%e detection of single stuck-at faults
) s-a-+

+ 0)1 +

, + + s-a-)

) 0+1

t%e only test t%at detects - s-a-) is )++ %o$ever, s-a-+ $ill mask it

Transistor&level faults
&%e ;6S transistor is considered to operate as an ideal s$itc%, $%ic% may be perturbed in its correct operation by t$o types of faults:
Stuck-open: one single transistor is permanently stuck in t%e open state, $%ere is can not conduct any current Stuck-s%ort: one single transistor is permanently s%orted irrespective of its gate voltage, and t%us can not be set into a non current-conducting state

&%e detection of a stuck-open fault requires t$o vectors to be applied to t%e circuit &%e detection of a stuck-s%ort fault requires t%e measurement of t%e circuit quiescent current 04DDQ1

Stuc%&open example
Stuck-open: transistor cannot be placed into current conducting state Vector +, time * t: initialiBation vector
V((

Vector . 0test for &H stuck-open1

' '
&: &H G

(
vector . time*tJ+

'
vector + time*t

&.

Two,vector stuc!,open test can e constructed y ordering two stuc!,at tests

&+

Stuc%&short example
Stuck-s%ort: impossible to turn transistor out of current conducting state2 t%us, in some configurations of t%e input, a s%ort is created, $%ic% s%ould not be t%e case in -;6S

Vector +: turn&+ and &. on

V((

'

&:

&H G

4DDQ pat% in faulty circuit

'
vector + time*t

&.

&+

0ridging faults
bridging fault represents a s%ort bet$een a group of signals

4n case a feedback pat% is created by t%e bridging fault, a memory effect may result, i.e. a combinational circuit may be converted into a sequential circuit

;odel of a bridging fault: +-dominant

J, ( ! J-

Redundant fault any fault t%at does not modify t%e input-output function of t%e circuit is called redundant fault Untestable fault a fault for $%ic% no test can be found is called an untestable fault2 redundant faults are untestable faults
, s-a-+ ,

1edundancy and untesta2le faults

/econvergent fanout structure

4dentification and removal of redundant faults is comple"

, , &%e circuit after removing t%e redundant fault

/edundancy is not al$ays undesirable

3ractice 3ro2lems !+#

-ro lem ': 4mplement a full adder using '(, 6/ and '6& gates, and determine t%e total number of 0i1 single stuck-at faults, 0ii1 multiple stuck-at faults. -ro lem *. 9enerate a minimum set of test vectors to detect all single stuck-at faults for an n-bit parity c%ecker implemented as a cascade of 0n-+1 e"clusive-6/ gates. /epeat t%e e"ercise $%ere eac% e"clusive-6/ gate is implemented by elementary logic gates 0 '(, 6/, ' '(, '6/, '6&

3ractice 3ro2lems !"#

-ro lem +. For a .-input -;6S ' '( circuit:
a. Find a t$o-pattern test for eac% single-transistor stuck-open fault. b. /earrange t%e eig%t vectors in a compact set, and s%o$ t%at t%is set can be constructed from t%e single stuck-at faults tests for t%e ' '( gate. c. For eac% stuck-at fault of t%e ' '( gate, find an equivalent transistor 0stuck-open, stuck-s%ort or combination1 fault.

-ro lem .. Find t%e minimum number of test vectors required to test for all single stuck-at faults in t%efollo$ing circuits:
a. .=>-input e"clusive-6/ gate b. ?<-input e"clusive-6/ gate c. +.-input e"clusive-'6/ gate d. ?@-input e"clusive-'6/ gate e. n =-input ' '( gate f. <-input 6/ gate g. full adder implemented using '(, 6/ and '6& gates %. n =-bit parity generator constructed using .-input e"clusive-6/ gates

3ractice 3ro2lems !$#

-ro lem /: Ssing functional fault modelling, determine t%e test sets for t%e follo$ing:
a. b. =-line-to-+-line multiple"er H-to-= decoder

-ro lem 0: -onsider t%e follo$ing circuit.

(etermine t%e fault equivalences among t%e t%ree faults, A s-a-), T sa-), and U s-a-). &%at is, are t%ese t%ree faults equivalent8 4f not, is any pair of t%ese t%ree faults equivalent8 #rove your ans$er.

3ractice 3ro2lems !$#

-ro lem /: Ssing functional fault modelling, determine t%e test sets for t%e follo$ing:
a. b. =-line-to-+-line multiple"er H-to-= decoder

-ro lem 0: -onsider t%e follo$ing circuit.

(etermine t%e fault equivalences among t%e t%ree faults, A s-a-), T sa-), and U s-a-). &%at is, are t%ese t%ree faults equivalent8 4f not, is any pair of t%ese t%ree faults equivalent8 #rove your ans$er.

3ractice 3ro2lems !4#

-ro lem 1: !quivalent fault collapsing %as been applied to t%e follo$ing circuit and collapsed faults are indicated $it% an DME. pply dominance fault collapsing and list t%e faults t%at remainC

3ractice 3ro2lems !5#

-ro lem 2: For t%e circuit belo$: a. F%at is t%e number of all potential fault sites8 b. (erive t%e equivalence collapsed fault list. F%at is t%e collapse ratio8 c. (erive t%e dominance collapsed fault list 0on top of t%e equivalence1. F%at is t%e collapse ratio8

3ractice 3ro2lems !4#

-ro lem /: !quivalent fault collapsing %as been applied to t%e follo$ing circuit and collapsed faults are indicated $it% an DME. pply dominance fault collapsing and list t%e faults t%at remainC

3ractice 3ro2lems !4#

-ro lem /: !quivalent fault collapsing %as been applied to t%e follo$ing circuit and collapsed faults are indicated $it% an DME. pply dominance fault collapsing and list t%e faults t%at remainC

;. 3. ,us%nel and F. (. gra$al, K!ssential of !lectronic &esting for (igital, ;emory, and ;i"ed Signal V3S4 -ircuits,L Springer, .))@

(dditional readings and references