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Code: 9A12301

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(Common to CSS and IT)

B.Tech II Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14 DIGITAL LOGIC DESIGN & COMPUTER ORGANIZATION Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** 1 (a) (b) Explain the operation of a computer. Convert the following numbers with the indicated bases to decimal: (4310)5, (198)12, (16.5)16, (26.24)8. Reduce the given function using Quine McClusky method: Max Marks: 70

F ( A, B, C , D, E , F ) = m(0,1,2,4,6,9,12,16,21,25,29,32,37,41,43,45,56,58,62,63)

3 (a) (b) 4 (a) (b) 5 (a) (b)

Discuss in detail about a demultiplexer with an example. Explain in detail about PAL. What is the use of fast multiplication circuits? Write about array multipliers. Multiply 10111 with 10011 using booths algorithm. How is the memory organized in a computer and how machine instructions coded into are memory words? Explain with the help of a schematic diagram. A memory byte location contains the pattern 10101010. What does this pattern represents when interpreted as a binary number? What does it represent as an ASCII code? What is meant by bit-oring and wide-branch addressing? List the two techniques used for grouping of control signals. With the help of a neat sketch, discuss about the compact disk with laser beam control mechanism. Explain the disadvantage of the magnetic tape for being a sequential access device. What is meant by trace and break point? Where it is used? Write short notes on: (i) Faults. (ii) Traps and aborts.

6 (a) (b) 7 (a) (b) 8 (a) (b)

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Code: 9A12301

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(Common to CSS and IT)

B.Tech II Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14 DIGITAL LOGIC DESIGN & COMPUTER ORGANIZATION Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** 1 With an example explain how division of two fixed point binary numbers when negative numbers are in signed-magnitude representation. Map the following function and simplify using K-map: F = (A+B+C) (A+B+C)(A+B+C)(A+B+C) F = (ABCD+ABCD+ABCD+ABCD+ABCD+ABCD) Implement full adder using decoder and OR gates. Design a serial adder in shift registers. Derive an algorithm in flowchart form for the comparison of two signed binary numbers when negative numbers are in signed-2s complement representation. By means of a subtraction operations with the signed-2s complement numbers. By scanning and comparing pairs of bits from left to right. Explain about I/P configuration of a basic computer. Explain about instruction cycle with the help of the flowchart. Draw the figure of ALU and explain its sequence of operation. Draw the timing diagram for a memory read operation and explain. Draw the block diagram of the cache memory system and explain the section. A block set-associative cache consists of 64 blocks divided into 4 block sets. The main memory contains 4096 blocks, each consists of 128 words of 16 bits length. (i) How many bits are there in main memory? (ii) How many bits are there in each of the TAG, SET and WORD fields? Explain the various features of USB. Write short notes on USB cables. Max Marks: 70

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8 (a) (b)

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Code: 9A12301

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(Common to CSS and IT)

B.Tech II Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14 DIGITAL LOGIC DESIGN & COMPUTER ORGANIZATION Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** 1 (a) (b) What is the gray code? What are the rules to construct gray code? Develop the 4 bit gray code for the decimal 0 to 15. What is the advantage of 2s complement representation in computers? Perform the following operations using 2s complement method: (i) (+35) - (+25). (ii) (-35) + (-25). Differentiate in detail the synchronous and asynchronous sequential circuits. Design the SR flip flop using NAND gates and explain its operation with the help of characteristic table and characteristic equation. Implement the following multiple output combinational logic using a 4 line to 16 line decoder. Y1 = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD Y2 = ABCD + AB CD + ABCD + ABCD Y3 = ABCD + ABCD + ABCD. Explain the terms multiplexing and demultiplexing. Explain arithmetic overflow and divide overflow with some examples for 2s complement numbers. Explain restoring method of division with two 4 bit numbers. List the register reference instructions and describe them. Draw the instruction cycle state diagram and explain. Explain how an encoded and decoded functions are separated in hardware control with a neat diagram. Explain about the control unit organization using microprogrammed architecture. Draw and explain the set associative cache organization. Give the comparison between mapping techniques. Explain in detail PCI commands. Explain the features of SCSI bus. Max Marks: 70

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3 (a)

(b) 4 (a) (b) 5 (a) (b) 6 (a) (b) 7 (a) (b) 8 (a) (b)

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Code: 9A12301

4
(Common to CSS and IT)

B.Tech II Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14 DIGITAL LOGIC DESIGN & COMPUTER ORGANIZATION Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** 1 (a) (b) 2 Write short notes on: (i) Error detecting codes. (ii) Error correcting codes. Give the detailed procedure to detect and correct a single error in a message. Using K-map determine the minimal expression for the following function with MAXTERMS and MINTERMS. F= 3 (a) (b) 4 (a) (b) 5 (a) (b) 6 (a) (b) 7 (a) (b) 8 (a) (b) Max Marks: 70

m (0, 2, 3, 4, 6, 7, 8, 12, 14, 15, 16, 18, 19, 20, 22, 23, 24, 28)

Write a note on PROM, PAL and PLA architecture. Compare static RAM and dynamic RAM. With a clear diagram explain the floating point addition-subtraction unit. Write IEEE standard floating-point formats for 32-bit representation and explain. With the help of neat diagram explain the memory organization indicating the word length and words. Discuss about branch target. Explain how microprocessor governs the sequencing in microprogram. Explain about the vertical and horizontal of a microprogrammed control with an example. Discuss about the most commonly used system organizations for cache memory. How cache read operation is executed? Draw and explain the timing diagram for synchronous input data transfer. Draw and explain the timing for synchronous output data transfer.

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