9S12XDP512DGV2

DOCUMENT NUMBER 9S12XDP512DGV2/D
MC9S12XDP512 Device User Guide V02.06
covers MC9S12XD-Family & MC9S12XA-Family

Original Release Date: June 2nd, 2003 Revised: November 18th January 2005 Motorola, Inc.
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
DOCUMENT NUMBER 9S12XDP512DGV2/D
Revision History
Version Revision Effective Number Date Date Author
V02.00 21 May 2004
Description of Changes 32K SRAM Changed COP Configuration Table 15-1Table 15-2 Added XGATE Address Mapping Figure 1-3 Added Access source signals ACC[2:0] Added reduced Threshold for EWAIT pin Changed Register Map Table 1-1 Updated detailed Register Map Removed ETEA bit from DBGSR Register DIRECT register moved to address $0011 Added Mode description to Section 4.1 Chip Configuration Summary System STOP/WAIT description Updated Detailed Register Map Added Spec Change Summary Updated Spec Change Summary Added Thermal Package Characteristics Table A-5 Updated Appendix B SPI Electrical Specifications Added B.2 External Bus Timing and B.2 External Tag Trigger Timing Added Oscillator and PLL electrical characteristics to Table A-18 and Table A-19 Added Table 0-1 Derivative Differences Corrected VDD35 = 3.15V minimum Added tfws fast wakeup from stop time to Table A-17 Corrected Figure 27-1
V02.01
8 Jun 2004
V02.02
9 Jul 2004 27 Jul 2004
V02.03
V02.04
13 Oct 2004
V02.05
18 Nov 2004

v02.06 18 Jan 2005
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
MC9S12XDP512 Device User Guide 9S12XDP512DGV2/D V02.06
Derivative Differences
Table 0-1 shows the MC9S12XD-Family members Table 0-1 MC9S12XD-Family members1
Device 9S12XDP5124 Package Flash RAM EEPROM XGATE CAN 144LQFP 112LQFP 144LQFP 512K 9S12XDT5125 112LQFP 80QFP 144LQFP 9S12XDT384 112LQFP 384K 80QFP 144LQFP 9S12XDT256 112LQFP 80QFP 144LQFP 9S12XD256 112LQFP 80QFP 9S12XDG128 9S12XD128 9S12XD64 112LQFP 80QFP 112LQFP 80QFP 80QFP 64K 128K 8K 4K 1K 10K 2K 256K 14K 16K yes 20K 4K 20K 32K 5 5 3 3 3 3 3 3 3 3 3 1 1 1 2 2 1 1 1 SCI 6 4 6 4 2 3 3 3 3 3 3 2 2 2 2 2 2 2 2 SPI 3 3 3 3 2 3 3 3 3 3 3 2 2 2 2 2 2 2 2 IIC 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A/D2 2/24 2/16 2/24 2/16 1/8 2/24 2/16 1/8 2/24 2/16 1/8 2/24 2/16 1/8 2/16 1/8 2/16 1/8 1/8 PWM 8 8 8 8 7 8 8 7 8 8 7 8 8 7 8 7 8 7 7 I/O3 119 91 119 91 59 119 91 59 119 91 59 119 91 59 91 59 91 59 59
NOTES: 1. All devices will be available in M, V and C temperature options 2. A/D is the number of modules/total number of A/D channels. 3. I/O is the sum of ports capable to act as digital input or output. 4. PC9S12XDP512MFVE and PC9S12XDP512MPVE samples are available to order. Please contact Local sales office. All other derivate parts and temperature variations will be available following MC Qualification (Q205). 5. PC9S12XDT512MFUE samples are available to order. Please contact Local sales office. All other derivate parts and temperature variations will be available following MC Qualification in (Q205).
Table 0-2 MC9S12XA-Family members

Device
3
Package Flash RAM EEPROM XGATE 144LQFP 112LQFP 512K 80QFP 144LQFP 32K 4K 16K yes
SCI 6 4 2 4 4 2 3 2
SPI 3 3 2 3 3 2 3 2
IIC 2 1 1 1 1 1 1 1
A/D1 2/24 2/16 1/8 2/24 2/16 1/8 2/16 1/8
PWM 8 8 7 8 8 7 8 7
I/O2 119 91 59 119 91 59 91 59
9S12XA512
9S12XA256
112LQFP 256K 80QFP 112LQFP 80QFP
9S12XA1285
128K
10K
2K
NOTES: 1. A/D is the number of modules/total number of A/D channels. 2. I/O is the sum of ports capable to act as digital input or output. 3. MC9S12XA512 samples will be available following MC Qualification (Q205), temperature option C and V 4. MC9S12XA256 samples will be available following MC Qualification (Q205), temperature option C and V 5. MC9S12XA128 samples will be available following MC Qualification (Q205), temperature option C and V
Pin out explanations: 144 Pin Packages Port A = 8, B = 8, C=8, D=8, E = 6 + 2 input only, H = 8, J = 7, K = 8, M = 8, P = 8, S = 8, T = 8, PAD = 24 25 inputs provide Interrupt capability (H =8, P= 8, J = 7, IRQ, XIRQ) Port A = 8, B = 8, E = 6 + 2 input only, H = 8, J = 4, K = 7, M = 8, P = 8, S = 8, T = 8, PAD = 16 22 inputs provide Interrupt capability (H =8, P= 8, J = 4, IRQ, XIRQ) Port A = 8, B = 8, E = 6 + 2 input only, J = 2, M = 6, P = 7, S = 4, T = 8, PAD = 8 11 inputs provide Interrupt capability (P= 7, J = 2, IRQ, XIRQ)
112 Pin Packages
80 Pin Packages
CAN0 can be routed under software control from PM1:0 to pins PM3:2 or PM5:4 or PJ7:6. CAN4 pins are shared between IIC0 pins. CAN4 can be routed under software control from PJ7:6 to pins PM5:4 or PM7:6. Versions with 5 CAN modules will have CAN0, CAN1, CAN2, CAN3 and CAN4 Versions with 4 CAN modules will have CAN0, CAN1, CAN2 and CAN4. Versions with 3 CAN modules will have CAN0, CAN1 and CAN4. Versions with 2 SPI modules will have SPI0 and SPI1. Versions with 3 SCI modules will have SCI0, SCI1 and SCI2. Versions with 4 SCI modules will have SCI0, SCI1, SCI2 and SCI4.
Versions with 1 IIC module will have IIC0. SPI0 can be routed to either Ports PS7:4 or PM5:2. SPI1 pins are shared with PWM3:0; In 144 and 112 pin versions SPI1 can be routed under software control to PH3:0. SPI2 pins are shared with PWM7:4; In 144 and 112 pin versions SPI2 can be routed under software control to PH7:4. In 80 pin packages SS-signal of SPI2 is not bonded out!
Ordering Information
The following figure provides an ordering number example for the MC9S12XD-Family devices.
MC9S12X DP512
C FU
Temperature Options C = -40C to 85C Package Option Temperature Option V = -40C to 105C M = -40C to 125C Device Title Package Options Controller Family FU = 80 QFP PV = 112 LQFP FV = 144 LQFP
Figure 0-1 Order Part Number Example
Document References
The Device Guide provides information about the MC9S12XDP512 device made up of standard HCS12 blocks and the S12X processor core This document is part of the customer documentation. A complete set of device manuals includes all the individual Block Guides of the implemented modules. In an effort to reduce redundancy all module specific information is located only in the respective Block Guide. If applicable, special implementation details of the module are given in the block description sections of this document.See Table 0-3 for names and versions of the referenced documents throughout the Device User Guide. Table 0-3 Document References1
User Guide
S12XCPU Reference Manual External Bus Interface (S12X_EBI) Block Guide Module Mapping Control (S12X_MMC) Block Guide Interrupt (S12X_INT) Block Guide Background Debug (S12X_BDM) Block Guide Debug (S12X_DBG) Block Guide Security (S12X9SEC) Block Guide Clock and Reset Generator (CRG) Block User Guide Enhanced Capture Timer (ECT_16B8C) Block User Guide Analog to Digital Converter 10 Bit 16 Channel (ATD_10B16C) Block UserGuide Analog to Digital Converter 10 Bit 8 Channels (ATD_10B8C) Block User Guide Inter IC Bus (IIC) Block User Guide Asynchronous Serial Interface (SCI) Block User Guide Serial Peripheral Interface (SPI) Block User Guide Pulse Width Modulator 8 Bit 8 Channel (PWM_8B8C) Block User Guide 512 K Byte Flash (FTX512K4) Block User Guide 4K Byte EEPROM (EETX4K) Block User Guide XGATE Block User Guide Motorola Scalable CAN (MSCAN) Block User Guide Voltage Regulator (VREG_3V3) Block User Guide Port Integration Module (PIM_9XD512) Block User Guide Oscillator (OSC_LCP) Block Guide Periodic Interrupt Timer (PIT_24B4C) Block Guide
Version
V01 V02 V02 V01 V02 V02 V02 V06 V02 V04 V03 V02 V05 V04 V01 V02 V02 V02 V03 V05 V02 V01 V01
Document Order Number

S12XCPUV1/D S12XEBIV2/D S12XMMCV2/D S12XINTV1/D S12XBDMV2/D S12XDBGV2/D S12X9SECV2/D S12CRGV6/D S12ECT16B8CV2/D S12ATD10B16CV4/D S12ATD10B8CV3/D S12IICV2/D S12SCIV5/D S12SPIV4/D S12PWM8B8CV1/D S12XFTX512K4V2/D S12XEETX4KV2/D S12XGATEV2/D S12MSCANV3/D S12VREG_3V3V5/D S12XDP512PIMV2/D S12OSCLCPV1/D S12PIT24B4CV1/D
NOTES: 1. Specification changes are shown in bold (Maskset L40V vs L15Y)
Specification Change Summary Maskset L40V vs L15Y

The following section lists all hardware and documentation changes. Hardware changes represent all functional changes on maskset L15Y vs L40V. (i.e. register movements) XSRAM Hardware Changes RAM size increased from 20K to 32K RAM write protection register moved to S12XMMC MC9S12XDP512V2 documentation doesnt include SRAM block guide Documentation Changes
XGATE Hardware Changes XGVBR became a 16-bit register Layout change of XGMCTL register: XGMCTL is now a 16-bit register Added XGFACT bit , when set MCU will never enter System Stop Mode Added mask bits for all control bits XGSS is now readable New instruction: TFR RD,PC Added XGSWEIFM bit to XGMCTL register XGATE Memory map and Software Error conditions described in S12x_mmc
Documentation Changes
S12X_BDM Hardware Changes Debugging XGATE while CPU in STOP/WAIT mode via BDM HW-commands possible Added reserved register at address $7F_FF0A and $7F_FF0B. Modified command delay information for BDM commands
Documentation Change
10
S12X9SEC Hardware Change Internal visibility available in Emulation Modes if MCU is secured but internal Flash and EEPROM accesses are blocked
PIM Hardware Changes Replaced NOACC with ACC[2:0] Added ECLKCTL register at address $001C Added CS3 output
S12X_MMC Hardware Changes Changed DIRECT address from $0012 to $0011 Moved MODE register ($000A) from S12X_EBI Renamed register EIFCTL to MEMCTL0 ($000B). Renamed register MISC to MEMCTL1 ($0013). Reorganization of MEMCTL0 bits to allow integrating new features (from [7:5] to [2:0]). Reorganization of MEMCTL1 bits to EROMON, ROMHM and ROMON only ([2:0]). Added CS3E in MEMCTL0 register (position 3) Added third chip select (CS3), and redefined CS2 XGATE read access to a secured Flash in expanded modes results in XGATE software error EROMON bit in register MMCCTL1 is (write never) instead of write once. Moved write protection features from XSRAM Moved features chip selects and Chip operating mode control from S12X_EBI Moved Modes of Operation description from S12X_EBI. Moved (EIFCTL->MEMCTL0) register ($000B) from S12X_EBI
11
S12X_EBI Hardware Changes Added EBISIZ register for scalable external address bus width (ASIZ[4:0]) and 8-bit data bus option (HDBE) Added EXSTR[2:0] bits to MODE register Added stretch functionality in Special Test Mode Made ECLKX2 available in all modes Added EBICTL register at $000E Moved EIFCTL bits NECLK, EDIVx, EWAITE to PIM Moved EIFCTL register bit EWAITE to EBICTL Moved MODE register bits ITHRS, IVIS to EBICTL Removed internal visibility feature in Special Test Mode (along with IVIS register bit) Moved addresses $000A (EIFCTL->MEMCTL0) and $000B (MODE) to S12X_MMC Block Guide Moved Modes of Operation description to S12X_MMC Moved features chip selects and Chip operating mode control to S12X_MMC Moved feature Free-running clock outputs to PIM
CRG Hardware Changes Added REFDV5 and REFDV4 bits to REFDV register Removed CWAI bit/feature Removed ROAWAI bit/feature Specification of Oscillator configuration via XCLKS pin has changed COP Watchdog Rate CR[2:0] and Mode WCOP specification changed
SPI Hardware Change Modified functionality of data reception
12
VREG3V3 Hardware Changes New API rate low register VREGAPIRL at address $02F5 New API rate high register VREGAPIRH at address $02F4 More precise API divider
DBG Hardware Changes Allows writing COMRV whilst armed Changed DBGCNT reset specification Changed Trace Buffer pointer specification Added Trace Buffer Read Unlock specification Added BRK bit specification Added Detail Mode trace buffer databus entry alignment XGATE Detail Mode trace buffer format changed Changed DBGSR[7] specification Removed ETEA bit. External tags now always end aligned Aligned Detailed Mode Data/Address trace buffer entries Simplified comparator access considerations
13
14
Table of Contents
Section 1 Introduction
1.1 1.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.6 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Device Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 MC9S12XDP512/MC9S12XA512 Local to Global Address Mapping . . . . . . . . . . . .34 Logical Address Maps of S12XD and S12XA Family Devices. . . . . . . . . . . . . . . . . .36 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Section 2 Signal Description

2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 2.3.1 EXTAL, XTAL Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 2.3.2 RESET External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 2.3.3 TEST Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 2.3.4 VREGEN Voltage Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 2.3.5 XFC PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 2.3.6 BKGD / MODC Background Debug and Mode Pin . . . . . . . . . . . . . . . . . . . . . . . .85 2.3.7 PAD[23:08] / AN[23:8] Port AD Input Pin of ATD1 . . . . . . . . . . . . . . . . . . . . . . . .85 2.3.8 PAD[07:00] / AN[7:0] Port AD Input Pins of ATD0 . . . . . . . . . . . . . . . . . . . . . . . .85 2.3.9 PA[7:0] / ADDR[15:8] / IVD[15:8] Port A I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . .85 2.3.10 PB[7:1] / ADDR[7:1] / IVD[7:1] Port B I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . .85 2.3.11 PB0 / ADDR0 / UDS / IVD[0] Port B I/O Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 2.3.12 PC[7:0] / DATA [15:8] Port C I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 2.3.13 PD[7:0] / DATA [7:0] Port D I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 2.3.14 PE7 / ECLKX2 / XCLKS Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 2.3.15 PE6 / MODB / TAGHI Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 2.3.16 PE5 / MODA / TAGLO / RE Port E I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 2.3.17 PE4 / ECLK Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
15
2.3.18 2.3.19 2.3.20 2.3.21 2.3.22 2.3.23 2.3.24 2.3.25 2.3.26 2.3.27 2.3.28 2.3.29 2.3.30 2.3.31 2.3.32 2.3.33 2.3.34 2.3.35 2.3.36 2.3.37 2.3.38 2.3.39 2.3.40 2.3.41 2.3.42 2.3.43 2.3.44 2.3.45 2.3.46 2.3.47 2.3.48 2.3.49 2.3.50 2.3.51 2.3.52 2.3.53
PE3 / LSTRB / LDS / EROMCTL Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . .88 PE2 / R/W / WE Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 PE1 / IRQ Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 PE0 / XIRQ Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 PH7 / KWH7 / SS2 / TXD5 Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 PH6 / KWH6 / SCK2 / RXD5 Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 PH5 / KWH5 / MOSI2 / TXD4 Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . .89 PH4 / KWH4 / MISO2 / RXD4 Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .89 PH3 / KWH3 / SS1 Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 PH2 / KWH2 / SCK1 Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 PH1 / KWH1 / MOSI1 Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 PH0 / KWH0 / MISO1 Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 PJ7 / KWJ7 / TXCAN4 / SCL0 / TXCAN0 PORT J I/O Pin 7 . . . . . . . . . . . . . . . . .90 PJ6 / KWJ6 / RXCAN4 / SDA0 / RXCAN0 PORT J I/O Pin 6 . . . . . . . . . . . . . . . .90 PJ5 / KWJ5 / SCL1 / CS2 PORT J I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 PJ4 / KWJ4 / SDA1 / CS0 PORT J I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 PJ2 / KWJ2 / CS1 PORT J I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 PJ1 / KWJ1 / TXD2 PORT J I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 PJ0 / KWJ0 / RXD2 / CS3 PORT J I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 PK7 / EWAIT / ROMCTL Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 PK[6:4] / ADDR[22:20] / ACC[2:0] Port K I/O Pin [6:4] . . . . . . . . . . . . . . . . . . . . .91 PK[3:0] / ADDR[19:16] / IQSTAT[3:0] Port K I/O Pins [3:0]. . . . . . . . . . . . . . . . . .91 PM7 / TXCAN3 / TXCAN4 / TXD3 Port M I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . .91 PM6 / RXCAN3 / RXCAN4 / RXD3 Port M I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . .92 PM5 / TXCAN0 / TXCAN2 / TXCAN4 / SCK0 Port M I/O Pin 5. . . . . . . . . . . . . . .92 PM4 / RXCAN0 / RXCAN2 / RXCAN4 / MOSI0 Port M I/O Pin 4 . . . . . . . . . . . . .92 PM3 / TXCAN1 / TXCAN0 / SS0 Port M I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . .92 PM2 / RXCAN1 / RXCAN0 / MISO0 Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . .92 PM1 / TXCAN0 Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 PM0 / RXCAN0 Port M I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 PP7 / KWP7 / PWM7 / SCK2 Port P I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . .93 PP6 / KWP6 / PWM6 / SS2 Port P I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 PP5 / KWP5 / PWM5 / MOSI2 Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . .93 PP4 / KWP4 / PWM4 / MISO2 Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . .93 PP3 / KWP3 / PWM3 / SS1 Port P I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 PP2 / KWP2 / PWM2 / SCK1 Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .93
16
2.3.54 PP1 / KWP1 / PWM1 / MOSI1 Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . .93 2.3.55 PP0 / KWP0 / PWM0 / MISO1 Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . .94 2.3.56 PS7 / SS0 Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 2.3.57 PS6 / SCK0 Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 2.3.58 PS5 / MOSI0 Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 2.3.59 PS4 / MISO0 Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 2.3.60 PS3 / TXD1 Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 2.3.61 PS2 / RXD1 Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 2.3.62 PS1 / TXD0 Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 2.3.63 PS0 / RXD0 Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 2.3.64 PT[7:0] / IOC[7:0] Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 2.4.1 VDDX1, VDDX2, VSSX1,VSSX2 Power & Ground Pins for I/O Drivers . . . . . . . .95 2.4.2 VDDR1, VDDR2, VSSR1, VSSR2 Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator95 2.4.3 VDD1, VDD2, VSS1, VSS2 Core Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 2.4.4 VDDA, VSSA Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . . . .95 2.4.5 VRH, VRL ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .96 2.4.6 VDDPLL, VSSPLL Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . . . .96 2.4.7 VREGEN On Chip Voltage Regulator Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Section 3 System Clock Description

3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Section 4 Modes of Operation

4.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 4.2 User Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 4.2.1 Normal Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 4.2.2 Normal Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 4.2.3 Special Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 4.2.4 Emulation of Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 4.2.5 Emulation of Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 4.2.6 Special Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 4.3 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 4.3.1 System Stop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 4.3.2 System Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 4.3.3 Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
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4.4 Freeze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 4.5 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 4.5.1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 4.5.2 ROMON and EROMON Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 4.5.3 Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 4.5.4 Voltage Regulator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 4.6 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Section 5 Resets and Interrupts

5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 5.2.1 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 5.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 5.3.1 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 5.3.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Section 6 S12X_CPU Block Description Section 7 S12X_MMC Block Description Section 8 S12_XEBI Block Description Section 9 S12_XINT Block Description Section 10 S12X_DBG Block Description Section 11 S12X_BDM Block Description Section 12 XGATE Block Description Section 13 Periodic Interrupt Timer (PIT) Block Description Section 14 Oscillator (OSC_LCP) Block Section 15 Clock and Reset Generator (CRG) Block Description Section 16 Enhanced Capture Timer (ECT) Block Description
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Section 17 10 Bit 8 channel Analog to Digital Converter (ATD0) Block Description Section 18 10 Bit 16 Channel Analog to Digital Converter (ATD1) Block Description Section 19 Inter-IC Bus (IIC) Block Description Section 20 Serial Communications Interface (SCI) Block Description Section 21 Serial Peripheral Interface (SPI) Block Description Section 22 Pulse Width Modulator (PWM) Block Description Section 23 Flash EEPROM 512K Block Description Section 24 EEPROM 4K Block Description Section 25 MSCAN Block Description Section 26 Port Integration Module (PIM) Block Description Section 27 Voltage Regulator (VREG_3V3) Block Description
27.1 Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Appendix A Electrical Characteristics

A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .123 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
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A.2.1 A.2.2 A.2.3 A.3 A.3.1 A.3.2 A.4 A.5 A.5.1 A.5.2 A.5.3 A.6
ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 ATD accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 NVM, Flash and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Appendix B Electrical Specifications

B.1 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 B.1.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 B.1.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 B.2 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 B.2.1 Normal Expanded Mode (external wait feature disabled) . . . . . . . . . . . . . . . . . . . .158 B.2.2 Normal Expanded Mode (external wait feature enabled). . . . . . . . . . . . . . . . . . . . .160 B.2.3 Emulation Single-Chip Mode (without wait states). . . . . . . . . . . . . . . . . . . . . . . . . .164 B.2.4 Emulation Expanded Mode (with optional access stretching) . . . . . . . . . . . . . . . . .166 B.3 External Tag Trigger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
Appendix C Package Information

C.1 C.2 C.3 C.4 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 144-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
20
List of Figures
Figure 0-1 Figure 1-1 Figure 1-2 Figure 1-3 Figure 1-4 Figure 1-5 Figure 1-6 Figure 1-7 Figure 1-8 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 2-6 Figure 2-7 Figure 3-1 Figure 27-1 Figure 27-2 Figure 27-3 Figure A-1 Figure A-2 Figure A-3 Figure A-4 Figure B-1 Figure B-2 Figure B-3 Figure B-4 Figure B-5 Figure B-6 Figure B-7 Figure B-8 Figure B-9 Order Part Number Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 MC9S12XDP512 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Local to Global Address Mapping S12X_CPU/S12X_BDM . . . . . . . . . . . . . . . .34 Local to Global Address Mapping XGATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 MC9S12XDP512/MC9S12XDT512/MC9S12XA512 Memory Map . . . . . . . . . . .36 MC9S12XDT384 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 MC9S12XDT256/MC9S12XD256/MC9S12XA256 Memory Map . . . . . . . . . . . .38 MC9S12XD128/MC9S12XDG128/MC9S12XA128 Memory Map . . . . . . . . . . . .39 MC9S12XD64 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 MC9S12XD-Family Pin Assignment 144 LQFP Package . . . . . . . . . . . . . . . . . .77 MC9S12XDP512 Pin assignments 112 LQFP Package . . . . . . . . . . . . . . . . . . .79 MC9S12XDP512 Pin assignments 80 QFP Package . . . . . . . . . . . . . . . . . . . . .80 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Loop Controlled Pierce Oscillator Connections (PE7=1). . . . . . . . . . . . . . . . . . .87 Full Swing Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . .87 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 LQFP144 recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 LQFP112 recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 QFP80 recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 SPI Master Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 SPI Master Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 SPI Slave Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 SPI Slave Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Example 1a: Normal Expanded Mode - Read Followed by Write{statement} . 158 Example 1b: Normal Expanded Mode - Stretched Read Access . . . . . . . . . . 160 Example 1b: Normal Expanded Mode - Stretched Write Access . . . . . . . . . . 161 Example 2a: Emulation Single-Chip Mode - Read Followed by Write. . . . . . . 164 Example 2b: Emulation Expanded Mode - Read with 1 Stretch Cycle . . . . . . 166
21
Figure B-10 Figure B-11 Figure 27-4 Figure C-1 Figure C-2
Example 2b: Emulation Expanded Mode - Write with 1 Stretch Cycle . . . . . . 167 External Trigger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 144-pin LQFP Mechanical Dimensions (case no. 918-03 . . . . . . . . . . . . . . . . .172 112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . 173 80-pin QFP Mechanical Dimensions (case no. 841B) . . . . . . . . . . . . . . . . . . . 174
22
List of Tables
Table 0-1 Table 0-2 Table 0-3 Table 1-1 Table 1-2 Table 2-1 Table 2-2 Table 4-1 Table 4-2 Table 4-3 Table 5-1 Table 15-1 Table 15-2 Table 17-1 Table 18-1 Table 27-1 Table A-1 Table A-2 Table A-3 Table A-4 Table A-5 Table A-6 Table A-7 Table A-8 thresholds Table A-9 Table A-10 Table A-11 Table A-12 Table A-13 Table A-14 Table A-15 Table A-16 MC9S12XD-Family members . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 MC9S12XA-Family members . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Device Register Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 MC9S12XDP512 Power and Ground Connection Summary. . . . . . . . . . . . . . . . .96 Mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Voltage Regulator VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Initial COP Rate Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 Initial WCOP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 ATD0 External Trigger Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 ATD1 External Trigger Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 Recommended decoupling capacitor choice . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 ESD and Latch-Up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .122 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 3.3V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 I/O Characteristics for Port C, D, PE5, PE6 and PK7 for reduced input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 ATD Operating Characteristics 5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 ATD Operating Characteristics 3.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 ATD Conversion Performance 5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 ATD Conversion Performance 3.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
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Table 27-2 Voltage Regulator Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 Table A-17 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 Table A-18 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 Table A-19 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 Table A-20 MSCAN Wake-up Pulse Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 Table B-1 Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 Table B-2 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 Table B-3 SPI Slave Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 Table B-4 Example 1a: Normal Expanded Mode Timing VDD35=5.0V (EWAITE = 0) . . . .159 Table B-5 Example 1a: Normal Expanded Mode Timing VDD35=3.0V (EWAITE = 0) All values: To Be Defined! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 Table B-6 Example 1b: Normal Expanded Mode Timing VDD35=5.0V (EWAITE = 1) . . . .162 Table B-7 Example 1b: Normal Expanded Mode Timing VDD35=3.0V (EWAITE = 1) All values: To Be Defined! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 Table B-8 Example 2a: Emulation Single-Chip Mode Timing VDD35=5.0V (EWAITE = 0) .165 Table B-9 Example 2b: Emulation Expanded Mode Timing VDD35=5.0V (EWAITE = 0) . .168 Table B-10 External Tag Trigger Timing VDD35=5.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
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Section 1 Introduction
1.1 Overview
The MC9S12XD family will retain the low cost, power consumption, EMC and code-size efficiency advantages currently enjoyed by users of Motorola's existing 16-Bit MC9S12 MCU family. Based around an enhanced S12 core, the MC9S12XD-Family will deliver 2 to 5 times the performance of a 25MHz S12 whilst retaining a high degree of pin and code compatibility with the S12. The MC9S12XD-Family introduces the performance boosting XGATE module. Using enhanced DMA functionality, this parallel processing module offloads the CPU by providing high speed data processing and transfer between peripheral modules, RAM and I/O ports. Providing up to 80MIPS of performance additional to the CPU, the XGATE can access all peripherals and the RAM block. The MC9S12XDP512 is composed of standard on-chip peripherals including 512K bytes of Flash EEPROM, 32K bytes of RAM, 4K bytes of EEPROM, six asynchronous serial communications interfaces (SCI), three serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, an 8-channel, 10-bit analog-to-digital converter, a 16-channel, 10-bit analog-to-digital converter, an 8-channel pulse-width modulator (PWM), five CAN 2.0 A, B software compatible modules (MSCAN12), two Inter-IC Bus blocks and a Periodic Interrupt Timer. The MC9S12XDP512 has full 16-bit data paths throughout. The non-multiplexed expanded bus interface available on the 144-Pin versions allows an easy interface to external memories. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. System power consumption can be further improved with the new fast exit from STOP mode feature. In addition to the I/O ports available in each module, up to 25 further I/O ports are available with interrupt capability allowing Wake-Up from STOP or WAIT mode. The MC9S12XDP512 will be available in 144-Pin LQFP with external bus interface and in 112-Pin LQFP or 80-Pin QFP package without external bus interface.
1.2 Features
HCS12X Core 16-bit HCS12X CPU i. Upward compatible with MC9S12 instruction set ii. Interrupt stacking and programmers model identical to MC9S12 iii. Instruction queue iv. Enhanced indexed addressing v. Enhanced instruction set EBI (External Bus Interface)
25
MMC (Module Mapping Control) INT (Interrupt Controller) DBG (Debug module to monitor HCS12X CPU and XGATE bus activity) BDM (Background Debug Mode) Parallel processing module offloads the CPU by providing high speed data processing and transfer Data transfer between Flash EEPROM, RAM, peripheral modules and I/O ports Four timers with independent time-out periods Time-out periods selectable between 1 and 224 bus clock cycles Low noise/low power pierce oscillator PLL COP watchdog Real time interrupt Clock monitor Fast wake-up from Stop Mode Digital filtering Programmable rising or falling edge trigger 512K byte Flash EEPROM 4K byte EEPROM 32K byte RAM 10-bit resolution External conversion trigger capability Five receive and three transmit buffers Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit Four separate interrupt channels for Rx, Tx, error and wake-up Low-pass filter wake-up function
XGATE (Peripheral Co-Processo)
PIT (Periodic Interrupt Timer)
CRG (Clock and Reset Generator)
8-bit ports with interrupt functionality
Memory
One 8-channel and one 16 channel Analog-to-Digital Converter
Five 1M bit per second, CAN 2.0 A, B software compatible modules
26
Loop-back for self test operation 16-bit main counter with 7-bit prescaler 8 programmable input capture or output compare channels Four 8-bit or two 16-bit pulse accumulators Programmable period and duty cycle 8-bit 8-channel or 16-bit 4-channel Separate control for each pulse width and duty cycle Center-aligned or left-aligned outputs Programmable clock select logic with a wide range of frequencies Fast emergency shutdown input Usable as interrupt inputs Six asynchronous Serial Communication Interfaces (SCI) with additional LIN support and selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse width Three Synchronous Serial Peripheral Interfaces (SPI) Compatible with IIC Bus standard Multi-master operation Software programmable for one of 256 different serial clock frequencies Two parallel, linear voltage regulators with bandgap reference Low Voltage detect (LVD) with Low Voltage Interrupt (LVI) Power On Reset (POR) circuit 3.3V - 5.5V operation Low Voltage Reset (LVR) Ultra Low Power Wake-up Timer I/O lines with 5V input and drive capability Input threshold on external bus interface inputs switchable for 3.3V or 5V operation 5V A/D converter inputs Operation at 80MHz equivalent to 40MHz bus speed
ECT (Enhanced Capture Timer)
8 PWM channels
Serial interfaces
IIC (Two Inter-IC Bus modules)
On chip Voltage Regulator
144 Pin LQFP, 112-Pin LQFP package and 80-Pin QFP package
27
Development support Single-wire background debug mode (BDM) 4 on-chip hardware breakpoints
1.3 Modes of Operation

User modes: Normal and Emulation Operating Modes Normal Single-Chip Mode Normal Expanded Mode Emulation of Single Chip Mode Emulation of Expanded Mode Special Single-Chip Mode with active Background Debug Mode Special Test Mode (Motorola use only)
Special Operating Modes
Low power modes: System Stop Modes Pseudo Stop Mod Full Stop Mode
System Wait Mode
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1.4 Block Diagram

Figure 1-1 shows a block diagram of the MC9S12XDP512 device.
29
Figure 1-1 MC9S12XDP512 Block Diagram
30
512K Byte Flash 32K Byte RAM 4K Byte EEPROM

VDDR VSSR VREGEN VDD1,2 VSS1,2 BKGD XFC VDDPLL VSSPLL EXTAL XTAL RESET TEST PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
ATD0
VRH VRL VDDA VSSA PAD00 PAD01 PAD02 PAD03 PAD04 PAD05 PAD06 PAD07
ATD1
VRH VRL VDDA VSSA
VRH VRL VDDA VSSA PAD08 PAD09 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PAD16 PAD17 PAD18 PAD19 PAD20 PAD21 PAD22 PAD23 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM7
Voltage Regulator
Single-wire Background Debug Module Clock and Reset Generation Module
CPU12X
Enhanced Multilevel Interrupt Module Periodic Interrupt COP Watchdog Clock Monitor Breakpoints
PLL
XGATE
Peripheral Co-Processor
DDRAD1 & AD1
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 EWAIT ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 UDS ADDR0 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
CAN2 CAN3 CAN4 SCI2 IIC1 IIC0
SCI3 Non-Multiplexed External Bus Interface (EBI)

VDD1,2 VSS1,2
RXD TXD
Digital Supply 2.5V
PLL Supply 2.5V

VDDPLL VSSPLL
Analog Supply 3-5V

VDDA VSSA
PWM
I/O Supply 3-5V

VDDX1,2 VSSX1,2
Voltage Regulator 3-5V

VDDR1,2 VSSR1,2
SPI1
RXD TXD RXD TXD
SCI4 SCI5
SPI2
SDA SCL SDA SCL PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 MISO MOSI SCK SS MISO MOSI SCK SS
KWJ0 KWJ1 KWJ2 KWJ4 KWJ5 KWJ6 KWJ7 KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7
PTM
CAN1
DDRM
Timer 4 channel 16 bit with Prescaler for internal timebases
CAN0
Module to Port Routing
XIRQ IRQ R/W/WE LSTRB/LDS/EROMCTL ECLK MODA/RE/TAGLO MODB/TAGHI ECLKX2/XCLKS IQSTAT0 IQSTAT1 IQSTAT2 IQSTAT3 8 Bit PPAGE ACC0 Allows 4MByte ACC1 Program space ACC2 ROMCTL/EWAIT
DDRE
PTE
Enhanced Capture Timer
SCI0 SCI1 SPI0

MISO MOSI SCK SS RXCAN TXCAN RXCAN TXCAN RXCAN TXCAN RXCAN TXCAN RXCAN TXCAN RXD TXD
PJ0 CS3 PJ1 PJ2 CS1 PJ4 CS0 PJ5 CS2 PJ6 PJ7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7
DDRP
DDRH
PTH
PTP
Signals shown in Bold-Italics are neither available on the 112 Pin nor on the 80 Pin Package Option Signals shown in Bold are not available on the 80 Pin Package
DDRS DDRJ
PTJ
PTS
AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 RXD TXD RXD TXD
DDRAD0 & AD0
DDRT
PTT
DDRK DDRA DDRB DDRC DDRD
PTK PTA PTB PTC PTD
31
1.5 Device Memory Map

1.5.1 Device Register Memory Map
Table 1-1 shows the device register memory map of the MC9S12XDP512 Table 1-1 Device Register Memory Map
Address
$0000 - $0009
Module
PIM (Port Integration Module)
Size (Bytes)
10 2 2 2 8 2 2 4 16 2 2 12 64 48 8 8 8 8 8 8 8 8 8 8 16 12 4 16 8 8 64
$000A - $000B MMC (Memory Map Control) $000C - $000D PIM (Port Integration Module) $000E - $000F $0010 - $0017 $0018 - $0019 EBI (External Bus Interface) MMC (Memory Map Control) Reserved
$001A - $001B Device ID register $001C - $001F PIM (Port Integration Module) $0020 - $002F $0030 - $0031 $0032 - $0033 $0034 - $003F $0040 - $007F $0080 - $00AF DBG (Debug Module) MMC (Memory Map Control) PIM (Port Integration Module) CRG (Clock and Reset Generator) ECT (Enhanced Capture Timer 16-bit 8 channel)s ATD1 (Analog to Digital Converter 10-bit 16 channel)
$00B0 - $00B7 IIC1 (Inter IC Bus) $00B8 - $00BF SCI2 (Serial Communications Interface) $00C0 - $00C7 SCI3 (Serial Communications Interface) $00C8 - $00CF SCI0 (Serial Communications Interface) $00D0 - $00D7 SCI1 (Serial Communications Interface) $00D8 - $00DF SPI0 (Serial Peripheral Interface) $00E0 - $00E7 IIC0 (Inter IC Bus) $00E8 - $00EF Reserved $00F0 - $00F7 $00F8 - $00FF $0100 - $010F $0110 - $011B SPI1 (Serial Peripheral Interface) SPI2 (Serial Peripheral Interface) Flash Control Register EEPROM Control Register
$011C - $011F MMC (Memory Map Control) $0120 - $012F $0130 - $0137 $0138 - $013F $0140 - $017F INT (Interrupt Module) SCI4 (Serial Communications Interface) SCI5 (Serial Communications Interface) CAN0 (Motorola Scalable Can)
32
Table 1-1 Device Register Memory Map

Address
$0180 - $01BF
Module
CAN1 (Motorola Scalable Can)
Size (Bytes)
64 64 64 64 64 32 16 8 8 40 24 40 24 64 64 1024
$01C0 - $01FF CAN2 (Motorola Scalable Can) $0200 - $023F $0240 - $027F $0280 - $02BF CAN3 (Motorola Scalable Can) PIM (Port Integration Module) CAN4 (Motorola Scalable Can)
$02C0 - $02DF ATD0 (Analog to Digital Converter 10 bit 8 channel $02E0 - $02EF Reserved $02F0 - $02F7 $02F8 - $02FF $0300 - $0327 $0328 - $033F $0340 - $0367 $0368 - $037F $0380 - $03BF Voltage Regulator Reserved Pulse Width Modulator 8 Channels Reserved Periodic Interrupt Timer Reserved XGATE
$03C0 - $03FF Reserved $0400 - $07FF Reserved
Reserved register space shown in Table 1-1 is not allocated to any module. This register space is reserved for future use. Writing to these locations have no effect. Read access to these locations returns zero.
33
1.5.2 MC9S12XDP512/MC9S12XA512 Local to Global Address Mapping

Figure 1-2 Local to Global Address Mapping S12X_CPU/S12X_BDM
$00_0000
$00_0800
2K Registers
$0000 2K Registers $0800 $0C00 $1000 $2000 $13_FC00 8K RAM $14_0000 $4000 Unpaged Flash $8000 PPAGE Flash 16K paged $C000 Unpaged Flash $FFFF Vectors
PPAGE=$FE PPAGE=$FF PPAGE=$E0
$0F_8000 $0F_DFFF $0F_E000 EPAGE RPAGE $0F_FFFF $10_0000 $13_F000
RAM 6*4K paged
EEPROM 1K paged 1K EEPROM RAM 4K paged
8K RAM
EEPROM 3*1K paged 1K EEPROM
$78_0000 PPAGES 29 * 16K
PPAGE=$FD
$7F_4000 $7F_8000 $7F_C000 $7F_FFFF
Unpaged 16K or PPAGE $FD Unpaged 16K or PPAGE $FE Unpaged 16K or PPAGE $FF
34
Figure 1-3 Local to Global Address Mapping XGATE XGATE Device Global Memory Map Local Memory Map $00_0000 2K Registers $00_0800 $00_1000 $0000 2K Registers $0800 RAM $0F_FFFF $10_0000 FLASH $0F_8000
$7FFF $8000
RAM
$78_0800 30KB FLASH $FFFF $78_7FFF $78_8000 Not Used by XGATE $7F_FFFF
35
1.5.3 Logical Address Maps of MC9S12XD and MC9S12XA-Family Devices

Figure 1-4 MC9S12XDP512/MC9S12XDT512/MC9S12XA512 Memory Map
$0000 $0000 $0800 $0C00 $1000 $2000 $07FF $0800 $0FFF $1000 $3FFF $4000 $4000 1K, 2K, 4K or 8K Protected Sector 16K Fixed Flash EEPROM 32K Bytes RAM eight * 4K pages accessible through $1000 - $1FFF 20K Bytes RAM on MC9S12XDT512 ve * 4K pages accessible through $1000 - $1FFF 4K Bytes EEPROM four * 1K pages accessible through $0800 - $0BFF 2K Register Space
$8000
$7FFF $8000 EXT $BFFF $BF00 $BFFF $C000 16K Page Window thirtytwo * 16K Flash EEPROM Pages
BDM visible on PPAGE = $FF (If Active) 16K Fixed Flash EEPROM
$C000
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active, except for specic BDM hardware commands, for details refer to BDM BlockGuide)
36
Figure 1-5 MC9S12XDT384 Memory Map

$0000 $0000 $0800 $0C00 $1000 $2000 $07FF $0800 $0FFF $1000 $3FFF $4000 $4000 1K, 2K, 4K or 8K Protected Sector 16K Fixed Flash EEPROM 20K Bytes RAM ve * 4K pages accessible through $1000 - $1FFF 4K Bytes EEPROM four * 1K pages accessible through $0800 - $0BFF 2K Register Space
$8000
$7FFF $8000 EXT $BFFF $BF00 $BFFF $C000 16K Page Window 24 * 16K Flash EEPROM Pages
$C000
37
Figure 1-6 MC9S12XDT256/MC9S12XD256/MC9S12XA256 Memory Map

$0000 $0000 $0800 $0C00 $1000 $2000 $07FF $0800 $0FFF $1000 $3FFF $4000 $4000 1K, 2K, 4K or 8K Protected Sector 16K Fixed Flash EEPROM 16K Bytes RAM 4 * 4K pages accessible through $1000 - $1FFF 14K Bytes RAM on MC9S12XD256 4K Bytes EEPROM four * 1K pages accessible through $0800 - $0BFF 2K Register Space
$8000
$C000
38
Figure 1-7 MC9S12XD128/MC9S12XDG128/MC9S12XA128 Memory Map

$0000 $0000 $0800 $0C00 $1000 $2000 $07FF $0800 $0FFF $1000 $3FFF $4000 $4000 1K, 2K, 4K or 8K Protected Sector 16K Fixed Flash EEPROM 10K Bytes RAM 8K Bytes RAM on MC9S12XD128 4K Bytes EEPROM four * 1K pages accessible through $0800 - $0BFF 2K Register Space
$8000
$C000
39
Figure 1-8 MC9S12XD64 Memory Map

$0000 $0000 $0800 $0C00 $1000 $2000 $07FF $0800 $0FFF $1000 $3FFF $4000 $4000 1K, 2K, 4K or 8K Protected Sector 16K Fixed Flash EEPROM 4K Bytes RAM one * 4K pages accessible through $1000 - $1FFF 4K Bytes EEPROM four * 1K pages accessible through $0800 - $0BFF 2K Register Space
$8000
$C000
40
1.5.4 Detailed Register Map

The following tables show the detailed register map of the MC9S12XDP512.
$0000 - $0009
Address $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 Name PORTA PORTB DDRA DDRB PORTC PORTD DDRC DDRD PORTE DDRE Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Port Integration Module (PIM) Map 1 of 5

Bit 7 PA 7 PB7 DDRA7 DDRB7 PC7 PD7 DDRC7 DDRD7 PE7 DDRE7 Bit 6 PA6 PB6 DDRA6 DDRB6 PC6 PD6 DDRC6 DDRD6 PE6 DDRE6 Bit 5 PA5 PB5 DDRA5 DDRB5 PC5 PD5 DDRC5 DDRD5 PE5 DDRE5 Bit 4 PA4 PB4 DDRA4 DDRB4 PC4 PD4 DDRC4 DDRD4 PE4 DDRE4 Bit 3 PA3 PB3 DDRA3 DDRB3 PC3 PD3 DDRC3 DDRD3 PE3 DDRE3 Bit 2 PA2 PB2 DDRA2 DDRB2 PC2 PD2 DDRC2 DDRD2 PE2 DDRE2 Bit 1 PA1 PB1 DDRA1 DDRB1 PC1 PD1 DDRC1 DDRD1 PE1 0 Bit 0 PA 0 PB0 DDRA0 DDRB0 PC0 PD0 DDRC0 DDRD0 PE0 0
$000A - $000B
Address $000A $000B Name MMCCTL0 MODE Read: Write: Read: Write:
Module Mapping Control (S12XMMC) Map 1 of 4

Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 0 Bit 3 0 0 Bit 2 CS2E 0 Bit 1 CS1E 0 Bit 0 CS0E 0
MODC
MODB
MODA
$000C - $000D
Address $000C $000D Name PUCR RDRIV

Bit 7 Read: PUPKE Write: Read: RDPK Write: Bit 6 BKPUE 0 Bit 5 0 0 Bit 4 PUPEE RDPE Bit 3 PUPDE RDPD Bit 2 PUPCE RDPC Bit 1 PUPBE RDPB Bit 0 PUPAE RDPA
41
$000E - $000F
Address $000E $000F Name EBICTL0 EBICTL1
External Bus Interface (S12XEBI) Map

Bit 7 Read: ITHRS Write: Read: EWAITE Write: Bit 6 0 0 Bit 5 HDBE 0 Bit 4 ASIZ4 0 Bit 3 ASIZ3 0 Bit 2 ASIZ2 Bit 1 ASIZ1 Bit 0 ASIZ0
EXSTR2 EXSTR1 EXSTR0
$0010 - $0017
Address $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 Name GPAGE DIRECT Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Module Mapping Control (S12XMMC) Map 2 of 4

Bit 7 0 DP15 0 0 0 0 Bit 6 GP6 DP14 0 0 0 0 Bit 5 GP5 DP13 0 0 0 0 Bit 4 GP4 DP12 0 0 0 0 Bit 3 GP3 DP11 0 0 0 0 Bit 2 GP2 DP10 0 Bit 1 GP1 DP9 0 Bit 0 GP0 DP8 0
Reserved
MMCCTL1 Reserved Reserved RPAGE EPAGE
EROMON 0 0
ROMHM 0 0
ROMON 0 0
RP7 EP7
RP6 EP6
RP5 EP5
RP4 EP4
RP3 EP3
RP2 EP2
RP1 EP1
RP0 EP0
$0018 - $001B
Address $0018 $0019 $001A $001B Name Reserved Reserved PARTIDH PARTIDL Read: Write: Read: Write: Read: Write: Read: Write:
Miscellaneous Peripheral
Bit 7 0 0 1 0 Bit 6 0 0 1 0 Bit 5 0 0 0 0 Bit 4 0 0 0 0 Bit 3 0 0 0 0 Bit 2 0 0 1 0 Bit 1 0 0 0 0 Bit 0 0 0 0 0
$001C - $001D
Address $001C $001D Name ECLKCTL Reserved

Bit 7 Read: NECLK Write: Read: 0 Write: Bit 6 NCLKX2 0 Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 EDIV1 0 Bit 0 EDIV0 0
42
$001E - $001F
Address $001E $001F Name IRQCR Reserved Read: Write: Read: Write:

Bit 7 IRQE 0 Bit 6 IRQEN 0 Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 0
$0020 - $0027
Address $0020 $0021 $0022 $0023 $0024 $0025 $0026 $0027 $00281 $00282 $0029 $002A $002B $002C $002D $002E $002F Name DBGC1 DBGSR DBGTCR DBGC2 DBGTBH DBGTBL DBGCNT DBGSCRX DBGXCTL (COMPA/C) DBGXCTL (COMPB/D) DBGXAH DBGXAM DBGXAL DBGXDH DBGXDL DBGXDHM DBGXDLM Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Debug Module (S12XDBG) Map

Bit 7 ARM TBF Bit 6 0 TRIG EXTF Bit 5 XGSBPE 0 TRANGE 0 Bit 13 Bit 5 0 Bit 12 Bit 4 Bit 4 BDM 0 0 Bit 3 Bit 2 Bit 1 Bit 0
DBGBRK SSF2
COMRV SSF1 SSF0
TSOURCE 0 Bit 15 Bit 7 0 0 0 SZE 0 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 0 NDB SZ Bit 22 14 6 14 6 14 6 0 0 Bit 14 Bit 6
TRCMOD CDCM Bit 11 Bit 3 CNT 0 SC3 RW RW 19 11 3 11 3 11 3 SC2 RWE RWE 18 10 2 10 2 10 2 Bit 10 Bit 2
TALIGN ABCM Bit 9 Bit 1 Bit 8 Bit 0
SC1 SRC SRC 17 9 1 9 1 9 1
SC0 COMPE COMPE Bit 16 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0
TAG TAG 21 13 5 13 5 13 5
BRK BRK 20 12 4 12 4 12 4
NOTES: 1. This represents the contents if the Comparator A or C control register is blended into this address 2. This represents the contents if the Comparator B or D control register is blended into this address
43
$0030 - $0031
Address $0030 $0031 Name PPAGE Reserved Read: Write: Read: Write:
Module Mapping Control (S12XMMC) Map 3of 4

Bit 7 PIX7 0 Bit 6 PIX6 0 Bit 5 PIX5 0 Bit 4 PIX4 0 Bit 3 PIX3 0 Bit 2 PIX2 0 Bit 1 PIX1 0 Bit 0 PIX0 0
$0032 - $0033
Address $0032 $0033 Name PORTK DDRK

Bit 7 Read: PK7 Write: Read: DDRK7 Write: Bit 6 PK6 DDRK6 Bit 5 PK5 DDRK5 Bit 4 PK4 DDRK4 Bit 3 PK3 DDRK3 Bit 2 PK2 DDRK2 Bit 1 PK1 DDRK1 Bit 0 PK0 DDRK0
$0034 - $003F
Address $0034 $0035 $0036 $0037 $0038 $0039 $003A $003B $003C $003D $003E $003F Name SYNR REFDV CTFLG CRGFLG CRGINT CLKSEL PLLCTL RTICTL COPCTL FORBYP CTCTL ARMCOP
Clock and Reset Generator (CRG) Map

Bit 7 Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: RTIF Write: Read: RTIE Write: Read: PLLSEL Write: Read: CME Write: Read: RTDEC Write: Read: WCOP Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Bit 7 Bit 6 0 0 0 PORF ILAF PSTP PLLON RTR6 RSBCK 0 0 0 6 Bit 5 SYN5 Bit 4 SYN4 Bit 3 SYN3 Bit 2 SYN2 Bit 1 SYN1 Bit 0 SYN0
REFDV5 REFDV4 REFDV3 REFDV2 REFDV1 REFDV0 0 0 0 Reserved For Factory Test LOCK TRACK LVRF LOCKIF 0 0 LOCKIE 0 0 PLLWAI FSTWKP RTR3 0 0 0 0 0 SCMIF SCMIE RTIWAI PCE RTR1 CR1 0 0 0 1 0 SCM 0 COPWAI SCME RTR0 CR0 0 0 0 Bit 0
AUTO RTR5 0 0 0 0 5
ACQ RTR4 0
PRE RTR2 CR2 0 0 0 2
0 0 Reserved For Factory Test 0 Reserved For Factory Test 0 0 4 3
44
$0040 - $007F
Address $0040 $0041 $0042 $0043 $0044 $0045 $0046 $0047 $0048 $0049 $004A $004B $004C $004D $004E $004F $0050 $0051 $0052 $0053 $0054 $0055 $0056 $0057 $0058 Name TIOS CFORC OC7M OC7D TCNT (hi) TCNT (lo) TSCR1 TTOV TCTL1 TCTL2 TCTL3 TCTL4 TIE TSCR2 TFLG1 TFLG2 TC0 (hi) TC0 (lo) TC1 (hi) TC1 (lo) TC2 (hi) TC2 (lo) TC3 (hi) TC3 (lo) TC4 (hi) Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Enhanced Capture Timer 16 Bit 8 Channels (ECT) Map

Bit 7 IOS7 0 FOC7 OC7M7 OC7D7 Bit 15 Bit 7 TEN TOV7 OM7 OM3 EDG7B EDG3B C7I TOI C7F TOF Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 6 IOS6 0 FOC6 OC7M6 OC7D6 14 6 TSWAI TOV6 OL7 OL3 EDG7A EDG3A C6I 0 C6F 0 14 6 14 6 14 6 14 6 14 Bit 5 IOS5 0 FOC5 OC7M5 OC7D5 13 5 TSFRZ TOV5 OM6 OM2 EDG6B EDG2B C5I 0 C5F 0 13 5 13 5 13 5 13 5 13 Bit 4 IOS4 0 FOC4 OC7M4 OC7D4 12 4 TFFCA TOV4 OL6 OL2 EDG6A EDG2A C4I 0 C4F 0 12 4 12 4 12 4 12 4 12 Bit 3 IOS3 0 FOC3 OC7M3 OC7D3 11 3 PRNT TOV3 OM5 OM1 EDG5B EDG1B C3I TCRE C3F 0 11 3 11 3 11 3 11 3 11 Bit 2 IOS2 0 FOC2 OC7M2 OC7D2 10 2 0 TOV2 OL5 OL1 EDG5A EDG1A C2I PR2 C2F 0 10 2 10 2 10 2 10 2 10 Bit 1 IOS1 0 FOC1 OC7M1 OC7D1 9 1 0 TOV1 OM4 OM0 EDG4B EDG0B C1I PR1 C1F 0 9 1 9 1 9 1 9 1 9 Bit 0 IOS0 0 FOC0 OC7M0 OC7D0 Bit 8 Bit 0 0 TOV0 OL4 OL0 EDG4A EDG0A C0I PR0 C0F 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8
45
$0040 - $007F
Address $0059 $005A $005B $005C $005D $005E $005F $0060 $0061 $0062 $0063 $0064 $0065 $0066 $0067 $0068 $0069 $006A $006B $006C $006D $006E $006F $0070 $0071 Name TC4 (lo) TC5 (hi) TC5 (lo) TC6 (hi) TC6 (lo) TC7 (hi) TC7 (lo) PACTL PAFLG PACN3 (hi) PACN2 (lo) PACN1 (hi) PACN0 (lo) MCCTL MCFLG ICPAR DLYCT ICOVW ICSYS Reserved TIMTST PTPSR PTMCPSR PBCTL PBFLG

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Read: 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI Write: Read: 0 0 0 0 0 0 PAOVF PAIF Write: Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Read: 0 0 MCZI MODMC RDMCL MCEN MCPR1 MCPR0 Write: ICLAT FLMC Read: 0 0 0 POLF3 POLF2 POLF1 POLF0 MCZF Write: Read: 0 0 0 0 PA3EN PA2EN PA1EN PA0EN Write: Read: DLY7 DLY6 DLY5 DLY4 DLY3 DLY2 DLY1 DLY0 Write: Read: NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0 Write: Read: SH37 SH26 SH15 SH04 TFMOD PACMX BUFEN LATQ Write: Read: 0 0 0 0 0 0 0 0 Write: Read: 0 0 0 0 0 0 0 0 Reserved For Factory Test Write: Read: PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 Write: Read: PTMPS7 PTMPS6 PTMPS5 PTMPS4 PTMPS3 PTMPS2 PTMPS1 PTMPS0 Write: Read: 0 0 0 0 0 0 PBEN PBOVI Write: Read: 0 0 0 0 0 0 0 PBOVF Write:
46
$0040 - $007F
Address $0072 $0073 $0074 $0075 $0076 $0077 $0078 $0079 $007A $007B $007C $007D $007E $007F Name PA3H PA2H PA1H PA0H MCCNT (hi) MCCNT (lo) TC0H (hi) TC0H (lo) TC1H (hi) TC1H (lo) TC2H (hi) TC2H (lo) TC3H (hi) TC3H (lo) Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:

Bit 7 PA3H7 PA2H7 PA1H7 PA0H7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 6 PA3H6 PA2H6 PA1H6 PA0H6 14 6 14 6 14 6 14 6 14 6 Bit 5 PA3H5 PA2H5 PA1H5 PA0H5 13 5 13 5 13 5 13 5 13 5 Bit 4 PA3H4 PA2H4 PA1H4 PA0H4 12 4 12 4 12 4 12 4 12 4 Bit 3 PA3H3 PA2H3 PA1H3 PA0H3 11 3 11 3 11 3 11 3 11 3 Bit 2 PA3H2 PA2H2 PA1H2 PA0H2 10 2 10 2 10 2 10 2 10 2 Bit 1 PA3H1 PA2H1 PA1H1 PA0H1 9 1 9 1 9 1 9 1 9 1 Bit 0 PA3H0 PA2H0 PA1H 0 PA0H0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0
$0080 - $00AF
Address $0080 $0081 $0082 $0083 $0084 $0085 $0086 $0087 $0088 Name ATD1CTL0 ATD1CTL1 ATD1CTL2 ATD1CTL3 ATD1CTL4 ATD1CTL5 ATD1STAT0 Reserved ATD1TEST0
Analog to Digital Converter 10-bit 16 Channels (ATD1) Map

Bit 7 Read: 0 Write: Read: ETRIG SEL Write: Read: ADPU Write: Read: 0 Write: Read: SRES8 Write: Read: DJM Write: Read: SCF Write: Read: 0 Write: Read: U Write: Bit 6 0 0 AFFC S8C SMP1 DSGN 0 0 U Bit 5 0 0 AWAI S4C SMP0 SCAN ETORF 0 U Bit 4 0 0 Bit 3 WRAP3 ETRIG CH3 Bit 2 WRAP2 ETRIG CH2 ETRIGE FIFO PRS2 CC CC2 0 Bit 1 WRAP1 ETRIG CH1 ASCIE FRZ1 PRS1 CB CC1 0 U Bit 0 WRAP0 ETRIG CH0 ASCIF FRZ0 PRS0 CA CC0 0 U
ETRIGLE ETRIGP S2C PRS4 MULT FIFOR 0 S1C PRS3 CD CC3 0
U U U Reserved For Factory Test
47

Address $0089 $008A $008B $008C $008D $008E $008F $0090 $0091 $0092 $0093 $0094 $0095 $0096 $0097 $0098 $0099 $009A $009B $009C $009D $009E $009F $00A0 $00A1 $00A2 Name ATD1TEST1 ATD1STAT2 ATD1STAT1 ATD1DIEN0 ATD1DIEN PORTAD0 PORTAD1 ATD1DR0H ATD1DR0L ATD1DR1H ATD1DR1L ATD1DR2H ATD1DR2L ATD1DR3H ATD1DR3L ATD1DR4H ATD1DR4L ATD1DR5H ATD1DR5L ATD1DR6H ATD1DR6L ATD1DR7H ATD1DR7L ATD1DR8H ATD1DR8L ATD1DR9H Bit 7 Read: 0 Write: Read: CCF15 Write: Read: CCF7 Write: Read: IEN15 Write: Read: IEN7 Write: Read: PTAD15 Write: Read: PTAD7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Bit 6 0 CCF14 CCF6 IEN14 IEN6 PTAD14 PTAD6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit 4 Bit 3 Bit 2 0 0 0 Reserved For Factory Test CCF13 CCF12 CCF11 CCF10 CCF5 IEN13 IEN5 PTAD13 PTAD5 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 CCF4 IEN12 IEN4 PTAD12 PTAD4 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 CCF3 IEN11 IEN3 PTAD11 PTAD3 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 CCF2 IEN10 IEN2 PTAD10 PTAD2 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 Bit 5 0 Bit 1 0 CCF9 CCF1 IEN9 IEN1 PTAD9 PTAD1 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 Bit 0 0 CCF8 CCF0 IEN8 IEN0 PTAD8 PTAD0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8
48

Address $00A3 $00A4 $00A5 $00A6 $00A7 $00A8 $00A9 $00AA $00AB $00AC $00AD $00AE $00AF Name ATD1DR9L ATD1DR10H ATD1DR10L ATD1DR11H ATD1DR11L ATD1DR12H ATD1DR12L ATD1DR13H ATD1DR13L ATD1DR14H ATD1DR14L ATD1DR15H ATD1DR15L Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit 6 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 Bit 5 0 13 0 13 0 13 0 13 0 13 0 13 0 Bit 4 0 12 0 12 0 12 0 12 0 12 0 12 0 Bit 3 0 11 0 11 0 11 0 11 0 11 0 11 0 Bit 2 0 10 0 10 0 10 0 10 0 10 0 10 0 Bit 1 0 9 0 9 0 9 0 9 0 9 0 9 0 Bit 0 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0
$00B0 - $00B7
Address $00B0 $00B1 $00B2 $00B3 $00B4 $00B5 $00B6 $00B7 Name IBAD IBFD IBCR IBSR IBDR Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Inter IC Bus (IIC1) Map

Bit 7 ADR7 IBC7 IBEN TCF D7 0 0 0 Bit 6 ADR6 IBC6 IBIE IAAS D6 0 0 0 Bit 5 ADR5 IBC5 MS/SL IBB D5 0 0 0 Bit 4 ADR4 IBC4 TX/RX IBAL D4 0 0 0 Bit 3 ADR3 IBC3 TXAK 0 D3 0 0 0 Bit 2 ADR2 IBC2 0 RSTA SRW D2 0 0 0 Bit 1 ADR1 IBC1 0 IBIF D1 0 0 0 Bit 0 0
IBC0 IBSWAI RXAK D0 0 0 0
49
$00B8 - $00BF
Address $00B8 $00B9 $00BA $00B8 $00B9 $00BA $00BB $00BC $00BD $00BE $00BF Name SCI2BDH1 SCI2BDL1 SCI2CR11 SCI2ASR12 SCI2ACR12 SCI2ACR22 SCI2CR2 SCI2SR1 SCI2SR2 SCI2DRH SCI2DRL
Asynchronous Serial Interface (SCI2) Map

Bit 7 Bit 6 Read: IREN TNP1 Write: Read: SBR7 SBR6 Write: Read: LOOPS SCISWAI Write: Read: RXEDGI 0 F Write: Read: RXEDGI 0 E Write: Read: 0 0 Write: Read: TIE TCIE Write: Read: TDRE TC Write: Read: 0 AMAP Write: Read: R8 T8 Write: Read: R7 R6 Write: T7 T6 Bit 5 TNP0 SBR5 RSRC 0 0 0 RIE RDRF 0 0 R5 T5 Bit 4 SBR12 SBR4 M 0 0 0 ILIE IDLE TXPOL 0 R4 T4 Bit 3 SBR11 SBR3 WAKE 0 0 0 TE OR RXPOL 0 R3 T3 Bit 2 SBR10 SBR2 ILT BERRV 0 Bit 1 SBR9 SBR1 PE BERRIF BERRIE Bit 0 SBR8 SBR0 PT BKDIF BKDIE BKDFE SBK PF RAF 0 R0 T0
BERRM1 BERRM0 RE NF BRK13 0 R2 T2 RWU FE TXDIR 0 R1 T1
NOTES: 1. Those registers are accessible if the AMAP bit in the SCI2SR2 register is set to zero 2. Those registers are accessible if the AMAP bit in the SCI2SR2 register is set to one
$00C0 - $00C7
Address $00C0 $00C1 $00C2 $00C0 $00C1 $00C2 $00C3 $00C4 Name SCI3BDH1 SCI3BDL1 SCI3CR11 SCI3ASR12 SCI3ACR12 SCI3ACR22 SCI3CR2 SCI3SR1

Bit 7 Bit 6 Read: IREN TNP1 Write: Read: SBR7 SBR6 Write: Read: LOOPS SCISWAI Write: Read: RXEDGI 0 F Write: Read: RXEDGI 0 E Write: Read: 0 0 Write: Read: TIE TCIE Write: Read: TDRE TC Write: Bit 5 TNP0 SBR5 RSRC 0 0 0 RIE RDRF Bit 4 SBR12 SBR4 M 0 0 0 ILIE IDLE Bit 3 SBR11 SBR3 WAKE 0 0 0 TE OR Bit 2 SBR10 SBR2 ILT BERRV 0 Bit 1 SBR9 SBR1 PE BERRIF BERRIE Bit 0 SBR8 SBR0 PT BKDIF BKDIE BKDFE SBK PF
BERRM1 BERRM0 RE NF RWU FE
50
$00C0 - $00C7
Address $00C5 $00C6 $00C7 Name SCI3SR2 SCI3DRH SCI3DRL Read: Write: Read: Write: Read: Write:

Bit 7 AMAP R8 R7 T7 Bit 6 0 T8 R6 T6 Bit 5 0 0 R5 T5 Bit 4 TXPOL 0 R4 T4 Bit 3 RXPOL 0 R3 T3 Bit 2 BRK13 0 R2 T2 Bit 1 TXDIR 0 R1 T1 Bit 0 RAF 0 R0 T0
$00C8 - $00CF
Address $00C8 $00C9 $00CA $00C8 $00C9 $00CA $00CB $00CC $00CD $00CE $00CF Name SCI0BDH1 SCI0BDL1 SCI0CR11 SCI0ASR12 SCI0ACR12 SCI0ACR22 SCI0CR2 SCI0SR1 SCI0SR2 SCI0DRH SCI0DRL

$00D0 - $00D7
Address $00D0 $00D1 Name SCI1BDH1 SCI1BDL1 Read: Write: Read: Write:

Bit 7 IREN SBR7 Bit 6 TNP1 SBR6 Bit 5 TNP0 SBR5 Bit 4 SBR12 SBR4 Bit 3 SBR11 SBR3 Bit 2 SBR10 SBR2 Bit 1 SBR9 SBR1 Bit 0 SBR8 SBR0
51
$00D0 - $00D7
Address $00D2 $00D0 $00D1 $00D2 $00D3 $00D4 $00D5 $00D6 $00D7 Name SCI1CR11 SCI1ASR12 SCI1ACR12 SCI1ACR22 SCI1CR2 SCI1SR1 SCI1SR2 SCI1DRH SCI1DRL

Bit 7 Bit 6 Read: LOOPS SCISWAI Write: 0 Read: RXEDGI F Write: 0 Read: RXEDGI E Write: Read: 0 0 Write: Read: TIE TCIE Write: Read: TDRE TC Write: Read: 0 AMAP Write: Read: R8 T8 Write: Read: R7 R6 Write: T7 T6 Bit 5 RSRC 0 0 0 RIE RDRF 0 0 R5 T5 Bit 4 M 0 0 0 ILIE IDLE TXPOL 0 R4 T4 Bit 3 WAKE 0 0 0 TE OR RXPOL 0 R3 T3 Bit 2 ILT BERRV 0 Bit 1 PE BERRIF BERRIE Bit 0 PT BKDIF BKDIE BKDFE SBK PF RAF 0 R0 T0
$00D8 - $00DF
Address $00D8 $00D9 $00DA $00DB $00DC $00DD $00DE $00DF Name SPI0CR1 SPI0CR2 SPI0BR SPI0SR Reserved SPI0DR Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Serial Peripheral Interface (SPI0) Map

Bit 7 SPIE 0 0 SPIF 0 Bit7 0 0 Bit 6 SPE 0 SPPR2 0 0 6 0 0 Bit 5 SPTIE 0 SPPR1 SPTEF 0 5 0 0 Bit 4 MSTR Bit 3 CPOL Bit 2 CPHA 0 SPR2 0 0 2 0 0 Bit 1 SSOE SPISWAI SPR1 0 0 1 0 0 Bit 0 LSBFE SPC0 SPR0 0 0 Bit0 0 0
MODFEN BIDIROE SPPR0 MODF 0 4 0 0 0 0 0 3 0 0
52
$00E0 - $00E7
Address $00E0 $00E1 $00E2 $00E3 $00E4 $00E5 $00E6 $00E7 Name IBAD IBFD IBCR IBSR IBDR Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Inter IC Bus (IIC0) Map

Bit 7 ADR7 IBC7 IBEN TCF D7 0 0 0 Bit 6 ADR6 IBC6 IBIE IAAS D6 0 0 0 Bit 5 ADR5 IBC5 MS/SL IBB D5 0 0 0 Bit 4 ADR4 IBC4 TX/RX IBAL D4 0 0 0 Bit 3 ADR3 IBC3 TXAK 0 D3 0 0 0 Bit 2 ADR2 IBC2 0 RSTA SRW D2 0 0 0 Bit 1 ADR1 IBC1 0 IBIF D1 0 0 0 Bit 0 0
IBC0 IBSWAI RXAK D0 0 0 0
$00E8 - $00EF
Address $00E8 $00E9 $00EA $00EB $00EC $00ED $00EE $00EF Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Reserved
Bit 7 0 0 0 0 0 0 0 0 Bit 6 0 0 0 0 0 0 0 0 Bit 5 0 0 0 0 0 0 0 0 Bit 4 0 0 0 0 0 0 0 0 Bit 3 0 0 0 0 0 0 0 0 Bit 2 0 0 0 0 0 0 0 0 Bit 1 0 0 0 0 0 0 0 0 Bit 0 0 0 0 0 0 0 0 0
$00F0 - $00F7
Address $00F0 $00F1 $00F2 $00F3 Name SPI1CR1 SPI1CR2 SPI1BR SPI1SR Read: Write: Read: Write: Read: Write: Read: Write:

Bit 7 SPIE 0 0 SPIF Bit 6 SPE 0 SPPR2 0 Bit 5 SPTIE 0 SPPR1 SPTEF Bit 4 MSTR Bit 3 CPOL Bit 2 CPHA 0 SPR2 0 Bit 1 SSOE SPISWAI SPR1 0 Bit 0 LSBFE SPC0 SPR0 0
MODFEN BIDIROE SPPR0 MODF 0 0
53
$00F0 - $00F7
Address $00F4 $00F5 $00F6 $00F7 Name Reserved SPI1DR Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write:

Bit 7 0 Bit7 0 0 Bit 6 0 6 0 0 Bit 5 0 5 0 0 Bit 4 0 4 0 0 Bit 3 0 3 0 0 Bit 2 0 2 0 0 Bit 1 0 1 0 0 Bit 0 0 Bit0 0 0
$00F8 - $00FF
Address $00F8 $00F9 $00FA $00FB $00FC $00FD $00FE $00FF Name SPI2CR1 SPI2CR2 SPI2BR SPI2SR Reserved SPI2DR Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:

Bit 7 SPIE 0 0 SPIF 0 Bit7 0 0 Bit 6 SPE 0 SPPR2 0 0 6 0 0 Bit 5 SPTIE 0 SPPR1 SPTEF 0 5 0 0 Bit 4 MSTR Bit 3 CPOL Bit 2 CPHA 0 SPR2 0 0 2 0 0 Bit 1 SSOE SPISWAI SPR1 0 0 1 0 0 Bit 0 LSBFE SPC0 SPR0 0 0 Bit0 0 0
MODFEN BIDIROE SPPR0 MODF 0 4 0 0 0 0 0 3 0 0
$0100 - $010F
Address $0100 $0101 $0102 $0103 $0104 $0105 $0106 $0107 Name FCLKDIV FSEC FTSTMOD FCNFG FPROT FSTAT FCMD FCTL
Flash Control Register (FTX512K4) Map

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Read: FDIVLD PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 Write: Read: KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 Write: Read: 0 0 0 MRDS WRALL Write: Read: 0 0 0 CBEIE CCIE KEYACC Write: Read: RNV6 FPOPEN FPHDIS FPHS1 FPHS0 FPLDIS Write: Read: CCIF 0 BLANK CBEIF PVIOL ACCERR Write: Read: 0 CMDB[6:0] Write: Read: NV7 NV6 NV5 NV4 NV3 NV2 Write: Bit 1 FDIV1 SEC1 0 0 Bit 0 FDIV0 SEC0 0 0
FPLS1 0
FPLS0 0
NV1
NV0
54
$0100 - $010F
Address $0108 $0109 $010A $010B $010C $010D $010E $010F Name FADDRHI FADDRLO FDATAHI FDATALO Reserved Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Flash Control Register (FTX512K4) Map

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 FADDRHI FADDRLO FDATAHI FDATALO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 2 Bit 1 Bit 0
$0110 - $011B
Address $0110 $0111 $0112 $0113 $0114 $0115 $0116 $0117 $0118 $0119 $011A $011B Name ECLKDIV Reserved Reserved ECNFG EPROT ESTAT ECMD Reserved EADDRHI EADDRLO EDATAHI EDATALO
EEPROM Control Register (EETX4K) Map

Bit 7 Bit 6 Read: EDIVLD PRDIV8 Write: Read: 0 0 Write: Read: 0 0 Write: Read: CBEIE CCIE Write: Read: RNV6 EPOPEN Write: Read: CCIF CBEIF Write: Read: 0 Write: Read: 0 0 Write: Read: 0 0 Write: Read: Write: Read: Write: Read: Write: Bit 5 EDIV5 0 0 0 RNV5 Bit 4 EDIV4 0 0 0 RNV4 Bit 3 EDIV3 0 0 0 EPDIS 0 CMDB[6:0] 0 0 0 0 EABLO EDHI EDLO 0 0 0 0 EABHI 0 Bit 2 EDIV2 0 0 0 EPS2 BLANK Bit 1 EDIV1 0 0 0 EPS1 0 Bit 0 EDIV0 0 0 0 EPS0 0
PVIOL
ACCERR
55
$011C - $011F
Address $011C $011D $011E $011F Name RAMWPC RAMXGU RAMSHL RAMSHU Read: Write: Read: Write: Read: Write: Read: Write:
Memory Map Control (S12XMMC) Map 4 of 4

Bit 7 RPWE 1 1 1 Bit 6 0 XGU6 SHL6 SHU6 Bit 5 0 XGU5 SHL5 SHU5 Bit 4 0 XGU4 SHL4 SHU4 Bit 3 0 XGU3 SHL3 SHU3 Bit 2 0 XGU2 SHL2 SHU2 Bit 1 AVIE XGU1 SHL1 SHU1 Bit 0 AVIF XGU0 SHL0 SHU0
$0120 - $012F
Address $0120 $0121 $0122 $0123 $0124 $0125 $0126 $0127 $0128 $0129 $012A $012B $012C $012D $012E $012F Name Reserved IVBR Reserved Reserved Reserved Reserved INT_XGPRIO INT_CFADDR INT_CFDATA0 INT_CFDATA1 INT_CFDATA2 INT_CFDATA3 INT_CFDATA4 INT_CFDATA5 INT_CFDATA6 INT_CFDATA7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Interrupt Module (S12XINT) Map

Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
IVB_ADDR[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
XILVL[2:0] 0 PRIOLVL[2:0] PRIOLVL[2:0] PRIOLVL[2:0] PRIOLVL[2:0] PRIOLVL[2:0] PRIOLVL[2:0] PRIOLVL[2:0] PRIOLVL[2:0] 0
INT_CFADDR[7:4] RQST RQST RQST RQST RQST RQST RQST RQST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
56
$00130 - $0137
Address $0130 $0131 $0132 $0130 $0131 $0132 $0133 $0134 $0135 $0136 $0137 Name SCI4BDH1 SCI4BDL1 SCI4CR11 SCI4ASR12 SCI4ACR12 SCI4ACR22 SCI4CR2 SCI4SR1 SCI4SR2 SCI4DRH SCI4DRL

$0138 - $013F
Address $0138 $0139 $013A $0138 $0139 $013A $013B $013C Name SCI5BDH1 SCI5BDL1 SCI5CR11 SCI5ASR12 SCI5ACR12 SCI5ACR22 SCI5CR2 SCI5SR1

Bit 7 Bit 6 Read: IREN TNP1 Write: Read: SBR7 SBR6 Write: Read: LOOPS SCISWAI Write: Read: RXEDGI 0 F Write: Read: RXEDGI 0 E Write: Read: 0 0 Write: Read: TIE TCIE Write: Read: TDRE TC Write: Bit 5 TNP0 SBR5 RSRC 0 0 0 RIE RDRF Bit 4 SBR12 SBR4 M 0 0 0 ILIE IDLE Bit 3 SBR11 SBR3 WAKE 0 0 0 TE OR Bit 2 SBR10 SBR2 ILT BERRV 0 Bit 1 SBR9 SBR1 PE BERRIF BERRIE Bit 0 SBR8 SBR0 PT BKDIF BKDIE BKDFE SBK PF
BERRM1 BERRM0 RE NF RWU FE
57
$0138 - $013F
Address $013D $013E $013F Name SCI5SR2 SCI5DRH SCI5DRL Read: Write: Read: Write: Read: Write:

Bit 7 AMAP R8 R7 T7 Bit 6 0 T8 R6 T6 Bit 5 0 0 R5 T5 Bit 4 TXPOL 0 R4 T4 Bit 3 RXPOL 0 R3 T3 Bit 2 BRK13 0 R2 T2 Bit 1 TXDIR 0 R1 T1 Bit 0 RAF 0 R0 T0
$0140 - $017F
Address $0140 $0141 $0142 $0143 $0144 $0145 $0146 $0147 $0148 $0149 $014A $014B $014C $014D $014E $014F $0150 $0153 $0154 $0157 Name CAN0CTL0 CAN0CTL1 CAN0BTR0 CAN0BTR1 CAN0RFLG CAN0RIER CAN0TFLG CAN0TIER CAN0TARQ CAN0TAAK CAN0TBSEL CAN0IDAC Reserved CAN0MISC CAN0RXERR CAN0TXERR CAN0IDAR0 CAN0IDAR3 CAN0IDMR0 CAN0IDMR3 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Motorola Scalable CAN - MSCAN (CAN0) Map

Bit 7 RXFRM CANE SJW1 SAMP WUPIF WUPIE 0 0 0 0 0 0 0 0 Bit 6 RXACT CLKSRC SJW0 Bit 5 CSWAI LOOPB BRP5 Bit 4 SYNCH LISTEN BRP4 Bit 3 TIME BORM BRP3 Bit 2 WUPE WUPM BRP2 Bit 1 SLPRQ SLPAK BRP1 Bit 0 INITRQ INITAK BRP0
TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 CSCIF CSCIE 0 0 0 0 0 0 0 0 RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF OVRIE TXE1 TXEIE1 RXF RXFIE TXE0 TXEIE0
RSTATE1 RSTATE0 TSTATE1 TSTATE0 0 0 0 0 0 IDAM1 0 0 0 0 0 0 0 IDAM0 0 0 0 0 0 0 0 0 0 0 TXE2 TXEIE2
ABTRQ2 ABTRQ1 ABTRQ0 ABTAK2 TX2 IDHIT2 0 0 ABTAK1 TX1 IDHIT1 0 0 ABTAK0 TX0 IDHIT0 0 BOHOLD
RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
AC7 AM7
AC6 AM6
AC5 AM5
AC4 AM4
AC3 AM3
AC2 AM2
AC1 AM1
AC0 AM0
58
$0140 - $017F
Address Name CAN0IDAR4 $0158 $015B CAN0IDAR7 $015C - CAN0IDMR4 $015F CAN0IDMR7 $0160 $016F $0170 $017F CAN0RXFG CAN0TXFG Read: Write: Read: Write: Read:

Bit 7 AC7 AM7 Bit 6 AC6 AM6 Bit 5 AC5 AM5 Bit 4 AC4 AM4 Bit 3 AC3 AM3 Bit 2 AC2 AM2 Bit 1 AC1 AM1 Bit 0 AC0 AM0
FOREGROUND RECEIVE BUFFER see Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Write: Read: FOREGROUND TRANSMIT BUFFER see Detailed MSCAN Foreground Receive and Transmit Buffer Layout Write:
Detailed MSCAN Foreground Receive and Transmit Buffer Layout

Address $xxx0 Name Extended ID Standard ID CANxRIDR0 Extended ID Standard ID CANxRIDR1 Extended ID Standard ID CANxRIDR2 Extended ID Standard ID CANxRIDR3 CANxRDSR0 CANxRDSR7 Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Write: Read: CANRxDLR Write: Read: Reserved Write: Read: CANxRTSRH Write: Read: CANxRTSRL Write: Extended ID Read: CANxTIDR0 Write: Standard ID Read: Write: Extended ID Read: CANxTIDR1 Write: Standard ID Read: Write: Extended ID Read: CANxTIDR2 Write: Standard ID Read: Write: Bit 7 ID28 ID10 ID20 ID2 ID14 Bit 6 ID27 ID9 ID19 ID1 ID13 Bit 5 ID26 ID8 ID18 ID0 ID12 Bit 4 ID25 ID7 SRR=1 RTR ID11 Bit 3 ID24 ID6 IDE=1 IDE=0 ID10 Bit 2 ID23 ID5 ID17 Bit 1 ID22 ID4 ID16 Bit 0 ID21 ID3 ID15
$xxx1
ID9
ID8
ID7
$xxx2
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
$xxx3 $xxx4$xxxB $xxxC $xxxD $xxxE $xxxF
DB7
DB6
DB5
DB4
DB3 DLC3
DB2 DLC2
DB1 DLC1
DB0 DLC0
TSR15 TSR7 ID28 ID10 ID20 ID2 ID14
TSR12 TSR4 ID25 ID7 SRR=1 RTR ID11
TSR11 TSR3 ID24 ID6 IDE=1 IDE=0 ID10
TSR10 TSR2 ID23 ID5 ID17
$xx10
$xx10
ID9
ID8
ID7
$xx12
59
Detailed MSCAN Foreground Receive and Transmit Buffer Layout

Address $xx13 $xx14$xx1B $xx1C $xx1D $xx1E $xx1F Name Extended ID CANxTIDR3 Standard ID CANxTDSR0 CANxTDSR7 CANxTDLR CANxTTBPR CANxTTSRH CANxTTSRL Bit 7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: ID6 Bit 6 ID5 Bit 5 ID4 Bit 4 ID3 Bit 3 ID2 Bit 2 ID1 Bit 1 ID0 Bit 0 RTR
DB7
DB6
DB5
DB4
DB3 DLC3
DB2 DLC2 PRIO2 TSR10 TSR2
PRIO7 TSR15 TSR7
PRIO6 TSR14 TSR6
PRIO5 TSR13 TSR5
PRIO4 TSR12 TSR4
PRIO3 TSR11 TSR3
$0180 - $01BF
Address $0180 $0181 $0182 $0183 $0184 $0185 $0186 $0187 $0188 $0189 $018A $018B $018C $018D $018E Name

Bit 2 WUPE WUPM BRP2 Bit 1 SLPRQ SLPAK BRP1 Bit 0 INITRQ INITAK BRP0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Read: RXACT SYNCH RXFRM CSWAI TIME CAN1CTL0 Write: Read: CANE CLKSRC LOOPB LISTEN BORM CAN1CTL1 Write: Read: SJW1 SJW0 BRP5 BRP4 BRP3 CAN1BTR0 Write: Read: SAMP TSEG22 TSEG21 TSEG20 TSEG13 CAN1BTR1 Write: Read: RSTAT1 RSTAT0 TSTAT1 WUPIF CSCIF CAN1RFLG Write: Read: WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 CAN1RIER Write: Read: 0 0 0 0 0 CAN1TFLG Write: Read: 0 0 0 0 0 CAN1TIER Write: Read: 0 0 0 0 0 CAN1TARQ Write: Read: 0 0 0 0 0 CAN1TAAK Write: Read: 0 0 0 0 0 CAN1TBSEL Write: Read: 0 0 0 IDAM1 IDAM0 CAN1IDAC Write: Read: 0 0 0 0 0 Reserved Write: Read: 0 0 0 0 0 CAN1MISC Write: Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 CAN1RXERR Write:
TSEG12 TSEG11 TSEG10 TSTAT0 TSTATE0 TXE2 TXEIE2 OVRIF OVRIE TXE1 TXEIE1 RXF RXFIE TXE0 TXEIE0
RXERR2 RXERR1 RXERR0
60
$0180 - $01BF
Address $018F $0190 $0191 $0192 $0193 $0194 $0195 $0196 $0197 $0198 $0199 $019A $019B $019C $019D $019E $019F $01A0 $01AF $01B0 $01BF Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 CAN1TXERR Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR0 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR1 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR2 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR3 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR0 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR1 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR2 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR3 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR4 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR5 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR6 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN1IDAR7 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR4 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR5 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR6 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN1IDMR7 Write: FOREGROUND RECEIVE BUFFER see Detailed MSCAN Foreground Receive Read: and Transmit Buffer Layout CAN1RXFG Write: Read: FOREGROUND TRANSMIT BUFFER see Detailed MSCAN Foreground Receive CAN1TXFG and Transmit Buffer Layout Write:
$01C0 - $01FF
Address $01C0 $01C1 $01C2 Name CAN2CTL0 CAN2CTL1 CAN2BTR0

Bit 7 Bit 6 Read: RXACT RXFRM Write: Read: CANE CLKSRC Write: Read: SJW1 SJW0 Write: Bit 5 CSWAI LOOPB BRP5 Bit 4 SYNCH LISTEN BRP4 Bit 3 TIME BORM BRP3 Bit 2 WUPE WUPM BRP2 Bit 1 SLPRQ SLPAK BRP1 Bit 0 INITRQ INITAK BRP0
61
$01C0 - $01FF
Address $01C3 $01C4 $01C5 $01C6 $01C7 $01C8 $01C9 $01CA $01CB $01CC $01CD $01CE $01CF $01D0 $01D1 $01D2 $01D3 $01D4 $01D5 $01D6 $01D7 $01D8 $01D9 $01DA $01DB Name

Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Read: SAMP TSEG22 TSEG21 TSEG20 TSEG13 CAN2BTR1 Write: Read: RSTAT1 RSTAT0 TSTAT1 WUPIF CSCIF CAN2RFLG Write: Read: WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 CAN2RIER Write: Read: 0 0 0 0 0 CAN2TFLG Write: Read: 0 0 0 0 0 CAN2TIER Write: Read: 0 0 0 0 0 CAN2TARQ Write: Read: 0 0 0 0 0 CAN2TAAK Write: Read: 0 0 0 0 0 CAN2TBSEL Write: Read: 0 0 0 IDAM1 IDAM0 CAN2IDAC Write: Read: 0 0 0 0 0 Reserved Write: Read: 0 0 0 0 0 CAN2MISC Write: Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 CAN2RXERR Write: Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 CAN2TXERR Write: Read: AC7 AC6 AC5 AC4 AC3 CAN2IDAR0 Write: Read: AC7 AC6 AC5 AC4 AC3 CAN2IDAR1 Write: Read: AC7 AC6 AC5 AC4 AC3 CAN2IDAR2 Write: Read: AC7 AC6 AC5 AC4 AC3 CAN2IDAR3 Write: Read: AM7 AM6 AM5 AM4 AM3 CAN2IDMR0 Write: Read: AM7 AM6 AM5 AM4 AM3 CAN2IDMR1 Write: Read: AM7 AM6 AM5 AM4 AM3 CAN2IDMR2 Write: Read: AM7 AM6 AM5 AM4 AM3 CAN2IDMR3 Write: Read: AC7 AC6 AC5 AC4 AC3 CAN2IDAR4 Write: Read: AC7 AC6 AC5 AC4 AC3 CAN2IDAR5 Write: Read: AC7 AC6 AC5 AC4 AC3 CAN2IDAR6 Write: Read: AC7 AC6 AC5 AC4 AC3 CAN2IDAR7 Write:
TSEG12 TSEG11 TSEG10 TSTAT0 TSTATE0 TXE2 TXEIE2 OVRIF OVRIE TXE1 TXEIE1 RXF RXFIE TXE0 TXEIE0
RXERR2 RXERR1 RXERR0 TXERR2 TXERR1 TXERR0 AC2 AC2 AC2 AC2 AM2 AM2 AM2 AM2 AC2 AC2 AC2 AC2 AC1 AC1 AC1 AC1 AM1 AM1 AM1 AM1 AC1 AC1 AC1 AC1 AC0 AC0 AC0 AC0 AM0 AM0 AM0 AM0 AC0 AC0 AC0 AC0
62
$01C0 - $01FF
Address $01DC $01DD $01DE $01DF $01E0 $01EF $01F0 $01FF Name CAN2IDMR4 CAN2IDMR5 CAN2IDMR6 CAN2IDMR7 CAN2RXFG CAN2TXFG Read: Write: Read: Write: Read: Write: Read: Write: Read:

Bit 7 AM7 AM7 AM7 AM7 Bit 6 AM6 AM6 AM6 AM6 Bit 5 AM5 AM5 AM5 AM5 Bit 4 AM4 AM4 AM4 AM4 Bit 3 AM3 AM3 AM3 AM3 Bit 2 AM2 AM2 AM2 AM2 Bit 1 AM1 AM1 AM1 AM1 Bit 0 AM0 AM0 AM0 AM0
$0200 - $023F
Address $0200 $0201 $0202 $0203 $0204 $0205 $0206 $0207 $0208 $0209 $020A $020B $020C $020D $020E $020F Name Read: CAN3CTL0 Write: Read: CAN3CTL1 Write: Read: CAN3BTR0 Write: Read: CAN3BTR1 Write: Read: CAN3RFLG Write: Read: CAN3RIER Write: Read: CAN3TFLG Write: Read: CAN3TIER Write: Read: CAN3TARQ Write: Read: CAN3TAAK Write: Read: CAN3TBSEL Write: Read: CAN3IDAC Write: Read: Reserved Write: Read: Reserved Write: Read: CAN3RXERR Write: Read: CAN3TXERR Write:
Motorola Scalable CAN - MSCAN (CAN3)

Bit 7 RXFRM CANE SJW1 SAMP WUPIF WUPIE 0 0 0 0 0 0 0 0 Bit 6 RXACT CLKSRC SJW0 Bit 5 CSWAI LOOPB BRP5 Bit 4 SYNCH LISTEN BRP4 Bit 3 TIME BORM BRP3 Bit 2 WUPE WUPM BRP2 Bit 1 SLPRQ SLPAK BRP1 Bit 0 INITRQ INITAK BRP0
TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 CSCIF CSCIE 0 0 0 0 0 0 0 0 RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF OVRIE TXE1 TXEIE1 RXF RXFIE TXE0 TXEIE0
RSTATE1 RSTATE0 TSTATE1 TSTATE0 0 0 0 0 0 IDAM1 0 0 0 0 0 0 0 IDAM0 0 0 0 0 0 0 0 0 0 0 TXE2 TXEIE2
RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
63
$0200 - $023F
Address $0210 $0211 $0212 $0213 $0214 $0215 $0216 $0217 $0218 $0219 $021A $021B $021C $021D $021E $021F $0220 $022F $0230 $023F Name CAN3IDAR0 CAN3IDAR1 CAN3IDAR2 CAN3IDAR3 CAN3IDMR0 CAN3IDMR1 CAN3IDMR2 CAN3IDMR3 CAN3IDAR4 CAN3IDAR5 CAN3IDAR6 CAN3IDAR7 CAN3IDMR4 CAN3IDMR5 CAN3IDMR6 CAN3IDMR7 CAN3RXFG CAN3TXFG Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read:
Motorola Scalable CAN - MSCAN (CAN3)

Bit 7 AC7 AC7 AC7 AC7 AM7 AM7 AM7 AM7 AC7 AC7 AC7 AC7 AM7 AM7 AM7 AM7 Bit 6 AC6 AC6 AC6 AC6 AM6 AM6 AM6 AM6 AC6 AC6 AC6 AC6 AM6 AM6 AM6 AM6 Bit 5 AC5 AC5 AC5 AC5 AM5 AM5 AM5 AM5 AC5 AC5 AC5 AC5 AM5 AM5 AM5 AM5 Bit 4 AC4 AC4 AC4 AC4 AM4 AM4 AM4 AM4 AC4 AC4 AC4 AC4 AM4 AM4 AM4 AM4 Bit 3 AC3 AC3 AC3 AC3 AM3 AM3 AM3 AM3 AC3 AC3 AC3 AC3 AM3 AM3 AM3 AM3 Bit 2 AC2 AC2 AC2 AC2 AM2 AM2 AM2 AM2 AC2 AC2 AC2 AC2 AM2 AM2 AM2 AM2 Bit 1 AC1 AC1 AC1 AC1 AM1 AM1 AM1 AM1 AC1 AC1 AC1 AC1 AM1 AM1 AM1 AM1 Bit 0 AC0 AC0 AC0 AC0 AM0 AM0 AM0 AM0 AC0 AC0 AC0 AC0 AM0 AM0 AM0 AM0
$0240 - $027F
Address $0240 $0241 $0242 $0243 Name PTT PTIT DDRT RDRT
Port Integration Module PIM_9DX (PIM) Map

Bit 7 Read: PTT7 Write: Read: PTIT7 Write: Read: DDRT7 Write: Read: RDRT7 Write: Bit 6 PTT6 PTIT6 DDRT7 RDRT6 Bit 5 PTT5 PTIT5 DDRT5 RDRT5 Bit 4 PTT4 PTIT4 DDRT4 RDRT4 Bit 3 PTT3 PTIT3 DDRT3 RDRT3 Bit 2 PTT2 PTIT2 DDRT2 RDRT2 Bit 1 PTT1 PTIT1 DDRT1 RDRT1 Bit 0 PTT0 PTIT0 DDRT0 RDRT0
64
$0240 - $027F
Address $0244 $0245 $0246 $0247 $0248 $0249 $024A $024B $024C $024D $024E $024F $0250 $0251 $0252 $0253 $0254 $0255 $0256 $0257 $0258 $0259 $025A $025B $025C Name PERT PPST Reserved Reserved PTS PTIS DDRS RDRS PERS PPSS WOMS Reserved PTM PTIM DDRM RDRM PERM PPSM WOMM MODRR PTP PTIP DDRP RDRP PERP Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:

Bit 7 PERT7 PPST7 0 0 PTS7 PTIS7 DDRS7 RDRS7 PERS7 PPSS7 WOMS7 0 PTM7 PTIM7 DDRM7 RDRM7 PERM7 PPSM7 Bit 6 PERT6 PPST6 0 0 PTS6 PTIS6 DDRS7 RDRS6 PERS6 PPSS6 WOMS6 0 PTM6 PTIM6 DDRM7 RDRM6 PERM6 PPSM6 Bit 5 PERT5 PPST5 0 0 PTS5 PTIS5 DDRS5 RDRS5 PERS5 PPSS5 WOMS5 0 PTM5 PTIM5 DDRM5 RDRM5 PERM5 PPSM5 Bit 4 PERT4 PPST4 0 0 PTS4 PTIS4 DDRS4 RDRS4 PERS4 PPSS4 WOMS4 0 PTM4 PTIM4 DDRM4 RDRM4 PERM4 PPSM4 Bit 3 PERT3 PPST3 0 0 PTS3 PTIS3 DDRS3 RDRS3 PERS3 PPSS3 WOMS3 0 PTM3 PTIM3 DDRM3 RDRM3 PERM3 PPSM3 Bit 2 PERT2 PPST2 0 0 PTS2 PTIS2 DDRS2 RDRS2 PERS2 PPSS2 WOMS2 0 PTM2 PTIM2 DDRM2 RDRM2 PERM2 PPSM2 Bit 1 PERT1 PPST1 0 0 PTS1 PTIS1 DDRS1 RDRS1 PERS1 PPSS1 WOMS1 0 PTM1 PTIM1 DDRM1 RDRM1 PERM1 PPSM1 Bit 0 PERT0 PPST0 0 0 PTS0 PTIS0 DDRS0 RDRS0 PERS0 PPSS0 WOMS0 0 PTM0 PTIM0 DDRM0 RDRM0 PERM0 PPSM0
WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0 0 PTP7 PTIP7 DDRP7 RDRP7 PERP7 MODRR6 MODRR5 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0 PTP6 PTIP6 DDRP7 RDRP6 PERP6 PTP5 PTIP5 DDRP5 RDRP5 PERP5 PTP4 PTIP4 DDRP4 RDRP4 PERP4 PTP3 PTIP3 DDRP3 RDRP3 PERP3 PTP2 PTIP2 DDRP2 RDRP2 PERP2 PTP1 PTIP1 DDRP1 RDRP1 PERP1 PTP0 PTIP0 DDRP0 RDRP0 PERP0
65
$0240 - $027F
Address $025D $025E $025F $0260 $0261 $0262 $0263 $0264 $0265 $0266 $0267 $0268 $0269 $026A $026B $026C $026D $026E $026f $0270 $0271 $0272 $0273 $0274 $0275 Name PPSP PIEP PIFP PTH PTIH DDRH RDRH PERH PPSH PIEH PIFH PTJ PTIJ DDRJ RDRJ PERJ PPSJ PIEJ PIEJ Reserved PT1AD0 Reserved DDR1AD0 Reserved RDR1AD0 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:

Bit 7 PPSP7 PIEP7 PIFP7 PTH7 PTIH7 DDRH7 RDRH7 PERH7 PPSH7 PIEH7 PIFH7 PTJ7 PTIJ7 DDRJ7 RDRJ7 PERJ7 PPSJ7 PIEJ7 PIFJ7 0 Bit 6 PPSP6 PIEP6 PIFP6 PTH6 PTIH6 DDRH7 RDRH6 PERH6 PPSH6 PIEH6 PIFH6 PTJ6 PTIJ6 DDRJ7 RDRJ6 PERJ6 PPSJ6 PIEJ6 PIFJ6 0 Bit 5 PPSP5 PIEP5 PIFP5 PTH5 PTIH5 DDRH5 RDRH5 PERH5 PPSH5 PIEH5 PIFH5 PTJ5 PTIJ5 DDRJ5 RDRJ5 PERJ5 PPSJ5 PIEJ5 PIFJ5 0 Bit 4 PPSP4 PIEP4 PIFP4 PTH4 PTIH4 DDRH4 RDRH4 PERH4 PPSH4 PIEH4 PIFH4 PTJ4 PTIJ4 DDRJ4 RDRJ4 PERJ4 PPSJ4 PIEJ4 PIFJ4 0 Bit 3 PPSP3 PIEP3 PIFP3 PTH3 PTIH3 DDRH3 RDRH3 PERH3 PPSH3 PIEH3 PIFH3 0 0 0 0 0 0 0 0 0 Bit 2 PPSP2 PIEP2 PIFP2 PTH2 PTIH2 DDRH2 RDRH2 PERH2 PPSH2 PIEH2 PIFH2 PTJ2 PTIJ2 DDRJ2 RDRJ2 PERJ2 PPSJ2 PIEJ2 PIFJ2 0 Bit 1 PPSP1 PIEP1 PIFP1 PTH1 PTIH1 DDRH1 RDRH1 PERH1 PPSH1 PIEH1 PIFH1 PTJ1 PTIJ1 DDRJ1 RDRJ1 PERJ1 PPSJ1 PIEJ1 PIFJ1 0 Bit 0 PPSS0 PIEP0 PIFP0 PTH0 PTIH0 DDRH0 RDRH0 PERH0 PPSH0 PIEH0 PIFH0 PTJ0 PTIJ0 DDRJ0 RDRJ0 PERJ0 PPSJ0 PIEJ0 PIFJ0 0
PT1AD07 PT1AD06 PT1AD05 PT1AD04 PT1AD03 PT1AD02 PT1AD01 PT1AD00 0 DDR1 AD07 0 RDR1 AD07 0 DDR1 AD06 0 RDR1 AD06 0 DDR1 AD05 0 RDR1 AD05 0 DDR1 AD04 0 RDR1 AD04 0 DDR1 AD03 0 RDR1 AD03 0 DDR1 AD02 0 RDR1 AD02 0 DDR1 AD01 0 RDR1 AD01 0 DDR1 AD01 0 RDR1 AD00
66
$0240 - $027F
Address $0276 $0277 $0278 $0279 $027A Name Reserved PER1AD0 PT0AD1 PT1AD1 DDR0AD1

Bit 7 Bit 6 Read: 0 0 Write: Read: PER1AD PER1AD 07 06 Write: Read: PT0AD1 PT0AD1 23 22 Write: Read: PT1AD1 PT1AD1 15 14 Write: Read: DDR0 DDR0 AD1 AD1 Write: 23 22 Read: DDR1 DDR1 AD1 AD1 Write: 15 14 Read: RDR0 RDR0 AD1 AD1 Write: 23 22 Read: RDR1AD RDR1AD 1 1 Write: 14 15 Read: PER0 PER0 AD1 AD1 Write: 23 22 Read: PER1 PER1 AD1 AD1 Write: 15 14 Bit 5 0 PER1AD 05 PT0AD1 21 PT1AD1 13 DDR0 AD1 21 DDR1 AD1 13 RDR0 AD1 21 RDR1AD 1 13 PER0 AD1 21 PER1 AD1 13 Bit 4 0 PER1AD 04 PT0AD1 20 PT1AD1 12 DDR0 AD1 20 DDR1 AD1 12 RDR0 AD1 20 RDR1AD 1 12 PER0 AD1 20 PER1 AD1 12 Bit 3 0 PER1AD 03 PT0AD1 19 PT1AD1 11 DDR0 AD1 19 DDR1 AD1 11 RDR0 AD1 19 RDR1AD 1 11 PER0 AD1 19 PER1 AD1 11 Bit 2 0 PER1AD 02 PT0AD1 18 PT1AD1 10 DDR0 AD1 18 DDR1 AD1 10 RDR0 AD1 18 RDR1AD 1 10 PER0 AD1 18 PER1 A1D 10 Bit 1 0 PER1AD 01 PT0AD1 17 PT1AD1 9 DDR0 AD1 17 DDR1 AD1 9 RDR0 AD1 17 RDR1AD 1 9 PER0 AD1 17 PER1 AD1 9 Bit 0 0 PER1AD 00 PT0AD1 16 PT1AD1 8 DDR0 AD1 16 DDR1 AD1 8 RDR0 AD1 16 RDR1AD 1 8 PER0 AD1 16 PER1 AD1 8
$027B
DDR1AD1
$027C
RDR0AD1
$027D
RDR1AD1
$027E
PER0AD1
$027F
PER1AD1
$0280 - $02BF
Address $0280 $0281 $0282 $0283 $0284 $0285 $0286 $0287 $0288 $0289 Name CAN4CTL0 CAN4CTL1 CAN4BTR0 CAN4BTR1 CAN4RFLG CAN4RIER CAN4TFLG CAN4TIER CAN4TARQ CAN4TAAK

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: RXACT SYNCH RXFRM CSWAI TIME WUPE SLPRQ INITRQ Write: Read: SLPAK INITAK CANE CLKSRC LOOPB LISTEN BORM WUPM Write: Read: SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Write: Read: SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 Write: Read: RSTAT1 RSTAT0 TSTAT1 TSTAT0 WUPIF CSCIF OVRIF RXF Write: Read: WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE Write: Read: 0 0 0 0 0 TXE2 TXE1 TXE0 Write: Read: 0 0 0 0 0 TXEIE2 TXEIE1 TXEIE0 Write: Read: 0 0 0 0 0 ABTRQ2 ABTRQ1 ABTRQ0 Write: Read: 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 Write:
67
$0280 - $02BF
Address $028A $028B $028C $028D $028E $028F $0290 $0291 $0292 $0293 $0294 $0295 $0296 $0297 $0298 $0299 $029A $029B $029C $029D $029E $029F $02A0 $02AF $02B0 $02BF Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: 0 0 0 0 0 TX2 TX1 TX0 CAN4TBSEL Write: Read: 0 0 0 IDHIT2 IDHIT1 IDHIT0 IDAM1 IDAM0 CAN4IDAC Write: Read: 0 0 0 0 0 0 0 0 Reserved Write: Read: 0 0 0 0 0 0 0 BOHOLD CAN4MISC Write: Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 CAN4RXERR Write: Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 CAN4TXERR Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN4IDAR0 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN4IDAR1 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN4IDAR2 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN4IDAR3 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN4IDMR0 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN4IDMR1 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN4IDMR2 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN4IDMR3 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN4IDAR4 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN4IDAR5 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN4IDAR6 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 CAN4IDAR7 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN4IDMR4 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN4IDMR5 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN4IDMR6 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 CAN4IDMR7 Write: FOREGROUND RECEIVE BUFFER see Detailed MSCAN Foreground Receive Read: and Transmit Buffer Layout CAN4RXFG Write: Read: FOREGROUND TRANSMIT BUFFER see Detailed MSCAN Foreground Receive CAN4TXFG and Transmit Buffer Layout Write:
68
$02C0 - $02DF
Address $02C0 $02C1 $02C2 $02C3 $02C4 $02C5 $02C6 $02C7 $02C8 $02C9 $02CA $02CB $02CC $02CD $02CE $02CF $02D0 $02D1 $02D2 $02D3 $02D4 $02D5 $02D6 $02D7 $02D8 Name ATD0CTL0 ATD0CTL1 ATD0CTL2 ATD0CTL3 ATD0CTL4 ATD0CTL5 ATD0STAT0 Reserved ATD0TEST0 ATD0TEST1 Reserved ATD0STAT1 Reserved ATD0DIEN Reserved PORTAD0 ATD0DR0H ATD0DR0L ATD0DR1H ATD0DR1L ATD0DR2H ATD0DR2L ATD0DR3H ATD0DR3L ATD0DR4H
Analog to Digital Converter 10 Bit 8 Channel (ATD0) Map

Bit 7 Read: 0 Write: Read: ETRIG SEL Write: Read: ADPU Write: Read: 0 Write: Read: SRES8 Write: Read: DJM Write: Read: SCF Write: Read: U Write: Read: U Write: Read: U Write: Read: 0 Write: Read: CCF7 Write: Read: 0 Write: Read: IEN7 Write: Read: 0 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Bit 6 0 0 AFFC S8C SMP1 DSGN 0 U U U 0 CCF6 0 IEN6 0 6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit 5 0 0 AWAI S4C SMP0 SCAN ETORF U U 0 0 CCF5 0 IEN5 0 5 13 0 13 0 13 0 13 0 13 Bit 4 0 0 Bit 3 0 0 Bit 2 WRAP2 ETRIG CH2 ETRIGE FIFO PRS2 CC CC2 U U 0 0 CCF2 0 IEN2 0 2 10 0 10 0 10 0 10 0 10 Bit 1 WRAP1 ETRIG CH1 ASCIE FRZ1 PRS1 CB CC1 U U 0 0 CCF1 0 IEN1 0 1 9 0 9 0 9 0 9 0 9 Bit 0 WRAP0 ETRIG CH0 ASCIF FRZ0 PRS0 CA CC0 U U SC 0 CCF0 0 IEN0 0 BIT 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8
ETRIGLE ETRIGP S2C PRS4 MULT FIFOR U U 0 0 CCF4 0 IEN4 0 4 12 0 12 0 12 0 12 0 12 S1C PRS3 0 0 U U 0 0 CCF3 0 IEN3 0 3 11 0 11 0 11 0 11 0 11
69
$02C0 - $02DF
Address $02D9 $02DA $02DB $02DC $02DD $02DE $02DF Name ATD0DR4L ATD0DR5H ATD0DR5L ATD0DR6H ATD0DR6L ATD0DR7H ATD0DR7L
Analog to Digital Converter 10 Bit 8 Channel (ATD0) Map

Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit 6 Bit6 14 Bit6 14 Bit6 14 Bit6 Bit 5 0 13 0 13 0 13 0 Bit 4 0 12 0 12 0 12 0 Bit 3 0 11 0 11 0 11 0 Bit 2 0 10 0 10 0 10 0 Bit 1 0 9 0 9 0 9 0 Bit 0 0 Bit8 0 Bit8 0 Bit8 0
$02E0 - $02EF
Address $02E0 - $02EF Name Reserved Read: Write:
Reserved
$02F0 - $02F7
Address $02F0 $02F1 $02F2 $02F3 $02F4 $02F5 $02F6 $02F7 Name
Voltage Regulator (VREG_3V3) Map

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Read: VREGHTCL Write: Read: 0 VREGCTRL Write: Read: VREGAPICL APICLK Write: Read: VREGAPITR APITR5 Write: Read: 0 VREGAPIRH Write: Read: VREGAPIRL APIR7 Write: Read: 0 Reserved Write: Read 0 Reserved Write:
Reserved for Factory Test 0 0 APITR4 0 APIR6 0 0 0 0 APITR3 0 APIR5 0 0 0 0 APITR2 0 APIR4 0 0 0 0 APITR1 APIR11 APIR3 0 0 LVDS APIFE APITR0 APIR10 APIR2 0 0 LVIE APIE 0 APIR9 APIR1 0 0 LVIF APIF 0 APIR8 APIR0 0 0
$02F8 - $02FF
Address $02F8 - $02FF Name Reserved Read: Write:
Reserved
70
$0300 - $0327
Address $0300 $0301 $0302 $0303 $0304 $0305 $0306 $0307 $0308 $0309 $030A $030B $030C $030D $030E $030F $0310 $0311 $0312 $0313 $0314 $0315 $0316 $0317 $0318 Name
Pulse Width Modulator 8 Bit 8 Channel (PWM) Map

Bit 6 PWME6 PPOL6 PCLK6 PCKB2 CAE6 CON45 0 0 6 6 0 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 6 6 6 6 Bit 5 PWME5 PPOL5 PCLK5 PCKB1 CAE5 CON23 0 0 5 5 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 5 5 5 5 Bit 4 PWME4 PPOL4 PCLK4 PCKB0 CAE4 CON01 0 0 4 4 0 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 4 4 4 4 Bit 3 PWME3 PPOL3 PCLK3 0 CAE3 PSWAI 0 0 3 3 0 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 3 3 3 3 Bit 2 PWME2 PPOL2 PCLK2 PCKA2 CAE2 PFRZ 0 0 2 2 0 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 2 2 2 2 Bit 1 PWME1 PPOL1 PCLK1 PCKA1 CAE1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 Bit 0 PWME0 PPOL0 PCLK0 PCKA0 CAE0 0 0 0 Bit 0 Bit 0 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0
Bit 7 Read: PWME7 PWME Write: Read: PPOL7 PWMPOL Write: Read: PCLK7 PWMCLK Write: Read: 0 PWMPRCLK Write: Read: CAE7 PWMCAE Write: Read: CON67 PWMCTL Write: PWMTST Read: 0 Test Only Write: Read: 0 PWMPRSC Write: Read: Bit 7 PWMSCLA Write: Read: Bit 7 PWMSCLB Write: Read: 0 PWMSCNTA Write: Read: 0 PWMSCNTB Write: Read: Bit 7 PWMCNT0 Write: 0 Read: Bit 7 PWMCNT1 Write: 0 Read: Bit 7 PWMCNT2 Write: 0 Read: Bit 7 PWMCNT3 Write: 0 Read: Bit 7 PWMCNT4 Write: 0 Read: Bit 7 PWMCNT5 Write: 0 Read: Bit 7 PWMCNT6 Write: 0 Read: Bit 7 PWMCNT7 Write: 0 Read: Bit 7 PWMPER0 Write: Read: Bit 7 PWMPER1 Write: Read: Bit 7 PWMPER2 Write: Read: Bit 7 PWMPER3 Write: Read: Bit 7 PWMPER4 Write:
71
$0300 - $0327
Address $0319 $031A $031B $031C $031D $031E $031F $0320 $0321 $0322 $0323 $0324 $0325 $0326 $0327 Name PWMPER5 PWMPER6 PWMPER7 PWMDTY0 PWMDTY1 PWMDTY2 PWMDTY3 PWMDTY4 PWMDTY5 PWMDTY6 PWMDTY7 PWMSDN Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Pulse Width Modulator 8 Bit 8 Channel (PWM) Map

Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 PWMIF 0 0 0 Bit 6 6 6 6 6 6 6 6 6 6 6 6 PWMIE 0 0 0 Bit 5 5 5 5 5 5 5 5 5 5 5 5 0 PWM RSTRT 0 0 0 Bit 4 4 4 4 4 4 4 4 4 4 4 4 PWMLVL 0 0 0 0 0 0 0 0 0 Bit 3 3 3 3 3 3 3 3 3 3 3 3 0 Bit 2 2 2 2 2 2 2 2 2 2 2 2 PWM7IN Bit 1 1 1 1 1 1 1 1 1 1 1 1 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0
PWM7IN PWM7E L NA 0 0 0 0 0 0
$0328 - $033F
Address $0328 - $033F Name Reserved Read: Write: Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
$0340 - $0367
Address $0340 $0341 $0342 $0343 Name PITCFLMT PITFLT PITCE PITMUX Read: Write: Read: Write: Read: Write: Read: Write:
Periodic Interrupt Timer (PIT) Map

Bit 7 PITE 0 0 0 Bit 6 PITSWAI 0 0 0 Bit 5 PITFRZ 0 0 0 Bit 4 0 0 0 0 Bit 3 0 0 PFLT3 PCE3 PMUX3 Bit 2 0 0 PFLT2 PCE2 PMUX2 Bit 1 0 PFLMT1 0 PFLT1 PCE1 PMUX1 Bit 0 0 PFLMT0 0 PFLT0 PCE0 PMUX0
72
$0340 - $0367
Address $0344 $0345 $0346 $0347 $0348 $0349 $034A $034B $034C $034D $034E $034F $0350 $0351 $0352 $0353 $0354 $0355 $0356 $0357 $0358 $0367 Name PITINTE PITTF PITMTLD0 PITMTLD1 PITLD0 (hi) PITLD0 (lo) PITCNT0 (hi) PITCNT0 (lo) PITLD1 (hi) PITLD1 (lo) PITCNT1 (hi) PITCNT1 (lo) PITLD2 (hi) PITLD2 (lo) PITCNT2 (hi) PITCNT2 (lo) PITLD3 (hi) PITLD3 (lo) PITCNT3 (hi) PITCNT3 (lo) Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Periodic Interrupt Timer (PIT) Map

Bit 7 0 0 Bit 6 0 0 Bit 5 0 0 Bit 4 Bit 3 PINTE3 0 PTF3 Bit 2 PINTE2 PTF2 Bit 1 PINTE1 PTF1 Bit 0 PINTE0 PTF0
PMTLD7 PMTLD6 PMTLD5 PMTLD4 PMTLD3 PMTLD2 PMTLD1 PMTLD0 PMTLD7 PMTLD6 PMTLD5 PMTLD4 PMTLD3 PMTLD2 PMTLD1 PMTLD0 PLD15 PLD7 PLD14 PLD6 PLD13 PLD5 PLD12 PLD4 PLD11 PLD3 PLD10 PLD2 PLD9 PLD1 PCNT9 PCNT1 PLD9 PLD1 PCNT9 PCNT1 PLD9 PLD1 PCNT9 PCNT1 PLD9 PLD1 PCNT9 PCNT1 0 PLD8 PLD0 PCNT8 PCNT0 PLD8 PLD0 PCNT8 PCNT0 PLD8 PLD0 PCNT8 PCNT0 PLD8 PLD0 PCNT8 PCNT0 0
PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT7 PLD15 PLD7 PCNT6 PLD14 PLD6 PCNT5 PLD13 PLD5 PCNT4 PLD12 PLD4 PCNT3 PLD11 PLD3 PCNT2 PLD10 PLD2
PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT7 0 PCNT6 0 PCNT5 0 PCNT4 0 PCNT3 0 PCNT2 0
$0368 - $037F
Address $0368 - $037F Name Reserved Read: Write:
Reserved
73
$0380 - $03BF
Address $0380 $0381 $0382 $0383 $0384 $0385 $0386 $0387 $0388 $0389 $038A $023B $023C $038D $038E $038F $0390 $0391 $0392 $0393 $0394 $0395 $0396 Name Read: XGMCTL Reserved XGCHID Reserved XGVBR XGVBR XGVBR XGVBR XGIF XGIF XGIF XGIF XGIF XGIF XGIF XGIF XGIF XGIF XGIF XGIF XGIF XGIF XGIF Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
XGATE Map
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 XGFACT M XGFACT XGCHID[6:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 2 0 Bit 1 0 Bit 0 XGIEM 0 XGSWEI F XGIE
XGEM
XGE 0 0 0 0
XGFRZM XGDBGM
XGFRZ XGDBG
XGSSM
XGSS
XGVBR[19:16]
XGVBR[15:8] XGVBR[7:1] 0 0 0 0 0 0 0 0 XGIF_78
XGIF_77 XGIF_76 XGIF_75 XGIF_74 XGIF_73 XGIF_72 XGIF_71 XGIF_70 XGIF_6F XGIF_6E XGIF_6D XGIF_6C XGIF_6B XGIF_6A XGIF_69 XGIF_68 XGIF_67 XGIF_66 XGIF_65 XGIF_64 XGIF_63 XGIF_62 XGIF_61 XGIF_60 XGIF_5F XGIF_5E XGIF_5D XGIF_5C XGIF_5B XGIF_5A XGIF_59 XGIF_58 XGIF_57 XGIF_56 XGIF_55 XGIF_54 XGIF_53 XGIF_52 XGIF_51 XGIF_50 XGIF_4F XGIF_4E XGIF_4D XGIF_4C XGIF_4B XGIF_4A XGIF_49 XGIF_48 XGIF_47 XGIF_46 XGIF_45 XGIF_44 XGIF_43 XGIF_42 XGIF_41 XGIF_40 XGIF_3F XGIF_3E XGIF_3D XGIF_3C XGIF_3B XGIF_3A XGIF_39 XGIF_38 XGIF_37 XGIF_36 XGIF_35 XGIF_34 XGIF_33 XGIF_32 XGIF_31 XGIF_30 XGIF_2F XGIF_2E XGIF_2D XGIF_2C XGIF_2B XGIF_2A XGIF_29 XGIF_28 XGIF_27 XGIF_26 XGIF_25 XGIF_24 XGIF_23 XGIF_22 XGIF_21 XGIF_20 XGIF_1F XGIF_1E XGIF_1D XGIF_1C XGIF_1B XGIF_1A XGIF_19 XGIF_18 XGIF_17 XGIF_16 XGIF_15 XGIF_14 XGIF_13 XGIF_12 XGIF_11 XGIF_10 XGIF_0F XGIF_0E XGIF_0D XGIF_0C XGIF_0B XGIF_0A XGIF_09 0
74
$0380 - $03BF
Address $0397 $0398 $0399 $039A $039B $039C $039D $039E $039F $03A0 $03A1 $03A2 $03A3 $03A4 $03A5 $03A6 $03A7 $03A8 $03A9 $03AA $03AB $03AC $03AD Name XGIF XGSWT (hi) XGSWT (lo) XGSEM (hi) XGSEM (lo) Reserved XGCCR XGPC (hi) XGPC (lo) Reserved Reserved XGR1 (hi) XGR1 (lo) XGR2 (hi) XGR2 (lo) XGR3 (hi) XGR3 (lo) XGR4 (hi) XGR4 (lo) XGR5 (hi) XGR5( lo) XGR6 (hi) XGR6 ( lo) Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
XGATE Map
Bit 7 0 0 Bit 6 0 0 Bit 5 0 0 Bit 4 0 Bit 3 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 0
0 0 XGSWTM[7:0] XGSWT[7:0]
0 0 XGSEMM[7:0] XGSEM[7:0]
0 0
0 0
0 0
0 0
XGN
XGZ
XGV
XGC
XGPC[15:8] XGPC[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
XGR1[15:8] XGR1[7:0] XGR2[15:8] XGR2[7:0] XGR3[15:8] XGR3[7:0] XGR4[15:8] XGR4[7:0] XGR5[15:8] XGR5[7:0] XGR6[15:8] XGR6[7:0]
75
$0380 - $03BF
Address $03AE $03AF $03B0 $03BF Name XGR7 (hi) XGR7 (lo) Reserved Read: Write: Read: Write: Read: Write:
XGATE Map
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
XGR7[15:8] XGR7[7:0] 0 0 0 0 0 0 0 0
$03C0 - $07FF
Address $03C0 - $07FF Name Reserved Read: Write:
Reserved
1.6 Part ID Assignments

The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B). The read-only value is a unique part ID for each revision of the chip. Table 1-2 shows the assigned part ID number and Mask Set number. Table 1-2 Assigned Part ID Numbers
Device MC9S12XDP512 MC9S12XDP512 Mask Set Number L40V L15Y Part ID1 $C400 $C410
NOTES: 1. The coding is as follows: Bit 15-12: Major family identifier Bit 11-8: Minor family identifier Bit 7-4: Major mask set revision number including FAB transfers Bit 3-0: Minor - non full - mask set revision
76
Section 2 Signal Description

This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. It is built from the signal description sections of the Block User Guides of the individual IP blocks on the device.
2.1 Device Pinout

The XD-Family of devices offers pin-compatible packaged devices to assist with system development and accommodate expansion of the application. The MC9S12XD-Family and MC9S12XA-Family devices are offered in the following package options: 144-pin LQFP package with an external bus interface (address/data bus) 112-pin LQFP without external bus interface 80-pin QFP without external bus interface
Most pins perform two or more functions, as described in more detail in Section 2.2 Signal Properties Summary. Figure 2-1, Figure 2-2 and Figure 2-3 show the pin assignments for the various packages.
Figure 2-1 MC9S12XD-Family Pin Assignment 144 LQFP Package
77
SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 CS1/KWJ2/PJ2 ACC2/ADDR22/PK6 IQSTAT3/ADDR19/PK3 IQSTAT2/ADDR18/PK2 IQSTAT1/ADDR17/PK1 IQSTAT0/ADDR16/PK0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 ACC1/ADDR21/PK5 ACC0/ADDR20/PK4 TXD2/KWJ1/PJ1 CS3/RXD2/KWJ0/PJ0 MODC/BKGD VDDX2 VSSX2 DATA8/PC0 DATA9/PC1 DATA10/PC2 DATA11/PC3 UDS/ADDR0/PB0 ADDR1/PB1 ADDR2/PB2 ADDR3/PB3 ADDR4/PB4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
PP4/KWP4/PWM4/MISO2 PP5/KPW5/PWM5/MOSI2 PP6/KWP6/PWM6/SS2 PP7/KWP7/PWM7/SCK2 PK7/ROMCTL/EWAIT VDDX1 VSSX1 PM0/RXCAN0 PM1/TXCAN0 PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ4/KWJ4/SDA1/CS0 PJ5/KWJ5/SCL1/CS2 PJ6/KWJ6/RXCAN4/SDA0/RXCAN0 PJ7/KWJ7/TXCAN4/SCL0/TXCAN0 VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 PM6/RXCAN3/RXCAN4/RXD3 PM7/TXCAN3/TXCAN4/TXD3 PAD23/AN23 PAD22/AN22 PAD21/AN21 PAD20/AN20 PAD19/AN19 PAD18/AN18 VSSA VRL
MC9S12XD-Family 144 LQFP
Pins shown in BOLD-ITALICS neither available on the 112 LQFP nor on the 80 QFP Package Option
Pins shown in BOLD are not available on the 80 QFP package
VRH VDDA PAD17/AN17 PAD16/AN16 PAD15/AN15 PAD07/AN07 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/AN00 VSS2 VDD2 PD7/DATA7 PD6/DATA6 PD5/DATA5 PD4/DATA4 VDDR2 VSSR2 PA7/ADDR15 PA6/ADDR14 PA5/ADDR13 PA4/ADDR12 PA3/ADDR11 PA2/ADDR10 PA1/ADDR9 PA0/ADDR8
78
ADDR5/PB5 ADDR6/PB6 ADDR7/PB7 DATA12/PC4 DATA13/PC5 DATA14/PC6 DATA15/PC7 TXD5/SS2/KWH7/PH7 RXD5/SCK2/KWH6/PH6 TXD4/MOSI2/KWH5/PH5 RXD4/MISO2/KWH4/PH4 XCLKS/ECLKX2/PE7 TAGHI/MODB/PE6 RE/TAGLO/MODA/PE5 ECLK/PE4 VSSR1 VDDR1 RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST SS1/KWH3/PH3 SCK1/KWH2/PH2 MOSI1/KWH1/PH1 MISO1/KWH0/PH0 PD0/DATA0 PD1/DATA1 PD2/DATA2 PD3/DATA3 LDS/LSTRB/PE3/EROMCTL WE/R/W/PE2 IRQ/PE1 XIRQ/PE0
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PB5 PB6 PB7 TXD5/SS2/KWH7/PH7 RXD5/SCK2/KWH6/PH6 TXD4/MOSI2/KWH5/PH5 RXD4/MISO2/KWH4/PH4 XCLKS/PE7 MODB/PE6 MODA/PE5 ECLK/PE4 VSSR1 VDDR1 RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST SS1/KWH3/PH3 SCK1/KWH2/PH2 MOSI1/KWH1/PH1 MISO1/KWH0/PH0 PE3 PE2 IRQ/PE1 XIRQ/PE0
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 PK3 PK2 PK1 PK0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 PK5 PK4 TXD2/KWJ1/PJ1 CS3/RXD2/KWJ0/PJ0 MODC/BKGD PB0 PB1 PB2 PB3 PB4
Figure 2-2 MC9S12XD-Family Pin assignments 112 LQFP Package
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
MC9S12XD-Family 112LQFP
Pins shown in BOLD are not available on the 80 QFP package
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
PP4/KWP4/PWM4/MISO2 PP5/KPW5/PWM5/MOSI2 PP6/KWP6/PWM6/SS2 PP7/KWP7/PWM7/SCK2 PK7/ROMCTL VDDX VSSX PM0/RXCAN0 PM1/TXCAN0 PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ6/KWJ6/RXCAN4/SDA0/RXCAN0 PJ7/KWJ7/TXCAN4/SCL0/TXCAN0 VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 PM6/RXCAN3/RXCAN4/RXD3 PM7/TXCAN3/TXCAN4/TXD3 VSSA VRL
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
VRH VDDA PAD15/AN15 PAD07/AN07 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/AN00 VSS2 VDD2 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
79
Figure 2-3 MC9S12XD-Family Pin assignments 80 QFP Package

PP4/KWP4/PWM4/MISO2 PP5/KWP5/PWM5/MOSI2 PP7/KWP7/PWM7/SCK2 VDDX VSSX PM0/RXCAN0/RXB PM1/TXCAN0/TXB PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ6/KWJ6/RXCAN4/SDA0/RXCAN0 PJ7/KWJ7/TXCAN4/SCL0/TXCAN0 VREGEN PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VRL 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/BKGD PB0 PB1 PB2 PB3 PB4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
MC9S12XD-Family 80 QFP
VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
80
PB5 PB6 PB7 XCLKS/PE7 MODB/PE6 MODA/PE5 ECLK/PE4 VSSR1 VDDR1 RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST PE3 PE2 IRQ/PE1 XIRQ/PE0
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
2.2 Signal Properties Summary

Table 2-1 summarizes the pin functionality. Table 2-1 Signal Properties Summary
Internal Pull Resistor
CTRL Reset State NA NA PULLUP RESET PIN PUCR NA Always on PER0 AD1/ PER1 AD1 PER1 AD0 PUCR PUCR PUCR PUCR PUCR PUCR DOWN Up NA Up
Pin Name Pin Name Pin Name Pin Name Pin Name Power Funct. 1 Funct. 2 Funct. 3 Funct. 4 Funct. 5 Supply
EXTAL XTAL RESET TEST VREGEN XFC BKGD MODC VDDPLL VDDPLL VDDR N.A. VDDX VDDPLL VDDR
Description
NA NA
Oscillator Pins External Reset Test Input Voltage Regulator Enable Input PLL Loop Filter Background Debug Port AD Inputs of ATD1, Analog Inputs of ATD1 Port AD Inputs of ATD0, Analog Inputs of ATD0 Port A I/O, Address Bus, Internal Visibility Data Port B I/O, Address Bus, Internal Visibility Data Port B I/O, Address Bus, Upper Data Strobe Port C I/O, Data Bus Port D I/O, Data Bus Port E I/O, System clock output, Clock Select Port E I/O, Tag High, Mode Input
PAD[23:08]
AN[23:8]
VDDA
Disabled
PAD[07:00] PA[7:0] PB[7:1] PB0 PC[7:0] PD[7:0] PE7
AN[7:0] ADDR[15:8] ADDR[7:1] ADDR0 DATA[15:8] DATA[7:0] ECLKX2
IVD[15:8] IVD[7:0] UDS XCLKS
VDDA VDDR VDDR VDDR
Disabled Disabled Disabled Disabled Disabled Disabled Up
VDDR VDDR VDDR
PE6
TAGHI
MODB
VDDR
While RESET pin is low: Down While RESET pin is low: Down PUCR PUCR PUCR PUCR Up Up Up Up
PE5 PE4 PE3 PE2 PE1
RE ECLK LSTRB R/W IRQ
MODA LDS WE
TAGLO EROMCTL
VDDR VDDR VDDR VDDR VDDR
Port E I/O, Read Enable, Mode Input, Tag Low Input Port E I/O, Bus Clock Output Port E I/O, Low Byte Data strobe, EROMON control Port E I/O, Read/Write Port E Input, Maskable Interrupt
81
MC9S12XDP512 Device User Guide 9S12XDP512DGV2/D V02.06 Internal Pull Resistor

CTRL Reset State Up Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Up Up Up Up Up Up Up Up
Description
PE0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PJ7 PJ6 PJ5 PJ4 PJ2 PJ1 PJ0 PK7
XIRQ KWH7 KWH6 KWH5 KWH4 KWH3 KWH2 KWH1 KWH0 KWJ7 KWJ6 KWJ5 KWJ4 KWJ2 KWJ1 KWJ0 EWAIT ADDR [22:20] ADDR19 ADDR18 ADDR17 ADDR16 TXCAN3 RXCAN3
SS2 SCK2 MOSI2 MISO2 SS1 SCK1 MOSI1 MISO1 TXCAN4 RXCAN4 SCL1 SDA1 CS1 TXD2 RXD2 ROMCTL
TXD5 RXD5 TXD4 RXD4 SCL0 SDA0 CS2 CS0 CS3
TXCAN0 RXCAN0
VDDR VDDR VDDR VDDR VDDR VDDR VDDR VDDR VDDR VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX
PUCR PERH/ PPSH PERH/ PPSH PERH/ PPSH PERH/ PPSH PERH/ PPSH PERH/ PPSH PERH/ PPSH PERH/ PPSH PERJ/ PPSJ PERJ/ PPSJ PERJ/ PPSJ PERJ/ PPSJ PERJ/ PPSJ PERJ/ PPSJ PERJ/ PPSJ PUCR
Port E Input, Non Maskable Interrupt Port H I/O, Interrupt, SS of SPI2, TXD of SCI5 Port H I/O, Interrupt, SCK of SPI2, RXD of SCI5 Port H I/O, Interrupt, MOSI of SPI2, TXD of SCI4 Port H I/O, Interrupt, MISO of SPI2, RXD of SCI4 Port H I/O, Interrupt, SS of SPI1 Port H I/O, Interrupt, SCK of SPI1 Port H I/O, Interrupt, MOSI of SPI1 Port H I/O, Interrupt, MISO of SPI1 Port J I/O, Interrupt, TX of CAN4, SCL of IIC0, TX of CAN0 Port J I/O, Interrupt, RX of CAN4, SDA of IIC0, RX of CAN0 Port J I/O, Interrupt, SCL of IIC1, Chip Select 2 Port J I/O, Interrupt, SDA of IIC1, Chip Select 0 Port J I/O, Interrupts, Chip Select 1 Port J I/O, Interrupts, TXD of SCI2 Port J I/O, Interrupts, RXD of SCI2 Port K I/O, EWAIT input, ROM On Control Port K I/O, Extended Addresses,Access Source for external Access Extended Address, PIPE status Extended Address, PIPE status Extended Address, PIPE status Extended Address, PIPE status Port M I/O, TX of CAN3&4, TXD of SCI3 Port M I/O RX of CAN3&4, RXD of SCI3
PK[6:4] PK3 PK2 PK1 PK0 PM7 PM6
ACC[2:0] IQSTAT3 IQSTAT2 IQSTAT1 IQSTAT0 TXD3 RXD3
TXCAN4 RXCAN4
VDDX VDDX VDDX VDDX VDDX VDDX VDDX
PUCR PUCR PUCR PUCR PUCR PERM/ PPSM PERM/ PPSM
Up Up Up Up Up Disabled Disabled
82
MC9S12XDP512 Device User Guide 9S12XDP512DGV2/D V02.06 Internal Pull Resistor

CTRL Reset State
Description
PM5 PM4 PM3 PM2 PM1 PM0 PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0 PS7 PS6 PS5 PS4 PS3 PS2 PS1
TXCAN2 RXCAN2 TXCAN1 RXCAN1 TXCAN0 RXCAN0 KWP7 KWP6 KWP5 KWP4 KWP3 KWP2 KWP1 KWP0 SS0 SCK0 MOSI0 MISO0 TXD1 RXD1 TXD0
TXCAN0 RXCAN0 TXCAN0 RXCAN0
TXCAN4 RXCAN4
SCK0 MOSI0 SS0 MISO0
VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX
PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS
Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Up Up Up Up Up Up Up
Port M I/OCAN0, CAN2, CAN4, SCK of SPI0 Port M I/O, CAN0, CAN2, CAN4, MOSI of SPI0 Port M I/O TX of CAN1, CAN0, SS of SPI0 Port M I/O, RX of CAN1, CAN0, MISO of SPI0 Port M I/O, TX of CAN0 Port M I/O, RX of CAN0 Port P I/O, Interrupt, Channel 7 of PWM, SCK of SPI2 Port P I/O, Interrupt, Channel 6 of PWM, SS of SPI2 Port P I/O, Interrupt, Channel 5 of PWM, MOSI of SPI2 Port P I/O, Interrupt, Channel 4 of PWM, MISO2 of SPI2 Port P I/O, Interrupt, Channel 3 of PWM, SS of SPI1 Port P I/O, Interrupt, Channel 2 of PWM, SCK of SPI1 Port P I/O, Interrupt, Channel 1 of PWM, MOSI of SPI1 Port P I/O, Interrupt, Channel 0 of PWM, MISO2 of SPI1 Port S I/O, SS of SPI0 Port S I/O, SCK of SPI0 Port S I/O, MOSI of SPI0 Port S I/O, MISO of SPI0 Port S I/O, TXD of SCI1 Port S I/O, RXD of SCI1 Port S I/O, TXD of SCI0
PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
SCK2 SS2 MOSI2 MISO2 SS1 SCK1 MOSI1 MISO1
83
Internal Pull Resistor

CTRL Reset State
Description
PS0 PT[7:0]
RXD0 IOC[7:0]
VDDX VDDX
PERS/ PPSS PERT/ PPST
Up Disabled
Port S I/O, RXD of SCI0 Port T I/O, Timer channels
NOTE:
For devices assembled in 80-pin and 112-pin packages all non-bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs. Refer to Table 2-1 for affected pins.
2.3 Detailed Signal Descriptions

2.3.1 EXTAL, XTAL Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET External Reset Pin

The RESET pin is an active low bidirectional control signal. It acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset.The RESET pin has an internal pullup device.
. 2.3.3 TEST Test Pin
This input only pin is reserved for test. This pin has a pulldown device.
NOTE:
The TEST pin must be tied to VSS in all applications.
2.3.4 VREGEN Voltage Regulator Enable Pin

This input only pin enables or disables the on-chip voltage regulator. The input has a pullup device.
84
2.3.5 XFC PLL Loop Filter Pin

Please ask your Motorola representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided.
VDDPLL CS R0 XFC CP VDDPLL
MCU
Figure 2-4 PLL Loop Filter Connections
2.3.6 BKGD / MODC Background Debug and Mode Pin

The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET. The BKGD pin has a pullup device.
2.3.7 PAD[23:08] / AN[23:8] Port AD Input Pins of ATD1

PAD[23:08] are general purpose input or output pins and analog inputs AN[23:8] of the analog to digital converter ATD1.
2.3.8 PAD[07:00] / AN[7:0] Port AD Input Pins of ATD0

PAD[07:00] are general purpose input or output pins and analog inputs AN[7:0] of the analog to digital converter ATD0.
2.3.9 PA[7:0] / ADDR[15:8] / IVD[15:8] Port A I/O Pins

PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the external address bus. In MCU emulation modes of operation, these pins are used for external address bus and internal visibility read data.
2.3.10 PB[7:1] / ADDR[7:1] / IVD[7:1] Port B I/O Pins

PB7-PB1 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the external address bus. In MCU emulation modes of operation, these pins are used for external address bus and internal visibility read data.
85
2.3.11 PB0 / ADDR0 / UDS / IVD[0] Port B I/O Pin 0

PB0 is a general purpose input or output pin. In MCU expanded modes of operation, this pin is used for the external address bus ADDR0 or as upper data strobe signal. In MCU emulation modes of operation, this pin is used for external address bus ADDR0 and internal visibility read data IVD0.
2.3.12 PC[7:0] / DATA [15:8] Port C I/O Pins

PC7-PC0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the external data bus. The input voltage thresholds for PC[7:0] can be configured to reduced levels, to allow data from an external 3.3V peripheral to be read by the MCU operating at 5.0V. The input voltage thresholds for PC[7:0] are configured to reduced levels out of reset in expanded and emulation modes. The input voltage thresholds for PC[7:0] are configured to 5V levels out of reset in normal modes.
2.3.13 PD[7:0] / DATA [7:0] Port D I/O Pins

PD7-PD0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the external data bus. The input voltage thresholds for PD[7:0] can be configured to reduced levels, to allow data from an external 3.3V peripheral to be read by the MCU operating at 5.0V. The input voltage thresholds for PD[7:0] are configured to reduced levels out of reset in expanded and emulation modes. The input voltage thresholds for PC[7:0] are configured to 5V levels out of reset in normal modes.
2.3.14 PE7 / ECLKX2 / XCLKS Port E I/O Pin 7

PE7 is a general purpose input or output pin. The XCLKS is an input signal which controls whether a crystal in combination with the internal loop controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuitry is used. The XCLKS signal selects the oscillator configuration during RESET low phase while a clock quality check is ongoing. This is the case for: Power on Reset or Low Voltage Reset Clock Monitor Reset Any Reset while in Self Clock Mode or Full Stop Mode
The selected oscillator configuration is frozen with the rising edge of RESET. The pin can be configured to drive the internal system clock ECLKX2.
86
Figure 2-5 Loop Controlled Pierce Oscillator Connections (PE7=1)
EXTAL
C1
MCU
Crystal or ceramic resonator C2
XTAL
VSSPLL
Figure 2-6 Full Swing Pierce Oscillator Connections (PE7=0)
EXTAL
C1
MCU RS* RB
Crystal or ceramic resonator C2
XTAL
VSSPLL
Figure 2-7 External Clock Connections (PE7=0)
EXTAL
CMOS-COMPATIBLE EXTERNAL OSCILLATOR
MCU
XTAL
not connected
87
2.3.15 PE6 / MODB / TAGHI Port E I/O Pin 6

PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is an input with a pull-down device which is only active when RESET is low. TAGHI is used to tag the high half of the instruction word being read into the instruction queue. The input voltage threshold for PE6 can be configured to reduced levels, to allow data from an external 3.3V peripheral to be read by the MCU operating at 5.0V. The input voltage threshold for PE6 is configured to reduced levels out of reset in expanded and emulation modes.
2.3.16 PE5 / MODA / TAGLO / RE Port E I/O Pin 5

PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the Read Enable RE output. This pin is an input with a pull-down device which is only active when RESET is low. TAGLO is used to tag the low half of the instruction word being read into the instruction queue. The input voltage threshold for PE5 can be configured to reduced levels, to allow data from an external 3.3V peripheral to be read by the MCU operating at 5.0V. The input voltage threshold for PE5 is configured to reduced levels out of reset in expanded and emulation modes.
2.3.17 PE4 / ECLK Port E I/O Pin 4

PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK. ECLK can be used as a timing reference.
2.3.18 PE3 / LSTRB / LDS / EROMCTL Port E I/O Pin 3

PE3 is a general purpose input or output pin. In MCU expanded modes of operation, LSTRB or LDS can be used for the low byte strobe function to indicate the type of bus access. At the rising edge of RESET the state of this pin is latched to the EROMON bit.
2.3.19 PE2 / R/W / WE Port E I/O Pin 2

PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the read/write output signal or write enable output signal for the external bus. It indicates the direction of data on the external bus.
2.3.20 PE1 / IRQ Port E Input Pin 1

PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
88
2.3.21 PE0 / XIRQ Port E Input Pin 0

PE0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.22 PH7 / KWH7 / SS2 / TXD5 Port H I/O Pin 7

PH7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral Interface 2 (SPI2). It can be configured as the transmit pin TXD of Serial Communication Interface 5 (SCI5).
2.3.23 PH6 / KWH6 / SCK2 / RXD5 Port H I/O Pin 6

PH6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral Interface 2 (SPI2). It can be configured as the receive pin RXD of Serial Communication Interface 5 (SCI5).
2.3.24 PH5 / KWH5 / MOSI2 / TXD4 Port H I/O Pin 5

PH5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 2 (SPI2). It can be configured as the transmit pin TXD of Serial Communication Interface 4 (SCI4).
2.3.25 PH4 / KWH4 / MISO2 / RXD4 Port H I/O Pin 2

PH4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 2 (SPI2). It can be configured as the receive pin RXD of Serial Communication Interface 4 (SCI4).
2.3.26 PH3 / KWH3 / SS1 Port H I/O Pin 3

PH3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral Interface 1 (SPI1).
2.3.27 PH2 / KWH2 / SCK1 Port H I/O Pin 2

PH2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 (SPI1).
89
2.3.28 PH1 / KWH1 / MOSI1 Port H I/O Pin 1

PH1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1).
2.3.29 PH0 / KWH0 / MISO1 Port H I/O Pin 0

PH0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 1 (SPI1).
2.3.30 PJ7 / KWJ7 / TXCAN4 / SCL0 / TXCAN0 PORT J I/O Pin 7

PJ7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the transmit pin TXCAN for the Motorola Scalable Controller Area Network controller 0 or 4 (CAN0 or CAN4) or as the serial clock pin SCL of the IIC0 module.
2.3.31 PJ6 / KWJ6 / RXCAN4 / SDA0 / RXCAN0 PORT J I/O Pin 6

PJ6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the receive pin RXCAN for the Motorola Scalable Controller Area Network controller 0 or 4 (CAN0 or CAN4) or as the serial data pin SDA of the IIC0 module.
2.3.32 PJ5 / KWJ5 / SCL1 / CS2 PORT J I/O Pin 5

PJ5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the serial clock pin SCL of the IIC1 module. It can be configured to provide a chip select output.
2.3.33 PJ4 / KWJ4 / SDA1 / CS0 PORT J I/O Pin 4

PJ4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the serial data pin SDA of the IIC1 module. It can be configured to provide a chip select output.
2.3.34 PJ2 / KWJ2 / CS1 PORT J I/O Pin 2

PJ2 is a general purpose input or output pins. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured to provide a chip select output.
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2.3.35 PJ1 / KWJ1 / TXD2 PORT J I/O Pin 1

PJ1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the transmit pin TXD of the Serial Communication Interface 2 (SCI2).
2.3.36 PJ0 / KWJ0 / RXD2 / CS3 PORT J I/O Pin 0

PJ0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the receive pin RXD of the Serial Communication Interface 2 (SCI2).It can be configured to provide a chip select output.
2.3.37 PK7 / EWAIT / ROMCTL Port K I/O Pin 7

PK7 is a general purpose input or output pin. During MCU emulation modes and normal expanded modes of operation, this pin is used to enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the state of this pin is latched to the ROMON bit. The EWAIT input signal maintains the external bus access until the external device is ready to capture data (write) or provide data (read). The input voltage threshold for PK7 can be configured to reduced levels, to allow data from an external 3.3V peripheral to be read by the MCU operating at 5.0V. The input voltage threshold for PK7 is configured to reduced levels out of reset in expanded and emulation modes.
2.3.38 PK[6:4] / ADDR[22:20] / ACC[2:0] Port K I/O Pin [6:4]

PK[6:4] are general purpose input or output pins. During MCU expanded modes of operation, the ACC[2:0] signals are used to indicate the access source of the bus cycle . This pins also provide the expanded addresses ADDR[22:20] for the external bus. In Emulation modes ACC[2:0] is available and is time multiplexed with the high addresses
2.3.39 PK[3:0] / ADDR[19:16] / IQSTAT[3:0] Port K I/O Pins [3:0]

PK3-PK0 are general purpose input or output pins. In MCU expanded modes of operation, these pins provide the expanded address ADDR[19:16] for the external bus and carry instruction pipe information.
2.3.40 PM7 / TXCAN3 / TXCAN4 / TXD3 Port M I/O Pin 7

PM7 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controller 3 or 4 (CAN3 or CAN4). PM7 can be configured as the transmit pin TXD3 of the Serial Communication Interface 3 (SCI3).
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2.3.41 PM6 / RXCAN3 / RXCAN4 / RXD3 Port M I/O Pin 6

PM6 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controller 3 or 4 (CAN3 or CAN4). PM6 can be configured as the receive pin RXD3 of the Serial Communication Interface 3 (SCI3).
2.3.42 PM5 / TXCAN0 / TXCAN2 / TXCAN4 / SCK0 Port M I/O Pin 5

PM5 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controllers 0, 2 or 4 (CAN0, CAN2 or CAN4). It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0).
2.3.43 PM4 / RXCAN0 / RXCAN2 / RXCAN4 / MOSI0 Port M I/O Pin 4

PM4 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controllers 0,2 or 4 (CAN0, CAN2 or CAN4). It can be configured as the master output (during master mode) or slave input pin (during slave mode) MOSI for the Serial Peripheral Interface 0 (SPI0).
2.3.44 PM3 / TXCAN1 / TXCAN0 / SS0 Port M I/O Pin 3

PM3 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controllers 1 or 0 (CAN1 or CAN0). It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 (SPI0).
2.3.45 PM2 / RXCAN1 / RXCAN0 / MISO0 Port M I/O Pin 2

PM2 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controllers 1 or 0 (CAN1 or CAN0). It can be configured as the master input (during master mode) or slave output pin (during slave mode) MISO for the Serial Peripheral Interface 0 (SPI0).
2.3.46 PM1 / TXCAN0 Port M I/O Pin 1

PM1 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controller 0 (CAN0).
2.3.47 PM0 / RXCAN0 Port M I/O Pin 0

PM0 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controller 0 (CAN0).
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2.3.48 PP7 / KWP7 / PWM7 / SCK2 Port P I/O Pin 7

PP7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 7 output. It can be configured as serial clock pin SCK of the Serial Peripheral Interface 2 (SPI2).
2.3.49 PP6 / KWP6 / PWM6 / SS2 Port P I/O Pin 6

PP6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 6 output. It can be configured as slave select pin SS of the Serial Peripheral Interface 2 (SPI2).
2.3.50 PP5 / KWP5 / PWM5 / MOSI2 Port P I/O Pin 5

PP5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 5 output. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 2 (SPI2).
2.3.51 PP4 / KWP4 / PWM4 / MISO2 Port P I/O Pin 4

PP4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 4 output. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 2 (SPI2).
2.3.52 PP3 / KWP3 / PWM3 / SS1 Port P I/O Pin 3

PP3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 3 output. It can be configured as slave select pin SS of the Serial Peripheral Interface 1 (SPI1).
2.3.53 PP2 / KWP2 / PWM2 / SCK1 Port P I/O Pin 2

PP2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 2 output. It can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 (SPI1).
2.3.54 PP1 / KWP1 / PWM1 / MOSI1 Port P I/O Pin 1

PP1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 1 output. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1).
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2.3.55 PP0 / KWP0 / PWM0 / MISO1 Port P I/O Pin 0

PP0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 0 output. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 1 (SPI1).
2.3.56 PS7 / SS0 Port S I/O Pin 7

PS7 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 (SPI0).
2.3.57 PS6 / SCK0 Port S I/O Pin 6

PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0).
2.3.58 PS5 / MOSI0 Port S I/O Pin 5

PS5 is a general purpose input or output pin. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.3.59 PS4 / MISO0 Port S I/O Pin 4

PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or slave output pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.3.60 PS3 / TXD1 Port S I/O Pin 3

PS3 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial Communication Interface 1 (SCI1).
2.3.61 PS2 / RXD1 Port S I/O Pin 2

PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial Communication Interface 1 (SCI1).
2.3.62 PS1 / TXD0 Port S I/O Pin 1

PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial Communication Interface 0 (SCI0).
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2.3.63 PS0 / RXD0 Port S I/O Pin 0

PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial Communication Interface 0 (SCI0).
2.3.64 PT[7:0] / IOC[7:0] Port T I/O Pins [7:0]

PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output compare pins IOC7-IOC0 of the Enhanced Capture Timer (ECT).
2.4 Power Supply Pins

MC9S12XDP512 power and ground pins are described below.
NOTE:
All VSS pins must be connected together in the application.
2.4.1 VDDX1, VDDX2, VSSX1,VSSX2 Power & Ground Pins for I/O Drivers
External power and ground for I/O drivers. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded.
2.4.2 VDDR1, VDDR2, VSSR1, VSSR2 Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator
External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded.
2.4.3 VDD1, VDD2, VSS1, VSS2 Core Power Pins

Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. This 2.5V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if VREGEN is tied to ground.
NOTE:
No load allowed except for bypass capacitors.
2.4.4 VDDA, VSSA Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog to digital converters.
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2.4.5 VRH, VRL ATD Reference Voltage Input Pins

VRH and VRL are the reference voltage input pins for the analog to digital converter.
2.4.6 VDDPLL, VSSPLL Power Supply Pins for PLL

Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the supply voltage to the Oscillator and PLL to be bypassed independently.This 2.5V voltage is generated by the internal voltage regulator.
NOTE:
No load allowed except for bypass capacitors. Table 2-2 MC9S12XDP512 Power and Ground Connection Summary
Pin Number
Mnemonic VDD1, 2 VSS1, 2 VDDR1 VSSR1 VDDX1 VSSX1 VDDX2 VSSX2 VDDR2 VSSR2 VDDA
144-pin LQFP 15, 87 16, 88 53 52 139 138 26 27 82 81 107
112-pin LQFP 13, 65 14, 66 41 40 107 106 N.A. N.A. N.A. N.A. 83
80-pin QFP 9, 49 10, 50 29 28 77 76 N.A. N.A. N.A. N.A. 59
Nominal Voltage 2.5 V 0V 5.0 V 0V 5.0 V 0V 5.0 V 0V 5.0 V 0V 5.0 V
Description Internal power and ground generated by internal regulator External power and ground, supply to pin drivers and internal voltage regulator External power and ground, supply to pin drivers External power and ground, supply to pin drivers External power and ground, supply to pin drivers Operating voltage and ground for the analog-to-digital converters and the reference for the internal voltage regulator, allows the supply voltage to the A/D to be bypassed independently. Reference voltages for the analog-to-digital converter. Provides operating voltage and ground for the Phased-Locked Loop. This allows the supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator. Internal Voltage Regulator enable/disable
VSSA
110
86
62
0V
VRL VRH VDDPLL
109 108 55
85 84 43
61 60 31
0V 5.0 V 2.5 V
VSSPLL
57
45
33
0V
VREGEN
127
97
N.A.
5V
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2.4.7 VREGEN On Chip Voltage Regulator Enable

Enables the internal 5V to 2.5V voltage regulator. If this pin is tied low, VDD1,2 and VDDPLL must be supplied externally.
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Section 3 System Clock Description

3.1 Overview
The Clock and Reset Generator module (CRG) provides the internal clock signals for the core and all peripheral modules. Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block User Guide for details on clock generation. SCI0 . . SCI 5 CAN0 . . CAN4 SPI0 . . SPI2
IIC0 & IIC1
ATD0 & ATD1
bus clock
PIT
EXTAL oscillator clock
ECT CRG
XTAL core clock
PIM
RAM
S12X
XGATE
FLASH
EEPROM
Figure 3-1 Clock Connections
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The MCUs system clock can be supplied in several ways enabling a range of system operating frequencies to be supported: the on chip Phase Locked Loop (PLL) the PLL self clocking the Oscillator
The clock generated by the PLL or Oscillator provides the main system clock frequencies Core Clock and Bus Clock. As shown in Figure 3-1 this system clocks are used throughout the MCU to drive the Core, the memories and the peripherals. The Program Flash memory and the EEPROM are supplied by the Bus Clock and the Oscillator clock.The Oscillator clock is used as a time base to derive the program and erase times for the NVMs. Consult the FTX512k4 block guide and the EETX4K block guide for more details on the operation of the NVMs. The CAN modules may be configured to have their clock sources derived either from the bus clock or directly from the Oscillator clock. This allows the user to select its clock based on the required jitter performance. Consult MSCAN block description for more details on the operation and configuration of the CAN blocks. In order to ensure the presence of the clock the MCU includes an on-chip Clock Monitor connected to the output of the Oscillator. The Clock Monitor can be configured to invoke the PLL self clocking mode or to generate a system reset if it is allowed to time out as a result of no oscillator clock being present. In addition to the clock monitor the MCU also provides a clock quality checker which performs a more accurate check of the clock. The clock quality checker counts a predetermined number of clock edges within a defined time window to insure that the clock is running. The checker can be invoked following specific events such as on wake-up or clock monitor failure.
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Section 4 Modes of Operation

4.1 Chip Configuration Summary
The MCU can operate in six different modes. The different modes, the state of ROMCTL and EROMCTL signal on rising edge of RESET and the security state of the MCU affects the following device characteristics: External bus interface configuration Flash in memory map or not Debug features enabled or disabled
The operating mode out of reset is determined by the states of the MODC, MODB and MODA signals during reset (see Table 4-1). The MODC, MODB and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB and MODA signals are latched into these bits on the rising edge of RESET. In Normal Expanded Mode and in Emulation Modes the ROMON bit and the EROMON bit in the MISC register defines if the on chip flash memory is the memory map or not.(see Table 4-1) For a detailed description of the ROMON and EROMON bits refer to the S12X_MMC Block Guide. The state of the ROMCTL signal is latched into the ROMON bit in the MISC register on the rising edge of the RESET . The state of the EROMCTL signal is latched into the EROMON bit in the MISC register on the rising edge of the RESET.
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Table 4-1 Chip Modes and Data Sources

Chip MODES Normal Single Chip Special Single Chip Emulation Single Chip Normal Expanded BKGD = MODC 1 0 0 1 PE6 = MODB 0 0 0 0 PE5 = MODA 0 0 1 1 PK7 = ROMCLT X X X 0 1 0 1 1 0 1 PE3 = EROMCTL X 0 1 X X X 0 1 X X DATA SOURCE1 Internal Emulation Memory Internal Flash External Application Internal Flash External Application Emulation Memory Internal Flash External Application Internal Flash
Emulation Expanded
Special Test
NOTES: 1. Internal means resources inside the MCU are read/written. Internal Flash means Flash resources inside the MCU are read/written. Emulation Memory means resources inside the emulator are read/written (PRU registers, flash replacement, RAM, EEPROM and Register Space are always considered internal). External Application means resources residing outside the MCU are read/written.
The configuration of the Oscillator can be selected using the XCLKS signal. (see Table 4-2) For a detailed description please refer to the CRG Block Guide.
Table 4-2 Clock Selection Based on PE7

PE7 = XCLKS
0 1
Description
Full swing pierce oscillator or external clock source selected Loop controlled pierce oscillator selected
The logic level on the voltage regulator enable pin VREGEN determines whether the on chip voltage regulator is enabled or disabled. (see Table 4-3)
Table 4-3 Voltage Regulator VREGEN

VREGEN
1 0
Description
Internal Voltage Regulator enabled Internal Voltage Regulator disabled, VDD1,2 and VDDPLL must be supplied externally
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4.1.1 Normal Expanded Mode

Ports K, A and B are configured as a 23-bit address bus, Ports C and D are configured as a 16-bit data bus, and Port E provides bus control and status signals. This mode allows 16-bit external memory and peripheral devices to be interfaced to the system. The fastest external bus rate is divide by 2 from the internal bus rate.
4.1.2 Normal Single-Chip Mode

There is no external bus in this mode. The processor program is executed from internal memory. Ports A, B,C,D, K, and most pins of Port E are available as general-purpose I/O.
4.1.3 Special Single-Chip Mode

This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The background debug module BDM is active in this mode. The CPU executes a monitor program located in an on-chip ROM. BDM firmware is waiting for additional serial commands through the BKGD pin. There is no external bus after reset in this mode.
4.1.4 Emulation of Expanded Mode

Developers use this mode for emulation systems in which the users target application is Normal Expanded Mode. Code is executed from external memory or from internal memory depending on the state of ROMON and EROMON bit. In this mode the internal operation is visible on external bus interface.
4.1.5 Emulation of Single-Chip Mode

Developers use this mode for emulation systems in which the user s target application is Normal Single-Chip Mode. Code is executed from external memory or from internal memory depending on the state of ROMON and EROMON bit . In this mode the internal operation is visible on external bus interface.
4.1.6 Special Test Mode

Motorola internal use only.
4.2 Low Power Modes

The microcontroller features two main low power modes. Consult the respective Block Guide for information on the module behavior in System Stop, System Pseudo Stop, and System Wait Mode. An important source of information about the clock system is the Clock and Reset Generator Block Guide (CRG).
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4.2.1 System Stop Modes

The System Stop Modes are entered if the CPU executes the STOP instruction and the XGATE doesnt execute a thread and the XGFACT bit in the XGMCTL register is cleared. Depending on the state of the PSTP bit in the CLKSEL register the MCU goes into Pseudo Stop Mode or Full Stop Mode. Please refer to CRG Block Guide. Asserting RESET, XIRQ, IRQ or any other interrupt end the System Stop Modes. 4.2.1.1 Pseudo Stop Mode In this mode the clocks are stopped but the oscillator is still running and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are turned off. This mode consumes more current than the System Stop Mode, but the wake up time from this mode is significantly shorter. 4.2.1.2 Full Stop Mode The oscillator is stopped in this mode. All clocks are switched off. All counters and dividers remain frozen.
4.2.2 System Wait Mode

This mode is entered when the CPU executes the WAI instruction. In this mode the CPU will not execute instructions. The internal CPU clock is switched off. All peripherals and the XGATE can be active in System Wait Mode. For further power consumption the peripherals can individually turn off their local clocks. Asserting RESET, XIRQ, IRQ or any other interrupt that has not been masked ends System Wait Mode.
4.2.3 Run Mode

Although this is not a low power mode, unused peripheral modules should not be enabled in order to save power.
4.3 Freeze Mode

The Enhanced Capture Timer, Pulse Width Modulator, Analog Digital Converters and the Periodic Interrupt Timer provide a software programmable option to freeze the module status during the Background Debug Module is active. This is useful when debugging application software. For detailed description of the behavior of the ATD0, ATD1, ECT, PWM and PIT during Background Debug Module is active consult the corresponding Block Guides.
4.4 Security
The MCU security feature allows the the protection of the on chip Flash and EEPROM memory. For a detailed description of the security features refer to the S12X9SEC Block Guide.
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Section 5 Resets and Interrupts

5.1 Overview
Consult the S12XCPU Block Guide for information on Exception Processing.
5.2 Vectors
5.2.1 Vector Table
Table 5-1 lists all interrupt sources and vectors in the default order of priority. The Interrupt module (S12XINT) provides an Interrupt Vector Base Register (IVBR) to relocate the vectors. Associated with each I-bit maskable service request is a configuration register.It selects if the service request is enabled, the service request priority level and whether the service request is handled either by the S12X CPU or by the XGATE module. Table 5-1 Interrupt Vector Locations
Vector Address1
$FFFE, $FFFC $FFFA Vector Base + $F8 Vector Base+ $F6 Vector Base+ $F4 Vector Base+ $F2 Vector Base+ $F0 Vector Base+ $EE Vector Base + $EC Vector Base+ $EA Vector Base+ $E8 Vector Base+ $E6 Vector Base+ $E4 Vector Base + $E2 Vector Base+ $E0 Vector Base+ $DE Vector Base+ $DC Vector Base + $DA Vector Base + $D8
XGATE Channel ID2

$78 $77 $76 $75 $74 $73 $72 $71 $70 $6F $6E $6D $6C
Interrupt Source
System Reset or Illegal Access Reset Clock Monitor Reset COP Watchdog Reset Unimplemented instruction trap SWI XIRQ IRQ Real Time Interrupt Enhanced Capture Timer channel 0 Enhanced Capture Timer channel 1 Enhanced Capture Timer channel 2 Enhanced Capture Timer channel 3 Enhanced Capture Timer channel 4 Enhanced Capture Timer channel 5 Enhanced Capture Timer channel 6 Enhanced Capture Timer channel 7 Enhanced Capture Timer overow Pulse accumulator A overow Pulse accumulator input edge SPI0
CCR Mask
None None None None None X-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit
Local Enable
None PLLCTL (CME, SCME) COP rate select None None None IRQCR (IRQEN) CRGINT (RTIE) TIE (C0I) TIE (C1I) TIE (C2I) TIE (C3I) TIE (C4I) TIE (C5I) TIE (C6I) TIE (C7I) TSRC2 (TOF) PACTL (PAOVI) PACTL (PAI) SPI0CR1 (SPIE, SPTIE)
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SCI0CR2 (TIE, TCIE, RIE, ILIE) SCI1CR2 (TIE, TCIE, RIE, ILIE) ATD0CTL2 (ASCIE) ATD1CTL2 (ASCIE) PIEJ (PIEJ7-PIEJ0) PIEH (PIEH7-PIEH0) MCCTL(MCZI) PBCTL(PBOVI) CRGINT(LOCKIE) CRGINT (SCMIE)
Vector Base+ $D6 Vector Base + $D4 Vector Base + $D2 Vector Base + $D0 Vector Base + $CE Vector Base + $CC Vector Base + $CA Vector Base + $C8 Vector Base + $C6 Vector Base + $C4 Vector Base + $C2 Vector Base + $C0 Vector Base + $BE Vector Base + $BC Vector Base + $BA Vector Base + $B8 Vector Base + $B6 Vector Base + $B4 Vector Base + $B2 Vector Base + $B0 Vector Base + $AE Vector Base + $AC Vector Base + $AA Vector Base + $A8 Vector Base + $A6 Vector Base + $A4 Vector Base + $A2 Vector Base + $A0 Vector Base + $9E Vector Base+ $9C Vector Base+ $9A Vector Base + $98 Vector Base + $96 Vector Base + $94 Vector Base + $92 Vector Base + $90
$6B $6A $69 $68 $67 $66 $65 $64 $63 $62 $61 $60 $5F $5E $5D $5C $5B $5A $59 $58 $57 $56 $55 $54 $53 $52 $51 $50 $4F $4E $4D $4C $4B $4A $49 $48
SCI0 SCI1 ATD0 ATD1 Port J Port H Modulus Down Counter underow Pulse Accumulator B Overow CRG PLL lock CRG Self Clock Mode
I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit Reserved
IIC0 Bus SPI1 SPI2 EEPROM FLASH CAN0 wake-up CAN0 errors CAN0 receive CAN0 transmit CAN1 wake-up CAN1 errors CAN1 receive CAN1 transmit CAN2 wake-up CAN2 errors CAN2 receive CAN2 transmit CAN3 wake-up CAN3 errors CAN3 receive CAN3 transmit CAN4 wake-up CAN4 errors CAN4 receive CAN4 transmit
I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit
IBCR0 (IBIE) SPI1CR1 (SPIE, SPTIE) SPI2CR1 (SPIE, SPTIE) ECNFG (CCIE, CBEIE) FCNFG (CCIE, CBEIE) CAN0RIER (WUPIE) CAN0RIER (CSCIE, OVRIE) CAN0RIER (RXFIE) CAN0TIER (TXEIE2-TXEIE0) CAN1RIER (WUPIE) CAN1RIER (CSCIE, OVRIE) CAN1RIER (RXFIE) CAN1TIER (TXEIE2-TXEIE0) CAN2RIER (WUPIE) CAN2RIER (CSCIE, OVRIE) CAN2RIER (RXFIE) CAN2TIER (TXEIE2-TXEIE0) CAN3RIER (WUPIE) CAN3RIER (CSCIE, OVRIE) CAN3RIER (RXFIE) CAN3TIER (TXEIE2-TXEIE0) CAN4RIER (WUPIE) CAN4RIER (CSCIE, OVRIE) CAN4RIER (RXFIE) CAN4TIER (TXEIE2-TXEIE0)
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Vector Base + $8E Vector Base+ $8C Vector Base + $8A Vector Base + $88 Vector Base + $86 Vector Base + $84 Vector Base + $82 Vector Base + $80 Vector Base + $7E Vector Base + $7C Vector Base + $7A Vector Base + $78 Vector Base + $76 Vector Base + $74 Vector Base + $72 Vector Base + $70 Vector Base + $6E Vector Base + $6C Vector Base + $6A Vector Base + $68 Vector Base + $66 Vector Base + $64 Vector Base + $62 Vector Base + $60 Vector Base+ $12 to Vector Base + $5E Vector Base + $10 $47 $46 $45 $44 $43 $42 $41 $40 $3F $3E $3D $3C $3B $3A $39 $38 $37 $36 $35 $34 $33 $32 Port P Interrupt PWM Emergency Shutdown SCI2 SCI3 SCI4 SCI5 IIC1 Bus Low Voltage interrupt LVI Autonomous Periodical interrupt API I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit PIEP (PIEP7-PIEP0) PWMSDN (PWMIE) SCI2CR2 (TIE, TCIE, RIE, ILIE) SCI3CR2 (TIE, TCIE, RIE, ILIE) SCI4CR2 (TIE, TCIE, RIE, ILIE) SCI5CR2 (TIE, TCIE, RIE, ILIE) IBCR (IBIE) VREGCTRL (LVIE) VREGAPICTRL (APIE)
Reserved Periodic Interrupt Timer Chanel 0 Periodic Interrupt Timer Chanel 1 Periodic Interrupt Timer Chanel 2 Periodic Interrupt Timer Chanel 3 XGATE Software Trigger 0 XGATE Software Trigger 1 XGATE Software Trigger 2 XGATE Software Trigger 3 XGATE Software Trigger 4 XGATE Software Trigger 5 XGATE Software Trigger 6 XGATE Software Trigger 7 XGATE Software Error Interrupt SRAM32K Access Violation Reserved Spurious Interrupt None I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit PITINTE (PINTE0) PITINTE (PINTE1) PITINTE (PINTE2) PITINTE (PINTE3) XGMCTL (XGIE) XGMCTL (XGIE) XGMCTL (XGIE) XGMCTL (XGIE) XGMCTL (XGIE) XGMCTL (XGIE) XGMCTL (XGIE) XGMCTL (XGIE) XGMCTL (XGIE) RAMWPC (AVIE)
NOTES: 1. 16 bits Vector Address based 2. For detailed description of XGATE Channel ID refer to XGATE Block Guide
5.3 Effects of Reset

When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module Block Guides for register reset states.
5.3.1 I/O pins

Refer to the PIM Block Guide for reset configurations of all peripheral module ports.
107
5.3.2 Memory
The RAM array is not initialized out of reset.
108
Section 6 S12X_CPU Block Description

Consult the S12X_CPU Block Guide for information about the S12XCPU module.
Section 7 S12X_MMC Block Description

Consult the S12X_MMC Block Guide for information about the S12XMMC module.
Section 8 S12_XEBI Block Description

Consult the S12X_EBI Block Guide for information about the S12XEBI module.
Section 9 S12_XINT Block Description

Consult the S12X_INT Block Guide for information about the S12XINT module.
Section 10 S12X_DBG Block Description

Consult the S12X_DBG Block Guide for information about the S12XDBG module.
Section 11 S12X_BDM Block Description

Consult the S12X_BDM Block Guide for information about the S12XBDM module.
Section 12 XGATE Block Description

Consult the XGATE Block Guide for information about the co-processor.
Section 13 Periodic Interrupt Timer (PIT) Block Description

The Periodic Interrupt Timer Module contains four hardware trigger signal lines PITTRIG0, PITTRIG1, PITTRIG2 and PITTRIG3. One for each timer channel. Table 17-1 and Table 18-1 show the connection of these trigger outputs on MC9S12XDP512 device. The trigger signal lines PITTRIG2 and PITTRIG3 are not used on MC9S12XDP512. Consult the PIT Block Guide for information about the Periodic Interrupt Timer module.When the PIT Block Guide refers to freeze mode this is equivalent to active BDM mode.
109
Section 14 Oscillator (OSC_LCP) Block

Consult the OSC_LCP Block Guide for information about the Oscillator Module.
Section 15 Clock and Reset Generator (CRG) Block Description

The COP timeout rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded on rising edge of RESET from the Flash Control Register FCTL ($0107) located in the Flash EEPROM block. See Table 15-1 and Table 15-2 for coding. The FCTL register is loaded from the Flash Configuration Field byte at global address $7F_FF0E during the reset sequence. For more information on FCTL register refer to the FTX512K4 Block Guide. If the MCU is secured the COP timeout rate is always set to the longest period (CR[2:0]=111) after COP reset.
Table 15-1 Initial COP Rate Conguration

NV[2:0] in FCTL Register 000 001 010 011 100 101 110 111 CR[2:0] in COPCTL Register 111 110 101 100 011 010 001 000
Table 15-2 Initial WCOP Conguration

NV[3] in FCTL Register 1 0 WCOP in COPCTL Register 0 1
Consult the CRG Block Guide for information about the Clock and Reset Generator module.
110
Section 16 Enhanced Capture Timer (ECT) Block Description

Consult the ECT_16B8C Block Guide for information about the Enhanced Capture Timer module. When the ECT_16B8C Block Guide refers to freeze mode this is equivalent to active BDM mode.
Section 17 10 Bit 8 channel Analog to Digital Converter (ATD0) Block Description

The ATD_10B8C module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG and ETRIG3. The external trigger allows the user to synchronize ATD conversion to external trigger events. Table 17-1 shows the connection of the external trigger inputs on MC9S12XDP512. Table 17-1 ATD0 External Trigger Sources
External Trigger Input ETRIG0 ETRIG1 ETRIG2 ETRIG3 Connectivity Pulse Width Modulator Channel 1 Pulse Width Modulator Channel 3 Periodic Interrupt Timer Hardware Trigger 0 Periodic Interrupt Timer Hardware Trigger 1
Consult the ATD_10B8C Block Guide for information about the Analog to Digital Converter module. When the ATD_10B8C Block Guide refers to freeze mode this is equivalent to active BDM mode.
Section 18 10 Bit 16 Channel Analog to Digital Converter (ATD1) Block Description

The ATD_10B16C module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG and ETRIG3. The external trigger feature allows the user to synchronize ATD conversion to external trigger events. Table 18-1 shows the connection of the external trigger inputs on MC9S12XDP512.
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Table 18-1 ATD1 External Trigger Sources

External Trigger Input ETRIG0 ETRIG1 ETRIG2 ETRIG3 Connectivity Pulse Width Modulator Channel 1 Pulse Width Modulator Channel 3 Periodic Interrupt Timer Hardware Trigger 0 Periodic Interrupt Timer Hardware Trigger 1
Consult the ATD_10B16C Block Guide for information about the Analog to Digital Converter module. When the ATD_10B16C Block Guide refers to freeze mode this is equivalent to active BDM mode.
Section 19 Inter-IC Bus (IIC) Block Description

There are two Inter-IC Bus blocks implemented (IIC0, IIC1) on the MC9S12XDP512 device. Consult the IIC Block Guide for information about each Inter-IC Bus module.
Section 20 Serial Communications Interface (SCI) Block Description

There are six Serial Communications Interfaces (SCI0, SCI1, SCI2, SCI3, SCI4 and SCI5) implemented on the MC9S12XDP512 device. Consult the SCI Block Guide for information about each Serial Communications Interface module.
Section 21 Serial Peripheral Interface (SPI) Block Description

There are three Serial Peripheral Interfaces(SPI0, SPI1 and SPI2) implemented on MC9S12XDP512. Consult the SPI Block Guide for information about each Serial Peripheral Interface module.
Section 22 Pulse Width Modulator (PWM) Block Description

Consult the PWM_8B8C Block Guide for information about the Pulse Width Modulator module. When the PWM _8B8CBlock Guide refers to freeze mode this is equivalent to active BDM mode.
Section 23 Flash EEPROM 512K Block Description

112
Consult the FTX512K4 Block Guide for information about the flash module.
The "S12 LRAE" is a generic Load RAM and Execute (LRAE) program which will be programmed into the flash memory of this device during manufacture. This LRAE program will provide greater programming flexibility to the end users by allowing the device to be programmed directly using CAN or SCI after it is assembled on the PCB. Use of the LRAE program is at the discretion of the end user and, if not required, it must simply be erased prior to flash programming. For more details of the S12 LRAE and its implementation, please see the S12 LREA Application Note (AN2546/D).
Section 24 EEPROM 4K Block Description

Consult the EETX4K Block Guide for information about the EEPROM module.
Section 25 MSCAN Block Description

There are five MSCAN modules (CAN4, CAN3, CAN2, CAN1 and CAN0) implemented on the MC9S12XDP512. Consult the MSCAN Block Guide for information about the Motorola Scalable CAN Module.
Section 26 Port Integration Module (PIM) Block Description

Consult the PIM_9XD Family Block Guide for information about the Port Integration Module.
Section 27 Voltage Regulator (VREG_3V3) Block Description

Consult the VREG3V3 Block Guide for information about the dual output linear voltage regulator. VREGEN is accessible externally The API Trimming bits APITR[5:0] need to be set by the customer if accurate period is wanted.
27.1 Recommended PCB Layout

The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. The following rules must be observed:
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Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins (C1 - C6). Central point of the ground star should be the VSSR pin. Use low ohmic low inductance connections between VSS1, VSS2 and VSSR. VSSPLL must be directly connected to VSSR. Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7, C8 and Q1 as small as possible. Do not place other signals or supplies underneath area occupied by C7, C8 and Q1 and the connection area to the MCU. Central power input should be fed in at the VDDA/VSSA pins.
Table 27-1 Recommended decoupling capacitor choice

Component
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 R1 Q1
Purpose
VDD1 lter cap VDD2 lter cap (not 80 QFP) VDDA lter cap VDDR lter cap VDDPLL lter cap VDDX lter cap OSC load cap
Type
ceramic X7R ceramic X7R ceramic X7R X7R/tantalum ceramic X7R X7R/tantalum
Value
220nF 220nF >=100nF >=100nF 200nF >=100nF
comes from crystal manufacturer OSC load cap PLL loop lter cap See PLL specication chapter PLL loop lter cap VDDX lter cap VDDX lter cap PLL loop lter res Quartz
X7R/tantalum X7R/tantalum
>=100nF >=100nF
See PLL specication chapter
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Figure 27-1 LQFP144 recommended PCB layout
VDDX
C6
VSSA VREGEN
C3
VDDA
VDD1 C1 VSS1 VSS2 C2 VDD2
VDDX2 VDDR2 C11 VSSX2 C12 VSSR2
VSSR1 C4 VDDR1 C5 C8 C9 C10 Q1 C7 VSSPLL VDDPLL R1
115
Figure 27-2 LQFP112 recommended PCB layout
VREGEN
VDDX
C6 VSSX
VSSA
C3
VDDA
VDD1 C1 VSS1 VSS2 C2 VDD2
VSSR C4 VDDR C5 C8 C9 C10 Q1 C7 VDDPLL R1 VSSPLL
116
Figure 27-3 QFP80 recommended PCB layout
VDDX
C6
VREGEN
VSSX
VSSA
C3
VDDA
VDD1 VSS2
C1 C2
VSS1 VDD2
VSSR C4 C5 VDDR
Q1 C8 C7 VSSPLL
VSSPLL
C10
R1
C9
VDDPLL
117
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Appendix A Electrical Characteristics

A.1 General
NOTE:
The electrical characteristics given in this section are preliminary and should be used as a guide only. Values cannot be guaranteed by Motorola and are subject to change without notice.
This supplement contains the most accurate electrical information for the MC9S12XDP512 microcontroller available at the time of publication. The information should be considered PRELIMINARY and is subject to change. This introduction is intended to give an overview on several common topics like power supply, current injection etc.
A.1.1 Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate.
NOTE:
P:
This classification is shown in the column labeled C in the parameter tables where appropriate.
Those parameters are guaranteed during production testing on each individual device. C: Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T: Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D: Those parameters are derived mainly from simulations.
A.1.2 Power Supply

The MC9S12XDP512 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator and PLL as well as the digital core. The VDDA, VSSA pair supplies the A/D converter and parts of the internal voltage regulator.
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The VDDX, VSSX, VDDR and VSSR pairs supply the I/O pins, VDDR supplies also the internal voltage regulator. VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the oscillator and the PLL. VSS1 and VSS2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection.
NOTE:
In the following context VDD35 is used for either VDDA, VDDR and VDDX; VSS35 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD35 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins. VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is used for the sum of the currents flowing into VDD1 and VDD2.
A.1.3 Pins
There are four groups of functional pins. A.1.3.1 I/O pins Those I/O pins have a nominal level in the range of 3.0V to 5.5V. This class of pins is comprised of all port I/O pins, the analog inputs, BKGD and the RESET pins.The internal structure of all those pins is identical, however some of the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently. A.1.3.2 Analog Reference This group is made up by the VRH and VRL pins. A.1.3.3 Oscillator The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by VDDPLL. A.1.3.4 TEST This pin is used for production testing only. A.1.3.5 VREGEN This pin is used to enable the on chip voltage regulator.
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A.1.4 Current Injection

Power supply must maintain regulation within operating VDD35 or VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD35) is greater than IDD35, the injection current may flow out of VDD35 and could result in external power supply going out of regulation. Ensure external VDD35 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption.
A.1.5 Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS35 or VDD35). Table A-1 Absolute Maximum Ratings1
Num
1 2 3 4 5 6 7 8 9 10 11 12 13
Rating
I/O, Regulator and Analog Supply Voltage Digital Logic Supply Voltage 2 PLL Supply Voltage (2) Voltage difference VDDX to VDDR and VDDA Voltage difference VSSX to VSSR and VSSA Digital I/O Input Voltage Analog Reference XFC, EXTAL, XTAL inputs TEST input Instantaneous Maximum Current Single pin limit for all digital I/O pins 3 Instantaneous Maximum Current Single pin limit for XFC, EXTAL, XTAL4 Instantaneous Maximum Current Single pin limit for TEST 5 Storage Temperature Range
Symbol
VDD35 VDD VDDPLL VDDX VSSX VIN VRH, VRL VILV VTEST ID IDL IDT T
stg
Min
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -25 -25 -0.25 65
Max
6.0 3.0 3.0 0.3 0.3 6.0 6.0 3.0 10.0 +25 +25 0 155
Unit
V V V V V V V V V mA mA mA C
NOTES: 1. Beyond absolute maximum ratings device might be damaged.
121

2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. 3. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA. 4. Those pins are internally clamped to VSSPLL and VDDPLL. 5. This pin is clamped low to VSSPLL, but not clamped high. This pin must be tied low in applications.
A.1.6 ESD Protection and Latch-up Immunity

All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table A-2 ESD and Latch-up Test Conditions
Model
Series Resistance Storage Capacitance Human Body Number of Pulse per pin positive negative Series Resistance Storage Capacitance Machine Number of Pulse per pin positive negative Minimum input voltage limit Latch-up Maximum input voltage limit 7.5 V
Description
Symbol
R1 C R1 C -
Value
1500 100 3 3 0 200 3 3 -2.5
Unit
Ohm pF
Ohm pF
Table A-3 ESD and Latch-Up Protection Characteristics

Num C
1 2 3 4
Rating
Symbol
VHBM VMM VCDM ILAT
Min
2000 200 500 +100 -100 +200 -200
Max
-
Unit
V V V mA
C Human Body Model (HBM) C Machine Model (MM) C Charge Device Model (CDM) Latch-up Current at TA = 125C C positive negative Latch-up Current at TA = 27C C positive negative
ILAT
mA
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A.1.7 Operating Conditions

This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data.
NOTE:
Please refer to the temperature rating of the device (C, V, M) with regards to the ambient temperature TA and the junction temperature TJ. For power dissipation calculations refer to Section A.1.8 Power Dissipation and Thermal Characteristics. Table A-4 Operating Conditions
Rating Symbol
VDD35 VDD VDDPLL VDDX VSSX fosc fbus
Min
3.15 2.35 2.35 -0.1 -0.1 0.5 0.5
Typ
5 2.5 2.5 0 0 -
Max
5.5 2.75 2.75 0.1 0.1 16 40
Unit
V V V V V MHz MHz
I/O, Regulator and Analog Supply Voltage Digital Logic Supply Voltage 1 PLL Supply Voltage (2) Voltage Difference VDDX to VDDR and VDDA Voltage Difference VSSX to VSSR and VSSA Oscillator Bus Frequency MC9S12XDP512C Operating Junction Temperature Range Operating Ambient Temperature Range 2 MC9S12XDP512V Operating Junction Temperature Range Operating Ambient Temperature Range (2) MC9S12XDP512M Operating Junction Temperature Range Operating Ambient Temperature Range (2)
TJ T
A
-40 -40
27
100 85
C C
TJ TA
-40 -40
27
120 105
C C
TJ TA
-40 -40
27
140 125
C C
NOTES: 1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source. 2. Please refer to Section A.1.8 Power Dissipation and Thermal Characteristics for more details about the relation between ambient temperature TA and device junction temperature TJ.
A.1.8 Power Dissipation and Thermal Characteristics

Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in C can be obtained from:
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T J = T A + ( P D JA ) T J = Junction Temperature, [ C ] T A = Ambient Temperature, [ C ] P D = Total Chip Power Dissipation, [W] JA = Package Thermal Resistance, [ C/W] The total power dissipation can be calculated from: P D = P INT + P IO P INT = Chip Internal Power Dissipation, [W]
Two cases with internal voltage regulator enabled and disabled must be considered: 1. Internal Voltage Regulator disabled P INT = I DD V DD + I DDPLL V DDPLL + I DDA V DDA 2 P IO = R DSON I IO i i
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR. For RDSON is valid: V OL R DSON = ----------- ;for outputs driven low I OL
V DD5 V OH R DSON = ----------------------------------- ;for outputs driven high I OH 2. Internal voltage regulator enabled P INT = I DDR V DDR + I DDA V DDA IDDR is the current shown in Table A-9 and not the overall current flowing into VDDR, which additionally contains the current flowing into the external loads with output high. 2 P IO = R DSON I IO i i
respectively
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR.
124
Table A-5 Thermal Package Characteristics1

Num C
1 2 3 4 5 6
Rating
Symbol
JA JA JA JA JA JA
Min
-
Typ
-
Max
45 35 46 36 50 38
Unit
o
T Thermal Resistance LQFP144, single sided PCB2 T Thermal Resistance LQFP144, double sided PCB with 2 internal planes3
C/W C/W
T Thermal Resistance LQFP112, single sided PCB2 T Thermal Resistance LQFP112, double sided PCB with 2 internal planes3
oC/W
C/W C/W
T Thermal Resistance QFP 80, single sided PCB2 T Thermal Resistance QFP 80, double sided PCB with 2 internal planes3
oC/W
NOTES: 1. The values for thermal resistance are achieved by package simulations 2. PC Board according to EIA/JEDEC Standard 51-2 3. PC Board according to EIA/JEDEC Standard 51-7
125
A.1.9 I/O Characteristics

This section describes the characteristics of all I/O pins. Table A-6 3.3V I/O Characteristics
Conditions are 3.15V < VDD35 <3.6V Temperature from -40C to +140C,unless otherwise noted
Num C
1 P Input High Voltage T Input High Voltage 2 P Input Low Voltage T Input Low Voltage 3 4 C Input Hysteresis
Rating
Symbol
V
IH
Min
0.65*VDD35 VSS35 - 0.3
Typ
250
Max
VDD35 + 0.3 0.35*VDD35 -
Unit
V V V V mV
VIH V
IL
VIL V
HYS
Input Leakage Current (pins in high impedance input P mode)1 Vin = VDD35 or VSS35 C P C P Output High Voltage (pins in output mode) Partial Drive IOH = 2mA Output High Voltage (pins in output mode) Full Drive IOH = 5.5mA Output Low Voltage (pins in output mode) Partial Drive IOL = +2mA Output Low Voltage (pins in output mode) Full Drive IOL = +5.5mA
IL
in
5 6 7 8 9 10 11 12 13 14 15 16
VOH VOH VOL VOL IPUL IPUH IPDH IPDL Cin IICS IICP tPULSE tPULSE
VDD35 0.4 VDD35 0.4 -6 6
0.4 0.4 -60 60 2.5 25 3
V V V V A A A A pF mA s s
Internal Pull Up Device Current, P tested at V Max. Internal Pull Up Device Current, C tested at V Min.
IH
Internal Pull Down Device Current, P tested at V Min.

IH
Internal Pull Down Device Current, C tested at V Max.

IL
D Input Capacitance Injection T Single Pin limit Total Device Limit. Sum of all injected currents P Port H, J, P Interrupt Input Pulse ltered3 P Port H, J, P Interrupt Input Pulse passed(3) current2
-2.5 -25
10
NOTES: 1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8 C to 12 C in the temperature range from 50 C to 125 C. 2. Refer to Section A.1.4 Current Injection, for more details 3. Parameter only applies in STOP or Pseudo STOP mode.
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Table A-7 5V I/O Characteristics

Conditions are 4.5V < VDD35 <5.5V Temperature from -40C to +140C,unless otherwise noted Num C
1 P Input High Voltage T Input High Voltage 2 P Input Low Voltage T Input Low Voltage 3 C Input Hysteresis Input Leakage Current (pins in high impedance input P mode)1 Vin = VDD35 or VSS35 C P C P Output High Voltage (pins in output mode) Partial Drive IOH = 2mA Output High Voltage (pins in output mode) Full Drive IOH = 10mA Output Low Voltage (pins in output mode) Partial Drive IOL = +2mA Output Low Voltage (pins in output mode) Full Drive IOL = +10mA
Rating
Symbol
V
IH
Min
0.65*VDD35 VSS35 - 0.3
Typ
250
Max
VDD35 + 0.3 0.35*VDD35 -
Unit
V V V V mV A
VIH V
IL
VIL V
HYS
Iin
5 6 7 8
OH
VDD35 0.8 VDD35 0.8 -
0.8 0.8
V V V V A A A A pF mA s s
VOH VOL V
OL
Internal Pull Up Device Current, P tested at V Max.

IL
IPUL IPUH IPDH IPDL Cin IICS IICP tPULSE tPULSE
-130
10
Internal Pull Up Device Current, C tested at V Min.

IH
-10
11
Internal Pull Down Device Current, P tested at V Min.

IH
130
12 13 14
Internal Pull Down Device Current, C tested at V Max.

IL
10
2.5 25 3
D Input Capacitance Injection current2 T Single Pin limit Total Device Limit. Sum of all injected currents P Port H, J, P Interrupt Input Pulse ltered3 P Port H, J, P Interrupt Input Pulse passed(3)
-2.5 -25
15 16
10
NOTES: 1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8 C to 12 C in the temperature range from 50 C to 125 C. 2. Refer to Section A.1.4 Current Injection, for more details 3. Parameter only applies in STOP or Pseudo STOP mode.
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Table A-8 I/O Characteristics for Port C, D, PE5, PE6 and PK7 for reduced input voltage thresholds
Conditions are 4.5V < VDD35 <5.5V Temperature from -40C to +140C,unless otherwise noted Num C
1 2 3 P Input High Voltage P Input Low Voltage C Input Hysteresis
Rating
Symbol
V
IH IL
Min
1.75
Typ
100
Max
-
Unit
V V mV
V V
0.75
HYS
A.1.10 Supply Currents

This section describes the current consumption characteristics of the device as well as the conditions for the measurements. A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 40MHz bus frequency using a 4MHz oscillator in loop controlled Pierce mode. Production testing is performed using a square wave signal at the EXTAL input. A.1.10.2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. No generally applicable numbers can
128
given. A very good estimate is to take the single chip currents and add the currents due to the external loads. Table A-9 Supply Current Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 P
Rating
Run supply currents Single Chip, Internal regulator enabled Wait Supply current All modules enabled, PLL on only RTI enabled (1) Pseudo Stop Current (API, RTI and COP disabled) 1, 2
Symbol
IDD35 IDDW
Min
Typ
Max
TBD TBD TBD
Unit
mA
P P
mA
C P C C P C P C P
-40C 27C 70C 85C "C" Temp Option 100C 105C "V" Temp Option 120C 125C "M" Temp Option 140C
IDDPS
TBD TBD TBD TBD TBD TBD TBD TBD TBD
TBD A
TBD TBD TBD
Pseudo Stop Current (API, RTI and COP enabled) C C C C C C C

(1), (2)
-40C 27C 70C 85C 105C 125C 140C Stop Current (2) -40C 27C 70C 85C "C" Temp Option 100C 105C "V" Temp Option 120C 125C "M" Temp Option 140C
IDDPS
TBD TBD TBD TBD TBD TBD TBD
C P C C P C P C P
IDDS
TBD TBD TBD TBD TBD TBD TBD TBD TBD
TBD A
TBD TBD TBD
NOTES: 1. PLL off 2. At those low power dissipation levels TJ = TA can be assumed
129
130
A.2 ATD Characteristics

This section describes the characteristics of the analog to digital converter.
A.2.1 ATD Operating Characteristics

The Table A-10 and Table A-11 show conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA VRL VIN VRH VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped. Table A-10 ATD Operating Characteristics 5V
Conditions are shown in Table A-4 unless otherwise noted, Supply Voltage 4.5V < VDDA < 5.5V
Num C
Reference Potential 1 2 3 4 D
Rating
Low High
Symbol VRL VRH VRH-VRL fATDCLK
Min VSSA VDDA/2 4.50 0.5 14 7 12 6
Typ
Max VDDA/2 VDDA
Unit V V V MHz Cycles s Cycles s s mA mA
C Differential Reference Voltage1 D ATD Clock Frequency ATD 10-Bit Conversion Period D
5.00
5.5 TBD 28 14 26 13 20 0.750 0.375
Clock Cycles2 NCONV10 Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV10 ATD 8-Bit Conversion Period Clock Cycles(2) Conv, Time at 2.0MHz ATD Clock fATDCLK
NCONV8 TCONV8 tREC IREF IREF
6 7 8
D Recovery Time (VDDA=5.0 Volts) P P Reference Supply current 2 ATD blocks on Reference Supply current 1 ATD block on
NOTES: 1. Full accuracy is not guaranteed when differential voltage is less than 4.50V 2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks.
131
Table A-11 ATD Operating Characteristics 3.3V

Conditions are shown in Table A-4 unless otherwise noted, Supply Voltage 3.3V < VDDA < 3.6V
Num C
Reference Potential 1 2 3 4 D
Rating
Low High
Symbol VRL VRH VRH-VRL fATDCLK
Min VSSA VDDA/2 3.0 0.5 14 7 12 6
Typ
Max VDDA/2 VDDA
Unit V V V MHz Cycles s Cycles s s mA mA
C Differential Reference Voltage1 D ATD Clock Frequency ATD 10-Bit Conversion Period D
3.3
3.6 TBD 28 14 26 13 20 0.500 0.250
Clock Cycles2 NCONV10 Conv, Time at 2.0MHz ATD Clock fATDCLK TCONV10 ATD 8-Bit Conversion Period Clock Cycles(2) Conv, Time at 2.0MHz ATD Clock fATDCLK
NCONV8 TCONV8 tREC IREF IREF
D Recovery Time (VDDA=5.0 Volts) P P Reference Supply current 2 ATD blocks on Reference Supply current 1 ATD block on
Motorola Confidential Proprietary
7 8
NOTES: 1. Full accuracy is not guaranteed when differential voltage is less than 4.50V 2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks.
A.2.2 Factors influencing accuracy

Three factors - source resistance, source capacitance and current injection - have an influence on the accuracy of the ATD. A.2.2.1 Source Resistance: Due to the input pin leakage current as specified in Table A-7 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowed. A.2.2.2 Source Capacitance When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input voltage 1LSB, then the external filter capacitor, Cf 1024 * (CINS- CINN). A.2.2.3 Current Injection There are two cases to consider.
132
1. A current is injected into the channel being converted. The channel being stressed has conversion values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive condition. 2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy of the conversion depending on the source resistance. The additional input voltage error on the converted channel can be calculated as VERR = K * RS * IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel. Table A-12 ATD Electrical Characteristics
Num C
1 2 3 4 5
Rating
Symbol
RS CINN CINS INA Kp Kn
Min
-
Typ
-
Max
1 10 22
Unit
K pF mA A/A A/A
C Max input Source Resistance Total Input Capacitance T Non Sampling Sampling C Disruptive Analog Input Current C Coupling Ratio positive current injection C Coupling Ratio negative current injection
-2.5
2.5 TBD TBD
A.2.3 ATD accuracy

A.2.3.1 5V Range Table A-13 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table A-13 ATD Conversion Performance 5V
Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV
fATDCLK = 2.0MHz Num C

1 2 3 4 5 6 7 8 P 10-Bit Resolution P 10-Bit Differential Nonlinearity P 10-Bit Integral Nonlinearity P 10-Bit Absolute P 8-Bit Resolution P 8-Bit Differential Nonlinearity P 8-Bit Integral Nonlinearity P 8-Bit Absolute Error(1) Error1
Rating
Symbol
LSB DNL INL AE LSB DNL INL AE
Min
Typ
5
Max
Unit
mV
1 2.5 -3 1.5 2.0 20 0.5 1.0 -1.5 0.5 1.0
1 2.5 3
Counts Counts Counts mV
0.5 1.0 1.5
Counts Counts Counts
133

NOTES: 1. These values include the quantization error which is inherently 1/2 count for any A/D converter.
A.2.3.2 3.3V Range Table A-14 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table A-14 ATD Conversion Performance 3.3V
Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 3.328V. Resulting to one 8 bit count = 13mV and one 10 bit count = 3.25mV
fATDCLK = 2.0MHz Num C

1 2 3 P 10-Bit Resolution P 10-Bit Differential Nonlinearity P 10-Bit Integral Nonlinearity P 10-Bit Absolute Error1 P 8-Bit Resolution P 8-Bit Differential Nonlinearity P 8-Bit Integral Nonlinearity P 8-Bit Absolute Error(1)
Rating
Symbol
LSB DNL INL AE LSB DNL INL AE
Min
Typ
3.25
Max
Unit
mV
1.5 3.5 -5 1.5 2.5 13 0.5 1.5 -2.0 1.0 1.5
1.5 3.5 5
Counts Counts Counts mV
4 5 6 7 8
0.5 1.5 2.0
Counts Counts Counts
NOTES: 1. These values include the quantization error which is inherently 1/2 count for any A/D converter.
A.2.3.3 ATD Accuracy Definitions For the following definitions see also Figure A-1. Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
Vi Vi 1 DNL ( i ) = -----------------------1 1LSB

The Integral Non-Linearity (INL) is defined as the sum of all DNLs: n
INL ( n ) =
i=1
Vn V0 DNL ( i ) = -------------------n 1LSB
134
DNL
LSB Vi-1
$3FF $3FE $3FD $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5
10-Bit Absolute Error Boundary Vi 8-Bit Absolute Error Boundary
$FF
$FE
10-Bit Resolution
$3F4 $3F3
$FD
9 8 7 6 5 4 3 2 1 0 5 10 15 20 25 30 35 40 50
Ideal Transfer Curve

2
10-Bit Transfer Curve
8-Bit Transfer Curve
5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120
Vin mV
Figure A-1 ATD Accuracy Definitions
NOTE:
Figure A-1 shows only definitions, for specification values refer to Table A-13.
135
8-Bit Resolution

136
A.3 NVM, Flash and EEPROM

NOTE:
Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for both Flash and EEPROM.
A.3.1 NVM timing

The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at a lower frequency a full program or erase transition is not assured. The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within the limits specified as fNVMOP. The minimum program and erase times shown in Table A-15 are calculated for maximum fNVMOP and maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz.
A.3.1.1 Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency fNVMOP and can be calculated according to the following formula.
1 1 t swpgm = 9 --------------------- + 25 ---------f NVMOP f bus

A.3.1.2 Burst Programming This applies only to the Flash where up to 64 words in a row can be programmed consecutively using burst programming by keeping the command pipeline filled. The time to program a consecutive word can be calculated as:
1 1 t bwpgm = 4 --------------------- + 9 ---------f NVMOP f bus

The time to program a whole row is:
t brpgm = t swpgm + 63 t bwpgm

Burst programming is more than 2 times faster than single word programming.
137
A.3.1.3 Sector Erase Erasing a 1024 byte Flash sector or a 4 byte EEPROM sector takes:
1 t era 4000 --------------------f NVMOP

The setup time can be ignored for this operation. A.3.1.4 Mass Erase Erasing a NVM block takes:
1 t mass 20000 --------------------f NVMOP

The setup time can be ignored for this operation. A.3.1.5 Blank Check The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup of the command.
t check location t cyc + 10 t cyc

Table A-15 NVM Timing Characteristics
Num C
1 2 3 4 5 6 7 8 9 10
Rating
Symbol
fNVMOSC fNVMBUS fNVMOP tswpgm tbwpgm tbrpgm tera tmass tcheck tcheck
Min
0.5 1 150 46 2 20.4 (2) 1331.2 (2) 20 5 100 (5) 11 6 11 (6)
Typ
Max
80 1
Unit
MHz MHz
D External Oscillator Clock D Bus frequency for Programming or Erase Operations D Operating Frequency P Single Word Programming Time D Flash Burst Programming consecutive word 4 D Flash Burst Programming Time for 64 Words (4) P Sector Erase Time P Mass Erase Time D Blank Check Time Flash per block D Blank Check Time EEPROM per block
200 74.5 3 31 (3) 2027.5 (3) 26.7 (3) 133 (3) 65546 7 2058(7)
kHz s s s ms ms tcyc tcyc
NOTES: 1. Restrictions for oscillator in crystal mode apply! 2. Minimum Programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency fbus.
138

3. Maximum Erase and Programming times are achieved under particular combinations of fNVMOP and bus frequency fbus. Refer to formulae in Sections Section A.3.1.1 Single Word Programming- Section A.3.1.4 Mass Erasefor guidance. 4. Burst Programming operations are not applicable to EEPROM 5. Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP. 6. Minimum time, if first word in the array is not blank 7. Maximum time to complete check on an erased block
A.3.2 NVM Reliability

The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The failure rates for data retention and program/erase cycling are specified at the operating conditions noted. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed.
NOTE:
All values shown in Table A-16 are target values and subject to further extensive characterization. Table A-16 NVM Reliability Characteristics
Num C
1 2 3 C
Rating
Data Retention at an average junction temperature of TJavg = 70C
Symbol
tNVMRET nFLPE nEEPE nEEPE
Min
15 1000 10,000
Typ
Max
Unit
Years
C Flash number of Program/Erase cycles C EEPROM number of Program/Erase cycles (40C TJ 0C) EEPROM number of Program/Erase cycles (0C < TJ 140C)
10,000
Cycles Cycles
100,000
Cycles
139
140
A.4 Voltage Regulator

Table 27-2 Voltage Regulator Electrical Characteristics
Num
1
C
P
Characteristic
Input Voltages Regulator Current Reduced Power Mode Shutdown Mode Output Voltage Core Full Performance Mode Reduced Power Mode Shutdown Mode Output Voltage PLL Full Performance Mode Reduced Power Mode2 Reduced Power Mode3 Shutdown Mode Low Voltage Interrupt5 Assert Level Deassert Level Low Voltage Reset6 Assert Level Power-on Reset7 Assert Level Deassert Level Trimmed API internal clock f / fnominal
Symbol
VVDDR,A IREG
Min
3.15
Typical
Max
5.5
Unit
V A A
20 12
50 40
VDD
2.35 1.6
2.5 2.5 1
2.75 2.75
V V V
VDDPLL
2.35 2.0 1.6
2.5 2.5 2.5 4
2.75 2.75 2.75
V V V
VLVIA VLVID VLVRA VPORA VPORD dfAPI
4.1 4.25
4.37 4.52
4.66 4.77
V V
2.25
0.97 - 10%
2.05 + 10%
V V
12
NOTES: 1. High Impedance Output 2. Current IDDPLL = 1mA (loop controlled Pierce Oscillator) 3. Current IDDPLL = 3mA (loop controlled Pierce Oscillator) 4. High Impedance Output 5. Monitors VDDA, active only in Full Performance Mode. Indicates I/O & ADC performance degradation due to low supply voltage. 6. Monitors VDD, active only in Full Performance Mode. MCU is monitored by the POR in RPM (see Figure A-1) 7. Monitors VDD. Active in all modes.
NOTE:
The electrical characteristics given in this section are preliminary and should be used as a guide only. Values in this section cannot be guaranteed by Motorola and are subject to change without notice.
141
142
A.5 Reset, Oscillator and PLL

This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase-Locked-Loop (PLL).
A.5.1 Startup
Table A-17 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the Clock and Reset Generator (CRG) Block Guide.
Table A-17 Startup Characteristics

Num C
1 2 3 4 5
Rating
Symbol
PWRSTL nRST PWIRQ tWRS tfws
Min
2 192 20
Typ
Max
Unit
tosc
D Reset input pulse width, minimum input time D Startup from Reset D Interrupt pulse width, IRQ edge-sensitive mode D Wait recovery startup time D Fast Wakeup from STOP1
196
nosc ns
14 50
tcyc us
NOTES: 1. VDD1/VDD2 Filter Capacitors 220nF, VDD35=5V, T= 25C
A.5.1.1 POR The release level VPORR and the assert level VPORA are derived from the VDD Supply. They are also valid if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self clock. The fastest startup time possible is given by nuposc. A.5.1.2 SRAM Data Retention Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing code when VDD35 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG Flags Register has not been set. A.5.1.3 External Reset When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset.
143
A.5.1.4 Stop Recovery Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR is performed before releasing the clocks to the system. If the MCU is woken-up by an interrupt and the fast wake-up feature is enabled (FSTWKP=1 and SCME=1), the system will resume operation in Self-Clock Mode after tfws. A.5.1.5 Pseudo Stop and Wait Recovery The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes. The controller can be woken up by internal or external interrupts. After twrs the CPU starts fetching the interrupt vector.
A.5.2 Oscillator
144
The device features an internal low-power loop controlled Pierce oscillator and a full swing Pierce oscillator/external clock mode. The selection of loop controlled Pierce oscillator or full swing Pierce oscillator/external clock depends on the XCLKS signal which is sampled during reset. Before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP or oscillator fail. tCQOUT specifies the maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum oscillator start-up time tUPOSC. The device also features a clock monitor. A Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Assert Frequency fCMFA. Table A-18 Oscillator Characteristics
Num
1a 1b 2 3 4 5 6 7 8 9 10 11
Rating
Symbol
fOSC fOSC iOSC tUPOSC tCQOUT fCMFA fEXT tEXTL tEXTH tEXTR tEXTF CIN VIH,EXTAL VIH,EXTAL VIL,EXTAL VIL,EXTAL VHYS,EXTAL
Min
4.0 0.5 100
Typ
Max
16 40
Unit
MHz MHz A
C Crystal oscillator range (loop controlled Pierce) C Crystal oscillator range (full swing Pierce) 12 P Startup Current C Oscillator start-up time (loop controlled Pierce) D Clock Quality check time-out P Clock Monitor Failure Assert Frequency P External square wave input frequency D External square wave pulse width low D External square wave pulse width high D External square wave rise time D External square wave fall time D Input Capacitance (EXTAL, XTAL inputs) P EXTAL Pin Input High Voltage5
TBD3 0.45 50 0.5 TBD TBD 100
504 2.5 200 TBD
ms s z MHz ns ns
TBD TBD TBD 0.75* VDDPLL VDDPLL + 0.3 0.25* VDDPLL VSSPLL -0.3 250
ns ns pF V V V V mV
12 T EXTAL Pin Input High Voltage5 P EXTAL Pin Input Low Voltage5 13 T EXTAL Pin Input Low Voltage5 14 C EXTAL Pin Input Hysteresis5
NOTES: 1. Depending on the crystal a damping series resistor might be necessary 2. XCLKS =0 3. fosc = 4MHz, C = 22pF. 4. Maximum value is for extreme cases using high Q, low frequency crystals 5. If full swing Pierce oscillator/external clock circuitry is used. (XCLKS=0)
145
A.5.3 Phase Locked Loop

The oscillator provides the reference clock for the PLL. The PLLs Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode. A.5.3.1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics.
Cp VDDPLL Cs fosc fref 1 refdv+1 fcmp R Phase K Detector Loop Divider 1 synr+1
XFC Pin
VCO KV fvco
1 2
Figure A-2 Basic PLL functional diagram The following procedure can be used to calculate the resistance and capacitance values using typical values for K1, f1 and ich from Table A-19. The grey boxes show the calculation for fVCO = 80MHz and fref = 4MHz. E.g., these frequencies are used for fOSC = 4MHz and a 40MHz bus clock. The VCO gain at the desired VCO frequency is approximated by: ( f 1 f vco ) ---------------------K 1 1V 126 80 -------------------- 195
KV = K1 e
= 195MHz V e
= -154.0MHz/V
The phase detector relationship is given by:
K = i ch K V = 3.5 A ( 154MHz V ) = 539.1Hz

ich is the current in tracking mode.
146
The loop bandwidth fC should be chosen to fulfill the Gardners stability criteria by at least a factor of 10, typical values are 50. = 0.9 ensures a good transient response.
2 f ref f ref 1 f C < ------------------------------------------ ----- ;( = 0.9 ) - f C < ------------4 10 10 2 + 1 + fC < 100kHz
And finally the frequency relationship is defined as
f VCO n = ------------ = 2 ( synr + 1 ) f ref
= 20
With the above values the resistance can be calculated. The example is shown for a loop bandwidth fC=20kHz:
2 n f C 2 20 20kHz R = ---------------------------- = -------------------------------------------- = 4.7k K ( 539.1Hz )

The capacitance Cs can now be calculated as:
2 0.516 C s = --------------------- = -------------- ;( = 0.9 ) = 5.5nF = ~ 4.7nF fC R fC R

The capacitance Cp should be chosen in the range of:
Cs Cs ------ C p -----20 10
A.5.3.2 Jitter Information
CP = 470pF
The basic functionality of the PLL is shown in Figure A-2. With each transition of the clock fcmp, the deviation from the reference clock fref is measured and input voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-3.
147
N-1
tmin1 tnom tmax1 tminN tmaxN
Figure A-3 Jitter Definitions The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N). Defining the jitter as:
t min ( N ) t max ( N ) J ( N ) = max 1 -------------------- , 1 -------------------- N t nom N t nom

For N < 1000, the following equation is a good fit for the maximum jitter:
j1 J ( N ) = ------- + j2 N
J(N)
10
20
Figure A-4 Maximum bus clock jitter approximation
148
This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent.
Table A-19 PLL Characteristics

Num C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Rating
Symbol
fSCM fVCO |trk| |Lock| |unl| |unt| tstab tacq tal K1 f1 | ich | | ich | j1 j2
Min
1 8 3 0 0.5 6
Typ
Max
5.5 80 4 1.5 2.5 8
Unit
MHz MHz %1 %(1) %(1) %(1) ms ms ms MHz/V MHz A A
P Self Clock Mode frequency D VCO locking range D Lock Detector transition from Acquisition to Tracking mode
D Lock Detection D Un-Lock Detection D Lock Detector transition from Tracking to Acquisition mode
C PLLON Total Stabilization delay (Auto Mode) 2 D PLLON Acquisition mode stabilization delay (2) D PLLON Tracking mode stabilization delay (2) D Fitting parameter VCO loop gain D Fitting parameter VCO loop frequency D Charge pump current acquisition mode D Charge pump current tracking mode C Jitter t parameter 1(2) C Jitter t parameter 2(2)
0.24 0.09 0.16 -195 126 38.5 3.5 0.9 0.02 1.3 0.12
% %
NOTES: 1. % deviation from target frequency 2. fosc = 4MHz, fBUS = 40MHz equivalent fVCO = 80MHz: REFDV = #$00, SYNR = #$09, Cs = 4.7nF, Cp = 470pF, Rs = 4.7k
149
150
A.6 MSCAN
Table A-20 MSCAN Wake-up Pulse Characteristics
Num C
1 2
Rating
Symbol
tWUP tWUP
Min
Typ
Max
2
Unit
s s
P MSCAN Wake-up dominant pulse ltered P MSCAN Wake-up dominant pulse pass
151
152
Appendix B Electrical Specifications

B.1 SPI Timing
This section provides electrical parametrics and ratings for the SPI. In Table B-1 the measurement conditions are listed. Table B-1 Measurement Conditions
Description
Drive mode Load capacitance on all outputs CLOAD1,
Value
full drive mode 50 (20% / 80%) VDDX
Unit
pF V
Thresholds for delay measurement points
NOTES: 1. Timing specified for equal load on all SPI output pins. Avoid asymmetric load.
B.1.1 Master Mode

In Figure B-1 the timing diagram for master mode with transmission format CPHA=0 is depicted.
SS1 (OUTPUT) 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 10 MOSI (OUTPUT)
1.if configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1 4 4
12
13
12
13
6 MSB IN2 BIT 6 . . . 1 9 MSB OUT2 BIT 6 . . . 1 LSB OUT LSB IN 11
Figure B-1 SPI Master Timing (CPHA=0) In Figure B-2 the timing diagram for master mode with transmission format CPHA=1 is depicted.
153
SS1 (OUTPUT) 1 2 SCK (CPOL = 0) (OUTPUT) 4 SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) PORT DATA
1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
12
13
12
13
6 MSB IN2 BIT 6 . . . 1 11 LSB IN
MASTER MSB OUT2
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
Figure B-2 SPI Master Timing (CPHA=1) In Table B-2 the timing characteristics for master mode are listed. Table B-2 SPI Master Mode Timing Characteristics
Num
1 1 2 3 4 5 6 9 10 11 12 13
Characteristic
SCK Frequency SCK Period Enable Lead Time Enable Lag Time Clock (SCK) High or Low Time Data Setup Time (Inputs) Data Hold Time (Inputs) Data Valid after SCK Edge Data Valid after SS fall (CPHA=0) Data Hold Time (Outputs) Rise and Fall Time Inputs Rise and Fall Time Outputs
Symbol
fsck tsck tlead tlag twsck tsu thi tvsck tvss tho tr trfo
Min
1/2048 2 8 8 20
Typ
1/2 1/2 1/2
Max
1/2 2048 29 15 8 8
Unit
fbus tbus tsck tsck tsck ns ns ns ns ns ns ns
154
B.1.2 Slave Mode

In Figure B-3 the timing diagram for slave mode with transmission format CPHA=0 is depicted.
SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 10 7 MISO (OUTPUT) see note 5 MOSI (INPUT) NOTE: Not defined! MSB IN SLAVE MSB 6 BIT 6 . . . 1 LSB IN 9 BIT 6 . . . 1 4 4 12 13 8 11 11 SEE NOTE 12 13 3
SLAVE LSB OUT
Figure B-3 SPI Slave Timing (CPHA=0) In Figure A-4 the timing diagram for slave mode with transmission format CPHA=1 is depicted.
155
SS (INPUT) 1 2 SCK (CPOL = 0) (INPUT) 4 SCK (CPOL = 1) (INPUT) 9 MISO (OUTPUT) see note 7 MOSI (INPUT) NOTE: Not defined! SLAVE 5 MSB IN MSB OUT 6 BIT 6 . . . 1 LSB IN 4 12 13 12 13 3
11 BIT 6 . . . 1 SLAVE LSB OUT
Figure B-4 SPI Slave Timing (CPHA=1) In Table B-3 the timing characteristics for slave mode are listed. Table B-3 SPI Slave Mode Timing Characteristics
Num
1 1 2 3 4 5 6 7 8 9 10 11 12 13
Characteristic
SCK Frequency SCK Period Enable Lead Time Enable Lag Time Clock (SCK) High or Low Time Data Setup Time (Inputs) Data Hold Time (Inputs) Slave Access Time (time to data active) Slave MISO Disable Time Data Valid after SCK Edge Data Valid after SS fall Data Hold Time (Outputs) Rise and Fall Time Inputs Rise and Fall Time Outputs
Symbol
fsck tsck tlead tlag twsck tsu thi ta tdis tvsck tvss tho tr trfo
Min
DC 4 4 4 4 8 8 20
Typ

Max
1/4 20 22 29 + 0.5 t bus 1 29 + 0.5 t bus 1 8 8
Unit
fbus tbus tbus tbus tbus ns ns ns ns ns ns ns ns ns
NOTES: 1. 0.5tbus added due to internal synchronization delay
156
B.2 External Bus Timing

The following conditions are assumed for all following external bus timing values: Crystal input within 45% to 55% duty Equal loads of pins Pad full drive (reduced drive must be off)
157
B.2.1 Normal Expanded Mode (external wait feature disabled)
CSx
ADDRx
addr1
addr2
2 RE
4 WE 8 6 7 10 DATAx (read) data1
11
(write) data2
EWAIT
UDS, LDS
Figure B-5 Example 1a: Normal Expanded Mode - Read Followed by Write{statement}
158
Table B-4 Example 1a: Normal Expanded Mode Timing VDD35=5.0V (EWAITE = 0)
No.
1 2 3 4 5 6 7 8 9 10 11
C
D D D D D C D D D D D
Characteristic
Frequency of internal bus Internal cycle time Frequency of external bus External cycle time (selected by EXSTR) Address 1 valid to RE fall Pulse width, RE Address 1 valid to WE fall Pulse width, WE Read data setup time (if ITHRS = 0) Read data setup time (if ITHRS = 1) Read data hold time Read enable access time Write data valid to WE fall Write data setup time Write data hold time
Symbol
fi tcyc fo tcyce tADRE PWRE tADWE PWWE tDSR tDSR tDHR tACCR tWDWE tDSW tDHW
Min
D.C. 25 D.C. 50 5 35 5 23 24
Max
40.0 20.0 -
Unit
MHz ns MHz ns ns ns ns ns ns ns ns ns ns ns ns
0 11 7 31 8
NOTES: 1. Includes the following signals: ADDRx, UDS, LDS, and CSx.
Table B-5 Example 1a: Normal Expanded Mode Timing VDD35=3.0V (EWAITE = 0) All values: To Be Dened!
No.
1 2 3 4 5 6 7 8 9 10 11
C
C C C C C C C C C C C
Characteristic
Frequency of internal bus Internal cycle time Frequency of external bus External cycle time (selected by EXSTR) Address
1
Symbol
fi tcyc fo tcyce tADRE PWRE tADWE PWWE tDSR tDSR tDHR tACCR tWDWE tDSW tDHW
Min
D.C. 25 D.C. 50
Max
40.0 20.0 -
Unit
MHz ns MHz ns ns ns ns ns ns ns
valid to RE fall
Pulse width, RE Address

1
valid to WE fall
Pulse width, WE Read data setup time (if ITHRS = 0) Read data setup time (if ITHRS = 1) Read data hold time Read enable access time Write data valid to WE fall Write data setup time Write data hold time
N/A -
ns ns ns ns ns
NOTES: 1. Includes the following signals: ADDRx, UDS, LDS, and CSx.
159
B.2.2 Normal Expanded Mode (external wait feature enabled)
CSx
ADDRx
addr1
addr2
2 RE
WE 8
6
7 DATAx 12 13 EWAIT (read) data1
UDS, LDS
Figure B-6 Example 1b: Normal Expanded Mode - Stretched Read Access
160
CSx
ADDRx
addr1
addr2
RE
4 WE 9
10 DATAx 12 13 EWAIT (write) data1
11
UDS, LDS
Figure B-7 Example 1b: Normal Expanded Mode - Stretched Write Access
161
Table B-6 Example 1b: Normal Expanded Mode Timing VDD35=5.0V (EWAITE = 1)
No.
1 2 3 4 5 6 7 8 9 10 11 12 13
C
D D D D D C D D D D D D D
Characteristic
Frequency of internal bus Internal cycle time Frequency of external bus External cycle time (selected by EXSTR) External cycle time (EXSTR+1EWAIT) Address
1
Symbol
fi tcyc fo tcyce tcycew tADRE PWRE tADWE PWWE tDSR tDSR tDHR
2 stretch cycles Min Max

D.C. 25 D.C. 75 100 5 85 5 73 24 40.0 13.3 0 71 7 81 8 0 37 20 47

D.C. 25 D.C. 100 125 5 110 5 98 24 40.0 10.0 0 86 7 106 8 0 62 45 72
Unit
MHz ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
valid to RE fall
2
Pulse width, RE Address

1
valid to WE fall
2
Pulse width, WE
Read data setup time (if ITHRS = 0) Read data setup time (if ITHRS = 1) Read data hold time Read enable access time Write data valid to WE fall Write data setup time Write data hold time Address to EWAIT fall Address to EWAIT rise
2 2
tACCR tWDWE tDSW tDHW tADWF tADWR
NOTES: 1. Includes the following signals: ADDRx, UDS, LDS, and CSx. 2. Affected by EWAIT.
Table B-7 Example 1b: Normal Expanded Mode Timing VDD35=3.0V (EWAITE = 1) All values: To Be Dened!
No.
1 2 3 4 5
C
C C C C
Characteristic
Frequency of internal bus Internal cycle time Frequency of external bus External cycle time (selected by EXSTR) External cycle time (EXSTR+1EWAIT) Address 1 valid to RE fall Pulse width, RE 2 Address
1
Symbol
fi tcyc fo tcyce tcycew tADRE PWRE tADWE PWWE

D.C. 25 D.C. 75 100 40.0 13.3 -

D.C. 25 D.C. 100 125 40.0 10.0 -
Unit
MHz ns MHz ns ns ns ns ns ns
valid to WE fall
2
Pulse width, WE
162
Table B-7 Example 1b: Normal Expanded Mode Timing VDD35=3.0V (EWAITE = 1) All values: To Be Dened!
No. C
C C C C C C C C C
Characteristic
Read data setup time (if ITHRS = 0) Read data setup time (if ITHRS = 1) Read data hold time Read enable access time 2 Write data valid to WE fall Write data setup time 2 Write data hold time Address to EWAIT fall Address to EWAIT rise
Symbol
tDSR tDSR tDHR tACCR tWDWE tDSW tDHW tADWF tADWR

-

-
Unit
ns ns
6 7 8 9 10 11 12 13
N/A -
ns ns ns ns ns ns ns
NOTES: 1. Includes the following signals: ADDRx, UDS, LDS, and CSx. 2. Affected by EWAIT.
163
B.2.3 Emulation Single-Chip Mode (without wait states)

1 2 3 1
ECLK2X
ECLK 4 ADDR [22:20]/ ACC [2:0] ADDR [19:16]/ IQSTAT [3:0] ADDR [15:0]/ IVD [15:0] 5 6 7
addr1
acc1
addr2
acc2
addr3
addr1
iqstat0
addr2
iqstat1
addr3
addr1
ivd0
addr2
ivd1
addr3
8 9 DATAx data0 (read) data1 10 12 R/W 12 (write) data2 11
LSTRB
Figure B-8 Example 2a: Emulation Single-Chip Mode - Read Followed by Write
164
Table B-8 Example 2a: Emulation Single-Chip Mode Timing VDD35=5.0V (EWAITE = 0)
No.
1 2 3 4 5 6 7 8 9 10 11 12
C
D D D D D D D D D D D Cycle time
Characteristic 1
Frequency of internal bus
Symbol
fi tcyc PWEH PWEL tAD tAH tIVDD tIVDH tDSR tDHR tDDW tDHW
Min
D.C. 25 11.5 11.5 0 0 12 0 0 -1
Max
40.0 5 4.5 5 5
Unit
MHz ns ns ns ns ns ns ns ns ns ns ns ns
Pulse width, E high Pulse width, E low Address delay time Address hold time IVDx delay time IVDx hold time
2 2
Read data setup time (ITHRS = 1 only) Read data hold time Write data delay time Write data hold time Read/write data delay time
3
tRWD
NOTES: 1. Typical Supply and Silicon, Room Temperature Only 2. Includes also ACCx, IQSTATx 3. Includes LSTRB
165
B.2.4 Emulation Expanded Mode (with optional access stretching)

1 2 3
ECLK2X
ECLK
4 ADDR [22:20]/ ACC [2:0] ADDR [19:16]/ IQSTAT [3:0] ADDR [15:0]/ IVD [15:0]
5 6
addr1
acc1
addr1
000
addr2
addr1
iqstat0
addr1
iqstat1
addr2
addr1
addr1
ivd1
addr2
8 9 DATAx data0 (read) data1
12
12
R/W
LSTRB
Figure B-9 Example 2b: Emulation Expanded Mode - Read with 1 Stretch Cycle
166
1 2 3
ECLK2X
ECLK 4 ADDR [22:20]/ ACC [2:0] ADDR [19:16]/ IQSTAT [3:0] ADDR [15:0]/ IVD [15:0] 5 6 addr1 acc1 addr1 000 addr2 7
addr1
iqstat0
addr1
iqstat1
addr2
addr1
addr1
addr2
10 DATAx (write) data1
11
12
12
R/W
LSTRB
Figure B-10 Example 2b: Emulation Expanded Mode - Write with 1 Stretch Cycle
167
Table B-9 Example 2b: Emulation Expanded Mode Timing VDD35=5.0V (EWAITE = 0)
No.
1 2 3 4 5 6 7 8 9 10 11 12
C
D D D D D D D D D D D
Characteristic 1
Internal cycle time Cycle time Pulse width, E high E falling to sampling E rising Address delay time Address hold time IVD delay time IVD hold time
2 2
Symbol
tcyc tcyce PWEH tEFSR tAD tAH tIVDD tIVDH tDSR tDHR tDDW tDHW tRWD
1 stretch cycle Min Max

25 50 11.5 35 0 0 12 0 0 -1 25 14 39.5 5 4.5 5 5

25 75 11.5 60 0 0 12 0 0 -1 25 14 64.5 5 4.5 5 5

25 100 11.5 85 0 0 12 0 0 -1 25 14 89.5 5 4.5 5 5
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns
Read data setup time Read data hold time Write data delay time Write data hold time Read/write data delay time 3
NOTES: 1. Typical Supply and Silicon, Room Temperature Only 2. Includes also ACCx, IQSTATx 3. Includes LSTRB
168
B.3 External Tag Trigger Timing

1 ECLK
ADDR
addr
DATAx data
R/W
TAGHI/ TAGLO
Figure B-11 External Trigger Timing
Table B-10 External Tag Trigger Timing VDD35=5.0V

No.
1 2 3
C
D D Cycle time
Characteristic 1
Frequency of internal bus
Symbol
fi tcyc tTS tTH
Min
D.C. 25 11.5 0
Max
40.0 -
Unit
MHz ns ns ns
TAGHI/LO setup time TAGHI/LO hold time
NOTES: 1. Typical Supply and Silicon, Room Temperature Only
169
170
Appendix C Package Information

C.1 General
This section provides the physical dimensions of the MC9S12XDP512 packages.
171
C.2 144-pin LQFP

Figure 27-4 144-pin LQFP Mechanical Dimensions (case no. 918-03
4X
0.20 T L-M N
4X 36 TIPS
0.20 T L-M N
PIN 1 IDENT 1
144
109
108
J1 J1 L M B V
140X
4X
C L X G
VIEW Y
36 73
B1
V1
VIEW Y
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M, N TO BE DETERMINED AT THE SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.35.
37
72
N A1 S1 A S
VIEW AB C 2 2 T 0.1 T
144X MILLIMETERS DIM MIN MAX A 20.00 BSC A1 10.00 BSC B 20.00 BSC B1 10.00 BSC C 1.40 1.60 C1 0.05 0.15 C2 1.35 1.45 D 0.17 0.27 E 0.45 0.75 F 0.17 0.23 G 0.50 BSC J 0.09 0.20 K 0.50 REF P 0.25 BSC R1 0.13 0.20 R2 0.13 0.20 S 22.00 BSC S1 11.00 BSC V 22.00 BSC V1 11.00 BSC Y 0.25 REF Z 1.00 REF AA 0.09 0.16 0 1 0 7 2 11 13
SEATING PLANE
PLATING
AA
C2 0.05 R2 R1
D 0.08
M
BASE METAL
0.25
GAGE PLANE
T L-M N (K) C1 (Y) VIEW AB (Z) E 1
SECTION J1-J1 (ROTATED 90 )

144 PL
172
C.3 112-pin LQFP package

4X PIN 1 IDENT 1 112
0.20 T L-M N
4X 28 TIPS 85 84
0.20 T L-M N
J1 J1 C L
4X
VIEW Y
108X
X X=L, M OR N
VIEW Y B L M B1 V1 V
AA
28
57
F D 0.13
M
BASE METAL
29
56
T L-M N
N A1 S1 A S
SECTION J1-J1 ROTATED 90 COUNTERCLOCKWISE

NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B INCLUDE MOLD MISMATCH. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.46. MILLIMETERS MIN MAX 20.000 BSC 10.000 BSC 20.000 BSC 10.000 BSC --1.600 0.050 0.150 1.350 1.450 0.270 0.370 0.450 0.750 0.270 0.330 0.650 BSC 0.090 0.170 0.500 REF 0.325 BSC 0.100 0.200 0.100 0.200 22.000 BSC 11.000 BSC 22.000 BSC 11.000 BSC 0.250 REF 1.000 REF 0.090 0.160 8 0 7 3 13 11 11 13
C2 C 0.050 2
VIEW AB 0.10 T
112X
SEATING PLANE
3 T
R2 0.25
GAGE PLANE
R1
C1 (Y) (Z) VIEW AB
(K) E
DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA 1 2 3
Figure C-1 112-pin LQFP mechanical dimensions (case no. 987)
173
C.4 80-pin QFP package

L
60 61 41 40
B B P
H A-B
V 0.05 D
C A-B
-A-
-B-
0.20
0.20
-A-,-B-,-DDETAIL A
DETAIL A
80 1 20
21
-D0.20
M
A H A-B S
0.05 A-B J
S
0.20 E C -CSEATING PLANE
C A-B
M DETAIL C -HH G
DATUM PLANE
D 0.20
M
C A-B
SECTION B-B
VIEW ROTATED 90
0.10 M
U T
DATUM PLANE
-H-
K W X DETAIL C
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
DIM A B C D E F G H J K L M N P Q R S T U V W X
MILLIMETERS MIN MAX 13.90 14.10 13.90 14.10 2.15 2.45 0.22 0.38 2.00 2.40 0.22 0.33 0.65 BSC --0.25 0.13 0.23 0.65 0.95 12.35 REF 5 10 0.13 0.17 0.325 BSC 0 7 0.13 0.30 16.95 17.45 0.13 --0 --16.95 17.45 0.35 0.45 1.6 REF
Figure C-2 80-pin QFP Mechanical Dimensions (case no. 841B)
174
User Guide End Sheet
175
FINAL PAGE OF 176 PAGES
176

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DOCUMENT NUMBER 9S12XDP512DGV2/D

MC9S12XDP512 Device User Guide V02.06

covers MC9S12XD-Family & MC9S12XA-Family

DOCUMENT NUMBER 9S12XDP512DGV2/D

9 Jul 2004 27 Jul 2004

MC9S12XDP512 Device User Guide 9S12XDP512DGV2/D V02.06

MC9S12XDP512 Device User Guide 9S12XDP512DGV2/D V02.06

MC9S12XDP512 Device User Guide V02.06

MC9S12XDP512 Device User Guide V02.06

Table 0-2 MC9S12XA-Family members

A/D1 2/24 2/16 1/8 2/24 2/16 1/8 2/16 1/8

I/O2 119 91 59 119 91 59 91 59

112LQFP 256K 80QFP 112LQFP 80QFP

112 Pin Packages

MC9S12XDP512 Device User Guide V02.06

MC9S12XDP512 Device User Guide V02.06

Figure 0-1 Order Part Number Example

MC9S12XDP512 Device User Guide V02.06

Document Order Number

NOTES: 1. Specification changes are shown in bold (Maskset L40V vs L15Y)

MC9S12XDP512 Device User Guide V02.06

Specification Change Summary Maskset L40V vs L15Y

MC9S12XDP512 Device User Guide V02.06

MC9S12XDP512 Device User Guide V02.06

SPI Hardware Change Modified functionality of data reception

MC9S12XDP512 Device User Guide V02.06

MC9S12XDP512 Device User Guide V02.06

MC9S12XDP512 Device User Guide 9S12XDP512DGV2/D V02.06

Section 2 Signal Description

MC9S12XDP512 Device User Guide 9S12XDP512DGV2/D V02.06

MC9S12XDP512 Device User Guide 9S12XDP512DGV2/D V02.06

Section 3 System Clock Description

Section 4 Modes of Operation

MC9S12XDP512 Device User Guide 9S12XDP512DGV2/D V02.06

Section 5 Resets and Interrupts

MC9S12XDP512 Device User Guide 9S12XDP512DGV2/D V02.06

Appendix A Electrical Characteristics

MC9S12XDP512 Device User Guide 9S12XDP512DGV2/D V02.06

Appendix B Electrical Specifications

Appendix C Package Information

MC9S12XDP512 Device User Guide V02.06

MC9S12XDP512 Device User Guide V02.06

MC9S12XDP512 Device User Guide V02.06

MC9S12XDP512 Device User Guide V02.06

MC9S12XDP512 Device User Guide 9S12XDP512DGV2/D V02.06

MC9S12XDP512 Device User Guide 9S12XDP512DGV2/D V02.06

XGATE (Peripheral Co-Processo)

PIT (Periodic Interrupt Timer)

CRG (Clock and Reset Generator)

8-bit ports with interrupt functionality

One 8-channel and one 16 channel Analog-to-Digital Converter

Five 1M bit per second, CAN 2.0 A, B software compatible modules

MC9S12XDP512 Device User Guide 9S12XDP512DGV2/D V02.06

ECT (Enhanced Capture Timer)

IIC (Two Inter-IC Bus modules)

On chip Voltage Regulator

MC9S12XDP512 Device User Guide 9S12XDP512DGV2/D V02.06

1.3 Modes of Operation

Special Operating Modes

System Wait Mode

MC9S12XDP512 Device User Guide 9S12XDP512DGV2/D V02.06

1.4 Block Diagram

MC9S12XDP512 Device User Guide 9S12XDP512DGV2/D V02.06

Figure 1-1 MC9S12XDP512 Block Diagram