Introduction
Traditionally, digital signal processing (DSP algorith!s are i!ple!ented using general purpose progra!!a"le DSP chips #or lo$-rate applications% Alternati&ely, special-purpose, #ixed #unction DSP chipsets and application-speci#ic integrated circuits (ASI's are used #or high-per#or!ance applications% Technological ad&ance!ents "y Xilinx in Field Progra!!a"le (ate Arrays (FP(As in the past )* years ha&e opened ne$ paths #or DSP design engineers% The FP(A !aintains the high speci#icity o# the ASI' $hile a&oiding its high de&elop!ent cost and its ina"ility to acco!!odate design !odi#ications a#ter production% +ighly adapta"le and design-#lexi"le, FP(As pro&ide opti!al de&ice utili,ation through conser&ation o# "oard space and syste! po$er-i!portant ad&antages not a&aila"le $ith !any stand-alone DSP chips% The #ast pace o# t$enty-#irst century co!puting de!ands solutions that target aggressi&e ti!eto!ar.et $indo$s o# opportunities% Spartan/-II is e##ecti&ely ta.ing o&er !any traditional ASSP !ar.ets% 0nli.e typical ASSP solutions, Xilinx Spartan-II allo$s designers to respond 1uic.ly and econo!ically to the e!ergence o# ne$, !ore e##icient IP core algorith!s% Xilinx Spartan-II FP(As pro&ide digital designers $ith a potentially unli!ited array o# highly recon#igura"le solutions% 2hen the design de!ands !ore than )33 4IPS, $hen ti!e-to!ar.et is critical, or $hen design adapta"ility is crucial, Spartan-II is the "est solution% The !ost co!!on digital "uilding "loc.s, li.e serial peripherals, D4A controllers, P'I controllers, and synthesi,a"le processors, are all readily reali,a"le using a Spartan-II de&ice% In #act, all the !ost "asic operations per#or!ed "y analog or digital electronic de&ices-#iltering, a!pli#ication, !odulation, storage, and co!putation-can "e i!ple!ented $ith Spartan-II% Figure ) sho$s ho$ Spartan-II can do all these things as a digital signal processor%
characteristics, phase linearity and sta"ility% 'o!pared to FIR #ilters, in#inite i!pulse response (IIR #ilters are not linear at the #ringes, and are not al$ays sta"le% FIR #ilters can "e expressed in "oth e1uation and graphical #or!at% Figure 6 sho$s t$o e1uations% The top e1uation (a is expressed as a di##erence e1uation, $hile the "otto! e1uation (" is expressed as a =-trans#or! e1uation% The FIR #ilter direct #or! (trans&ersal structure is sho$n in Figure 9% There are generally #i&e steps in the design o# a digital #ilter: )% Speci#y the #ilter re1uire!ents% 6% 'alculate the #ilter coe##icients% 9% 0se a suita"le structure to represent the #ilter% >% Analy,e the e##ects o# #inite $ord length on the #ilter?s per#or!ance% *% I!ple!ent the #ilter in so#t$are and:or hard$are% Steps 6, 9, and > are usually grouped together $hen using auto!ated tools% Figure > sho$s that the #ilter coe##icients "asically correspond to the i!pulse response o# the #ilter "eing characteri,ed% Theoretically, the i!pulse response o# a #ilter is o"tained "y $atching the output a#ter applying an i!pulse at the #ilter?s input% Figure > also sho$s ho$ the FIR #ilter #its into the sche!e o# digital signal processing% There can "e se&eral FIR #ilters used in one application% Figure * sho$s the end-user-supplied speci#ications #or an exa!ple #ilter, a lo$-pass #ilter in this case% The speci#ications #or "and-pass and high-pass #ilters are &ery si!ilar% @asically, one speci#ies the pass"and #re1uency (#p , transition $idth (#s A #p , stop"and attenuation (ds , and the sa!pling #re1uency% The B+(# B axis represents the !agnitude o# the signal "eing #iltered and the # axis is the #re1uency% As an exercise in FIR #iltering, the $indo$ !ethod $ill "e used% Although it is not as e##icient as the opti!al !ethod, $hich generally gi&es s s!aller nu!"er o# coe##icients than other !ethods, the $indo$ !ethod $ill su##ice%
$here standards are still e&ol&ing, such as in the areas o# &ideo and i!age processing% The real strength o# the Spartan-II #a!ily o# FP(As is that FIR #iltering, as $ell as digital signal processing tas.s in general, can "e i!ple!ented in a &ariety o# $ays $ithout "eing hindered "y DSP 'P0 architecture (Figure )6 % This !eans that the designer can ta.e #ull ad&antage o# the FP(As progra!!a"le #a"ric to #it the re1uire!ents o# any application% Figure 11: Spartan-II in Products $ith <&ol&ing Standards A $ide range o# arith!etic #unctions #or #ast Fourier trans#or!s (FFTs , con&olution and #iltering algorith!s, as $ell as the surrounding peripheral circuitry can "e i!ple!ented into the Xilinx FP(A and recon#igured on-the-#ly% 2hen designing a DSP syste! in an FP(A, the data can "e processed ta.ing ad&antage o# single-chip, paralleled structures (Figure )6 and Figure )9 and arith!etic algorith!s to exceed the per#or!ance o# a single general-purpose DSP de&ice% Distri"uted Arith!etic6 used #or array !ultiplication is Lust one o# the approaches used to increase data "and$idth and throughput "y as !uch as se&eral order o# !agnitudes in FP(As% ;ne exa!ple is a )7-tap, 8-"it FIR #ilter% It can support !ore than I83 4IPS at * !illion sa!ples per second $hile occupying less than )3*3 gates, or I3P o# the *3 'E@s in the s!allest !e!"er o# the Spartan-II #a!ily, the X'6S)*% This de&ice has a total o# O7 'E@s and runs at 633 4+, $ith a 6%*K supply% Ta"le 9 "elo$ sho$s all the Spartan-II #a!ily !e!"ers% Di##ering #ro! con&entional data processing, DSP operations lend the!sel&es to highly pipelined parallel execution, and the Spartan-II architecture, $ith its thousands o# loo.-up ta"les and #lip-#lops, is the ideal plat#or! #or this% 'o!pared to general-purpose DSP processors, Xilinx FP(As achie&e identical results !uch !ore 1uic.ly, and at a lo$er cost% 'o!pared to dedicated ASI' solutions, Xilinx FP(As o##er #aster ti!e-to-!ar.et and less ris.% And Xilinx has so#t$are tools, as Figure )> sho$s, to help auto!ate this !ethod o# i!ple!enting #a!iliar DSP algorith!s% Xilinx? DSP Eogi';R< products are co!plex, para!eteri,ed DSP "uilding "loc.s that deli&er per#or!ance and density e1ual to or "etter then a hand-tuned i!ple!entation% Eogi';R< DSP !odules can "e used $ith K+DE, Kerilog, or sche!atic-capture design !ethodologies% +igher le&el DSP cores are a&aila"le #ro! Xilinx Alliance';R< partners% Figure )* and Figure )7 sho$ the Xilinx ';R< (enerator (0I%
Spartan-II Su!!ary
Flexi"ility o# DSP Processors 5 ;##-the-shel# de&ices 5 Faster ti!e-to-!ar.et 5 Rapid adoption o# ne$ standards 5 Real-ti!e prototyping Per#or!ance o# 'usto! I's 5 Parallel processing 5 Support high data rates 5 ;pti!al "it $idths 5 Co real-ti!e so#t$are coding Ad&antages o# the Xilinx FIR Filter Solution 5 +igh-per#or!ance #inite i!pulse response (FIR , hal#-"and, +il"ert trans#or! and
interpolated #ilters 5 +ighly para!eteri,a"le 5 6-to-6*7 tap sy!!etrical i!pulse response 5 6-to-)68 tap non-sy!!etrical i!pulse response 5 )-to-96-"it input data precision 5 signed or unsigned input data
5 )-to-96-"it coe##icient precision 5 )-to-8 channels 5 'oe##icient sy!!etry exploited (sy!!etric:negati&e-sy!!etric to produce co!pact
i!ple!entations 5 Data-#lo$ style core inter#ace and control 5 +igh per#or!ance and density guaranteed through Relational Placed 4acro (RP4 !apping and place!ent and S!art-IP technology #or !ax per#or!ance As Figure )I sho$s, Xilinx? solution, ta.es ad&antage o# the entire spectru! o# FIR #ilter i!ple!entations $hich gi&e cost-e##ecti&e and high-per#or!ance solutions "oth #or FIR #iltering and general purpose digital signal processing%
Cotes: )% 73> cycles #or opti!i,ed )7-tap FIR in a )%) (+, DSP% 6% FIR #ilter reali,ed in FP(A using #ully Parallel Distri"uted Arith!etic%
'onclusion
The Xilinx FIR #ilter 'ore produces a highly para!eteri,a"le, area-e##icient, high-per#or!ance i!ple!entation% +ighly opti!i,ed single-rate, hal#-"and, +il"ert trans#or!, and interpolated FIR #ilters can "e #ully reali,ed $ith the #ilter co!piler%