A Single Phase Grid Connected DC-AC Inverter With Reactive Power Control For Residential PV Application

A Single Phase Grid Connected DC/AC Inverter with
Reactive Power Control for Residential PV Application

by
Xiangdong Zong
A thesis submitted in conformity with the requirements
for the degree of Masters of Applied Science
Graduate Department of Electrical and Computer Engineering
University of Toronto
Copyright 2011 by Xiangdong Zong
Abstract
A Single Phase Grid Connected DC/AC Inverter with Reactive Power Control for
Residential PV Application
Xiangdong Zong
Masters of Applied Science
Graduate Department of Electrical and Computer Engineering
University of Toronto
2011
This Master of Applied Science thesis presents a single phase grid connected DC/AC
inverter with reactive power (VAR) control for residential photovoltaic (PV) applications.
The inverter, utilizing the voltage sourced inverter (VSI) conguration, allows the local
residential PV generation to actively supply reactive power to the utility grid. A low
complexity grid synchronization method was introduced to generate the parallel and
orthogonal components of the grid voltage in a highly computationally ecient manner
in order to create a synchronized current reference to the current control loop. In addition,
the inverter is able to use a small long life lm type capacitor on the DC-link by utilizing a
notch lter on the voltage control loop. Simulations were performed on PSCAD/EMTDC
platform and a prototype was also developed in the lab to prove the eectiveness of the
controllers and the grid synchronization method.
ii
Acknowledgements
First I would like to express my gratitude to my supervisor Professor Peter Lehn for his
wisdom, patience, and for giving me the opportunity to study with him and this exciting
project for my thesis. His guidance and support were the most important assets that led
the completion of this thesis.
I would also like to thank my loving parents Youjin and Guanghui for their uncon-
ditional love and support, and my wife Xiaolin for sticking with me through thick and
thin over the last ve years.
Finally I would like to acknowledge and give thanks to all the people working in the
power lab for their support, especially Damien Frost and Gregor Simeonov.
iii
Contents
List of Abbreviations vii
1 Introduction 1
1.1 Background and Motivation . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Literary Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.1 Grid connected PV systems . . . . . . . . . . . . . . . . . . . . . 4
1.2.2 Controls of the VSI . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.3 Reducing the Size of the DC-link Capacitor . . . . . . . . . . . . 8
1.2.4 Grid Synchronization Techniques . . . . . . . . . . . . . . . . . . 10
1.3 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Single Phase Grid Connected Inverter Design 13
2.1 Inverter Specications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 Switching Circuit Conguration . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 DC-link Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.1 Electrolytic Capacitors vs. Film Capacitors . . . . . . . . . . . . 15
2.3.2 Sizing the DC-link Capacitor . . . . . . . . . . . . . . . . . . . . 18
2.4 Output Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4.1 Filter Conguration . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 Controller Design 25
iv
3.1 Current Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.1 Plant Modelling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.2 Proportional Resonant Controller . . . . . . . . . . . . . . . . . . 27
3.1.3 Closed-Loop Stability . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2 Grid Synchronization Method . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2.1 Grid Voltage Estimator . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2.2 Grid Voltage Amplitude Identier . . . . . . . . . . . . . . . . . . 38
3.2.3 Synchronized Current Reference Creation . . . . . . . . . . . . . . 41
3.2.4 Discussion of the Proposed Grid Synchronization Method . . . . . 41
3.3 Voltage Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.3.1 Voltage Loop Modelling . . . . . . . . . . . . . . . . . . . . . . . 43
3.3.2 DC Voltage Compensator . . . . . . . . . . . . . . . . . . . . . . 46
3.4 Digital Implementation of the Controller . . . . . . . . . . . . . . . . . . 46
3.4.1 Switching Frequency Consideration . . . . . . . . . . . . . . . . . 48
3.4.2 Per-unitize and Fixed Number Format . . . . . . . . . . . . . . . 48
4 PSCAD/EMTDC Simulation Results 49
4.1 Inverter Current Loop Simulation . . . . . . . . . . . . . . . . . . . . . . 49
4.1.1 Steady State Response . . . . . . . . . . . . . . . . . . . . . . . . 51
4.1.2 Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.2 Inverter Voltage Loop Simulation . . . . . . . . . . . . . . . . . . . . . . 53
4.2.1 Steady State Response . . . . . . . . . . . . . . . . . . . . . . . . 53
4.2.2 Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5 Inverter Experimental Results 58
5.1 Steady State Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.2 Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
v
6 Conclusion and Future Work 65
6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
A IEEE-1547 Standard on Harmonic Current Injection 67
B PR Controller Behaviour 68
C Harmonics Table for Switch Mode Inverters 70
Bibliography 71
vi
List of Abbreviations
AC Alternating Current
DC Direct Current
DR Distributed Resources
LF Loop Filter
microFIT micro-feed-in tari
MPPT Maximum Power Point Tracking
OPA Ontario Power Authority
PCC Point of Common Coupling
PD Phase Detector
PI Proportional Integral
PLL Phase Locked Loop
PR Proportional Resonant
PV photovoltaic
SOGI Second Order Generalised Integrator
SPWM Sinusoidal Pulse Width Modulation
vii
TDD Total Demand Distortion
THD Total Harmonic Distortion
VCO Voltage Controlled Oscillator
VSI Voltage Sourced Inverter
viii
List of Tables
2.1 Inverter specications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 Output lter parameters and their chosen values . . . . . . . . . . . . . . 24
3.1 PR compensators parameters and systems parameters . . . . . . . . . . 30
4.1 Inverter current loop simulation power stage parameters . . . . . . . . . 50
4.2 Active and reactive power measurement of the current loop simulation . . 51
4.3 Active and reactive power measurement of the voltage loop simulation . . 54
5.1 Summary of measured power factor and TDD . . . . . . . . . . . . . . . 59
A.1 Maximum harmonic current distortion in percent of current(I)
a
. . . . . 67
C.1 Generalized harmonics of V
Ao
for a large m
f
. . . . . . . . . . . . . . . . 70
ix
List of Figures
1.1 Past technology - centralized inverters . . . . . . . . . . . . . . . . . . . 5
1.2 Two stage inverter congurations . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Instantaneous output power of a single phase inverter at unity displace-
ment factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 An example of an active power decoupling circuit . . . . . . . . . . . . . 9
2.1 Power stage conguration of the single phase PV inverter . . . . . . . . . 14
2.2 Generic DC-link voltage waveform . . . . . . . . . . . . . . . . . . . . . 15
2.3 Full bridge conguration with PWM unipolar voltage switching scheme . 16
2.4 Output LCL lter of the inverter . . . . . . . . . . . . . . . . . . . . . . 21
2.5 Magnitude plot of the output lter transfer function H
f
(s) . . . . . . . . 23
2.6 Magnitude plot of H
f
(j) using selected lter components values . . . . 24
3.1 The inverter controller overall block diagram . . . . . . . . . . . . . . . . 26
3.2 Current controller block diagram . . . . . . . . . . . . . . . . . . . . . . 27
3.3 Bode plot of (a) ideal PR compensator, (b) non-ideal PR compensator,
K
c
p
=1, K
c
i
=2000, =0.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4 The bode plot of the uncompensated and compensated current loop gain 31
3.5 Overview of the grid synchronizer and VAR controller . . . . . . . . . . 32
3.6 Feedback loop of the grid voltage estimator . . . . . . . . . . . . . . . . . 33
x
3.7 (a) State trajectory of the estimator, (b)Peak voltage phasor diagram of
the estimators input and outputs . . . . . . . . . . . . . . . . . . . . . . 34
3.8 Bode plot of
V
g
(j)
Vg(j)
and
V
g
(j)
Vg(j)
. . . . . . . . . . . . . . . . . . . . . . . 36
3.9 Turn on trajectory of the estimators state variables with dierent k
sync
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.10 Time domain response of the estimators state variables . . . . . . . . . . 38
3.11 Zoomed in time domain response of the distorted grid voltage v
g
(t), the
estimators output and its desired values . . . . . . . . . . . . . . . . . . 39
3.12 Power factors vs. grid frequencies for Q=0 while neglecting switching
harmonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.13 Inverter power stage diagram . . . . . . . . . . . . . . . . . . . . . . . . 43
3.14 Phasor diagram of i
g
and its two components . . . . . . . . . . . . . . . 44
3.15 Voltage loop of the inverter . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.16 Eect of the double-line frequency ripple on the current reference signal . 45
3.17 Bode plot of the uncompensated and compensated voltage loop gain . . 47
4.1 Inverter current loop simulation setup . . . . . . . . . . . . . . . . . . . . 50
4.2 PSCAD/EMTDC simulation result of the grid voltage estimators outputs
and their desired values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.3 Steady state response of the current loop simulation . . . . . . . . . . . . 52
4.4 Step response of the current loop simulation . . . . . . . . . . . . . . . . 53
4.5 Inverter voltage loop simulation setup . . . . . . . . . . . . . . . . . . . . 54
4.6 Steady state response of the current loop simulation . . . . . . . . . . . . 55
4.7 TDD vs. i
gn
when running pure real power and reactive power for voltage
loop simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.8 Voltage loop simulation based on the DC-link voltage step change . . . . 57
4.9 Step response of the voltage loop simulation based on the DC input current
step change and i
ref
g
step change . . . . . . . . . . . . . . . . . . . . . . . 57
xi
5.1 Inverter experimental setup . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.2 Steady state operation of the inverter. From top to bottom: DC-link
voltage V
n
dc
=140V on CH1 at 50V/Div, grid voltage v
g
=60V(RMS) on
CH4 at 100V/Div and output current i
g
=10A (RMS) on CH3 at 20A/Div.
Time scale 5ms/Div . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.3 TDD vs. i
gn
when running pure real power and reactive power . . . . . . 61
5.4 DC-link voltage step response of the inverter. (a) From top to bottom:
DC-link voltage v
dc
(t) on CH1 at 10V/Div, grid voltage v
g
(t) on CH4
at 100V/Div and output current i
gn
on CH3 at 2A/Div. Time scale
20ms/Div. (b) From top to bottom: DC-link voltage v
dc
(t) on CH1 at
50V/Div, grid voltage v
g
(t) on CH4 at 100V/Div and output current i
gn
(t)
on CH3 at 10A/Div. Time scale 20ms/Div . . . . . . . . . . . . . . . . . 63
5.5 Input power step change and i
ref
g
step change response of the inverter.
(a) from top to bottom: DC-link voltage v
dc
(t) on CH1 at 50V/Div, grid
voltage v
g
(t) on CH4 at 100V/Div and output current i
gn
(t) on CH3 at
10A/Div, time scale 10ms/Div. (b) from top to bottom: DC-link voltage
v
dc
g
(t) on CH4 at 100V/Div and
output current i
gn
(t) on CH3 at 5A/Div, time scale 100ms/Div . . . . . . 64
B.1 Frequency response of the PR controller with each parameter changes . . 69
xii
Chapter 1
Introduction
This chapter introduces the main topic of this thesis, a single phase grid connected
DC/AC inverter with reactive power (VAR) control for residential photovoltaic (PV)
applications. In this work, the foci are on the control of the inverter and the grid
synchronization technique. Another challenge involves the reduction of the size of the
DC-link capacitor in order to use long life lm capacitor in a low cost manner.
First, a brief background on the single phase PV grid connected inverter is presented
along with the motivation of this work. Then, a literary review on the PV inverter
system congurations, controls, DC-link capacitor reduction techniques and the grid
synchronization methods are presented. The objectives of this work is stated at the end
of this chapter.
The remainder of the work is organized as follows:
Chapter 2 describes the design of the inverters power stage including the selection of
the switching circuits, DC-link capacitor consideration, and the output lter design.
Chapter 3 focuses on the control methods of the inverter which consist of a current
controller along with a low complexity grid synchronization technique and a DC voltage
controller.
Chapter 4 shows the PSCAD/EMTDC simulation results for the grid connected in-
1
Chapter 1. Introduction 2
verter. The validation of the current loop control and the voltage control are shown.
Chapter 5 shows the experimental results for the grid connected inverter. The steady
state operation and the transient response results of the inverter are shown and discussed.
Chapter 6 summarizes the thesis, and the future directions that can be investigated.
1.1 Background and Motivation
Integration of PV power generation systems in the grid plays an important role in securing
the electric power supply in an environmentally-friendly manner. Grid-connected PV
inverters are needed to extract the energy from the PV modules and feed it into the utility
grid while ensuring the power quality follows certain grid interconnection standards such
as IEEE-1547 [1].
In addition to large scale rural solar farms, the market of residential PV power gen-
erations has grown rapidly in recent years by the encouragement of local governments
and utility companies. For example, in 2009, Ontario Power Authority (OPA) launched
the micro-feed-in tari (microFIT) program to provide opportunities for homeowners,
farmers and small business owners to develop mircro renewable electricity generation
projects (10 kilowatts or less in size). Under the microFIT program, they will be paid a
much higher price for the electricity that the projects produce comparing to the standard
price people pay for their electricity. Particularly, for PV rooftop generation, the contract
price paid is 80.2 cents/kWh, whereas the blended rate of electricity in Ontario is 7.74
cents/kWh in the summer period. Therefore, with the help of such stimulation programs,
a growing market exists for residential PV inverters. Many companies such as National
Semiconductor and Enphase are expanding their business in the area of residential PV
inverters.
Unlike rural solar farms, residential PV modules require the grid-connected inverters
to be small, low-power and single-phase units. In North America, a split phase electricity
distribution system, also referred to as 3-wire, single-phase, mid-point neutral system, is
commonly used for single family residential and light commercial applications. There are
two live conductors in the system providing 240V between them; both live conductors
are referred as hot wires. The neutral wire is centre tapped from the output of the
distribution transformer, thus the hot to neutral voltage is 120V. The safety ground
connects cases of equipments to earth ground as a protection against faults. Such a
system makes it possible to supply 120V for ordinary receptacle service at home, while
also having 240V available for major appliances such as electric ranges and water heaters.
The frequency of the system is 60Hz. Therefore, single phase, 60Hz and 120/240V point
of common coupling (PCC) voltage can be used as a basic guideline when designing the
grid connected PV inverters and their controls.
As more distributed resources (DR) become integrated into the grid at the distri-
bution level, the trend that the DR units actively supply reactive power to the grid
has appeared. Having the capability of supplying reactive power with local DRs would
not only help grid stability [24] but will also partially reduce the burden of delivering
reactive power from central generation to the local distribution level for compensating
of inductive load [5]. Although purposeful injection of reactive power or attempting to
regulate voltage by a distributed generator is not currently permitted by IEEE-1547,
there is a trend of changing such standard based on the reasons mentioned above. In
fact, in recent years, researchers have explored methods for single phase inverters to gain
the ability of supplying reactive power to the grid [6] [7]. Therefore, it is benecial that
the single phase DC/AC grid connected inverter would have the feature of controlling
reactive power.
This thesis will therefore focus on designing a single phase grid connected DC/AC
inverter with VAR control for residential PV application.
1.2 Literary Review
1.2.1 Grid connected PV systems
Grid connected PV systems are categorized based on the number of power stages. The
past technology used single stage centralized inverter congurations. The present and fu-
ture technology focus predominantly on the two stage inverters where a DC/DC converter
is connected in between the PV modules and the DC/AC inverter.
1.2.1.1 Single Stage Centralized Inverters
A general summary of the evolution of the PV system congurations are described in [8].
The rst generation of the grid connected PV systems directly connect centralized grid
connected DC/AC inverter to an array of PV modules, shown in Figure 1.1(a). The
PV modules are connected in series, also referred to as PV strings, in order to provide
sucient output voltage. The PV strings are then connected in parallel through string
diodes in order to achieve high power production. In this conguration, the centralized
DC/AC inverter is subjected to handle, maximum power point tracking (MPPT), grid
current control and voltage amplication if necessary. Although the conguration is
simple, the drawbacks are substantial. One of the biggest is the poor energy harvesting
capabilities of the centralized MPPT due to shading, panel mismatch and degradation
factors [9]. Other drawbacks may include losses in the string diodes and the non-exibility
of the design.
Reduced power versions of the centralized inverter conguration were developed to
have separated MPPT for each PV string, Figure 1.1(b). The systems are referred to as
string inverters. They oer higher energy harvesting than central converters and eliminate
the loss associated with string diodes. Although this conguration is advantageous in
the two aforementioned ways, people would still try to seek a more exible design which
allows them to start their PV power plants with fewer modules and to easily enlarge the
DC
AC
AC grid
PV string
Stringdiodes
(a) Centralized inverter conguration
DC
AC
PV string
DC
AC
PV string
AC
grid
(b) Reduced centralized inverter con-
guration
Figure 1.1: Past technology - centralized inverters
system in the future. For this reason, DC/DC converters can be connected in between
the PV modules and the DC/AC inverters to provide MPPT and voltage amplication
so that fewer PV modules can be used in each string. Further system enlargements can
also be easily achieved with the help of the DC/DC converters.
1.2.1.2 Two Stage Inverters
In order to improve the energy harvesting capabilities and design exibility, dedicated
DC/DC converters, which perform MPPT for each PV string can be connected in the
middle between the PV modules and the DC/AC inverter [8], Figure 1.2. The system
shown in Figure 1.2(a) has its PCC at the AC terminal. This system type benets
from its modularity and the capability of plug-and-play installation by users that possess
limited knowledge of electrical systems. The output from the DC/DC converter in this
conguration can be either a low ripple DC voltage, or a modulated current that follows a
rectied sine wave. In the latter case, the DC/DC converter handles MPPT and output
current regulation while the DC/AC inverter switches at the grid frequency to unfold
the rectied sine wave. Reference [10] is an example of the unfolding conguration. The
DC
AC
DC
DC
DC
AC
DC
DC
AC
grid
PV string
PV string
(a) Two stage inverter PCC at AC terminal
DC
AC
DC
DC
DC
DC
AC
grid
PV string
PV string
(b) Two stage inverter PCC at DC/AC inverter in-
put
Figure 1.2: Two stage inverter congurations
slow switching scheme of the DC/AC inverter allows usage of slow switching devices, e.g
BJTs. In the case that the output is a low ripple DC voltage, the DC/DC converter
performs MPPT and voltage amplication if necessary. The DC/AC inverter is then a
voltage sourced inverter (VSI) which handles the output current regulation and DC bus
voltage regulation. The VSI usually uses a self commutating half bridge or full bridge
conguration as its switching circuit.
In the system shown in Figure 1.2(b), multiple DC/DC converters feed a single VSI.
The DC/DC converters handle MPPT and voltage amplication if necessary and the
central DC/AC inverter is again a VSI which handles the output current regulation and
intermediate DC bus voltage regulation. In this thesis, we focus on the VSI design of the
DC/AC inverter which is commonly used in the two stage PV inverter systems of types
shown in Figure 1.2(a) and 1.2(b) above.
1.2.2 Controls of the VSI
There are three major output current control techniques for the single phase VSI: hys-
teresis band, predictive, and sinusoidal pulse width modulation (SPWM) control [11] [12].
Traditional hysteresis controllers normally have an error band within a xed range [13].
In such controllers, if the measured output current is lower than the lower limit of the
hysteresis band of the reference current, the bridge increases its output voltage, increas-
ing the current. On the contrary, when the output current is higher than the upper
limit of the hysteresis band of the reference current, the bridge reduces its output volt-
age, decreasing the current. This type of controller has the advantage of simplicity and
robustness, but the xed error band would cause constant varying switching frequency,
which may increase the complexity of designing the output lters and the heat sinks of
the switches. An example of an adaptive hysteresis band current controller which can
achieve almost constant switching frequency to overcome the aforementioned problems
is stated in [14].
Predictive controllers calculate the required bridge output voltage to force the mea-
sured output current to follow the reference value. This type of control oers a potential
to achieve precise current control with minimum distortions [15] [16]. However, the
controller needs complicated calculations and requires a very accurate knowledge of the
system parameters. Reference [17] proposed an adaptive predictive current controller
which has more tolerance for system parameter mismatch, i.e. unexpected changes of
actual inductance with magnetic eld intensity, temperature, etc. A fuzzy logic controller
was also proposed in [18] which provides robust performance under parameter and load
disturbances.
The SPWM control has a long history and is easy to implement. The traditional
method of SPWM control uses a proportional-integral (PI) compensator in the feedback
loop to regulate the output current. However, while PI compensators have excellent
performances on regulating DC quantities, tracking a sinusoidal current reference would
lead to steady state magnitude and phase errors [19]. Then, over the past two decade,
researchers have explored use of proportional-resonant (PR) controller, while can provide
innite gain at the reference signals oscillating frequency [20] [21]. The PR controller,
P
out
t 1/(2f
g
)
V
g
rms
I
g
rms
Figure 1.3: Instantaneous output power of a single phase inverter at unity displacement
factor
based on the internal model principle rst proposed by Francis and Wonham [22],
has the ability to eliminate the steady state error when tracking a sinusoidal wave and is
commonly used in single phase inverter systems [21,23,24]. This thesis takes advantage of
the PR compensator and implements the current controller using SPWM control theory.
1.2.3 Reducing the Size of the DC-link Capacitor
One of the challenges when designing single phase VSIs for PV application is the selection
of the DC-link capacitor. The instantaneous output power of a single phase inverter is
graphically shown in Figure 1.3, which contains a constant and a double-line frequency
power component. Therefore, the DC-link contains power pulsation with twice the grid
frequency. Often, large electrolytic capacitors are connected to the DC-link to absorb
this power pulsation so that the DC-link voltage ripple can be kept small. However, most
PV module manufactures oer 25 year warranties on 80% of the initial eciency and ve
years warranty on materials and workmanship [8]. Therefore, electrolytic capacitors with
large capacitance can not be used in PV applications because of their short lifetime.
Many techniques were proposed to reduce the size of the DC-link capacitor while
maintaining a good inverter power quality so that a more reliable lm type capacitor can
DC
AC
vg(t)
iin
idc
idecouple
C
dc
C
decouple
S
1
S
2
Decouplingcircuit
Figure 1.4: An example of an active power decoupling circuit
be used.
Methods like [25] and [26] uses an auxiliary circuit to circulate the double-line fre-
quency ripple power. Figure 1.4 is an example shown in [25], where the bidirectional
DC/DC converter is used as the decoupling circuit and the decoupling capacitor is al-
lowed to contain a large ripple component. In addition to the fact that an auxiliary circuit
would increase the energy loss, the inductor and the capacitor size used in the auxiliary
circuit has to be suciently large. Meanwhile, the switches used in the auxiliary circuit
must have rating comparable to the main power stage switches. Therefore, although
such methods can solve the problem of double-line frequency ripple, they are not a viable
solution considering the extra cost and energy loss associated with the introduction of
the auxiliary circuit.
Other methods [27] and [28] use control methods such as predictive and hysteresis
band control on the DC-link voltage. Both methods were able to average out the
double-line frequency ripple by only sampling the DC-link voltage every AC cycle so
that the output current would stay unaected by the large ripple component. This thesis
utilizes a notch lter in the control loop to average out the double-line frequency that
appeared on the DC-link voltage. A detail analysis of the DC-link capacitor can be found
in Section 2.3.
1.2.4 Grid Synchronization Techniques
A conventional method of grid synchronization for grid connected DC/AC inverter is to
duplicate the grid voltage so that output current reference has the same phase as the
grid voltage [30]. While this method is simple, it carries the distortions and transients
from the grid to the output current, which is undesirable for grid connected applications.
In addition, this method of grid synchronization cannot provide inverters the ability of
controlling reactive power ow.
Phase locked loops (PLL) are commonly used in the single phase grid connected
inverters. Stationary frame PLLs only take the grid voltage as the input and do not
require additional signal. The typical stationary frame PLL employs a sinusoidal multi-
plier phase detector (PD), a loop lter (LF) and a voltage controlled oscillator (VCO).
Reference [31] modied the stationary frame PLLs with additional state feedback terms.
These feedback terms increase the synchronization speed, improve the immunity to input
noise and disturbances, and eliminate the double-line frequency ripple term generated
from the PD.
Synchronous frame (dq) PLLs are also commonly used in the modern grid connected
inverters. Such types of systems convert the oscillating grid voltage and its emulated
orthogonal component () to DC quantities (dq) using - dq transform. Then a PI
regulator can be used to regulate either V
d
or V
q
to be zero so that the phase of the d
or q component can be locked. The methods of generating the orthogonal component
are dierent. In [32], a all pass lter is used on the input to have the phase of the gird
voltage delayed by 90
. However, the all pass lter would also carry distortions from
the input. Others such as [33] and [34] generate the orthogonal component based on a
second order generalised integrator (SOGI). This structure eectively lters out the high
frequency distortion on the input and the orthogonal component before they are fed into
the - dq transform. The synchronous frame PLLs, although not explicitly specied,
has the potential to provide sucient phase information to the controller for the reactive
current reference generation. This eectively allows the inverter to have the ability of
controlling reactive power ow. Although this type of PLLs has the aforementioned
merits, its implementation process can be complicated due to the need for an orthogonal
component generator and sin and cos operations in the - dq transform.
This thesis proposes a low complexity grid synchronization method which extracts
both the parallel component and the orthogonal component from the grid voltage while
suciently ltering out grid distortions. The grid synchronizer is easy to implement and
provides the inverter the capability of controlling the reactive power generation without
the need for dq frame transformation.
1.3 Objectives
The objectives of this works are as follows:
Ensure that the voltage on the DC side of the VSI and the output current are well
regulated by choosing appropriate inverter topology, the output lter conguration
and proper control methods.
The output current should meet the standard associated with larger 3-phase PV
inverters as laid out in IEEE-1547. This will enable grid code compliance if a large
number of inverters are clustered together and grid interfaced at the same PCC.
Use high reliable energy storage components (i.e. lm capacitors) to increase the
life-span of the inverter in a low cost manner.
Introduce a new method of grid synchronization which gives the inverter the capa-
bility of controlling the reactive power generation at minimal computational burden.
Exploit new generation MOSFETs and low cost MCUs to maximize switching fre-
quency and drive down output lter size and cost.
Chapter 2
Single Phase Grid Connected
Inverter Design
In this chapter, the design of the single phase PV inverter power stage is described,
Figure 2.1. Firstly, the inverter design specications are given. Secondly, based on the
specications, the choice of the switching scheme is briey described. Thirdly, the selec-
tion of the DC-link capacitor is discussed based on its lifetime and size. Following this,
the design equations on DC-link capacitance are developed based on the power balance
and double-line frequency ripple voltage. Finally, the design guide for the output lter
is discussed based on the IEEE-1547 standard and the lter conguration is described.
2.1 Inverter Specications
The basic specications for the inverter design are listed in Table 2.1. Since the design
primarily focuses on the control and the grid synchronization method of the inverter,
the eciency target of the inverter is not specied because it is outside of the scope.
Although maximizing eciency is not the focus of this work, loss considerations still
drive selection of a viable converter topology.
In addition, Figure 2.2 illustrates a general waveform of the DC-link voltage to show
13
Chapter 2. Single Phase Grid Connected Inverter Design 14
v
g
(t)
+
-
i
g
(t)
Lg
Li
Cf
Rd
+
-
sa sb
sa
low
sb
low
i
dc
(t)
Cdc
i
gn
(t)
v
dc
(t)
v
t
(t)
Figure 2.1: Power stage conguration of the single phase PV inverter
the denition of the nominal DC-link voltage and the ripple component.
Rated grid voltage, V
rated
g
250V (RMS)
Rated grid current, I
rated
g
10A (RMS)
Switching frequency range, f
sw
>20kHz,<45kHz
Nominal DC-link voltage, V
n
dc
400V
Percentage DC-link voltage ripple (peak to nominal) 10%
Table 2.1: Inverter specications
2.2 Switching Circuit Conguration
A full bridge conguration with SPWM unipolar voltage switching scheme is used (Fig-
ure 2.3) as the switching circuit of the inverter. By selecting the full bridge conguration,
the minimal allowed DC-link voltage can be set to be the peak value of the AC grid volt-
age (plus margins). Thus, power MOSFETs, instead of higher voltage IGBTs, can be
used as the switching devices which enables use of a high switching frequency (> 20kHz)
without indroduction of excessive switching loss.
Furthermore, showing in Figure 2.3(d), using unipolar voltage switching scheme eec-
v
dc
(t)
v
dc,ripple
(t)
V
dc
n
t
Figure 2.2: Generic DC-link voltage waveform
tively moves the rst major harmonic of the bridge output voltage from order m
f
1 to
the order of 2m
f
1, where m
f
is the frequency modulation ratio - the ratio between the
switching frequency and the fundamental frequency. The output lter thus reduces its
size for free. Since this full bridge conguration with SPWM unipolar voltage switch-
ing scheme is commonly used in voltage sourced inverters, further investigations will not
be presented in this thesis. A full detail analysis can be found in [35].
2.3 DC-link Capacitor
This section discusses the two types of capacitors that can be used as the DC-link buer-
ing capacitor. A brief comparison is made based on their life time and power decoupling
ability. Methods of ensuring the inverters power quality while using a capacitor that has
a small capacitance are also discussed. Finally, the calculation of the DC-link capacitance
is shown in this section.
2.3.1 Electrolytic Capacitors vs. Film Capacitors
The DC-link capacitor is important for the power decoupling between the input power to
the inverter and their output power to the utility grid. Normally, electrolytic capacitors
are used for their large capacitance and low cost. However, in PV applications where the
+
-
vdc(t)
+
-
vt(t)
sa sb
sa
low
sb
low
A
B
(a) Full bridge conguration
t
v
r
e
f
(
-
v
r
e
f )
v
s
a
w
0
(b) Unipolar SPWM switching scheme
t
vdc
-vdc
0
vt
vt,fund(t)
(c) Waveform of the bridge output voltage
dc
h t
v
V)
(
h
0
0.2
0.4
0.6
0.8
1.0
1
mf 2mf 3mf 4mf
(2mf-1) (2mf+1)
(d) Harmonics on the nominlized frequency spectrum
Figure 2.3: Full bridge conguration with PWM unipolar voltage switching scheme
inverters are usually exposed to outdoor temperatures, the lifetime of such electrolytic
capacitors is shorten drastically according to the equation below [8] [36]:
L
op
= L
op
(0) 2
T
0
T
h
T
(2.1)
where L
op
is the operational lifetime, L
op
(0) is the specied operational lifetime at the
hot-spot temperature T
0
(can be found in the product datasheets), T
h
is the operating
temperature and T is the degree Celsius increase that would results in half the oper-
ational life (also can be found in the product datasheet). Typically, L
op
(0) is between
3000 hours to 6000 hours (8 months to 16 months) at 85
C for electrolytic capacitors

with rated voltage above 400V [37].
In PV applications, since most PV module manufactures oer 25 year warranties on
80% of the initial eciency and ve years warranty on materials and workmanship [8],
the lifetime of the electrolytic capacitors have become a major limiting component inside
a PV inverter.
Film capacitors are a clear the alternative given their long life expectancy and wide
operating temperature range. Unfortunately, lm capacitors are far more expensive than
the electrolytic ones in term of cost per farad, hence the size of the capacitance has to
be smaller to keep the price of the capacitor acceptable. However, smaller capacitance
would weaken the power decoupling ability of the DC-link capacitor which may cause
DC-link voltage uctuations that lead to distortion of the inverter output current to the
grid.
There are two factors that can cause undesirable DC-link voltage variations. The
rst one, which can be referred to as the transient DC uctuation is caused by the rapid
increase/decrease of the input power owing into the DC-link capacitor. The quality
of the output current can be optimized by using a very fast current controller or by an
optimal current adjustment method stated in [29] and [28]. However, in PV application,
the chance of rapid DC input power variation is little due to the nature of the sun as
well as the processing delay of MPPT in the front end DC/DC converter. Therefore, the
transient DC uctuation is not a major concern when designing a VSI for PV application.
The second factor, which can be referred to as the AC uctuation of the DC-link
voltage is caused by the double-line frequency ripple power generated from the grid
side (refer to Equation (2.4)). This double-line frequency ripple component can couple
through the DC voltage control loop to cause a signicant amount of distortion on the
current reference signal.
Therefore, methods need to be taken so that the inverter output current is immune
to the double-line frequency ripple on the DC-link voltage. A notch lter or an average
lter can be applied to the feedback signal of the DC-link voltage in the voltage control
loop, so that this double-line frequency ripple component is ltered out before entering
the voltage controller. This prevents the output current from having distortions that
are resulted from the DC voltage control loop. Furthermore, we also employ a nonlinear
DC voltage feedforward to the output of the current controller so that the modulation
signal that is sent to the SPWM modulator cancels out the eect of the double-line
frequency ripple that appears on the DC-link (refer to Figure 3.1 in Chapter 3). A
further discussion on the double-line frequency ripple component reduction method can
be found in Section 3.3.
In this thesis, a notch lter is employed in the DC voltage control loop to keep the
output current from the distortion caused by the double-line frequency ripple voltage. As
a result, the inverter has a relatively large tolerance on the voltage ripple that appeared
on the DC-link, thus a lm capacitor with relatively small capacitance can be used to
keep the DC-link capacitor at an acceptable price.
2.3.2 Sizing the DC-link Capacitor
To limit the magnitude of the double-line frequency ripple voltage to the specied level,
the DC link capacitor is sized according to the following equations:
Assuming the grid voltage and the grid current are:
v
g
(t) =

V
g
cos(
g
t) (2.2)
i
g
(t) =

I
g
cos(
g
t ) (2.3)
Then the instantaneous output power can be easily obtained as:
P
out
(t) =

V
g

I
g
cos(
g
t)cos(
g
t ) = V
rms
g
I
rms
g
cos + V
rms
g
I
rms
g
cos(2
g
t ) (2.4)
This can be rewritten to be:
P
out
(t) = Scos + Scos(2
g
t ) (2.5)
where S is the apparent power which has a unit of VA. Then assuming (i) the instan-
taneous input power equals to the instantaneous output power of the inverter, (ii) the
DC capacitance lters out the high switching frequency components in the DC current
i
dc
(t), and (iii) the DC-link has a nominal voltage of V
n
dc
,
V
n
dc
i
dc
(t)
= Scos + Scos(2
g
t ) (2.6)
The i
dc
(t) can be separated as a DC component, I
dc
and an AC component, i
dc,ripple
(t).
Then the double-line frequency component can be extracted such that:
V
n
dc
i
dc,ripple
(t) = Scos(2
g
t ) (2.7)
Rearranging the above equation yields:
i
dc,ripple
(t) =
S
V
n
dc
cos(2
g
t ) =

I
dc,ripple
cos(2
g
t ) (2.8)
Then the capacitance of the DC-link capacitor can be easily obtained given the mag-
nitude of the maximum allowed ripple voltage, V
max
dc,ripple
:
C
dc
=
I
dc,ripple
2
g
V
max
dc,ripple
=
S
2
g
V
n
dc
V
max
dc,ripple
(2.9)
Finally, substituting, these parameters from the inverter specications.
C
dc
=
2.5kV A
2 377rad/s 400V 40V
= 207.2F (2.10)
Based on this, a 230F Cornell Dubilier lm type capacitor which as a life expectancy
of 200,000 hours (44 years) at 60
C was selected to be used in the prototype.

2.4 Output Filter Design
As discussed in Section 2.2, the lowest order harmonics that appeared on the harmonic
spectrum of the output voltage of the full-bridge are at the sidebands of 2m
f
. Since the
inverter switching frequency is set to be greater than the audible frequency (20kHz), the
lowest order of the harmonics of the inverter is (2m
f
1) = 665. According to the IEEE
DR interconnection standard, IEEE-1547 [1]
1
, any current harmonic which has an order
that is greater than 35 must have a magnitude that is no greater than 0.3% of the rated
current of the DR output, and the total demand distortion (TDD)
2
has to be under 5%
(the original harmonic regulation table in IEEE-1547 can be found in Appendix A). If
the lowest order harmonics of this inverter can be reduced to 0.3%, the TDD can be
readily kept under 5%. Thus, the primary design guide for the inverter output lter is to
make the magnitude of the major harmonic current of the inverter less than 0.3% of the
rated current. In addition, as IEEE-1547 also stated, the harmonic current injections
shall be exclusive of any harmonic currents due to harmonic voltage distortion present in
the Area Electrical Power System (EPS) without the DR connected, the output lter
vg(t)
vt(t)
Li Lg
Cf
Rd
ig(t)
+
-
+
-
LCL Filter
Figure 2.4: Output LCL lter of the inverter
design will not take harmonic grid voltage distortions into consideration.
2.4.1 Filter Conguration
A third order LCL lter, Figure 2.4, was used to meet the aforementioned harmonic
reduction target. A switching frequency of 30kHz was selected based on considerations
for the lter size and the practical implementation of the digital controller.
v
t
(t) stands for the terminal voltage or the output voltage of the full bridge, which
consists of a fundamental component and higher order harmonics components. Solv-
ing the grid current in Laplace domain using superposition yields the following transfer
functions:
I
g
(s)
V
t
(s)
Vg=0
=
sC
f
R
d
+ 1
s
3
L
i
L
g
C
f
+ s
2
C
f
R
d
(L
i
+ L
g
) + s(L
i
+ L
g
)
(2.11)
I
g
(s)
V
g
(s)
Vt=0
=
s
2
L
i
C
f
+ sC
f
R
d
+ 1
s
3
L
i
L
g
C
f
+ s
2
C
f
R
d
(L
i
+ L
g
) + s(L
i
+ L
g
)
(2.12)
From the above Equation (2.11) and (2.12), one can observe that the grid current i
g
(t)
1
IEEE-1547 directly references the grid current harmonic distortion limits for general distribution
systems stated in IEEE-519 [38]
2
TDD: the total root-sum-square harmonic current distortion, in percent of the maximum demand
load current or the rated DR current capacity [1]
depends on both the terminal voltage v
t
(t) and the grid voltage v
g
(t). As discussed before,
the output lter design will not take harmonic grid voltage distortion into consideration
because IEEE-1547 allows the presence of harmonic current distortion caused by grid
voltage distortion. Therefore, Equation (2.12) will not be taken into consideration in
output lter design.
The terminal voltage v
t
(t) contains a fundamental component and higher frequency
components which could result in higher frequency distortions on the grid current i
g
(t).
Therefore, Equation (2.11) is used as the output lter transfer function as:
H
f
(s) =
I
g
(s)
V
t
(s)
Vg=0
=
sC
f
R
d
+ 1
s
3
L
i
L
g
C
f
+ s
2
C
f
R
d
(L
i
+ L
g
) + s(L
i
+ L
g
)
(2.13)
The RMS value of the higher order frequency components of v
t
(t) can be calculated
using the look up table from [35] (refer to Appendix C), given the nominal DC-link
voltage V
n
dc
:
|V
t
(jh
g
)| =
1
2
2
(
V
Ao
)
h
1/2V
n
dc
V
n
dc
2
=
1
2
k(h)V
n
dc
(2.14)
The (
V
Ao
)
h
is the peak value of each harmonic voltage between one leg of the bridge
and the centre point of the DC-link, v
Ao
(t). In full bridge conguration, v
t
(t) = 2v
Ao
(t).
k(h) =
(
V
Ao
)
h
1/2V
n
dc
is tabulated as a function of m
a
and the orders of harmonics (refer to
Appendix C for details about the harmonics table). Therefore, combining (2.13) and
(2.14), the RMS value of the harmonic current can be expressed as:
|I
g
(jh
g
)| =
1
2
|H
f
(jh
g
)| k(h) V
n
dc
(2.15)
Remember that |I
g
(jh
g
)| can not exceed 0.3% of the rated current of the inverter.
Therefore, given the RMS value of the rated grid current I
rated
g
the following relationship
can be derived:
0dB

g i
L L
1
g i f
g i
L L C
L L
-70dB
376614
-20dB/dec
-60dB/dec
PeakdependsonR
d
|Hf(jw)|
Figure 2.5: Magnitude plot of the output lter transfer function H
f
(s)
|H
f
(jh
g
)| k(h) V
n
dc
2 I
rated
g
< 0.3% (2.16)
Rewrite for |H
f
(jh
g
)|, then
|H
f
(jh
g
)| <
0.3%
2 I
rated
g
V
n
dc
k(h)
(2.17)
Given from Appendix C, the worst case k(h) at 2m
f
1 is 0.37. Then, substituting
the parameters from the inverter specication and using a switching frequency of 30kHz,
we get the magnitude of the lter transfer function |H
f
(jh
g
)| at (2m
f
1):
H
f
_
j
_
(2m
f
1)377
_
_
H
f
_
j(376614)
_
=
0.3%
2 10A
400V 0.37
= 2.86 10
4
= 70dB
(2.18)
With the transfer function of the lter derived in Equation (2.13), the generic magni-
tude plot of H
f
(s) can be drawn as shown in Figure 2.5. At = 376614, the magnitude
of H
f
(j376614) from the magnitude plot of H
f
(j) should at most be -70dB. This is the
guideline of choosing the values for L
i
, L
g
, C
f
and R
d
. Finally, the LCL lter compo-
nents are chosen following this guideline and the values of each component are shown in
Table 2.2. The MATLAB magnitude plot of the lter is shown in Figure 2.6, and it can
L
i
L
g
C
f
R
d
300H 100H 30F 1.5
Table 2.2: Output lter parameters and their chosen values
10
0
10
1
10
2
10
3
10
4
10
5
10
6
100
80
60
40
20
0
20
40
60
80
M
a
g
n
i
t
u
d
e

(
d
B
)
Bode Diagram
Frequency (rad/sec)
Figure 2.6: Magnitude plot of H
f
(j) using selected lter components values
be seen that with the components chosen in Table 2.2, the magnitude of H
f
(j) is under
-70dB at =376614.
Chapter 3
Controller Design
The discussion of the controller for the inverter can be divided into three parts: 1) current
controller, 2) grid synchronization and 3) DC voltage controller. A block diagram of the
controller is shown in Figure 3.1. Similarly to the control of a three phase VSI, the
current controller is used to regulate the current injected into the grid and the voltage
controller is used to regulate the DC voltage at a desirable level. Unlike the three phase
VSI, the active and the reactive power of the single phase VSI cannot be controlled by
varying i
d
and i
q
in the d-q frame. Instead, a grid synchronizer block is proposed to
create a grid current reference which has the control of the active and the reactive power
ow.
3.1 Current Controller
A single phase feedback current loop is used to regulate the grid current. A proportional
resonant (PR) compensator is used to track a sinusoidal current reference signal. The
plant modelling, PR compensator design and the closed loop stability is discussed in this
section. The current controller block diagram is shown in Figure 3.2.
25
Chapter 3. Controller Design 26
vg(t)
+
-
ig(t)
Lg
Li
Cf
Rd
+
-
sa sb
sa
low
sb
low
idc(t)
Vdc
ref
G
v
(s)
NotchFilter
vdc
fil
+
-
ev
ref
g
i
||
Grid
Synchronization
ref
g
i

ref
g
i
G
i
(s)
vdc
vg(t)
ig
+
-
ei
VoltageController
Current Controller
Grid
Synchronization
Cdc
SPWM
vref
a
vref
b
sa sa
low
sb sb
low
) (
1
t v
dc
*-1
ign(t)
vdc(t)
vt(t)
DC
voltage
feedward
Figure 3.1: The inverter controller overall block diagram
3.1.1 Plant Modelling
Before designing the loop compensator, the plant model of the inverter can be derived
from Section 2.4.1 by combining equation (2.11) and (2.12), which yields:
I
g
(s) = G
f
(s)
_
s
2
L
i
C
f
+ sC
f
R
d
+ 1
sC
f
R
d
+ 1
V
g
V
t
_
(3.1)
where,
G
f
(s) =
sC
f
R
d
+ 1
s
3
L
i
L
g
C
f
+ s
2
C
f
R
d
(L
i
+ L
g
) + s(L
i
+ L
g
)
(3.2)
Since the magnitude and phase response of
s
2
L
i
C
f
+sC
f
R
d
+1
sC
f
R
d
+1
are 0dB and 0
at the
fundamental frequency of V
g
(j). Therefore, equation (3.1) can be simplied to equa-
tion (3.3).
I
g
(s)
.
= G
f
(s)(V
g
V
t
) (3.3)
G
i
(s) G
f
(s)
Vg(s)
+
-
Ig(s)
Ig
ref
(s)
+
-
Vt(s)
Plant
Current Controller
Figure 3.2: Current controller block diagram
Given the plant model, a PR compensator, G
i
(s) is then added to the closed loop
and the equivalent closed loop diagram can be seen in Figure 3.2.
3.1.2 Proportional Resonant Controller
Normally in a three phase VSI SPWM based current controller, the 60Hz three phase grid
signals can be transformed into DC quantities by performing the ABC to d-q transform
(Parks transform) so that the current reference can be set to be a DC quantity and a
PI compensator is sucient to track the DC reference signal. However, in a single phase
inverter, the grid signals cannot be transformed into DC quantities so that the reference
signal to the feedback loop has to be sinusoidal.
In high switching frequency converters, such as power factor corrected (PFC) power
supplies, non-DC quantities can still be regulated using a simple PI compensator because
of their fast switching frequency, i.e. 200kHz. However, in this PV inverter, switching at
such high frequency is not an option considering the switching loss associated with the
MOSFETs and their reverse conducting diodes that are connected to a DC-link with a
relatively high voltage level. Therefore, for this PV inverter that is switching at 30kHz, a
PI compensator is no longer sucient to track the reference. A higher order compensator
is needed to used as a substitute.
According to Figure 3.2, the relationship between the input and the output of the
current loop can be derived as:
I
g
(s) = H
i
(s)I
ref
g
(s) + H
v
(s)V
g
(s) (3.4)
where,
H
i
(s) =
G
i
(s)G
f
(s)
G
i
(s)G
f
(s) 1
(3.5)
H
v
(s) =
G
f
(s)
1 G
i
(s)G
f
(s)
(3.6)
To successfully track the i
ref
g
(t) signal without steady state errors, the magnitude of
H
i
(j) in Equation (3.5) has to equal to 1 at the fundamental frequency of the i
ref
g
(t).
Thus, it is clear that if G
i
(j) has a innite gain at the fundamental frequency, H
i
(j)
would have a unity gain. On the other hand, if G
i
(j) has a innite gain at the fundamen-
tal frequency, H
i
(j) in Equation (3.6) would results in 0 at the fundamental frequency
so that the H
v
(j) term can be neglected. Therefore, it is not necessary to have the grid
voltage feed-forward in the current control loop. To conclude, the compensator, G
i
(j)
has to have a innite gain at the fundamental frequency in order to track the current
reference, i
ref
g
(t).
A proportional-resonant (PR) compensator meets the aforementioned controller re-
quirement. An ideal PR compensator which has an innite gain at
o
has a transfer
function shown in Equation (3.7) and a generic bode plot is shown in Figure 3.3(a).
However, the innite gain of the controller leads an innite quality factor of the system,
which cannot be achieved in either analog or digital controller implementation. Further-
more, since the gain of an ideal PR compensator at other frequencies is low, it is no
adequate either to eliminate the higher order harmonics inuenced by the grid voltage or
to react to slight grid frequency variation. This is undesirable because the harmonic grid
voltage distortion would results in a signicant amount of harmonic grid current distor-
tion. Therefore, a damping term is introduced to form a non-ideal PR compensator
transfer function shown in Equation (3.8). This damping term reduces the innite gain
0
50
100
150
200
250
300
M
a
g
n
i
t
u
d
e

(
d
B
)
10
1
10
2
10
3
10
4
450
405
360
315
270
P
h
a
s
e

(
d
e
g
)
Bode Diagram
Frequency (rad/sec)
(a) Ideal PR compensator
0
5
10
15
20
25
30
M
a
g
n
i
t
u
d
e

(
d
B
)
10
0
10
1
10
2
10
3
10
4
10
5
90
45
0
45
90
P
h
a
s
e

(
d
e
g
)
Bode Diagram
Frequency (rad/sec)
(b) Non-deal PR compensator
Figure 3.3: Bode plot of (a) ideal PR compensator, (b) non-ideal PR compensator, K
c
p
=1,
K
c
i
=2000, =0.1
at the fundamental frequency to a nite large gain but increases the bandwidth of the
compensator. A generic bode plot of the non-ideal PR compensator is shown in Fig-
ure 3.3(b). In order to understand the non-ideal PR controllers behaviour, three groups
of bode plots are drawn in Appendix B to demonstrate how the PR controllers response
varies by changing the each parameter in the transfer function.
G
i
(s) = K
c
p
+
K
c
i
s
s
2
+
2
o
(3.7)
G
i
(s) = K
c
p
+
K
c
i
s
s
2
+ 2
o
s +
2
o
(3.8)
3.1.3 Closed-Loop Stability
The closed loop gain of the current control loop with the PR compensator can be simply
obtained by Equation (3.9). The PR compensators parameters and systems parameters
are chosen in Table 3.1.
T
c
(s) = G
i
(s)G
f
(s) =
_
K
c
p
+
K
c
i
s
s
2
+
o
s +
2
o
_
sC
f
R
d
+ 1
s
3
L
i
L
g
C
f
+ s
2
C
f
R
d
(L
i
+ L
g
) + s(L
i
+ L
g
)
(3.9)
K
c
p
K
c
i
L
i
L
g
C
f
R
d
3 20000 0.01 300H 100H 30F 1.5
Table 3.1: PR compensators parameters and systems parameters
The bode plot of the uncompensated loop gain and the compensated loop gain is
shown in Figure 3.4. It can be seen from the compensated current loop gain, the large
system bandwidth would give the current controller a fast response. Meanwhile, having
a phase margin of 50.9
demonstrates closed loop stability.

100
80
60
40
20
0
20
M
a
g
n
i
t
u
d
e

(
d
B
)
10
3
10
4
10
5
10
6
270
225
180
135
90
P
h
a
s
e

(
d
e
g
)
Bode Diagram
Gm = 9.43 dB (at 2.22e+004 rad/sec) , Pm = 90 deg (at 2.54e+003 rad/sec)
Frequency (rad/sec)
(a) Uncompensated current loop gain
100
50
0
50
100
M
a
g
n
i
t
u
d
e

(
d
B
)
10
0
10
1
10
2
10
3
10
4
10
5
10
6
225
180
135
90
45
0
P
h
a
s
e

(
d
e
g
)
Bode Diagram
Gm = 14.2 dB (at 3.33e+004 rad/sec) , Pm = 50.9 deg (at 1.12e+004 rad/sec)
Frequency (rad/sec)
(b) Compensated current loop gain
Figure 3.4: The bode plot of the uncompensated and compensated current loop gain
3.2 Grid Synchronization Method
A low complexity method of grid synchronization is introduced in this section. Eort has
been taken to minimize the computational processes of reproducing a parallel component
and an orthogonal component of the grid voltage by means of using only a two by two
state matrix. The reactive power can then be controlled once the orthogonal component
of the grid is obtained.
The grid voltage synchronizer consists of two parts: (i) a grid voltage estimator, (ii)
an amplitude identier. An overview of the grid synchronizer is shown in Figure 3.5.
3.2.1 Grid Voltage Estimator
The grid voltage estimator takes the grid voltage as its input and outputs one signal
which is aligned with the grid voltage (parallel component) and the other signal which is
90
leading the grid voltage (orthogonal component). This estimator has a state space
form of:
Gridvoltage
estimator
v
g
|| g
v
g
v
ref
g
i
||

Amplitude
identifier
g
V
ref
g
i

i
g
ref
Figure 3.5: Overview of the grid synchronizer and VAR controller

v
g
+
-
e=v
g
-x
1
x
1
y
e D x C y
e B x A x

x
1
=[1 0] y
Figure 3.6: Feedback loop of the grid voltage estimator
_
_
x
1
x
2
_
_
=
A
..
_
_
0
o
o
0
_
_
_
_
x
1
x
2
_
_
+
B
..
_
_
k
sync
0
_
_
(v
g
x
1
) (3.10)
_
_
v
g
v
g
_
_
=
_
_
y
1
y
2
_
_
=
C
..
_
_
1 0
0 1
_
_
_
_
x
1
x
2
_
_
The above state space form the estimator takes v
g
x
1
as its input and outputs x
1
as
the parallel component of v
g
. Thus, this essentially resembles a feedback loop illustrated
in Figure 3.6, where the output x
1
tracks v
g
.
The reference signal of this feedback loop is v
g
, a sinusoidal signal oscillating at the
grid frequency
g
. The state matrix

A provides the grid voltage estimator a internal
oscillator oscillating at the
o
. This provides the estimator an innite gain at
o
in the
frequency domain.
The k
sync
term introduces damping to the oscillator which widens the estimators
bandwidth and reduces the gain at
o
. As a result, x
1
tracks the input v
g
, at its funda-
mental frequency while also rejecting other harmonics that appeared on the grid voltage.
Following this, the output y
1
is denoted as v
g
to illustrate the its alignment with the
grid voltage and the output y
2
is denoted as v
g
to illustrate it is orthogonal to the
grid voltage. The state trajectory and the peak voltage phasor diagram are shown in
Im
Re
||
g
V
g
V
x1
x2
wo
(a) (b)
Figure 3.7: (a) State trajectory of the estimator, (b)Peak voltage phasor diagram of the
estimators input and outputs
Figure 3.7.
The state space form of the compensator (Equation (3.10)) can be further rewritten
to the standard state space form shown in Equation (3.11) so that v
g
is expressed as the
input to the estimator and the outputs are the parallel component and the orthogonal
component of v
g
.
_
_
x
1
x
2
_
_
=
A
..
_
_
k
sync

o
o
0
_
_
_
_
x
1
x
2
_
_
+
B
..
_
_
k
sync
0
_
_
(v
g
) (3.11)
_
_
v
g
v
g
_
_
=
_
_
y
1
y
2
_
_
=
C
..
_
_
1 0
0 1
_
_
_
_
x
1
x
2
_
_
3.2.1.1 Simulations of the Grid Voltage Estimator
The behaviour of this grid synchronizer was further analyzed by means of studying its
responses in both frequency and time domain.
First, the bode plot of each output of the compensators responses are shown in Fig-
ure 3.8. In Figure 3.8(a), the
V
g
(j)
Vg(j)
response has a magnitude of 0dB and a phase of
0
at the grid fundamental frequency and lters out distortions at any other frequen-
cies. In Figure 3.8(b), the
V
g
(j)
Vg(j)
response also keeps the magnitude at 0dB at the grid
fundamental frequency but only lters out distortions at higher frequencies. Meanwhile,
the phase of the
V
g
(j)
Vg(j)
response is at 90
at the grid fundamental frequency so that v

g
leads v
g
by 90
. It can also be observed from Figure 3.8, the more the k

sync
increases, the
less the synchronizer are sensitive to slight variations of the grid fundamental frequency
but more vulnerable to noise at other frequencies. Furthermore, the larger the k
sync
gets,
the wider the controllers bandwidth extends, which means the faster the v
g
locks on v
g
.
Then, the turn-on trajectories of the state variables x
1
and x
2
are shown in Fig-
ure 3.9 for dierent k
sync
values. Zero initial conditions are assumed in each case. From
the two plots, several observations can be extracted. First, the nal state trajectories are
identical circles proving that x
1
and x
2
are sinusoidal functions with 90
phase dierence.
Second, the radius of the circle equals to the magnitude of the grid voltage indicating
that both sinusoidal functions have an amplitude that equals to the magnitude of the
grid voltage. This eectively proves that the grid estimator resembles the fundamental
component of the grid voltage and emulates an orthogonal component with the same
magnitude. Third, with the initial conditions of states x
1
and x
2
equal to zero, the plot
with the larger k
sync
has a faster speed to reach the nal trajectory.
Furthermore, we investigate how well the grid estimator responses to inputs that
contain both harmonics and a frequency variation. Figure 3.10 shows the time domain
simulation based on the worst case conditions on the frequency variations of the grid
provided by IEEE-1547 standard [1] and the percentage voltage harmonics on the grid
provided by IEEE-519 standard [38]. According to IEEE-519, the worst case harmonics
that would appear on the grid voltage is 3% of the fundamental voltage at each harmonic,
with a total harmonic distortion (THD) of 5%. The worst grid frequency is 59.3Hz
according to IEEE-1547.
80
70
60
50
40
30
20
10
0
M
a
g
n
i
t
u
d
e

(
d
B
)
10
0
10
1
10
2
10
3
10
4
10
5
90
45
0
45
90
P
h
a
s
e

(
d
e
g
)
Bode Diagram
Frequency (rad/sec)
Ksync=100
Ksync=300
Ksync=500
Ksync=1000
(a) bode plot of
V
g
(j)
Vg(j)
100
80
60
40
20
0
20
M
a
g
n
i
t
u
d
e

(
d
B
)
10
0
10
1
10
2
10
3
10
4
10
5
0
45
90
135
180
P
h
a
s
e

(
d
e
g
)
Bode Diagram
Frequency (rad/sec)
Ksync=100
Ksync=300
Ksync=500
Ksync=1000
(b) bode plot of
V
g
(j)
Vg(j)
Figure 3.8: Bode plot of
V
g
(j)
Vg(j)
and
V
g
(j)
Vg(j)
x2
x1
g
V
(a) Turn on trajectory when k

sync
=200
x2
x1
g
V
(b) Turn on trajectory when k

sync
=600
Figure 3.9: Turn on trajectory of the estimators state variables with dierent k
sync
values
Normally, the harmonics that appeared on the grid voltage are predominately low
order odd harmonics due to thyristor bridges and diode rectiers in the system. The
harmonics that are multiple of three are mainly trapped inside the delta connection
of distribution transformers so that they are not presented in the local grid. There-
fore, the predominate harmonics that appeared on the local grid are in the order of
5
th
, 7
th
, 11
th
, 13
th
.... The simulation takes the worst case percentage of harmonics from
the lowest order and add them up until the worst case THD is reached. Based on this,
the simulation uses a 3% of each harmonic of 5
th
, 7
th
and 11
th
order so that they add up
to have a THD of 5% on the grid voltage. The worst case grid fundamental frequency of
59.3Hz is used in this simulation. k
sync
= 200 is used for the grid voltage estimator.
While Figure 3.10 illustrates the turn on transition of each state variables of the
estimator in time domain, Figure 3.11 shows the zoomed-in version of the results which
contain the distorted grid voltage, the desired x
1
and x
2
waveform and the resulting x
1
and x
2
from the grid estimator.
Finally, given the grid voltage estimators internal oscillators frequency
o
is 377rads/s
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
400
300
200
100
0
100
200
300
400
x1
vg
(a) Time domain response of x
1
vs. v
g
(t)
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
400
300
200
100
0
100
200
300
400
vg
x2
(b) Time domain response of x
2
vs. v
g
(t)
Figure 3.10: Time domain response of the estimators state variables
(60Hz), the power factors of the inverter at dierent grid frequencies are shown in Fig-
ure 3.12 for dierent k
sync
values neglecting switching harmonics and assuming the reac-
tive power compensation feature of the inverter is turned o. One can observe that as
k
sync
gets larger, the more consistent that the power factors become over a certain range
of frequencies.
3.2.2 Grid Voltage Amplitude Identier
A grid voltage amplitude identier is needed to determine the amplitude of the grid
voltage. It has a form of the following:
0.114 0.116 0.118 0.12 0.122 0.124 0.126 0.128 0.13
400
300
200
100
0
100
200
300
400
Vg
x1(desired)
(a) Desired x
1
vs. v
g
(t)
0.114 0.116 0.118 0.12 0.122 0.124 0.126 0.128 0.13
400
300
200
100
0
100
200
300
400
x1
x1(desired)
(b) Desired x
1
vs. x
1
0.126 0.128 0.13 0.132 0.134 0.136 0.138 0.14 0.142 0.144
400
300
200
100
0
100
200
300
400
Vg
x2(desired)
(c) Desired x
2
vs. v
g
(t)
0.128 0.13 0.132 0.134 0.136 0.138 0.14 0.142
400
300
200
100
0
100
200
300
400
x2
x2(desired)
(d) Desired x
2
vs. x
2
Figure 3.11: Zoomed in time domain response of the distorted grid voltage v
g
(t), the
estimators output and its desired values
50 52 54 56 58 60 62 64 66 68 70
0.85
0.9
0.95
1
1.05
Freqeuncy (Hz)
P
o
w
e
r

F
a
c
t
o
r

(
P
F
)
K
sync
=200
K
sync
=300
K
sync
=500
K
sync
=1000
Figure 3.12: Power factors vs. grid frequencies for Q=0 while neglecting switching har-
monics
V
g
=
_
v
2
g
+ v
2
g
(3.12)
Equivalently, we may also write

V
g
=
_
x
2
1
+ x
2
2
which is graphically displayed in the
transient state plane plot of Figure 3.9.
Other options of implementing the amplitude identier may include peak detection
for the grid voltage or peak detection for either output of the grid voltage estimator. Both
methods avoid using the square root operand, the latter one is more preferred because
the grid voltage estimator lters out the harmonic distortions that appeared on the grid
voltage so that the peak detection for the output of the estimator is more accurate than
for the grid voltage itself.
3.2.3 Synchronized Current Reference Creation
Once the v
g
and v
g
are obtained from the grid voltage estimator, and

V
g
is obtained
from the amplitude identier, the control of the phase of the synchronized current refer-
ence becomes possible. Therefore, given the grid reference currents parallel and orthog-
onal components, i
ref
g
and i
ref
g
, a synchronized current reference signal can be obtained
by the following equation:
i
ref
g
=
i
ref
g
v
g
+ i
ref
g
v
g
V
g
(3.13)
Since the parallel component of the current reference i
ref
g
is aligned with the grid
voltage, this part of the current then controls the active power ow to the grid. On the
other hand, since the orthogonal component of the current reference i
ref
g
is 90
leading
the grid voltage, this part of the current controls the reactive power ow to the grid.
Therefore, the input i
ref
g
and i
ref
g
are the input control commands for the active and
reactive power.
3.2.4 Discussion of the Proposed Grid Synchronization Method
The proposed grid synchronization method is advantageous in two major ways. Firstly,
comparing with the conventional method of single phase grid synchronization method
as discussed in [30] where v
g
(t) is simply duplicated for parallel synchronization, the
proposed grid synchronizer not only reproduces a ltered signal that is in phase with
grid voltage, but also emulates an orthogonal component of the grid voltage, which can
be used to generate reactive power reference to the inverter. Therefore, the inverter
gains the ability of controlling the reactive power ow comparing to the conventional
PV inverters that only transfer active power due to their inability of reproducing an
orthogonal component of the current reference.
Secondly, other systems [32] [33] [34] which uses a synchronous frame PLL to lock
on the phase of the grid voltage would need zero voltage crossing detection to reset the
integrator and the d-q transformations used which would need sin and cos calculations.
Both actions increase the complexity of the implementing the synchronizer in a digital
processor. On the other hand, the proposed grid synchronizer only uses a two by two
state matrix and a two by two output matrix to generate the parallel component and the
orthogonal component. This method therefore lowers the computational burden of the
digital processor signicantly.
The down side of the synchronization method is that since the grid estimator has
a xed oscillator frequency
o
, exposure to large frequency variation would result in
undesirable power factor downgrade (refer to Figure 3.12). Although increasing k
sync
would minimize the eect, the noise suppression ability of the estimator would be hurt.
Another down side of the grid synchronization method is its need of a square root
calculation in the amplitude identier, which could increase the processing time of the
digital processor. Fortunately, the fast xed point square root algorithm can be used
in this case which signicantly increase the processing speed of square root calculation.
Other viable options such as peak detection on the output of the estimator would avoid
the square root calculation, therefore can be used as a substitute.
Finally, a k
sync
= 200 is used in the PSCAD/EMTDC simulation and the prototype
designed in the lab. This selection of k
sync
is more focused on noise suppression than
immunity to frequency variation because the grid frequency can be set exactly in 60Hz
in PSCAD/EMTDC simulation, and the grid frequency in the lab is well regulated at
60Hz with a maximum variation less than 0.5Hz.
3.3 Voltage Controller
The DC-link voltage can be regulated by a closed loop voltage controller. Figure 3.13 is
a simplied power stage diagram which is used to analyze the DC voltage behaviour.
+
-
vdc(t)
ig(t)
Lg
Li
Cf
Rd
H
vt(t)
vg(t)
Cdc
idc(t)
Figure 3.13: Inverter power stage diagram
3.3.1 Voltage Loop Modelling
The dierential equation on the DC side is:
C
dc
dv
dc
(t)
dt
= i
dc
(t) (3.14)
Again, i
dc
(t) consists of two components, a DC component, I
dc
and a double-line
frequency AC component, i
dc,ripple
(t). Both of them can be obtained from the power
balance equation:
v
dc
(t)i
dc
(t) =

V
g
cos(
g
t)
I
g
cos(
g
t ) (3.15)
v
dc
(t)I
dc
+ v
dc
(t)i
dc,ripple
(t) =
V
g
I
g
2
cos +
V
g
I
g
2
cos(2
g
t ) (3.16)
From equation (3.16), the two components of the DC current can be expressed as:
I
dc
=
V
g
2v
dc
(t)
I
g
cos =
V
rms
g
2v
dc
(t)
I
g
cos (3.17)
i
dc,ripple
(t) =
V
g
I
g
cos(2
g
t )
2v
dc
(t)
(3.18)
Since we align the parallel component of the current reference signal with the grid
voltage using a grid synchronization function block, the grid current i
g
(t) has its parallel
component aligned with the grid voltage as shown in the phasor digram in Figure 3.14.
Im
||
g
I
g
I
Re

g
I
g
V
Figure 3.14: Phasor diagram of i

g
and its two components
Therefore, Equation (3.17) can be rewritten to be
I
dc
=
V
rms
g
2v
dc
(t)
I
g
(3.19)
Then, we linearize these parameters to about the nominal grid voltage V
n
g
and nominal
DC voltage V
n
dc
:
I
dc
=
V
n
g
2V
n
dc
I
g
(3.20)
Then, the complete model of the voltage loop can be drawn and is shown in Fig-
ure 3.15.
A notch lter, H
n
(s), has a form of Equation (3.21) is applied to the voltage loop
to lter out the double-line frequency current ripple component i
dc,ripple
(t) because the
double-line frequency ripple current produces a double-line frequency ripple voltage on
the DC-link. This is undesirable because this ripple signal would couple through the
voltage controller and cause undesirable high frequency component would appear on the
current reference signal of the current control loop, Figure 3.16. (Note: A, B, C, D, E,
F in the gure are constant numbers)
H
notch
=
s
2
+ 2
1
n
s +
2
n
s
2
+ 2
2
n
s +
2
n
(3.21)
G
v
(s)
ig||
ref
G
c
(s)
ig
ref
ig
n
dc
n
g
V
V
2
H
n
(s)
dc
sC
1
idc vdc
vdc
fil
Vdc
ref +
-
Current Loop
NotchFilter
Grid
Synchronization
Voltage
Compensator
||
||

g g
I i
Gridde-
synchronization
g
g
V
v
||
||
g
g
v
V
Figure 3.15: Voltage loop of the inverter
Vdc
n
+vdc,ripple(t)
Vdc
ref
+
-
DC voltage
compensator
C+Dcos(2wgt)
Grid
sychronization
vg(t)
ref
g
i
||
ig
ref
A+Bcos(2wgt)
Ecos(wgt)+Fcos(wgt)cos(2wgt)
Gridcurrent
control loop
Undesired!
ig
Figure 3.16: Eect of the double-line frequency ripple on the current reference signal
where
n
is twice the fundamental frequency,
1
is chosen to be 0.008 and
2
is chosen
to be 1.
The current synchronization block in the diagram is the part that the parallel
current reference, which is generated from the voltage controller, is converted to a grid
synchronized sinusoidal signal which is discussed in Section 3.2.
The current loop, G
c
(s) has a form of:
G
c
(s) =
G
i
(s)G
f
(s)
G
i
(s)G
f
(s) 1
(3.22)
where G
i
(s) is the PR controller from the current loop and G
f
(s) is the plant model
derived in Equation (3.2).
The gird de-synchronization block
|Vg|
V
g
is used to extract the current that is equivalent
to the parallel current reference i
ref
g
generated from the voltage controller. The output
of this block is denoted as i
g
, and it equals to the peak value of the parallel component
of the grid current

I
g
. This block works like an inverse d-q transform, except it is in
a single phase system instead of a three phase system.
3.3.2 DC Voltage Compensator
A simple PI controller is used as the DC voltage loop compensator, which has the form
of:
G
v
(s) = K
v
p
+
K
v
i
s
(3.23)
The uncompensated loop gain and the compensated loop gain of this voltage feedback
loop is shown in Figure 3.17. A selection of K
v
p
= 0.1 and K
v
i
= 1 yields a phase margin
of 60
in the compensated loop as shown in Figure3.17(b)

3.4 Digital Implementation of the Controller
A 32-bit xed point Microchip PIC microcontroller (MCU) was used to implement the
controller. This microcontroller is a relatively low cost choice comparing to other oating
point microcontrollers. Although oating point calculations can be done in this PIC
MCU, it was nally concluded that such computations consume excessive computational
time. Therefore, xed point calculations must be performed and trigonometry (i.e. sin
and cos) calculations must be avoided. As a result, the digital controller was written in a
per-unitized system using a xed number format. All the s-domain controller functions
are transfered into the digital domain using the bilinear transform.
150
100
50
0
50
M
a
g
n
i
t
u
d
e

(
d
B
)
10
1
10
2
10
3
10
4
10
5
10
6
180
135
90
45
0
P
h
a
s
e

(
d
e
g
)
Bode Diagram
Gm = Inf , Pm = 18.5 deg (at 558 rad/sec)
Frequency (rad/sec)
(a) Uncompensated voltage loop gain
200
150
100
50
0
50
100
150
200
M
a
g
n
i
t
u
d
e

(
d
B
)
10
1
10
0
10
1
10
2
10
3
10
4
10
5
10
6
180
135
90
45
0
P
h
a
s
e

(
d
e
g
)
Bode Diagram
Gm = Inf dB (at 0 rad/sec) , Pm = 61 deg (at 173 rad/sec)
Frequency (rad/sec)
(b) Compensated voltage loop gain
Figure 3.17: Bode plot of the uncompensated and compensated voltage loop gain
3.4.1 Switching Frequency Consideration
For the design of a MOSFET based inverter, the switching frequency is primarily limited
by the switching loss and the reverse recovery loss of the body diodes. Another limiting
factor to the switching frequency of a DC/AC inverter is the CPU performance of the
digital controller. In our case, the PWM output compare registers have to be updated at
the very beginning of each switching cycle. This means the inverter control computations
have to be nished in one switching cycle. Therefore, the CPU speed and the complexity
of the controller implementation algorithm directly limits the switching frequency of the
inverter. Based on the experimental result, a switching frequency of 30kHz would give
sucient time for the CPU to nish the controller computation. This chosen switching
frequency would also not introduce excessive losses on the MOSFET switches.
3.4.2 Per-unitize and Fixed Number Format
Inside the digital controller, all the system parameters such as voltages and currents
were per-unitized to their base values, which are normally chosen to be the system rated
values. Then, they were scaled to a xed number format (e.g. 4.12 format) for xed point
calculations. For example, a voltage quantity, V being expressed into a 4.12 format and
per-unitized based on V
base
would be:
V
p.u
4.12
=
V 2
12
V
base
(3.24)
Chapter 4
PSCAD/EMTDC Simulation
Results
This chapter shows the PSCAD/EMTDC simulation results of the grid connected in-
verter. The current controller and the voltage controller were simulated separately to
validate each controller. The validation of the grid synchronizer is also shown in the
simulation. Table 4.1 shows the power stage parameters used in the simulation.
In the last chapter, the grid current i
g
(t) that is used in the control loop has a direction
owing from the grid to the inverter. In this chapter and Chapter 5, in order to illustrate
the resulting current owing from the inverter into the grid, i
gn
(t) is used for the grid
current pointing toward the grid from now on.
4.1 Inverter Current Loop Simulation
Figure 4.1 shows the PSCAD/EMTDC simulation setup for the current loop of the
DC/AC inverter. The DC-link capacitor is replaced with a xed DC voltage source.
i
ref
g
and i
ref
g
are the input commands to the controller loop which control the amount of
active and reactive power being generated.
The performance of the grid voltage estimator is shown in Figure 4.2. The estimators
49
Chapter 4. PSCAD/EMTDC Simulation Results 50
Grid nominal voltage V
n
g
250V (RMS)
DC-link nominal voltage V
n
dc
400V (RMS)
Bridge side inductor L
i
300H
Grid side inductor L
g
100H
Filter capacitor C
f
30F
Filter damping resistor R
d
1.5
Switching frequency f
sw
30kHz
Table 4.1: Inverter current loop simulation power stage parameters
outputs are shown with their desired values. Since the grid voltage used in the simulation
is a perfect sinusoidal wave with 60Hz, the estimators outputs are perfectly aligned with
their desired values in steady state.
Vg(t)
Lg
Li
Cf
Rd
+
-
sa sb
sa
low
sb
low
vdc
ref
g
i
||
Grid
Synchronization
ref
g
i

ref
g
i
G
i
(s)
vg
ig
+
-
ei
Current Controller
Grid
Synchronization
SPWM
vref
a
vref
b
sa sa
low
sb
) (
1
t v
dc
*-1
DC
voltage
feedward
ig(t)
ign(t)
vt(t)
sb
low
Figure 4.1: Inverter current loop simulation setup
|| g
v
g
v
vg
g
v
desired
(a) Start-up transisient
|| g
v
g
v
vg
g
v
desired
(b) Zoomed in result
Figure 4.2: PSCAD/EMTDC simulation result of the grid voltage estimators outputs
and their desired values
4.1.1 Steady State Response
The steady state response of the current loop simulation results are shown in Figure 4.3.
Simulation is done for the inverter output grid current i
gn
(t) being regulated at 10A
(RMS). Three dierent sub-gures are used to show that the inverters output grid current
i
gn
(t) and the grid voltage are in phase (Figure 4.3(a)), o phase by 90
(Figure 4.3(b))
and 45
o phase (Figure 4.3(c)) . Table 4.2 shows the measured average active power
and reactive power in each case from the P,Q meter of PSCAD/EMTDC to prove that
the inverter is capable of transferring pure active power, pure reactive power and both.
Figure 4.3(a) Figure 4.3(b) Figure 4.3(c)
Measured active power (kW) 2.5 0 1.767
Measured reactive power (kVar) 0 2.5 1.767
Table 4.2: Active and reactive power measurement of the current loop simulation
(a) Grid current and voltage are in phase (b) Grid current lags the voltage by 90
(c) Grid current lags the voltage by 45
Figure 4.3: Steady state response of the current loop simulation

4.1.2 Transient Response
The transient response of the current loop simulation results are shown in Figure 4.4
for the output grid current steps up from 0A to 10A (RMS). Simulations are done in
two dierent circumstances where in Figure 4.4(a), the current is in phase with the grid
voltage and in Figure 4.4(b), the current lags 90
the grid voltage.

The grid voltage v
g
(t), inverter output current i
gn
(t) and the current input command
i
ref
g
and i
ref
g
are shown from top to bottom of each sub-gure. It can be observed that
the current step response has a settling time less than 2ms and a percentage overshoot
that is less than 30%.
Figure 4.4: Step response of the current loop simulation

4.2 Inverter Voltage Loop Simulation
Figure 4.5 is the PSCAD/EMTDC setup for the voltage loop simulation, the DC current
source is intended to emulate a front-end DC-DC converter which is capable of feeding
constant current or constant power into the DC link. In the control loop, the voltage
controller is added such that the DC-link voltage is regulated by the feedback loop. Unlike
the current loop simulation, i
ref
g
is now the output of the voltage controller instead of an
input command. i
ref
g
is still a input command that has the ability to control the reactive
power ow.
4.2.1 Steady State Response
The steady state response of the voltage loop simulation results are shown in Figure 4.6.
Simulation is done for the inverter outputting a grid current of 10A (RMS). The DC-
link voltage v
dc
(t), grid voltage v
g
(t) and the output grid current i
gn
(t) are shown from
top to bottom of each sub-gure. Three dierent sub-gures are used to show that the
inverters output grid current i
gn
(t) and the grid voltage are in phase (Figure 4.6(a)),
o phase by 90
(Figure 4.6(b)) and 45
o phase (Figure 4.6(c)). Table 4.3 shows the

vg(t)
+
-
ig(t)
Lg
Li
Cf
Rd
+
-
sa sb
sa
low
sb
low
idc(t)
Vdc
ref
G
v
(s)
NotchFilter
vdc
fil
+
-
ev
ref
g
i
||
Grid
Synchronization
ref
g
i

ref
g
i
G
i
(s)
vdc
vg(t)
ig
+
-
ei
VoltageController
Current Controller
Grid
Synchronization
Cdc
SPWM
vref
a
vref
b
sa sa
low
sb sb
low
) (
1
t v
dc
*-1
ign(t)
vdc(t)
vt(t)
DC
voltage
feedward
Iin
Figure 4.5: Inverter voltage loop simulation setup
Figure 4.6(a) Figure 4.6(b) Figure 4.6(c)
Measured active power (kW) 2.5 0 1.766
Measured reactive power (kVar) 0 2.5 1.767
Table 4.3: Active and reactive power measurement of the voltage loop simulation
measured average active power and reactive power in each case from the P,Q meter of
PSCAD/EMTDC to prove that the inverter is capable of transferring pure active power,
pure reactive power and both.
In addition, the TDDs are measured for the output grid current in the entire current
operating range when the when the inverter is running pure real power, Figure 4.7(a),
and pure reactive power, Figure 4.7(b). One can observe that the grid current TDD is
far below the 5% threshold stated in IEEE-1547/IEEE-519
1
.
1
systems stated in IEEE-519
(c) Grid current lags the voltage by 45
Figure 4.6: Steady state response of the current loop simulation

4.2.2 Transient Response
Figure 4.8 shows the step response of the system when the DC-link voltage reference
steps up from 400V to 440V. Figure 4.8(a) is based on when the constant DC current
source is disconnect and the reactive power command i
ref
g
is set to be 0A. It can be seen
that when the voltage reference signal requests a step change, the grid output current
has to reverse to supply current to charge the DC-link capacitor to the desired voltage
level.
Figure 4.8(b) is based on when the constant DC-current source is disconnected and
0 1 2 3 4 5 6 7 8 9 10
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
i
gn
(A),90 inphase
T
D
D
(
%
)
(a) Grid current and voltage are in phase
0 1 2 3 4 5 6 7 8 9 10
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
i
gn
(A),90 lag
T
D
D
(
%
)
(b) Grid current lags the voltage by 90
Figure 4.7: TDD vs. i

gn
when running pure real power and reactive power for voltage
loop simulation
the reactive power command i
ref
g
is set to be 10A (RMS) so that the inverter is supplying
pure reactive power. It can be seen that the DC-link voltage step causes little impact
on the output current i
gn
(t) when the inverter is supplying pure reactive power. This
is because the voltage loop only depends on the parallel axis so that the active power
should have the full impact on the DC-link voltage whereas the reactive power should
have minimum impact. Both DC-link voltage step response has a settling time less than
20ms and a percentage overshoot less than 30%.
The input current step response is simulated based on the DC input current step
change from 0 to 10A (RMS), Figure 4.9(a). The reactive power step response is simulated
based on the i
ref
g
step change from 0 to 10A (RMS), Figure 4.9(b). It can be seen that
the i
ref
g
step change has little impact on the DC-link voltage than the input current step
change. This is because the voltage loop control is decoupled from the orthogonal axis.
(a) Grid current is 0A (b) Grid current lags the voltage by 90
Figure 4.8: Voltage loop simulation based on the DC-link voltage step change
(a) DC input current step change (b) i
ref
g
step change
Figure 4.9: Step response of the voltage loop simulation based on the DC input current
step change and i
ref
g
step change
Chapter 5
Inverter Experimental Results
This chapter shows the inverters experimental results. A prototype was built based on
the inverter specication. The inverters controller is implemented fully on a 32bits xed
point PIC32MX340F256H microcontroller. Voltage and current signals are sampled using
the internal 10-bit analog-to-digital converter inside the microcontroller. The output
compare module of the microcontroller allows the modulation signal to be compared
with an internal timer signal to resemble a SPWM function block.
In the experimental setup, a DC voltage source which has a greater magnitude than
the regulated DC-link voltage is connected at the DC-link capacitor through a variable
resistor so that the DC-link gets roughly a constant current from the DC source. This is
used to emulate the front end DC/DC converter in the PV system. A transformer and a
variac are connected at the AC grid end to provide isolation and AC voltage adjustability.
The experimental setup is shown in Figure 5.1.
5.1 Steady State Operation
Figure 5.2 shows the steady state operating DC-link voltage v
dc
(t), grid voltage v
g
(t), and
the grid output current i
gn
(t). Due to the limiting voltage level and current limit of the
DC power supply available in the lab, the inverters grid voltage is downgraded to 60V
58
Chapter 5. Inverter Experimental Results 59
vg(t)
+
-
Lg
Li
Cf
Rd
+
-
Vt
sa sb
sa
low
sb
low
Cdc Vin
Rin
1:1
. .
vdc(t)
ig(t)
ign(t)
Sin
Figure 5.1: Inverter experimental setup
(RMS). Therefore, in this section, the inverter is running 600VA with V
n
dc
=140V, v
g
=60V
(RMS), i
gn
=10A (RMS) and the grid frequency of 60Hz. The three sub-gures illustrate
when the inverter is outputting pure real power, pure reactive power with 90
lagging
power factor, and the mix with real and reactive power with 0.8 lagging power factor.
Table 5.1 is a summary of the measured power factor, output current TDD in each case.
It can be seen that the power factor in each case is very close to expected values and
the TDD is under 5% which is under the limit of IEEE-1547/IEEE-519 standard
1
. This
set of experimental results demonstrate the inverters ability of controlling the reactive
power ow. Furthermore, it can also be seen that with a fairly large double line frequency
voltage ripple presented on the DC-link, the output gird current is hardly distorted. This
proves the eectiveness of the notch lter in the voltage control loop.
Theoretical power factor measured power factor TDD (%)
1.0 (Figure 5.2(a)) 0.99 2.73
0 lagging (Figure 5.2(b)) 0.01 lagging 2.26
0.8 lagging (Figure 5.2(c)) 0.79 lagging 2.36
Table 5.1: Summary of measured power factor and TDD
Furthermore, Figure 5.3 shows the amount of output grid current TDD in the entire
1
vdc(t)
vg(t)
ign(t)
(a) Grid current is in phase with the voltage
vdc(t)
vg(t)
ign(t)
vdc(t)
vg(t)
ign(t)
(c) Grid current lags the voltage by 36.8
(PF=0.8, lag-
ging)
Figure 5.2: Steady state operation of the inverter. From top to bottom: DC-link voltage
V
n
dc
=140V on CH1 at 50V/Div, grid voltage v
g
=60V(RMS) on CH4 at 100V/Div and
output current i
g
=10A (RMS) on CH3 at 20A/Div. Time scale 5ms/Div
0 1 2 3 4 5 6 7 8 9 10
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
i
gn
(A),in phase
T
D
D
(
%
)
(a) TDD(%) vs. i
gn
where i
gn
is in phase with V
g
0 1 2 3 4 5 6 7 8 9 10
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
i
gn
(A), 90degree lagging
T
D
D
(
%
)
(b) TDD(%) vs. i
gn
where i
gn
is 90
lags V
g
Figure 5.3: TDD vs. i
gn
when running pure real power and reactive power
current operating range when the inverter is running pure real power, Figure 5.3(a), and
pure reactive power, Figure 5.3(b). In the PSCAD/EMTDC simulation, the TDD in the
entire current operating range is much smaller as compared to the experimental results.
This is because the harmonic distortions that appeared in the experimental results are
mainly caused by the grid voltage low frequency distortions. IEEE-1547 states that the
harmonics current injection shall be exclusive to the grid voltage harmonic distortions, so
the extra percent of harmonic distortions shown in the experimental results is acceptable.
Besides, the amount of TDD in the entire current operating range of this inverter is still
less than 5% threshold stated in IEEE-1547/IEEE-519
1
.
5.2 Transient Response
The transient response of the inverter is tested through the step change of the DC-link
voltage, input current and the reactive power controlling command i
ref
g
.
Figure 5.4 shows the transient response of the inverter when the DC-link voltage
steps up from 120V to 140V. Figure 5.4(a) is when the grid current is 0A. Figure 5.4(b)
is when the grid current is at 7A, 90
lagging the grid voltage. The DC voltage transient

response demonstrates good system dynamics where the DC-link voltage settling time is
around 20ms and the percentage overshoot is less than 30% in each case. The result is
similar to the simulation result of the voltage step response, where the DC-link voltage
settling time is around 20ms and the percentage overshoot is less than 30%.
Figure 5.5(a) shows the step response of the input power to the DC-link. This exper-
iment is done by closing the switch (S
in
in Figure 5.1) between the DC voltage power
supply and the DC-link after the DC-link has been regulated at 140V. This action enables
an input current step change. The long settling time of the DC-link voltage is expected
because at the transients, the input current cannot be kept at a constant value due to
the interaction between the xed DC voltage of the DC power supply and the transient
that happens at the DC-link voltage.
Figure 5.5(b) shows the step response of the inverter when the reactive power con-
trolling command i
ref
g
steps up from 0A to 10A (RMS) and the DC-link voltage is kept
at constant 140V. The settling time of the current step is less than 2ms and the percent-
age overshoot is around 30%. As comparing to the input power step response shown in
Figure 5.5(a), this response of the i
ref
g
step change demonstrate good decoupling of the
parallel and orthogonal axis of the controller as the step change in i
ref
g
causes little
impact on the DC-link voltage.
The transient responses of the inverter have the same behaviour as they are shown in
the simulation section. For the step response in DC-link voltage, both PSCAD/EMTDC
simulation and lab experiment show good system dynamics, where a settling time of 20ms
and a percentage overshoot that is less than 30% are achieved. For the step response in
i
ref
g
, both PSCAD/EMTDC simulation and lab experiment show a good decoupling of
the parallel axis and the orthogonal axis.
v
dc
(t)
v
g
(t)
i
gn
(t)
(a) Grid current i
gn
is 0A
v
dc
(t)
v
g
(t)
i
gn
(t)
Figure 5.4: DC-link voltage step response of the inverter. (a) From top to bottom:
DC-link voltage v
dc
g
output current i
gn
on CH3 at 2A/Div. Time scale 20ms/Div. (b) From top to bottom:
DC-link voltage v
dc
g
output current i
gn
(t) on CH3 at 10A/Div. Time scale 20ms/Div
vdc(t)
vg(t)
ign(t)
(a) input power step response of the inverter
vdc(t)
vg(t)
ign(t)
(b) i
ref
g
step response of the inverter
Figure 5.5: Input power step change and i
ref
g
step change response of the inverter. (a)
from top to bottom: DC-link voltage v
dc
g
(t) on
gn
(t) on CH3 at 10A/Div, time scale 10ms/Div.
(b) from top to bottom: DC-link voltage v
dc
g
(t) on
gn
(t) on CH3 at 5A/Div, time scale 100ms/Div
Chapter 6
Conclusion and Future Work
6.1 Conclusion
This research presented a single phase grid connected DC/AC inverter with reactive
power (VAR) control for residential PV application. It was shown that residential PV
power generation has garnered much attention in todays demand for renewable energy.
Grid interconnection standards such as IEEE-1547 are used to regulate the power quality
of the local DR power injection. As a consequence, single phase, low power VSIs are
commonly used for the interconnection between PV modules and the utility grid to ensure
that the power quality meets grid standard. Furthermore, as more distributed resources
such as local PV generation is integrated into the grid at the distribution level, the trend
that the DR units actively supply reactive power to the grid has appeared. Therefore,
this work proposed a solution for the VSI to actively control the reactive power injecting
to the grid. This leads to the main contribution of this work, which is the design of a low
complexity grid synchronization method that does not rely on use of high performance
control platforms for creating parallel and orthogonal component of the grid voltage in
order to control the real and reactive power ow. The synchronization method inherently
attenuates grid distortion and is immune to slight grid frequency variations. Meanwhile,
65
Chapter 6. Conclusion and Future Work 66
due to the manufactures guarantee on the life time of PV inverters, the VSI was designed
to use a small, more reliable, lm type capacitor on the DC-link in a cost eective way
while maintaining a good output power quality.
Simulations were performed on PSCAD/EMTDC platform and a prototype was also
developed in the lab to prove the eectiveness of the controller and the grid synchroniza-
tion method. A PR compensator and a PI compensator were used in the current control
loop and the voltage control loop respectively. It was shown that the resulting phase
dierence between the gird current and the voltage are very close to the expected values,
which proves the inverters ability of controlling reactive power ow. Furthermore, with a
small value lm type capacitor being place on the DC-link, the notch lter in the voltage
control loop was be able to average out the large double-line frequency voltage ripple
that appeared on the DC-link, so that the output grid current stayed unaected by the
DC-link double-line frequency voltage ripple. As a result, the total demand distortion of
the grid current stayed under 5 % which is acceptable by the IEEE-1547 grid intercon-
nection standard
1
. The system outputs, i
gn
(t) and v
dc
(t) also show acceptable behaviours
during transient responses in terms of percentage overshoot and settling time.
6.2 Future Work
The future work of this research can extend to design the front end DC/DC converter
so that a two stage PV inverter system can be built for the analysis of the inverters
response when it is connected to a power source that is generated from the PV modules
instead of a constant DC current source that is used in the lab.
This research furthermore opens up the topic of actively exchanging reactive power
with the utility grid at the distribution level. The control and communication methods
between these type of local DRs and the central dispatch would be a useful area of study.
1
Appendix A
IEEE-1547 Standard on Harmonic
Current Injection
1
When the DR is serving balanced linear loads, harmonic current injection into the
Area Electrical Power System (EPS) at the PCC shall not exceed the limits stated below
in Table A.1. The harmonic current injections shall be exclusive of any harmonic currents
due to harmonic voltage distortion present in the Area EPS without the DR connected.
Table A.1: Maximum harmonic current distortion in percent of current(I)
a
Individual Total
harmonic h < 11 11 h < 17 17 h < 23 23 h < 35 35 h demand
order h distortion
(odd harmonics)
b
(TDD)
Percent (%) 4.0 2.0 1.5 0.6 0.3 5.0
a
I=the DR unit rated current capacity
b
Even harmonics are limited to 25% of the odd harmonic limits above
1
67
Appendix B
PR Controller Behaviour
The PR controllers behaviour were studied by looking at the bode plots when changing
each parameter. Again, the transfer function of an non-ideal PR controller is:
G
i
(s) = K
c
p
+
K
c
i
s
s
2
+ 2
o
s +
2
o
(B.1)
Figure B.1(a) shows the frequency response of the PR controller when K
c
i
changes
from 1 to 1000, with one decade interval. K
c
p
is set to be 0, is set to be 0.001. As shown
in the plot, with K
c
i
increases, the gain of the controller increases whereas the bandwidth
stays constant.
Figure B.1(b) shows the frequency response of the PR controller when changes from
0.001 to 1, with one decade interval. K
c
p
is set to be 0, K
i
is set to be 1. As shown in the
plot, with increases, the peaking of the magnitude at the resonant frequency decreases.
Figure B.1(c) shows the frequency response of the PR controller when K
c
p
changes
from 1 to 1000, with one decade interval. K
c
i
is set to be 1000, is set to be 0.001. As
shown in the plot, with K
c
p
increases, the magnitude at all frequencies increases but the
bandwidth of the controller got reduced and the phase amplitude decreases.
68
Appendix B. PR Controller Behaviour 69
100
50
0
50
100
M
a
g
n
i
t
u
d
e

(
d
B
)
10
1
10
2
10
3
10
4
90
45
0
45
90
P
h
a
s
e

(
d
e
g
)
Bode Diagram
Frequency (rad/sec)
Ki=1
Ki=10
Ki=100
Ki=1000
(a) Frequency response when K
c
i
changes
100
80
60
40
20
0
20
M
a
g
n
i
t
u
d
e

(
d
B
)
10
1
10
2
10
3
10
4
90
45
0
45
90
P
h
a
s
e

(
d
e
g
)
Bode Diagram
Frequency (rad/sec)
=0.001
=0.01
=0.1
=1
(b) Frequency response when changes
0
10
20
30
40
50
60
70
80
M
a
g
n
i
t
u
d
e

(
d
B
)
10
0
10
1
10
2
10
3
10
4
10
5
90
45
0
45
90
P
h
a
s
e

(
d
e
g
)
Bode Diagram
Frequency (rad/sec)
Kp=1
Kp=10
Kp=100
Kp=1000
(c) Frequency response when K
c
p
changes
Figure B.1: Frequency response of the PR controller with each parameter changes
Appendix C
Harmonics Table for Switch Mode
Inverters
H
H
H
H
H
H
H
H
H
H
h
m
a
0.2 0.4 0.6 0.8 1.0
Fundamental 0.2 0.4 0.6 0.8 1.0
m
f
1.242 1.15 1.006 0.818 0.601
m
f
2 0.016 0.0061 0.131 0.220 0.318
m
f
4 0.018
2m
f
1 0.190 0.326 0.370 0.341 0.181
2m
f
3 0.024 0.071 0.139 0.212
2m
f
5 0.013 0.033
3m
f
0.335 0.123 0.083 0.171 0.113
3m
f
1 0.044 0.139 0.203 0.176 0.062
3m
f
3 0.012 0.047 0.104 0.157
3m
f
5 0.016 0.044
4m
f
1 0.163 0.157 0.008 0.105 0.068
4m
f
3 0.012 0.070 0.132 0.115 0.009
4m
f
5 0.034 0.084 0.119
4m
f
7 0.017 0.050
Table C.1: Generalized harmonics of V
Ao
for a large m
f
70
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A Single Phase Grid Connected DC-AC Inverter With Reactive Power Control For Residential PV Application

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A Single Phase Grid Connected DC/AC Inverter with

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C for electrolytic capacitors

C was selected to be used in the prototype.

demonstrates closed loop stability.

Figure 3.5: Overview of the grid synchronizer and VAR controller

at the grid fundamental frequency so that v

. It can also be observed from Figure 3.8, the more the k

(a) Turn on trajectory when k

(b) Turn on trajectory when k

Figure 3.14: Phasor diagram of i

in the compensated loop as shown in Figure3.17(b)

(c) Grid current lags the voltage by 45

Figure 4.3: Steady state response of the current loop simulation

the grid voltage.

Figure 4.4: Step response of the current loop simulation

(Figure 4.6(b)) and 45

o phase (Figure 4.6(c)). Table 4.3 shows the

(c) Grid current lags the voltage by 45

Figure 4.6: Steady state response of the current loop simulation

Figure 4.7: TDD vs. i

lagging the grid voltage. The DC voltage transient

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