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Defense Nuclear Agency

Alexandria, VA 22310-3398
Transient Radiation Effects on Electronics (TREE)
Handbook
Formerly "Design Handbook for TREE, Chapters 1-6"
Lewis Cohn, et al.
Defense Nuclear Agency
6801 Telegraph Road
Alexandria, VA 22303
December 1995
Technical Report
CONTRACT NO. DNA 001 -93-C-0050
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4. TITLE AND SUBTITLE
Transient Radiation Effects on Electronics (TREE) Handbook
Formerly "Design Handbook for TREE, Chapters 1-6"
6. AUTHOR(S)
Lewis Cohn (DNA) Manfred Espig, Al Wolicki (KSC), Mayrant Simons
(Research), Clay Rogers (JAYCOR) and Alfred Costantine (Dames)
7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES)
Defense Nuclear Agency Kaman Sciences Corp.
6801 Telegraph Road 2560 Huntington Avenue
Alexandria, VA 2231-3398 Suite 200
Alexandria, VA 22303
9. SPONSORlNGlMONlTORlNG AGENCY NAME(S) AND ADDRESS(ES)
Defense Nuclear Agency
6801 Telegraph Road
Alexandria, VA 2231 0-3398
RAESICohn
11. SUPPLEMENTARY NOTES
5. FUNDING NUMBERS
C - DNA 001-93-C-0050
PE - 62715H
PR - RD
TA - RA
WU- DH329580, DH329590,
DH329600, DH329780
8. PERFORMING ORGANIZATION
REPORT NUMBER
10. SPONSORING/MONITORING
AGENCY REPORT NUMBER
DNA-H-95-61
This work was sponsored by the Defense Nuclear Agency under RDT&E RMC Code 846620 RD RA
00005 CSTl3310A 259040.
12a. DISTRIBUTION/AVAILABILIN STATEMENT
Approved for public release; distributions is unlimited
12b. DISTRIBUTION CODE
13. ABSTRACT (Maximum 200 words)
The objectives of the Transient Radiation Effects on Electronics (TREE) Handbook are to (1) provide
information about radiation effects on semiconductor devices and materials, (2) provide guidelines for
microelectronic radiation-hardening technology, and (3) serve as a reference for radiation hardness
assurance and microelectronic radiation testing. The radiation environments addressed in this
handbook include those produced by nuclear weapons effects (NWE) and natural space. The NWE
environment includes x-rays, gamma rays, and neutrons. The natural space environment includes
photons and electrons trapped in the Van Allen belt, and neutrons, heavy ions, and cosmic rays found in
space.
14. SUBJECT TERMS
Ionizing Radiation Dose Rate
Electronic Circuits Hardening
Nuclear Weapon Effects Single Event Phenomena
15. NUMBER OF PAGES
506
16. PRICE CODE
20. LIMITATION OF ABSTRACT
SAR
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OF REPORT
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7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) (Continued).
Research Triangle Institute
P.O. Box 14086
Research Triangle Park, NC 27709-4086
JAYCOR
P.O. Box 1577
Santa Monica, CA 90406-1 577
Dames and Moore
One Blue Hill Plaza
Pearl River, NY 10965
i i UNCLASSIFIED
TREE HANDBOOK
TABLE OF CONTENTS
Section
Page
....................................................................................................................................
List of Figures xx
...............................................................................................................................
List of Tables xxxvii
Chapter 1 Introduction
.................................................................................................
1.1 Objectives and Applicability 1-1
........................................................................................................
1.2 Handbook Organization 1-1
.................................................................................
1.3 Nuclear Weapon Effects Environments 1-2
..................................................................................
1.4 Natural Space Radiation Environment 1-5
....................................................................................................
1.4.1 Trapped Radiation 1-5
..........................................................................
1.4.1.1 Trapped Radiation Domains 1-7
............................................................................
1.4.1.2 Trapped Radiation Models 1-9
........................................................................
1.4.1.3 Trapped Radiation Variations 1-9
...........................................................................................
1.4.1.4 Flux-Free Time 1-12
...............................................................................
1.4.1.5 Artificial Enhancement 1-12
....................................................................................
1.4.1.6 Emerging Radiation 1-14
..............................................................................
1.4.1.7 Ionizing Radiation Dose 1-15
..................................... 1.4.1.8 Susceptibility of Electronics to Permanent Damage 1-19
................................................................................................
1.4.2 Transiting Radiation 1-20
.....................................................................................
1.4.2.1 Solar Cosmic Rays 1-20
.................................................................................
1.4.2.2 Galactic Cosmic Rays 1-21
...............................................................................
1.4.2.3 Geomagnetic Shielding 1-22
..............................................................................
1.4.2.4 Transport and Shielding 1-22
..............................................................................
1.4.2.5 Ionizing Radiation Dose 1-27
...................................................
1.4.2.6 Single-Event Susceptibility of Electronics 1-27
............................................................................................................
1.4.3 Conclusions 1-28
.....................................................................................
1.5 Systems Development Background 1-28
.......................................................................................................
1.5.1 Hostile Threats 1-28
.............................................................................
1.5.1.1 Nuclear Space Radiation 1-28
..............................................................................
1.5.1.2 Natural Space Radiation 1-29
TREE Handbook . Table of Contents
Section
1.5.2 Balanced Hardening Concept .................................................................................. 1-29
1.5.3 Emphasis on Electronics ......................................................................................... 1-29
1.5.4 Life-Cycle Survivability and Hardness ................................................................... 1-29
1.6 System Nuclear Hardening and Survivability Requirements ................................................ 1-31
1.7 Nuclear Threat Environments and Nuclear Specification Development ................................ 1-31
............................................................ 1.7.1 Minimum Adequate Hardness Specification 1-32
1.7.2 Nuclear Environment Criteria Development ........................................................... 1-33
1.7.3 Nuclear Environment Description ........................................................................... 1-34
1.7.4 Nuclear Environment Specification at the System .................................................... 1-36
1.7.4.1 Neutrons ................................................................................................... 1-36
1.7.4.2 Gamma Rays ....................................................................................... 1-36
1.7.4.3 X Rays ................................................................................................... 1-36
1.7.4.4 Ionizing Radiation Dose .......................................................................... 1-37
1.7.4.5 Nuclear EMP ............................................................................................ 1-37
1.7.4.6 SGEMP ................................................................................................. 1-37
............................................................................................................... 1.8 List of References 1-37
Chapter 2 Ionizing Radiation Effects
.................................................................. 2.1 Radiation Sources and Interaction With Matter 2-1
2.1.1 Sources and Types of Radiation ............................................................................. 2-1
2.1.1.1 Photon Interactions ................................................................................... 2-2
2.1.1.2 Charged-Particle Interactions .................................................................... 2-3
.................................................................................. 2.1.1.3 Neutron Interactions 2-4
2.1.2 Ionization and Atomic Displacements .................................................................... 2-4
2.1.3 Radiation Exposure Terminology ........................................................................... 2-5
........................... 2.1.4 Overview of Primary Radiation Effects on Electronic Materials 2-5
2.1.5 Characteristics of Specific Radiation Environments .............................................. 2-8
2.2 Basic Mechanisms of Ionizing Radiation Effects on Electronic Materials and Devices .... 2-9
............................................................... 2.2.1 Radiation Response of MOS Structures 2-10
2.2.2 Physical Processes Underlying the Radiation Response of MOS Devices ........... 2-14
Section
TREE Handbook . Table of Contents
Page
.................................................................................... 2.2.2.1 Initial Hole Yield 2-14
.......................................................................................
2.2.2.2 Hole Transport -2- 16
......................................................
2.2.2.3 Deep Hole Trapping and Annealing -2- 19
.........................................................
2.2.2.4 Radiation-Induced Interface Traps 2-23
........................................... 2.3 Ionizing Radiation Dose Effects on Semiconductor Devices 2-26
..................................................................................................
2.3.1 Effects on Diodes 2-26
...............................................................................
2.3.1.1 Conventional Diodes 2-26
......................................................................
2.3.1.2 Voltage-Reference Diodes 2.27
..................................................................................
2.3.1.3 Microwave Diodes 2-27
......................................................... 2.3.2 Effects on Junction Field-Effect Transistors 2-27
2.3.3 Effects on Bipolar Transistors ............................................................................ 2-27
2.3.4 Effects on MOSFETs ............................................................................................ 2-29
.............................................................................
2.3.5 Effects on Four-Layer Devices 2-31
...............................................................................
2.3.6 Effects on Integrated Circuits 2-31
...................................................................................
2.3.6.1 Bipolar Linear ICs 2-31
..................................................................................
2.3.6.2 Bipolar Digital ICs 2-32
.....................................................................................
2.3.6.3 MOS Digital ICs 2-32
2.4 Metal-Oxide-Semiconductor Field-Effect Transistor Ionizing Radiation
Dose Response .................................................................................................................. 2-34
2.4.1 Threshold Voltage Shifts ...................................................................................... 2-34
2.4.1.1 Rebound Effects ...................................................................................... 2-35
2.4.1.2 Apparent Dose-Rate Effects ................................................................... 2-37
2.4.1.3 Trapped-Hole Saturation Effects ............................................................ 2-37
2.4.2 Ionizing Radiation Dose Classification Scheme ................................................... 2-38
............................................ 2.4.3 Ionizing Radiation-Dose-Induced Leakage Currents 2-38
.......................................................... 2.4.4 Gate-Oxide Radiation-Hardening Methods 2-42
2.4.5 Ionizing Radiation Dose Effects on MOSFET Mobility ...................................... 2-43
2.4.6 Other MOSFET Ionizing Radiation Dose Effects ................................................ 2-45
TREE Handbook . Table of Contents
Section Pae;e
....... 2.5 Metal-Oxide-Semiconductor Integrated Circuit Ionizing Radiation Dose Response 2-46
.......................................................................................... 2.5.1 Power-Supply Current 2-46
....................................................................................
2.5.2 Circuit Timing Parameters 2-48
2.5.3 Input and Output Voltage and Current Parameters ............................................... 2-49
2.5.4 Minimum and Maximum Frequency Parameters ................................................. 2-51
..........................................
2.5.5 Operating Margins Versus Ionizing Radiation Dose 2 - 5 2
2.5.6 Summary ............................................................................................................... 2-53
2.6 Ionizing Radiation Dose Effects on Bipolar Transistors ................................................ 2-54
.....................................................................................
2.6.1 Current Gain Degradation 2-55
..................................................................
2.6.2 Radiation-Induced Leakage Currents 2-57
........................... 2.7 Ionizing Radiation Dose Effects on Linear Bipolar Integrated Circuits 2-58
..................................................... 2.8 Ionizing Radiation Dose Effects on Gallium Arsenide 2-60
2.9 Power Semiconductor Devices and Integrated Circuits .................................................... 2-62
................................................................................................ 2.9.1 Power Distribution 2-62
............................................... 2.9.2 Power Semiconductor Device and IC Application 2-63
.............................................................................
2.9.3 Power Semiconductor Devices 2-67
2.9.4 Power Integrated Circuits ..................................................................................... 2-70
2.9.5 Radiation Effects and Hardening Strategies ......................................................... 2-73
.......................................................................
2.9.5.1 CMOS and BJT Devices 2-74
.....................................................................................
2.9.5.2 DMOS Devices 2-74
2.10 Nonvolatile Memory Technology ......................................................................... 2-75
................................ 2.10.1 Floating-Gate Erasable Programmable Read-only Memory 2-79
............ 2.10.2 Floating-Gate Electrically Erasable Programmable Read-only Memory 2-82
.......... 2.10.3 Silicon-Nitrate-Oxide Semiconductor Nonvolatile Memory Technology 2-85
2.10.3.1 Design Considerations .......................................................................... 2-86
2.10.3.2 Radiation Effects ................................................................................... 2-88
2.10.4 Thin-Film Magnetic Nonvolatile Memories ......................................................... 2-90
...................................................
2.10.5 Ferroelectric Nonvolatile Memory Technology 2-91
Section
TREE Handbook . Table of Contents
........................................................................ 2.10.5.1 Technology Description 2-93
................................................................................... 2.10.5.2 Radiation Effects 2-95
2.10.6 Summary ............................................................................................................... 2-95
2.11 Radiation Effects on Optical Fibers and Electro-Optic Components ............................... 2-97
2.1 1.1 Optical Fibers ........................................................................................................ 2-97
2.1 1.2 Radiation Effects on Fiber Optics ......................................................................... 2-99
......................................................................................
2.1 1.3 Radiation Environments 2- 110
................................................................ 2.1 1.3.1 Natural Space Environment 2- 110
2.1 1.3.2 Strategic Radiation (Combined Nuclear Weapons and
............................................................... Natural Space) Environment 2- 110
2.1 1.4 Summary ............................................................................................................. 2-1 12
..........................................................................................................
2.12 List of References 2 112
Chapter 3 Ionizing Dose Radiation Effects on Semiconductor Microelectronics
..................................................................................
3.1 Diode Transient Radiation Response 3. 1
...................................................
3.2 Diode Transient Radiation Response Equivalent Circuit 3-4
3.3 Transient Ionizing Radiation Response of Bipolar Transistors .......................................... 3-9
3.3.1 Photocurrent Modeling ........................................................................................... 3-9
.................................................. 3.3.2 Alternative Total Photocurrent Response Model 3-14
................................................................................ 3.3.3 Physical Photocurrent Model 3-15
..................... 3.3.4 Other Transient Ionizing Radiation Effects on Bipolar Transistors 3. 16
......................................................................... 3.3.4.1 Nonlinear Photocurrents 3-16
.......................................................................... 3.3.4.2 Radiation Storage Time 3-17
...................................................... 3.4 Transient Ionizing Radiation Response of MOSFETs 3-18
..................................................... 3.4.1 MOSFET Photocurrent Model Development -3- 18
.......................................................... 3.4.2 MOSFET Photocurrent Equivalent Circuit 3-20
3.5 Transient Ionizing Radiation Effects on Silicon ICs on Insulating Substrates ................. 3-21
............................................................................ 3.5.1 Silicon-on-Insulator Transistors 3-22
3.5.2 Silicon-on-Sapphire Technology Devices ............................................................ 3-25
TREE Handbook . Table of Contents
Section
3.6 Transient Ionizing Dose Rate Response of Gallium Arsenide
Semiconductor Devices .................................................................................................... 3-25
..................................................................................... 3.6.1 pn Junction Photocurrents 3-25
........................................................................................ 3.6.2 Substrate Photocurrents 3-25
...................................................................................
3.6.3 Substrate Charge Trapping 3-25
............................................................ 3.6.4 Semi-Insulating Substrate Shunt Currents 3-26
................................ 3.7 Transient Ionizing Dose-Rate Upset Response of Microelectronics 3-26
...................................................................................... 3.7.1 CMOS SRAM Operation 3-26
..................................................................................................
3.7.2 Upset Definitions 3-28
........................................................................................ 3.7.3 Integrated Circuit Upset 3-28
3.7.4 Pushout Upset ....................................................................................................... 3-33
3.8 Latchup in Integrated Circuits .......................................................................................... 3-33
3.8.1 Four-Layer Latchup in Bipolar Transistors .......................................................... 3-35
............................................... 3.8.2 Four-Layer Latchup in CMOS Integrated Circuits 3-36
.................................................................................. 3.8.3 Other Latchup Mechanisms 3-41
................................................................................................ 3.8.3.1 Snapback 3-41
................................................................................ 3 3.3.2 Second Breakdown 3-41
3.8.4 Latchup Windows ................................................................................................. 3-43
................................................................................................
3.8.5 Latchup Mitigation 3-44
3.9 Transient Radiation Effects on Electro-Optical and Passive Components ....................... 3-45
3.9.1 Electro-Optical Components ................................................................................. 3-45
3.9.1.1 Optical Fibers ......................................................................................... 3-46
3.9.1.2 Electro-Optical Devices ......................................................................... 3-50
3.9.2 Passive Components ............................................................................................. 3-50
3.9.2.1 Resistors ................................................................................................. 3-50
3.9.2.2 Capacitors .............................................................................................. 3-52
..................................................................................................
3.10 Single-Event Phenomena 3-54
3.10.1 Historical Background ........................................................................................ 3-55
3.10.2 SEP Environments .............................................................................................. 3-57
TREE Handbook . Table of Contents
Section Parre
3.10.3 Basic Single-Event Phenomena Mechanisms ..................................................... 3-58
3.10.3.1 Upset Phenomenology ......................................................................... 3-58
............................................................................................
3.10.3.2 Funneling 3-59
.................................................................................
3.10.3.3 Physical Analysis 3-60
......................................................................... 3.10.3.4 SEU in Linear Circuits 3-61
.......................................................................
3.10.3.5 Upsets in Logic Circuits 3-61
................................... 3.10.3.6 Simultaneous Multiple Single-Bit Event Upset 3-63
................................................... 3.10.4 Circuit Response to Single-Event Phenomena 3-63
.............................................................................. 3.10.4.1 Single-Event Upset 3-63
.................................................................. 3.10.4.2 Single-Event Gate Rupture 3-66
...........................................................................
3.10.4.3 Single-Event Burnout 3-68
................................................... 3.10.4.4 Single-Event Latchup and Snapback 3-68
................................................................................. 3.10.5 SEP Testing and Modeling 3-68
................................. 3.10.5.1 Modeling Upset Rates in Natural Environments 3-69
............................................................ 3.10.5.2 SEU Characterization Methods 3-70
............................................................
3.10.5.3 Alternative Screening Methods 3-71
.......................................................................
3.10.5.4 Calculation and Models 3-72
.......................................................................... 3.10.6 SEU Hardening and Processing 3-72
3.10.6.1 Metal-Oxide Semiconductors .............................................................. 3-72
3.10.6.2 Bipolar Memories ................................................................................ 3-73
................................................................... 3.10.6.3 Gallium Arsenide Devices 3-73
3.10.7 System Approaches to SEP-Induced Errors ....................................................... 3-73
...................................................................................
3.10.7.1 Error Prevention 3-73
................................................. 3.10.7.2 Error Toleration and Error Correction 3-73
3.10.8 Conclusion .......................................................................................................... 3-74
3.11 List of References .............................................................................................................. 3-74
Chapter 4 Displacement Damage Effects
.......................................................................... 4.1 Basic Mechanisms of Displacement Effects 4-1
TREE Handbook . Table of Contents
Section
........................................................................................... 4.2 Atomic Displacement Processes 4-2
....................................................................................... 4.3 Dynamics of Atomic Displacement 4-3
................................................................................... 4.3.1 Damage Creation and Models 4.3
............................................................................................. 4.3.1.1 Gossick Model 4-4
4.3.1.2 Mueller-Wilsey-Rosen Model ....................................................................... 4-5
................................................................................................. 4.3.1.3 Srour Model 4-5
.................................................................. 4.3.2 Energy Deposition by Incident Radiation 4-6
..................................... 4.3.3 Conversion of Kerma Factor to Non-Ionizing Energy Loss 4-11
................................ 4.3.4 Conversion of Non-Ionizing Energy Loss to Displaced Atoms 4-12
................................ 4.4 Displacement Damage Effects on Semiconductor Electrical Properties 4-12
.............................................................................. 4.4.1 Recombination Lifetime Effects 4-15
......................................................................................... 4.4.2 Carrier Removal Effects 4-21
............................................................................................................... 4.4.3 Annealing 4-23
........................................................ 4.4.3.1 Annealing in Semiconductor Materials 4-23
................................................................. 4.4.3.2 Annealing in Bipolar Transistors 4-25
............................................................................................... 4.4.4 pn Junction Leakage 4-26
.................................................................... 4.4.4.1 Junction Leakage Mechanisms 4-27
4.4.4.2 Junction Leakage Equation ......................................................................... 4-29
................................................................................................. 4.4.5 Mobility Reduction 4-29
4.5 Displacement Damage Effects on Silicon-Based Devices .................................................... 4-30
.......................................................................................... 4.5.1 Conventional pn Diodes 4-31
4.5.2 Voltage Reference Diodes ...................................................................................... 4-32
4.5.3 Microwave Diodes ................................................................................................. 4-33
4.5.4 Bipolar Transistors ................................................................................................. 4-33
4.5.5 Junction Field-Effect Transistors ............................................................................. 4-37
4.5.6 Metal-Oxide Semiconductor Field-Effect Transistors .............................................. 4-37
4.5.7 Four-Layer Devices ................................................................................................ 4-38
4.5.8 Bipolar Digital Integrated Circuits ........................................................................... 4-39
TREE Handbook . Table of Contents
Section Page
4.5.9 Linear Integrated Circuits ........................................................................................ 4-40
4.5.10 Metal-Oxide Semiconductor Digital Integrated Circuits .......................................... 4-42
4.5.1 1 Memories. Microprocessors. and Gate Arrays ......................................................... 4-42
...................... 4.6 Displacement Damage Effects on Gallium Arsenide Field-Effect Transistors 4.42
4.7 Displacement Damage Effects on Optical Fibers and Optoelectronic Devices ...................... 4-42
4.7.1 Light-Emitting Diodes ............................................................................................ 4-45
............................................................................................ 4.7.2 Injection Laser Diodes 4-48
4.7.3 Photodetectors ........................................................................................................ 4-49
4.7.4 Optical Fibers ......................................................................................................... 4-53
4.8 Displacement Damage Effects on Silicon Sensor Arrays ..................................................... 4-54
4.8.1 CTE Degradation .................................................................................................... 4.55
4.8.2 Radiation-Induced Dark-Current Behavior .............................................................. 4-56
4.8.2.1 Radiation-Induced Dark-Current Increases Produced
by Bulk Generation Centers ...................................................................... 4-58
4.8.2.2 Dark-Current Spike (Single-Particle) Effects ............................................. 4-60
4.8.2.3 Dark Current Annealing ............................................................................ 4-63
4.8.2.4 Radiation-Hardening Approaches ............................................................. 4.63
4.9 List of References ............................................................................................................... 4.64
Chapter 5 Component and Circuit Design
5.1 Introduction ......................................................................................................................... 5-1
5.1.1 Initial Information Requirements ............................................................................ 5-1
5.1.2 Selection of Suitable Approach .............................................................................. 5-2
5.1.3 Design Phase ........................................................................................................... 5-2
5.1.4 Circuit Construction and Testing ............................................................................ 5-2
5.1.5 Hardness Verification ............................................................................................. 5-3
5.2 Hardening Methodology ..................................................................................................... 5-3
5.3 Device Selection for Hardened Circuits ............................................................................. 5-4
5.3.1 Semiconductor Device Selection ............................................................................ 5-4
TREE Handbook - Table of Contents
Section
5.3. 1.1 Neutron Environment ..... ............................... ............. .............................. 5-4
5.3. 1. 2 Ionizing Radiat ion Dose Rale Environment ...... ...... ...... .. .. .... .... .. ............. 5A
5.3. 1.3 Ionizing R,ldi,Hion Dose Environment ........ .. ...... ..... ... .... ........... ............ .. . 5-6
5.3.2 Capaci tor Selection ........... .......................... ........ .................................................... 5-7
5.4 Circuil Design Modifications for Hardening ..... ............. .................................................... 5-7
5.4.1 Current Limit ing ....................................................... .............................................. 5-8
5.4.2 Photocurrent Compensat ion ........................... .......... .. ........ .. ..... ..... ....................... .. 5-8
5.4.3 Filtering .. ............ ....... .. .............................. ........ ... ...... .. ..... ....... ...................... .... .... . 5-8
5.4.4 Clipping and Clamping ......... .... ,. , ............ , .. , ........ " .... " ...... .. ..... " ... ...... " .... " ........ ",.5-9
5.4. 5 Feedback. "" .. " "" .. "" .. " ."" .. """ .. " """. "" .. " """ .. """" ...... "" .. """. "." "",,"'''' " .. 5- 10
5.4.6
5.4.7
5.4.8
Temperature Compensation ......... ,', .... ,', ............... , ..... ,', ... _ ........ , ..... , ..... , ......... , .... 5-11
Time SequenCing and Time Delays .... " .... .... .............. " ..... ......... .... ,', ... " .... , ........ , 5- 11
Low- l mpcdancc Circuitry .... . ........................................................... ......... 5-11
5.4.9 Device Packaging .... .. ......... .. . ..... ............ . " .. "."" .. . "" "." ... " .... " ... " .... " ..... 5- 1 I
:5.5 Circuil-Hardening Guidelines ... ,', ...... ........ " .............. ,"' .... " ..... " .... " .... ,", .. ,', .... ,, ... , .... , ... 5- I 2
5.5.1 Neutron,c; .... , ............... , ............ .......... , ........ , ....... , ..... .. .................. , ..... , .......... , .... ,.5- J 2
5.5.1. 1 Li near Circuit s .. , ........ , ....... " ..... ,', ............. , .......................... , ..... , ... , ..... ".5- 12
5.5.1.2 Bipolar Digital Circuits ......... , .... " ........ " ..... , ............. , .......... " .... " ......... ,' 5- 14
5.5. 1.3 Sl1mmary of Neutron Hardening Guidelines .... " ..... " .... " ..... , .... " ... " ..... , 5- 15
5,5,2 Ionizing Radintion Dose Rate .... " ........ " .... . ,"', ..... ,', .. " .. ... ,"', .. ,", .. " ...... ..... .......... 5- 15
5.5,2.1 Linear Circuits .... , ............ .... , ............. ,", .................... , .... , ................ " ... ,.5- I 5
5.5.2.2 Digi tal Circllils ......... " ....... " ...................... , ...... " .... , .......................... " ... 5-17
5.5.2.3 Latchup ......... , ....... , ......... " .... " ..... , .. , ...... " ............ , ..... " ..... , ........... , .... , .... 5-18
5.5.2.4 Summary of Ionizing Radi at ion Dose Rate Hardening Guidelines ..... ",5-J 9
5.5.3 Ionizing Radintion Dose Hardening Guidelines ." ...... .. ... .. " .... .. ... "" .... " .. " .......... 5- 19
5.5.3.! Linear Circuits , ...... , .... ,"', .... ,', ..... ,', ....... , ..... ,", .. " .. .... ,', ..... ,, .. "., .. " ... " .... 5-l9
5.5.3.2 Digital Circuits ........................ ,., ...... ,'" ...... , .... " ............. , .......... , .......... , .. 5-20
5.5.3.3 Summary of Ionizing Radiation Dose Hardeni ng Guidelines ................ 5-21
5.5.4 Dose-Enhanccnlent EITects .. " ..... . .. , .. ... ,., ..................... , ........ , ...... , ... , ..... , .... , ... , .... 5-22
""
TREE Handbook . Table of Contents
Section Paae
...................................................................................
5.5.5 Single-Event Phenomena 5 - 2 2
............................................................... 5.5.5.1 Bulk/Epitaxial CMOS Circuits 5-23
....................................................
5.5.5.2 CMOSISOS and CMOSISOI Circuits 5-24
...............................................................
5.5.5.3 Bipolar Digital Logic Circuits 5-24
......................................................................
5.5.5.4 GaAs Technology Circuits 5-27
................................................................................ 5.6 System-Level Hardening Guidelines 5-29
..............................................................................
5.6.1 Hardened Information Storage 5-29
...................................................... 5.6.2 Redundancy and Fault-Tolerance Techniques 5-30
.........................................................................
5.6.3 Circumvention/Reset Techniques 5-32
.................................................................................
5.6.4 Operate-Through Technique 5-32
......................................................................................
5.6.5 Power-Source Hardening 5-34
...................................................................... 5.6.6 Time Sequencing and Time Delays 5-35
.......................................................................................................
5.6.7 Periodic Reset 5-35
...........................................................................................
5.6.8 Shielding Techniques 5-35
.................................................. 5.7 Analysis Techniques for Circuit and System Hardening 5-35
5.7.1 Device Models ...................................................................................................... 5-38
.................................................................. 5.7.2 Ionizing Radiation Dose-Rate Effects 5-39
.....................................................................
5.7.2.1 Example Upset Calculation 5-40
.....................................................
5.7.2.2 Example Recovery-Time Calculation 5-40
.......................................................
5.7.3 Ionizing Radiation Dose and Neutron Effects 5-41
..................................................................................
5.7.3.1 Screening Analysis 5-41
....................................................................................
5.7.3.2 Detailed Analysis 5-42
.............................................................................................. 5.7.4 Single-Event Effects 5-44
.....................................................................................
5.8 Radiation Testing Considerations 5-46
5.9 Hardening Resources Required ......................................................................................... 5-47
5.9.1 Hardening Costs .................................................................................................... 5-47
5.9.2 Nuclear Effects Experience ................................................................................... 5-48
5.10 Evaluation and Hardening of Existing Equipment ........................................................... 5-48
5.10.1 Assessment Considerations ................................................................................... 5-49
TREE Handbook . Table of Contents
Section Page
.............................................................. 5.10.2 System Element Hardness Classification 5-49
5.10.3 Hardening Constraints .......................................................................................... 5-51
............................................................................ 5.10.4 Hardening Technique Selection 5-51
5.11 List of References ............................................................................................................. 5-53
Chapter 6 Radiation Response Testing and Hardness Assurance
................................................................................................ 6.1 Radiation Response Testing 6-1
6.1.1 Test Planning .......................................................................................................... 6-1
6.1.2 Test Guidelines ....................................................................................................... 6-2
6.1.3 Ionizing Radiation Dose Testing ............................................................................ 6-2
6.1.3.1 Radiation Sources ..................................................................................... 6-2
......................................................................................... 6.1.3.2 6 0 ~ o Dosimetry 6-3
6.1.3.3 Dose Enhancement Effects (60Co) ............................................................ 6-3
.................................................................................................... 6.1.3.4 Test Plan 6-4
.......................................................................................... 6.1.3.5 Test Procedure 6-4
............................................................................. 6.1.3.5.1 Sample Size 6-4
...................................................................... 6.1 .3.5.2 Exposure Levels 6-5
............................................................... 6.1.2.5.3 Exposure Conditions 6-5
6.1.3.6 Total Ionizing Dose Time Dependent Effects .......................................... 6-6
........................................................................... 6.1.3.7 Electrical Measurements 6-6
............................................................................................ 6.1.3.8 Data Analysis 6-6
......................................................................................... 6.1.3.9 Documentation 6 - 6
............................................. 6.1.3.10 References for Ionizing Total Dose Testing 6-7
.................................................................... 6.1.4 Ionizing Radiation Dose Rate Testing 6-8
6.1.4.1 Test Facilities ............................................................................................ 6-8
.................................................................................................... 6.1.4.2 Test Plan 6-9
6.1.4.3 Upset Test Procedure ................................................................................ 6-9
6.1.4.3.1 General .................................................................................... 6-9
6.1.4.3.2 Samplesize ........................................................................... 6-11
TREE Handbook . Table of Contents
Section
............................................................. 6.1.4.3.3 Exposure Conditions 6. 11
.............................. 6.1.4.3.4 Electrical Measurement-Digital Devices 6-12
........................... 6.1.4.3.5 Electrical Measurements - Linear Devices 6-13
..........................................................................
6.1.4.4 Latchup Test Procedure 6-15
6.1.4.4.1 General .................................................................................. 6-15
6.1.4.4.2 Samplesize ........................................................................... 6-15
..........................................................
6.1.4.4.3 Latchup Path Analysis 6-16
.............................................................
6.1.4.4.4 Exposure Conditions 6-16
.......................................................
6.1.4.4.5 Electrical Measurements 6-16
...............................................................
6.1.4.4.6 Latchup Condition 6-16
............................................................
6.1.4.5 Survivability/Burnout Procedure 6-17
6.1.4.5.1 General .................................................................................. 6-17
6.1.4.5.2 Samplesize ........................................................................... 6-17
............................................................. 6.1.4.5.3 Exposure Conditions 6-17
....................................................... 6.1.4.5.4 Electrical Measurements 6-17
........................................................................................
6.1.4.6 Documentation 6-19
...........................................................
6.1.4.7 References for Dose Rate Testing 6-19
............................................................ 6.1.5 Displacement (Neutron) Damage Testing 6-21
...................................................................................
6.1.5.1 Radiation Sources 6-21
................................................................................................
6.1.5.2 Dosimetry 6-22
.......................................................
6.1.5.3 Licensing for Radioactive Materials 6-22
6.1 . 5.4 Test Plan .................................................................................................. 6-23
........................................................................................
6.1.5.5 Test Procedure 6-23
...........................................................................
6.1.5.5.1 Sample Size 6-23
....................................................................
6.1.5.5.2 Exposure Levels 6-23
............................................................. 6.1.5.5.3 Exposure Conditions 6-23
.........................................................................
6.1.5.6 Electrical Measurements 6-23
........................................................................................
6.1 . 5.7 Documentation 6-23
6.1 . 5.8 References for Neutron Testing .............................................................. 6-24
TREE Handbook . Table of Contents
Section Pag;e
.......................................................................................................... 6.1.6 SEE Testing 6-25
6.1.6.1 Objective ................................................................................................. 6-25
.......................................................................................... 6.1.6.2 Tesi Facilities 6-25
6.1.6.3 Test Plan .................................................................................................. 6-26
6.1.6.4 Estimation of Upset Cross Sections and Upset Rates ............................. 6-28
6.1.6.4.1 Heavy Ions ............................................................................ 6-28
6.1.6.4.2 Proton Reactions ................................................................... 6-29
6.1.6.4.3 Alpha Particles ...................................................................... 6-29
6.1.6.5 Test Procedure ........................................................................................ 6-29
6.1.6.5.1 Sample Size ........................................................................... 6-29
6.1.6.5.2 Dosimetry .............................................................................. 6-29
6.1.6.5.3 Radiation Levels ................................................................... 6-30
.............................................................................. 6.1.6.5.4 Test Steps 6-30
6.1.6.6 Exposure Conditions ............................................................................... 6-30
6.1.6.7 Electrical Measurements ......................................................................... 6-30
6.1.6.8 Data Analysis .......................................................................................... 6-31
........................................................................................ 6.1.6.9 Documentation 6-31
6.1.6.10 References for SEU Testing .................................................................... 6-31
6.2 Radiation Dosimetry ......................................................................................................... 6-32
6.2.1 Dosimetry for Ionizing Radiation Dose (Total Dose) Effects .............................. 6-32
6.2.2 Radiation Sources ................................................................................................. 6-32
6.2.3 Dosimeters ............................................................................................................ 6-33
6.2.4 Dose Enhancement ................................................................................................ 6-33
6.2.5 Time Dependent Effects (TDE) ............................................................................ 6-34
6.2.6 Ionizing Radiation Dose Testing Standards .......................................................... 6-34
6.2.7 Dosimetry for Dose Rate Effects .......................................................................... 6-35
6.2.8 Radiation Sources ............................................................................................... 6-35
6.2.9 Dosimeters ............................................................................................................ 6-35
6.2.10 Neutron Dosimetry ................................................................................................ 6-35
xvi
TREE Handbook . Table of Contents
Section Pane
............................................................................................. 6.2.1 1 Dosimetry Summary 6-37
..............................................................................................................
6.2.12 Cautions 6 - 3 8
.................................................................... 6.2.13 Applicable Measurement Standards 6-38
.............................................................................................................
6.2.14 References 6-38
..........................................................................................................
6.3 Hardness Assurance 6-39
..............................................................................
6.3.1 Hardness Assurance Concepts 6-39
6.3.1.1 Ground Rules for System Hardness Assurance ...................................... 6-39
.......................................................................................
6.3.1.2 Design Margins 6-40
............................................. 6.3.1.3 Radiation Environments to be Considered 6-41
.................................. 6.3.1.3.1 Ionizing Radiation Dose (Total Dose) 6-41
.................................................................... 6.3.1.3.2 Neutron Fluence 6-41
................................................................
6.3.1.3.3 Ionizing Dose Rate 6-41
6.3.1.3.3.1 Ionizing Dose Rate Due to Gamma Rays ........ 6-41
.................. 6.3.1.3.3.2 Ionizing Dose Rate Due to X Rays 6-41
.............................................................. 6.3.1.3.4 Single Event Effects 6-42
.................................................................. 6.3.1.3.5 Combined Effects 6-42
.................................................................... 6.3.2 Piecepart-Level Hardness Assurance 6-42
6.3.2.1 Hardness Assurance Procedure - Lot Acceptance Tests ......................... 6-42
6.3.2.1.1 DNA Committee on RHA Device Specifications ................. 6-43
............................................ 6.3.2.1.2 Hardness Assurance Guidelines 6-44
................................................................... 6.2.2.2 Hardness Critical Categories 6-45
................................................................ 6.3.2.2.1 Unacceptable Parts 6-45
.................................................................... 6.3.2.2.2 Acceptable Parts 6-45
................................................................................ 6.3.2.3 Piecepart Categories 6-46
................................... 6.3.2.3.1 Design Margin Break Point Example 6.48
.................................. 6.3.2.3.2 Parts Categorization Criteria Example 6-49
6.3.2.4 Lot Acceptance Tests .............................................................................. 6-50
6.3.2.4.1 Variables Method for Lot Acceptance .................................. 6-50
6.3.2.4.2 Lot Tolerance Percent Defective Method for
..................................................................... Lot Acceptance 6-52
Section
TREE Handbook . Table of Contents
Pane
6.3.2.4.3 Radiation Overtests ............................................................... 6-52
6.3.2.4.4 Application of Statistical Concepts ....................................... 6-54
........................................................................................... 6.3.2.5 Existing Data 6-54
................................................................................................. 6.3.3 Parts Procurement 6-55
6.3.3.1 MIL-STD Radiation Hardness Assured (RHA) Device Specifications .. 6.55
....................... 6.3.3.1.1 RHA Parts on the Qualified Parts List (QPL) 6-55
........... 6.3.3.1.2 RHA Parts with Standard Military Drawings (SMD) 6-56
... 6.3.3.1.3 RHA Parts from a Qualified Manufacturer's Line (QML) 6-57
6.3.3.2 Non RHA Parts ....................................................................................... 6-57
............................................................................. 6.3.3.3 Procurement Controls 6-58
............................................................. 6.3.4 Parts Qualification and Acceptance Tests 6-60
.................................................. 6.3.4.1 Pieceparts Qualifications Test Program 6-61
............................................................................. 6.3.4.1.1 RHA Parts 6-61
..................................................................... 6.3.4.1.2 Non RHA Parts 6.61
................................................ 6.3.4.1.3 Radiation Test Environments 6.64
............. 6.3.4.1.3.1 Ionizing Radiation Dose (Total Dose) 6.64
6.3.4.1.3.2 Ionizing Radiation Dose Rate .......................... 6-65
6.3.4.1.3.3 Displacement Damage ..................................... 6.65
......................................... 6.3.4.1.3.4 Single Event Effects 6-66
6.3.4.1.3.5 Heating Effects ................................................. 6.66
6.3.4.1.3.6 Combined Effects ............................................. 6-66
6.3.4.2 Pieceparts Acceptance Testing ............................................................... 6-66
............................................................................. 6.3.4.2.1 RHA Parts 6.66
6.3.4.2.2 Non RHA Parts ..................................................................... 6-66
6.4 System Level Hardness ..................................................................................................... 6-68
6.4.1 Hardness Assurance Procedures ........................................................................... 6-68
............................................................................................................. 6.5 List of References 6.70
xviii
TREE Handbook . Table of Contents
Section Page
Appendix 6A: Data Item Description .......................................................................................... 6A-1
Appendix 6B: Single Event Upset Test Facility .......................................................................... 6B-1
Appendix 6C: Cosmic-Ray Upset Rate Calculation .................................................................... 6C-1
Tree Handbook Index ..................................................................................................................... I- 1
Tree Handbook AbbreviationIAcronym List ................................................................................ A-1
Tree Handbook Symbol List .......................................................................................................... S- 1
TREE Handbook . List of Figures
Figure
Chapter 1 Introduction
1-1 The geometric cavity .......................................................................................................... 1-6
......................................................................... 1-2 Trapped particle trajectory and drift motion 1-7
1-3 Charged-particle distribution in the magnetosphere ............................................................ 1-8
1-4 Trapped proton population as a function of energy .............................................................. 1-9
1-5 Equatorial radial profiles for proton fluxes ........................................................................ 1-10
............................................................... 1-6 Low-earth orbit proton fluxes. composite spectra 1-11
1-7 Low-earth orbit electron fluxes. composite spectra ............................................................ 1-11
. 1-8 Geostationary electron spectra ........................................................................................ 1 12
1-9 Electron flux profile for a worst-case pass through the South American anomaly ............... 1-13
1-10 Isochronal contours for electron longevity following the Starfish
. nuclear detonation in July 1962 ................................................... , . , .............................. 1 14
1-1 1 Electron dose (180 day) in LEO orbits as a function of altitude enhanced by the nuclear
detonations shown ................................................................... , . , .............................. 1 . 14
1-12 Ten-year doses in GEO orbit enhanced by a 100 kt nuclear burst with saturated belts .
Doses are behind a 100 mil aluminum slab shield augmented by the Ta shielding shown ... 1-14
1 . 13 Emerging electron spectra behind various thicknesses of spherical aluminum shields ........ 1. 16
1-14 Emerging bremsstrahlung spectra behind various thicknesses of spherical
................................................................ ............................................ . aluminum shields , 1 16
1-15 Emerging trapped proton spectra behind various thicknesses of spherical
.............................................................................................................. aluminum shields 1 . 17
................................................................ 1 . 16 Daily doses for LEO (500.km, 60-degree orbit) 1 . 17
1-17 World map contours of total electron plus bremsstrahlung dose (radslmsec) at
500-km altitude for a spherical aluminum shleld thickness of 0.2 &m2 ..................................... 1 . 18
1-18 Daily electron doses for GEO for a silicon target behind solid-sphere
. aluminum shielding .......................................................................................................... 1 18
1- 19 Ten year total dose for various typical orbits at the center of aluminum sphere based
................................................... .................................................. . on AP8/AE8 models , 1 19
1-20 Ten year total dose for various orbits behind a semi-inifite slab
. based on AP81AE8 models ................................................................................................ 1 19
1-2 1 Solar flare proton events for solar cycles 19. 20. and 2 1 ..................................................... 1-21
1-22 Cosmic-ray spectral distributions ...................................................................................... 1-22
1-23 Relative abundance of nuclei in galactic cosmic radiation .................................................. 1-22
...................................... 1-24 Contours of total energy required to penetrate the magnetosphere 1-23
TREE Handbook . List of Figures
Figure
........................................................ 1-25 Total energy required to penetrate the magnetosphere 1-24
1-26 Magnetospheric attenuation of solar flare proton spectra for a 500-km
........................................................................................................
high-inclination LEO 1-24
....................... 1-27 Magnetospheric attenuation of cosmic-ray silicon atoms for a 600-km LEO 1-25
1-28 Emerging solar flare proton spectra behind various spherical
............................................................................................
aluminum shield thicknesses 1- 25
1-29 Integral LET spectra for the attenuated interplanetary spectrum during
.............................................................................................
one anomalously large event 1-26
1-30 Galactic cosmic-ray solar spectra emerging behind spherical aluminum shields
of various thicknesses ....................................................................................................... 1-26
1-3 1 Unattenuated solar flare proton dose emerging behind spherical aluminum shielding ......... 1.27
.......................................................................................
1-32 Life-cycle survivability program 1-30
1-33 Hardening and hardness assurance (HA) incorporated into normal system
............................................................................................................ development tasks 1-31
1-34 System acquisition life cycle for a hardened system .......................................................... 1-32
................................ 1-35 Simplified procedure for developing a nuclear hardness specification 1-34
......................................................................................
1-36 Weapon system specification tree 1-35
Chapter 2 Ionizing Radiation Effects
2- 1 Relative importance of three photon interactions as a function of atomic number and
photon energy .................................................................................................................... 2-3
2-2 Schematic indicating primary radiation effects and secondary effects in electronic
............................................................................................................................ materials 2.4
2-3 Stopping power versus particle energy for electrons and protons incident on silicon ...... 2-6
2-4 Schematic of ionization process in semiconductors and insulators; ionization leads
to transient photocurrents and buildup of trapped charge (space-charge effects) .
[Effective measure of damage is charge yield per unit dose (electron/hole pairs
............................................................................................................................ per rad).] 2-6
2-5 Schematic of n-channel MOSFET illustrating the basic effect of ionizing-radiation-
dose-induced charging of the gate oxide .......................................................................... 2-9
2-6 Schematic energy band diagram of Si 02 MOS structure for positive gate bias ............. 2-10
............. 2-7 Illustration of recombination. transport. and trapping of carriers in Si 02 films 2. 12
2-8 Capacitance-voltage curves corresponding to the conditions illustrated in
Figure 2-7 ........................................................................................................................ 2. 13
TREE Handbook - List of Figures
Figure
2-9 Schematic time-dependent threshold-voltage recovery of an n-channel MOSFET
following pulsed irradiation, relating the major response features to underlying
physical processes ........................................................................................................... .2- 13
Schematic diagrams indicating limiting pair separation distances for the geminate
and columnar recombination models .............................................................................. $2- 15
Experimentally measured fractional hole yield versus electric field (in Si 02)
for several incident particles ............................................................................................ 2- 16
Schematic diagrams of the trapped-modulated and hopping transport models, both
of which lead to large dispersion in carrier transit times ................................................. 2-17
Normalized flatband voltage recovery data following pulsed 12-MeV LINAC
electron irradiation of 96.5-nm oxide MOS capacitor under 1-MV/cm oxide field
for various temperatures .................................................................................................. 2- 18
Normalized flatband voltage recovery data following pulsed LINAC
electron-beam exposure for 96.5-nm oxide MOS capacitor at 80K and
for oxide fields from 3 to 6 MV/cm ................................................................................. 2- 18
Normalized flatband voltage recovery data of Figure 2-13 (E,, = 1 MVIcm)
replotted with time scaled to half-recovery time, illustrating the universality
of response with respect to temperature. ......................................................................... .2- 19
Effect of processing on hole trapping; threshold voltage shift versus ionizing
radiation dose for two n-channel MOSFETs (VG = +10 volts) receiving
different high-temperature processing ............................................................................ .2-20
Bias dependelice of radiation-induced voltage shift; flatband voltage shift versus gate
voltage for an MOS capacitor following a 1-Mrad (Si02) exposure (to, = 70 nm) ........ .2-20
Schematic of hole-trapping process ................................................................................. 2-21
Long-term annealing data for three MOSFETs of varying radiation hardness;
devices received the doses indicated to produce comparable initial shifts ...................... 2-22
Schematic of trapped-hole removal by electron tunneling from silicon substrate.. ........ .2-22
High-frequency 1-MHz C-V curves of MOS Al-gate capacitor at several times
following pulsed electron beam irradiation ..................................................................... 2-24
Integrated interface trap density between midgap and inversion surface potentials
as a function of time following pulsed electron-beam (LINAC) exposure for
several oxide field values; 0.8-Mrad dose, wet-oxide A1 gate, t,, = 96.5 nm ................. 2-25
Oxide field dependence of radiation-induced interface trap buildup following
1-Mrad (Si02) irradiation in three MOS capacitors having different gate structures ..... 2-25
Normalized reference voltage change DVZ for zener diodes at 25OC versus ionizing
radiation dose ................................................................................................................... 2-27
TREE Handbook . List of Figures
Figure
2-25
2-26
2-27
2-28
2-29
2-30
2-3 1
2-32
2-33
2-34
2-35
2-36
2-37
2-38
2-39
2-40
2-4 1
2-42
2-43
Ionizing-radiation-dose-induced hFE degradation dependence on irradiation
...................................................................................................................
bias condition 2-28
........................................................................... hFE degradation for 2N2222 transistors 2-28
hFE degradation for five identical 2N2 102 transistors from same day's production ....... 2.28
Normalized saturation voltage change DVCE(SAT) for general-purpose
........................................................... transistors at 25OC versus ionizing radiation dose 2-29
Normalized change in collector base cutoff current DICBO for general-purpose
transistors at 25OC versus ionizing radiation dose ........................................................... 2-30
Ionizing radiation dose effects in field-effect transistors ................................................. 2-31
Linear IC parameter variations with ionizing radiation dose ........................................... 2-32
Ionizing radiation dose thresholds for digital bipolar integrated circuits ........................ 2-33
Ionizing radiation dose thresholds for MOS technologies ............................................... 2-33
Schematic time-dependent threshold voltage recovery of an n-channel MOSFET
following pulsed irradiation. indicating the room-temperature time regimes associated
with the various basic physical processes and possible long-term responses .................. 2-34
Radiation-induced threshold shift in enhancement MOSFET drain current versus
.............................................................................................. gate voltage characteristics 2-35
Threshold voltage shift of n-channel MOS transistor during 1 Mrad 6 0 ~ o
irradiation and subsequent anneal; VT separated into shifts due to interface
trapped charge (Vit ) and oxide trapped charge (Vat ) ....................................................... 2-36
Threshold voltage versus ionizing radiation dose for irradiated n- and p-channel
MOSFETs. illustrating the effect of hole-trapping saturation and continued
interface trap buildup in n-channel devices ..................................................................... 2-37
Schematic of MOS device structure ................................................................................ 2-39
Modern. recessed field-oxide MOS structure indicating charge buildup and
induced current leakage paths in the bird's beak regions of the device ........................... 2-39
Radiation-induced increase in subthreshold leakage currents in n-channel field-oxide
transistor test structure subjected to a series of 10-krad(Si02) pulses; VDD = 5 volts .... 2-39
Cross section of hardened transistor demonstrating radiation-induced leakage
path mitigation via boron implantation ............................................................................ 2-40
Schematic diagram illustrating back-channel current leakage in
silicon-on-sapphire MOS transistor ................................................................................. 2.41
I-V curve components for an SO1 transistor .................................................................... 2-41
TREE Handbook - List of Figures
Figure
2-44 Flatband voltage recovery data at 220K for three as-grown oxide MOS
capacitor thicknesses under constant 10-volt applied gate bias [vertical bars
indicate 75 percent recovery point] .................................................................................. 2-42
Model schematic of trapped hole removal in thin gate-oxide MOS structures by
electron tunneling from both Si substrate and poly-Si gate ............................................. 2-43
Threshold and flatband voltage shifts per Mrad(Si02) at 80K ...................................... 2-43
Recovery of threshold voltage shift and transconductance change following
pulsed e-beam irradiation at 77OK for a MOSFET with a 5.3-nm gate oxide ................. 2-44
Normalized effective channel mobility as a function of radiation-induced interface
trap density ...................................................................................................................... .2-44
Ionizing radiation dose degradation of the parameter k' as a function of voltage
........................................................................................ for n- and p-channel transistors 2-45
Surface recombination velocity of a depleted surface as a function of ionizing
radiation dose [prerad value of S = 5 c ds e c ] .................................................................. 2-45
n-channel transistor subthreshold current characteristics; x indicates zero gate
.............................................................................................................. voltage intercept .2-46
Integrated circuit standby power-supply current correlated with zero gate voltage
transistor intercept [Figure 2-5 11 ..................................................................................... 2-47
Standby power-supply current for a I-kbit CMOS SRAM as a function of ionizing
radiation dose .................................................................................................................. .2-47
Standby power-supply current for a 16-kbit CMOS SRAM as a function of
ionizing radiation dose for a test pattern that is the complement of that stored during
irradiation; a noncomplemented pattern (all zeroes) is shown for comparison .............. .2-47
Ionizing radiation dose to cause failure for a Sandia SA3001 2-kbit CMOS SRAM
as a function of dose rate ................................................................................................. 2-48
Read access time for a 16-kbit CMOS SRAM as a function of radiation dose for three
power-supply voltages ..................................................................................................... 2-48
Read access time for a 16-kbit CMOS SRAM as a function of radiation dose and after
rebound (a post-irradiation biased anneal) ....................................................................... 2-48
Normalized read access time for a 4-kbit CMOS SRAM as a function of
radiation dose ................................................................................................................... 2-49
Change in read access time for a 2-kbit CMOS SRAM as a function of dose for
two dose rates ................................................................................................................... 2-49
Maximum functional frequency for a microprocessor as a function of dose and
anneal time for parts fabricated with two different processes ......................................... 2-50
TREE Handbook . List of Figures
Figure
2-6 1 Input voltage switching points for CMOS and TTL buffers as a function of dose
and post-radiation unbiased anneal at room temperature ................................................ 2-50
n-channel output buffer current drive as a function of radiation dose and
post-irradiation biased anneal for parts fabricated with two different processes ............. 2-51
Maximum and minimum power-supply voltages at 5 MHz for a 64.bit.
clocked CMOS/SOS static shift register as a function of radiation dose ........................ 2-51
Maximum and minimum functional frequency at 5 volts for a clocked
CMOS/SOS dynamic shift register with on-chip clock driver circuits as a function
............................................................................................................... of radiation dose 2-52
Principal features determining internal operating margins for a sense amplifier
. .
in a static memory circuit ................................................................................................. 2-52
Dependence of circuit ionizing radiation dose failure level on dose rate ........................ 2-54
Crystalline emitter transistor cross section ...................................................................... 2-55
Polysilicon emitter transistor cross section ...................................................................... 2-55
Gain degradation after exposure to an ionizing radiation dose of 250 krads(Si) ............. 2.56
Ratio of base currents for two poly-Si emitter devices. illustrating that at
low doses. base currents are approximately in the ratio of emitter areas (A).
and at higher doses. the ratio approaches that of the perimeters (P) ................................ 2-57
Change in l / b as a function of dose rate [all data taken at room temperature; time
measured from start of irradiation] .................................................................................. 2-57
Regions of possible radiation-induced charge buildup and leakage currents in
recessed.oxide. bipolar. walled emitter device ................................................................ 2-58
Effects of ionizing gamma dose on leakage current for a typical bipolar transistor ........ 2-58
Effect of finite open-loop voltage gain. input offset voltage. and input offset
current on the performance of an operational amplifier .................................................. 2-59
Linear IC parameter variation with ionizing radiation dose ............................................ 2-60
Effect of irradiation on the drain current-gate voltage characteristic of epitaxial
GaAs JFET; channel region doping density. 10I7/cm3 ........................................................... 2-61
Pulsed radiation response characteristics at various levels of drain current
for a GaAs JFET .............................................................................................................. 2.6 1
Schematic cross section of gate region GaAs JFET. indicating the effects of transient
substrate charging ............................................................................................................ 2-61
Centralized power architecture ........................................................................................ 2-62
Distributed power architecture ......................................................................................... 2-63
xxv
TREE Handbook . List of Figures
Figure
2-8 1
2-82
2-83
2-84
2-85
2-86
2-87
2-88
2-89
2-90
2-9 1
2-92
2-93
2-94
2-95
2-96
2-97
2-98
2-99
PaJg
............................................................................. Switch-mode power supply schematic 2-64
.............................................................. Output voltage of a switch-mode power supply 2-64
Output voltage of a switch-mode power supply using an L-C filter network ................. 2-64
................................................................................ PWM control circuit block diagram 2-65
Control circuit waveforms ............................................................................................... 2-65
Step-down (buck) converter schematic ............................................................................ 2-66
Step-up (boost) converter schematic ................................................................................ 2-66
Step-down converter with isolation ................................................................................. 2-67
Cross section of a double-diffused MOS (DMOS) structure ........................................... 2-69
Symbol for a DMOS device ............................................................................................. 2-70
DMOS output characteristics ........................................................................................... 2-70
.........................................................
DMOS transfer characteristics (transconductance) 2.70
...................................................................................
Resonant converter control circuit 2-71
Cross section of two lateral DMOS structures employing junction isolation .................. 2-72
Cross section of a lateral DMOS employing dielectric isolation ..................................... 2-72
Smart power IC (PIC) cross section using DMOS. CMOS. BJT. and diode circuits ...... 2.73
......................... Effect of ionizing radiation dose on DMOS (80-cell) transconductance 2-75
Effect of ionizing radiation dose on DMOS (80-cell) threshold voltage ......................... 2-75
Rebound effect demonstrated on an 80-cell DMOS subjected to 1 Mrad(Si)
ionizing radiation dose and the effects of annealing; dose rate = 179 rads(Si)/sec ......... 2.75
High-voltage device termination structure (field shield) ................................................. 2-76
Examples of nonvolatile memory technology usage in a military aircraft ...................... 2-77
Reprogramming ease hierarchy for solid-state memory devices ..................................... 2-79
Computer memory hierarchy: data recovery speed ......................................................... 2-79
Typical performance characteristics of solid-state electronic nonvolatile memory
..................................................................................................................... technologies 2.80
Typical endurance characteristics of solid-state electronic nonvolatile memory
..................................................................................................................... technologies 2.8 1
Ionizing radiation dose hardness of nonvolatile memory elements for solid-state
...................................................................................... electronic memory technologies 2.8 1
xxvi
TREE Handbook . List of Figures
Cross section of a typical EPROM floating-gate transistor ............................................. 2-82
Threshold voltage shifts of a floating-gate transistor as a function of ionizing dose
for transistors programmed with different initial threshold voltages ............................... 2-83
........................................... Cross section of a typical EEPROM floating-gate transistor 2-83
EEPROM memory array of FLOTOX cells for a byte architecture ................................ 2-84
Cross section of an SNOS memory transistor showing the typical thicknesses of
the various layers of the dielectric (memory) stack ......................................................... 2-85
Cross section of a typical SNOS memory cell having separate MOS
.............................................................................................................. access transistors 2-87
Cross section of an SNOS memory cell with a merged MOS access transistor .............. 2-87
Effect of irradiation on SNOS threshold voltage for transistors written into
different initial states . [At 5 x lo4 seconds. the transistors were irradiated with
500 krads(Si)] ................................................................................................................... 2.89
Retention curve for an SNOS transistor in the "1" state in a low-dose-rate
(0.09 radlsec) environment .............................................................................................. 2-89
Structure of a thin-film magnetic memory current .......................................................... 2-90
Structure of the ferroelectric perovskite crystal type AB03. showing the two stable
positions of the B ion that lead to the permanent polarization state ................................ 2-91
Typical hysteresis curve for a ferroelectric thin film. showing several important
parameters ........................................................................................................................ 2.92
Conceptual operation of a ferroelectric memory capacitor .............................................. 2-92
Cross section of a ferroelectric capacitor memory cell .................................................... 2-93
............... Cross section of a ferroelectric transistor in the Westinghouse 1 -mm process 2-94
Effect of 60~o-ionizing radiation dose (225 rads[Si]/sec) on the switched
polarization charge of thin-film ferroelectric capacitors prepared by different
processing techniques ...................................................................................................... 2.95
Hysteresis curves for ferroelectric thin-film capacitors before irradiation and after
...................................................................... irradiation with 0.. -5.. and +5-volt biases 2-97
..................................................................... Propagation of light rays in an optical fiber 2-97
...................................... Dispersion effects for a variety of fiber types and light sources 2-98
..................................................................... Contributions to attenuation in glass fibers
2-99
Attenuation in a moderate-water-content fiber .............................................................. 2- 100
TREE Handbook . List of Figures
Figure
2-128
2-129
Schematic of a typical draw tower for optical fiber production ................................... 2-102
Drawing-induced defect absorption in an unirradiated step-index pure silica
core fiber ....................................................................................................................... 2. 102
Schematic drawing of time-dependent effects in an optical fiber during and after
exposure to ionizing radiation [the time scale is logarithmic] ...................................... 2-103
Comparison of 60~o-induced attenuation in a variety of high- and low-loss fibers
and glasses 1 hour after irradiation ............................................................................... 2. 104
Induced attenuation spectra for a variety of doped and pure silica core fibers
at room temperature 1 hour after 100 krads 60~o-irradiation [note that both
boron and phosphate doping increase the infrared attenuation] ................................... 2-105
60~o-i nduced attenuation at -55OC and 0.82 pm in a variety of pure core fibers ......... 2. 106
60Co-irradiation of pure silica core fibers illustrating the effect of fiber coating
on radiation response .................................................................................................... 2. 107
60Co-irradiation of step-index fibers at various temperatures ...................................... 2- 107
Effect of temperature on the ionizing-radiation-induced attenuation in
various fibers ................................................................................................................. 2. 108
60Co-irradiation of single-mode fibers at 22 radslsec showing induced attenuation
at the first.. second.. and third-window wavelengths ................................................... 2-108
Radiation-induced loss in a single.mode. low-OH fiber during irradiation at -55OC
and after irradiation to 10 krads(Si) (1. 300 rads[Si]/min) at several light output
power levels at 0.872 pn .............................................................................................. 2-109
Estimated effects of initial and final attenuation on core (Ge) and oxygen-to-reagent
.................................................................................. ratio used during core deposition 2-1 10
Estimated effect of kinetic recovery order and half-life of incremental loss on the
.......................... two-way interaction of core oxygen-to-reagent ratio and draw speed 2-1 1 1
Chapter 3 Ionizing Dose Radiation Effects on Semiconductor Microelectronics
3- 1 (a. b) pn junction minority-carrier densities .................................................................................. 3-2
3-2 pn junction diode radiation.inclusive. steady-state current-voltage (I-V) characteristic ......... 3.3
3-3 Primary photocurrent for the 2N105 1 collector-base junction .............................................. 3-4
3-4 Normalized photocurrent as a function of dose rate ............................................................. 3-4
3-5 (a. b) Measured and predicted waveforms (100 nsec) normalized to the peak
of the measured waveform at 5.0 x lo9 rads (Si)/sec ............................................................ 3-5
3-6 Radiation-inclusive diode transient model ........................................................................... 3-5
TREE Handbook . List of Figures
Figure Page
.......................................................................................
3-7 Ideal diode photocurrent response 3-6
3-8
1 12
....................................................................................... Error function of (Vz) versus th 3-6
3-9
Peak diode photocurrent as a function of radiation pulse width ............................................ 3-7
.........................................................................................
3- 10 Diode burnout equivalent circuit 3.8
3- 1 1 Radiation intensity versus radiation pulse width for burnout threshold ................................. 3-8
.................................................................................... 3-12 Plot of f(t) versus normalized time 3-11
3-13 Predicted and measured collector photocurrent waveforms for a 2N336 ............................ 3-12
3- 14 Predicted and measured peak collector photocurrent versus dose
....................................................................................................... for a 2N336 transistor 3-12
................................................ 3-15 Collector photocurrent waveforms for a 2N1051 transistor 3-13
........................................................................ 3- 16 First-order transistor photoresponse model 3. 14
........................................................................ 3- 17 Common-emitter transistor photoresponse 3. 14
...................................................................................... 3- 18 Planar bipolar transistor structure 3. 15
3-19 Transistor nonlinear photocurrent behavior with dose rate for two values
for collector base voltage ................................................................................................. 3-16
3-20 Lateral photocurrent flow within a circular transistor ......................................................... 3-17
3-2 1 Collector current and dose-rate pulse versus time showing radiation storage time .............. 3. 18
................................................................................ 3-22 (a. b) Radiation-inclusive transistor models 3.18
................................................................................................ 3-23 Bounded collection region 3.19
............................................................. 3-24 Collection region bounded by a high-low junction 3-19
3-25 Typical MOSFET structure ............................................................................................... 3-20
3-26 Local photocurrents produced by a dose-rate event in a CMOS inverter ............................ 3-20
3-27 Local photocurrents produced by a dose-rate event in SRAM cell ..................................... 3-21
3-28 Cross sections of CMOS bulk. CMOS Epi. CMOSISOS and
(a.b. c)
CMOSISOI transistors ...................................................................................................... 3-23
3-29 Cross section of CMOS SO1 transistor showing parasitic bipolar
and back-gate devices ....................................................................................................... 3-23
3-30 Schematic illustration of SO1 transistor ............................................................................. 3.24
3-3 1 Three-dimensional representation of an n-channel SO1 device ........................................... 3-24
3-32 Cross section of enhancement mode GaAs JFET. indicating source-drain
shunt current path through semi-insulating substrate .......................................................... 3-27
TREE Handbook . List of Figures
Figure
3-33 Reported and projected short-pulse dose-rate-upset thresholds ........................................... 3-27
3-34 CMOS SRAM cell ......................................................................................................... 3-28
3-35 Local photocurrents produced by a dose-rate event in a CMOS inverter ............................ 3-29
3-36 Local photocurrents produced by a dose-rate event in an SRAM cell ................................ 3-29
3-37 A photocurrent waveform typical of a CMOS SRAM cell fabricated on a bulk silicon
substrate exposed to neutrons in order to reduce minority-carrier lifetimes ......................... 3-31
3-38 Rail-to-rail current drawn by a simulated RAM cell as a function of
railspan voltagefor various dose rates ................................................................................ 3-31
3-39 Global linear network supplying voltage to the cells and including linear
models of RAM cells ........................................................................................................ 3-31
3-40 Chip-level representation of the power-supply distribution typical
of a CMOS SRAM ........................................................................................................... 3-32
3-41 Representation of the voltage span across RAM cells within an array
under norrnal unirradiated operating conditions ................................................................. 3.32
3-42 (a. b) Representation of the voltage span across a bulk RAM cell array
............................................................................................. subjected to dose-rate events 3.32
3-43 Range of SRAM upset levels due to pushout ..................................................................... 3-33
3-44 Effect of radiation pulse timing on SRAM pushout and upset levels .................................. 3-33
3-45 Four-layer latchup (pnpn) characteristics ........................................................................... 3-34
(a.b.c. d)
3-46 Cross section of two closely spaced isoplanar npn transistors showing the
substrate latchup path ........................................................................................................ 3-35
3-47 Cross section and circuit diagram of a two-output ISL inverter .......................................... 3-37
3-48 Cross section and circuit diagram of a two-output STL inverter ......................................... 3-37
3-49 Cross section of inverter circuit in n-well CMOS .............................................................. 3-38
3-50 Parasitic bipolar portion of an n-well CMOS inverter ........................................................ 3-38
3-5 1 Complete circuit schematic for n-well CMOS inverter ...................................................... 3-39
3-52 Parasitic bipolar portion of a four-terminal pnpn structure ................................................. 3-40
3-53 Illustrative pnpn I-V characteristic .................................................................................... 3.40
3-54 The snapback phenomenon: I-V characteristics and
(a. b)
a lumped-parameter representation .................................................................................... 3.42
3-55 Typical second-breakdown characteristic .......................................................................... 3.43
XXX
TREE Handbook . List of Figures
Figure
3-56 Safe operating area bounds for silicon transistors for peak junction
.......................................................................................................
temperature at 150' C 3.43
....................... Collector current versus collector-emitter voltage under second breakdown 3-43
Transient attenuation in a variety of fibers ......................................................................... 3-46
Radiation sensitivity of fibers ............................................................................................ 3-47
Transient ionization effects in fibers .................................................................................. 3-48
Parameter effects on attenuation in a high-OH fiber .......................................................... 3-49
............................................................ Parameter effects on attenuation in a low-OH fiber 3-49
............................. Resistor exposure-rate dependence; external air ionization not included 3.5 1
Effects of potting depth on current injection for carbon composition resistor
with epoxy and ceramic cases ........................................................................................... 3-52
Effects of applied voltage on current injection for a 100-kW 1-watt carbon
............................................................................ composition resistor in 112-inch Silastic 3.52
.......................................................................
Capacitor photoconductivity characteristics 3-53
....................................................................
Prompt conductivity versus gamma dose rate 3-53
...............................................................................................
Capacitor equivalent circuit 3-54
Composition of the heavy-ion cosmic-ray spectrum as a function of atomic number .......... 3-58
Critical charge necessary to cause upset decreases as feature-size decreases ....................... 3-59
Response of a diode junction field to heavy-ion penetration ............................................... 3-59
Charge-collection curves for a circuit array. showing that maximum charge
is collected at the struck node due to funneling .................................................................. 3-60
Error propagation in the Intel 80186 microprocessor logic circuit ...................................... 3-62
................................................. DRAM schematic showing four information-storage cells 3-64
Diagram of a vertical slice of a single MOS DRAM cell ................................................... 3-64
Schematic of a bulk CMOS SRAM showing upset-sensitive junctions .............................. 3-65
Basic types of commonly used bipolar memory cells ......................................................... 3-66
Cross section of a bipolar transistor showing three of the many possible paths
for high-particle intersection with pn junction: (a) emitter-base-collector region.
(b) base-collector region. and (c) collector region .............................................................. 3-66
SEM photograph of heavy-ion induced failure induced by 252Cf fission fragments ........... 3.67
TREE Handbook . List of Figures
Figure Page
3-80 Cross section and schematic representation of the two parastic bipolar transistors
............................................................................................ (a. b) inherent in a CMOS structure 3-69
........................................................................... 3-8 1 Typical cyclotron layout for SEU testing 3-70
...................................................... 3-82 Calculated LET distribution of 252Cf fission fragment 3-71
Chapter 4 Displacement Damage Effects
4- 1 Schematic indicating primary radiation effects and secondary effects
........................................................................................................... in electronic devices 4.2
4-2 Schematic of atomic displacement damage in a crystalline solid .......................................... 4-2
4-3 Energy loss in tissue for neutrons and protons [proton energy loss indicated
................................................................... separately for electronic and nuclear processes] 4-4
4-4 Nuclear fraction of total energy loss for protons and neutrons striking a silicon target .......... 4.4
4-5 Gossick model for defect clusters in neutron-irradiated n-type silicon .................................. 4-5
4-6 Typical recoil-atom track with primary energy of 50 keV .................................................... 4-6
4-7 Typical recoil-atom track with primary energy of 50 keV. calculated using the
Firsov interaction radius [tic marks denote 10-nm increments] ............................................ 4-7
4-8 Distributions of primary recoil energies for elastic and inelastic interactions
.................................................................................. in 14-MeV neutron-irradiated silicon 4.7
4-9 Angular distributions of elastic and inelastic interactions in 14-MeV
.................................................................................................... neutron-irradiated silicon 4.7
4-10 Damage factor ratios for bipolar transistors for protons. deuterons. and helium ions
of 1-MeV-equivalent(Si) neutrons as a function of energy ............................................... 4-10
4-1 1 Five effects that can occur due to the presence of defect centers
........................................................................................................ in forbidden bandgap 4. 13
4- 12 Relative sensitivity of lifetime. carrier concentration. and mobility
................................................................................................... to neutron bombardment 4-14
. .
.................................................................................... 4- 13 Damage constant versus resistivity 4. 17
4-14 Injection dependence of lifetime damage constant in silicon of various
resistivities at 76OK and 300K ......................................................................................... 4-17
4- 15 Damage constants K. and K versus resistivity for various injection ratios
1 S
......................................................... (x=dn/no. p/po.r,, = 5 x 10 /no. rp=2. 5 x 4-18
4- 16 Measured and computed damage constant K, versus emitter current density ...................... 4. 19
TREE Handbook . List of Figures
Figure
4-17 Resistivity relative to the pre-irradiation level of n- and p-doped silicon
versus neutron fluence for various dopant densities ........................................................... 4-23
Exponential resistivity-fluence dependence in silicon normalized to its assumed
pre-irradiation value of 1013 ....................................................................................................................... 4-23
Typical annealing factor for modem integrated circuitry in bipolar transistors
subject to neutron fluence ................................................................................................. 4-26
Annealing factor versus time after neutron irradiation for various injection levels
and repetition rates ............................................................................................................ 4-26
Isothermal slow annealing characteristics for typical bipolar transistors ............................. 4-27
Isochronal slow annealing characteristics for typical bipolar transistors;
annealing time 20 minutes ................................................................................................ 4-27
Annealing factor versus time after neutron pulse for bipolar transistors
for various VBE at room temperature ................................................................................. 4-28
Rapid annealing factor for bipolar transistors at various temperatures ................................ 4-28
Short-term annealing nomograph for fission-neutron-irradiated silicon devices .................. 4-28
Approximate thresholds for neutron-induced degradation in various
semiconductor technologies .............................................................................................. 4.30
Illustrative comparison of pre- and post-neutron voltage-current characteristics
of a pn diode ..................................................................................................................... 4.3 1
Normalized change in forward voltage VF for rectifying diodes at 25OC
versus neutron fluence ...................................................................................................... 4-32
Normalized change in reverse leakage current IR for rectifying diodes at 25OC
versus neutron fluence ...................................................................................................... 4-32
................ Typical. gain degradation versus neutron fluence for various types of transistors 4-33
............................... Neutron damage factor as a function of collector current and material 4.34
Comparison of hFE degradation ......................................................................................... 4-34
......................... Nomograph for calculating approximate hFE degradation values in silicon 4-36
............. Transient and permanent damage to transistor current gain after neutron exposure 4.37
Room-temperature annealing. short- and long-term recovery processes
in neutron-irradiated silicon .............................................................................................. 4.36
Short-term annealing factors as a function of collector current for low- and
medium-power silicon npn transistors ............................................................................... 4-37
Normalized change in VCE(SAT) for general-purpose transistors at 25OC
versus neutron fluence ...................................................................................................... 4-38
TREE Handbook . List of Figures
Figure
4-38 Normalized change in ICBo for general-purpose transistors at 25OC versus
neutron fluence ................................................................................................................. 4.39
SCR two-transistor equivalent model schematic and symbol ............................................. 4-40
Neutron threshold for digital bipolar integrated circuits ..................................................... 4.40
........................................................................ Neutron effects in linear integrated circuits 4-41
Effect of irradiation on drain cussent-gate voltage characteristics of epitaxial GaAs PET;
3
channel-region doping density = l0l7 n/cm ........................................... .. .................................. 4-44
Calculated normalized transconductance versus neutron fluence for GaAs JFETs
operating in the hot-electron range for three channel-doping concentrations ....................... 4-44
Schematic diagram of a typical fiber-optic link showing environmental effects
on different components of the link ................................................................................... 4-45
Effect of neutron damage on the normalized output of a variety of LEDs.
.................................................................................................... constant current at 25OC 4-47
Bunus-type LED structure characterized by a high-radiance emitting region ..................... 4-47
Dependence of neutron-induced degradation of normalized light output
on current density ............................................................................................................. 4.48
Neutron-induced degradation of GaAs laser diodes ........................................................... 4-49
Neutron-induced degradation of 1. 25. m InGaAsP laser diodes ....................................... 4.50
Neutron damage in two types of photodetectors ................................................................ 4-51
Phototransistor light current as a function of irradiance after neutron irradiation ................. 4-52
Heterolayer structure of an ionizing-radiation-hardened AlGaAsIGaAs photodiode ........... 4.53
Effect of different radiation types on optical fibers (-30 dBm of 0.85-mm
optical signal during exposure); T = 23C ......................................................................... 4-55
Proton damage factor based on CASSINI test data ............................................................ 4-56
Differential proton spectrum; daily proton contribution through various
shield thicknesses in the Hubble Space Telescope during a solar minimum;
593.krn. 28.5.degree orbit ................................................................................................. 4.57
Differential damage spectra for the Hubble Space Telescope during a 593. h.
28.5.degree orbit ............................................................................................................... 4.57
Daily changes in CTE for the Hubble Space Telescope during a 593.km7
28.5.degree orbit ............................................................................................................... 4.58
CTE degradation for the Hubble Space Telescope as a function of spacecraft
time in orbit; 593.km7 28.5.degree orbit ............................................................................ 4-59
TREE Handbook . List of Figures
Figure Page
4-59 Change in dark-current density for a neutron-irradiated charge-coupled device
..................................... compared to model calculation results (Kg = 1.4 x lo7 n-sec/cm2) 4-61
4-60 Neutron-induced dark current per unit depletion region volume for silicon devices
......................................................................................................
versus neutron fluence 4.6 1
4-61 Measured change in dark-current density produced by single
............................................................................................ 14-MeV neutron interactions 4.6 1
4-62 Measured distribution of new damage events after 1 x 101 n/cm2 fluence;
mean value of entire distribution is 1.5 ni4/cm2 ..................................................................................... 4-62
4-63 Normalized dark-current density versus reciprocal temperature with
neutron fluence as a parameter. illustrating the effect of reducing operating
....................................................................................
temperature on radiation tolerance 4-64
Chapter 5 Component and Circuit Design
....................................................................
5- 1 Generalized hardened circuit design procedure 5. 1
............................................................ 5-2 Examples of photocurrent compensation techniques 5-9
....................... 5-3 Examples of photocurrent filtering techniques for linear and digital circuits 5-10
...........................................................................................
5-4 SEU hit response descriptions 5-25
.......................................................... 5-5 Circuit diagram of a gated-feedback bipolar SRAM 5.25
5-6 Circuit schematic for a gated-feedback CML SRAM cell .................................................. 5-26
..................................... 5-7 Cross-sectional representation of HFET device physical structure 5.29
5-8 Circuit schematic of an enhancement/depletion MESFET SRAM cell
................................................................ showing possible single-event-induced currents 5-30
5-9 Circuit schematic of a resistor-decoupling approach to hardening and
....................................................................... enhancement/depletion SRAM cell to SEU 5.3 1
5-10 Circuit schematic of an 8-transistor cell to harden an enhancement/depletion
........................................................................................................... SRAM cell to SEU 5.3 1
5-1 1 Generalized circumvention scheme ................................................................................... 5.33
5-12 Time lines for allowable outage budget ............................................................................. 5-34
................................................................................ 5- 13 Typical inherent spacecraft shielding 5.36
5-14 Accumulated dose over a 5-year mission as a function of aluminum shielding
thickness for a circular. 60-degree orbit at 2. 100 nrni altitude ............................................. 5-37
5- 15 Schematic of a common-emitter radiation-equivalent circuit .............................................. 5-38
TREE Handbook . List of Figures
Figure
5-16
5-17
5- 18
5-19
5-20
5-2 1
5-22
Pae;e
JFET circuit (2N3380) used to illustrate an upset calculation ............................................. 5-41
........................................................................ Example circuit for recovery-time analysis 5.42
............................................ Measurements and analyses required for error-rate prediction 5.45
.......... Memory-cell model for computer-aided circuit analysis to determine critical charge 5.46
....................................... Block diagram to determine if circuit survivability is mandatory 5-50
Block diagram of methodology for evaluating existing equipment ..................................... 5-50
Existing equipment hardening cost factors ........................................................................ 5-52
Chapter 6 Radiation Response Testing and Hardness Assurance
....................................................................... 6- 1 Container for Dose-Enhancement Reduction 6.3
6-2 Recommended Test Plan Outline for Long Term Ionization Tests ....................................... 6-5
6-3 Ionizing Radiation Dose Rate Test Plan Outline ................................................................ 6-11
.................................................................. 6-4 Transient Upset Test Flow for Digital Devices 6-14
................................................................... 6-5 Block Diagram of Typical LINAC Test Setup 6. 15
............................................................................................................
6-6 Latchup Test Flow 6. 18
.......................................................................................
6-7 Survivability/Burnout Test Flow 6-20
................................................................................
6-8 Suggested Neutron Test Plan Outline 6-24
6-9 Suggested SEE Test Plan Outline ...................................................................................... 6-28
.....................................................
6-10 Production Variations in Piecepart Radiation Response 6.43
........................... 6-1 1 Relationship Between Design Margins and Hardness Critical Categories 6.47
................................................... 6- 12 Hardness Critical Item (HCI) Categorization Flow Chart 6.48
................................... 6- 13 Relationship Between Design Margin and Transistor Current Gain 6.5 1
6-14 Relationship Between Elements of the Hardness Assurance Effort
and the Production Flow ................................................................................................... 6-62
xxxvi
TREE Handbook . List of Tables
Table Parre
Chapter 1 Introduction
................................................................ 1-1 NH&S requirements for representative systems 1-33
Chapter 2 Ionizing Radiation Effects
2- 1 Important terminology and units of radiation exposure .................................................... 2-5
2-2 Electronlhole pair generation energies and pair densities generated by 1 rad .................. 2-7
2-3 Characteristic radiation output and pertinent features of natural space.
nuclear explosions. and nuclear reactors .......................................................................... 2-8
2-4 Categorization matrix of possible ionizing radiation dose response types for
MOS devices. indicating qualitative features of response for each type ........................ 2-38
2-5 The effect of critical radiation environments on devices ................................................ 2-73
2-6 Summary of potential nonvolatile technologies ............................................................. 2-80
2-7 Comparison of several characteristics of solid-state electronic nonvolatile memory
.................................................................................................................... technologies 2.96
2-8 Properties of optical fibers .............................................................................................. 2-96
2-9 Fiber-optic parameters that affect radiation response .................................................. -2- 101
2-10 Impact of system requirements on fiber choice ............................................................ 2- 1 1 1
Chapter 3 Ionizing Dose Radiation Effects on Semiconductor Microelectronics
3-1 Transient effects on resistors .......................................................................................... 3-51
3-2 Composition of cosmic rays ............................................................................................ 3-57
Chapter 4 Displacement Damage Effects
4- 1 Calculated values (x lop3) of NIEL (E.P. Si) for neutrons. electrons. protons.
and deuterons incident on silicon .................................................................................... 4. 13
4-2 Failure mechanisms for semiconductor devices ............................................................. 4.3 1
4-3 Transistor damage factors and neutron failure levels for 50-percent hFE degradation ... 4-35
4-4 Neutron degradation in typical linear integrated circuits ................................................ 4-43
4-5 Neutron response of memories and microprocessors ..................................................... 4-44
4-6 Values for generation lifetime damage coefficient obtained from measurements
..................... performed on neutron-irradiated silicon devices by various investigators 4-60
TREE Handbook . List of Tables
Table
Chapter 5 Component and Circuit Design
5- 1 Semiconductor device selection guidelines for minimizing neutron damage
........................................................................................................... of sensitive devices 5-5
5-2 Device selection guidelines for transient ionization ......................................................... 5-6
5-3 Highly sensitive semiconductor devices ........................................................................... 5-7
5-4 Summary of bipolar flip-flop hardening techniques ....................................................... 5-27
5-5 Examples of device failure thresholds ............................................................................ 5-42
5-6 Screening parameters for various device types ............................................................... 5-43
5-7 Estimated Cost Increments Between Operational Military Satellites and
Nuclear Hardened Military Satellites .............................................................................. 5-48
Chapter 6 Radiation Response Testing and Hardness Assurance
............................................................................................... 6- 1 Dose Enhancement Factors 6-4
6-2 Linear Accelerator (LINAC) Characteristics .................................................................... 6-9
6-3 Flash X-Ray Simulator Characteristics ........................................................................... 6-10
6-4 Transient Upset Test Matrix for Logic Devices ............................................................. 6-13
6-5 Reactor Simulator Summary ........................................................................................... 6-22
6-6 Representative SEE Test Facilities ................................................................................. 6-27
6-7 One-sided Tolerance Limits. KTL (N. C = 0.9. P) ......................................................... 6-53
6-8 LTPD Sampling Plan ...................................................................................................... 6-55
6-9 MIL-STD Radiation Hardness Assurance Specifications ............................................... 6-57
6- 10 Group E (Radiation Hardness Assurance Tests) ............................................................. 6-59
6-1 1 HCC Requirements for Procuring. Marking. Sampling and Testing
of Non-RHA Pieceparts .................................................................................................. 6-64
xxxviii
CHAPTER 1
INTRODUCTION
1.1 Objectives and Applicability serve as a useful reference for program managers
The objective of the Transient Radiation EIfects
and system Program officers (SPOs) who must
on Electronics (TREE) Handbook is to (I) provide
manage the development of systems that have
information about radiation effects on semiconduc-
nuclear hardening and survivability requirements.
tor devices and materials, (2) provide guidelines
In addition, the handbook can serve as a guide for
for microelectronic radiation-hardening techno]-
making a qualitative aSSe~~ment of a system's t0l-
ogy, and (3) serve as a reference for radiation hard-
mince to radiation effects.
ness assurance and microelectronic radiation
testing.
The radiation environments addressed in this
handbook include those produced by nuclear
weapon effects (NWE) and natural space. The
NWE environment includes x rays, gamma rays,
and neutrons. The natural space environment in-
cludes protons and electrons trapped in the Van
Allen belt, and neutrons, heavy ions, and cosmic
rays found in space. Sections 1.3 and 1.4 describe
these radiation environments (threats) and present
information that will serve as background material
for subsequent discussions of radiation effects as
well as microelectronic radiation-hardening re-
quirements.
In general, there are two basic effects to be con-
sidered: ionization and atomic displacement.
X-ray, gamma-ray, electron, proton, and heavy-ion
interactions result in ionizing effects. Atomic dis-
placement effects are primarily the result of neu-
trons, protons, and heavy ions. These particles
also produce ionization, but only as a secondary
effect. Similarly, electrons and other charged par-
ticles can produce displacement effects.
This handbook is designed as a reference
manual for individuals with scientific backgrounds
(e.g., electronic and electrical engineers, physi-
cists, electronic technicians) who do not possess
in-depth knowledge of radiation effects on elec-
tronics and electro-optics. The handbook should
1.2 Handbook Organization
The information in this handbook is organized
into seven chapters. Chapter 1 is an introduction
to the subjects covered in this handbook. The en-
vironments of interest are described in summary
form. These are the NWE and natural space envi-
ronments. In addition, system development back-
grounds and the system nuclear hardening
requirements are discussed. Chapter 1 concludes
with a section on nuclear specification develop-
ment at the system level.
Chapter 2 discusses ionizing radiation dose
effects on electronic devices and circuits. The
chapter begins with radiation sources and their in-
teraction with matter. Basic mechanisms of ioniz-
ing radiation effects on electronic materials are
discussed. The chapter then addresses ionizing ra-
diation dose effects on linear and digital integrated
circuits fabricated from metal oxide semiconductor
(MOS) and bipolar transistors. Additional sections
describe nonvolatile memory technology and opti-
cal devices and optical fibers.
Chapter 3 presents ionizing dose rate effects in
microelectronics. The effects of ionizing dose rate
are presented for the same types of electronic de-
vices and circuits as discussed in Chapter 2 for
ionizing radiation dose. Transient upset and
latchup phenomena in integrated circuits are also
addressed. Chapter 3 concludes with a discussion
of single-event phenomena (SEP).
Chapter 4 presents displacement damage effects (EMP) by interaction with the atmosphere, weapon
on electronic devices and circuits. The basic debris, and system enclosures.
mechanisms of atomic displacement are discussed
The weapons designer usually describes the
in sufficient detail to aid the reader in calculating
nuclear explosion output in terms of energy, time,
its effects on circuit design. The effects on silicon-
direction, and integrated totals for gamma rays,
based microelectronics, GaAs devices, optical de-
neutrons, and rays. The system designer usually
vices, and silicon sensor arrays are then presented
describes the radiation field as it impinges on the
in more detail.
system in terms of energy per unit area, neutron
Chapter 5 covers the topics of component and
circuit design. Hardening methods based on de-
vice selection are presented after a brief introduc-
tion to hardened design procedures. Specific
hardening guidelines for linear and nonlinear cir-
cuits are given for displacement, ionizing radiation
dose rate, ionizing radiation dose, and single-event
effects (SEE). Basic analysis techniques and de-
vice models are discussed. Chapter 5 concludes
with a discussion of system-level guidelines and
the resources required for hardening. A final sec-
tion briefly discusses the evaluation of existing
systems.
Chapter 6 is concerned with radiation response
testing and hardness assurance. A discussion of
response testing includes information on test plan-
ning, testing guidelines, simulation facilities, and
testing specifics for each environment as well as
for combined environments. Radiation dosimetry
considerations are also included. The hardness as-
surance section describes basic concepts, piece-
part hardness assurance procedures and guidelines,
hardness categories, design margin, and statistical
concepts for hardening. Parts procurement and
acceptance tests are also addressed. A list of stan-
dard documents and specifications for testing and
parts procurement is included.
Chapter 7 contains the explanations for the acro-
nyms and symbols used in the handbook, as well
as a glossary defining the handbook's terminology.
1.3 Nuclear Weapon Effects Erasrironments
The primary nuclear explosion outputs of con-
cern in electronic systems are the neutrons, gamma
rays, and x rays. These outputs also generate sec-
ondary radiations and electromagnetic pulse
fluence, gamma exposure, and pulse shape as af-
fected by radiation transport through some inter-
vening material. Finally, the designer of the
individual electronic piece part or circuit is con-
cerned with describing the radiation in units that
are convenient for defining the radiation effect to
be taken into account, in terms of energy deposi-
tion per unit mass or volume, such as 1-MeV
equivalent neutron fluence, gamma dose, gamma
dose rate, and radiation pulse shape.
Most of the energy released in a nuclear explo-
sion heats the material of the nuclear device to
temperatures of tens of millions of degrees. A
fraction (0.1 to 10 percent) escapes promptly in the
form of fast neutrons and prompt gamma rays.
This intense thermal source radiates most of its
energy in the form of x rays.
After the prompt radiations have been emitted
from the nuclear explosion, a residue of hot, radio-
active debris remains. Some of its energy con-
tinues to be radiated as thermal energy in the
ultraviolet and visual regions of the spectrum.
Subsequent radioactive decay of the debris pro-
duces lower intensity gamma rays as well as high-
energy electrons. These electrons are particularly
important for high-altitude nuclear detonations,
which may inject the electrons into orbits trapped
by the earth's magnetic field.
If the explosion occurs within or near the atmo-
sphere, the prompt radiations interact with the at-
mosphere and produce secondary effects. The
x rays are absorbed most strongly and, depending
upon altitude, the air is heated by the interaction to
produce an intense thermal source and a blast
wave in the air. The neutrons interact with the at-
mosphere to produce secondary gamma rays. The
gamma rays interact to produce secondary elec- thermalization depend strongly on the interacting
trons. These secondary electrons in turn interact materials and the system configuration. All of the
with the air and produce additional electrons. The radiation of interest for transient radiation effects
net result is negatively charged electrons flowing on electronics arrive at the equipment within 1 sec-
radially outward from the explosion, while the ond.
heavier ions remain behind. If the explosion oc-
curs in a homogeneous (constant density) atmo-
sphere, two shells of charge are created: an inner
positive ion shell, and an outer negative electron
shell. A large local electric field is created in the
radial direction; however, under such conditions,
no electromagnetic field is radiated away. In prac-
tice, the earth's magnetic field, the earth's surface,
and other inhomogeneities will result in an EMP
emanating from the source region.
The general time frame for the arrival of the
various radiation components at the electronics
package is important. For the purposes of elec-
tronic vulnerability, the prompt gamma radiation
can be considered as a single pulse. Since the
flight time for x rays and gamma rays of all ener-
gies equals the speed of light, unscattered photons
arrive at the equipment with the same time distri-
bution they had at the source, with a time delay of
3.33 p s e c h from the weapon burst. The arrival
of the gamma pulse approximately coincides with
the unscattered prompt x rays.
The neutrons arrive after the initial gamma and
x-ray radiation. Their arrival time depends on the
neutron energy and the range to the receiver. The
first neutrons to arrive are the unscattered 14-MeV
neutrons. Their time of flight is 19.3 pseclkm;
therefore, they will arrive 16 pseckm after photon
arrival. The photons resulting from neutron inelas-
tic scattering also begin to arrive at about this time.
Within 32.8 pseckm (arrival time after photon ar-
rival for 4-MeV neutrons), the photons resulting
from neutron inelastic scattering is complete, since
the inelastic-scatter contribution is negligible for
lower-energy neutrons. Within 69.0 p s e c h , most
of the unscattered 1-MeV neutrons will have been
deposited. The photons resulting from neutron cap-
ture (or thermalization) typically will peak shortly
after the arrival of the 1-MeV neutrons. Both the
thermalization time and the capture time following
Gamma rays interact with matter in three ways.
In the Compton effect, the gamma ray collides
with an electron and some of its energy is trans-
ferred to the electron. This energetic electron
slows down through the scattering process, pro-
ducing a large quantity of low-energy electrons.
Secondary photons, which have less energy than
gamma rays, are also created. The Compton pro-
cess is the dominant ionization mechanism for
electronic materials such as silicon. In the photo-
electric effect, a photon, with energy somewhat
greater than the binding energy of an electron in an
atom, transfers all of its energy to the electron,
which is then ejected from the atom. Since the
photon involved in the photoelectric effect trans-
fers all of its energy, it ceases to exist and is said to
be absorbed. The third type of interaction is pair
production. When a gamma-ray photon with en-
ergy in excess of 1.02 MeV passes near the
nucleus of an atom, the photon may be converted
into matter with the formation of an equally but
oppositely charged pair of electrons. The positive
electron soon interacts with a negative electron to
form two photons, each having an energy of at
least 0.51 MeV. In some cases, if the interaction
takes place near the nucleus of a heavy atom, only
one photon of about 1.02-MeV energy may be cre-
ated. [For more details see EM-1, Chapter 8 (Kaul
et al., 1990)l.
Fast neutrons can produce ionization indirectly.
As neutrons undergo elastic and inelastic scattering
as well as capture in a material, emitted gamma
rays can cause ionization. In addition, collision of
a neutron with an atom may impart sufficient en-
ergy to the atom for it to cause ionization. The
14-MeV neutrons arising from fusion reactions in
a weapon are particularly important. Thermalized
neutrons can also contribute ionization by neutron-
capture gamma rays, particularly in those materials
that undergo (n,a) and (n,p) reactions.
Once the charged particles are created by the positively and negatively charged carriers, the con-
ionization processes (either primary or secondary), centration of minority carriers in the device is tem-
they undergo various reactions. Coulomb colli- porarily increased by ionizing radiation, and the
sions result in further ionization events. This pro- electrical operation of the device may be adversely
cess is very effective as long as the resultant affected.
progenies have energies greater than the ionization
potential of the medium in which they move.
Eventually, all the energy is dissipated by the cre-
ation of (almost) thermalized carriers (e.g., elec-
trons, ions, holes). Meanwhile, the initial particle
energy has been distributed over a volume encom-
passed by the primary and secondary particle
ranges and some net charge displacement has
occurred. The thermalized progenies are free to
move in the material, scattering frequently and fol-
lowing a random-walk pattern. If the concentra-
tion of electric charge carriers throughout the
material is not uniform and if no externally applied
electric field is present, the carriers will move from
regions of high concentration to regions of low
concentration. This movement is known as diffu-
sion and when it occurs, it is superimposed on the
normal random movement. If an applied electric
field is present, the carriers drift in the electric field
while they undergo random scattering. If impuri-
ties or lattice defects are present in the material (as
they always are in solid-state devices), carriers
may be captured (trapped) and immobilized by
impurity atoms and lattice defects (traps). Eventu-
ally, the trapped carriers will be annihilated by
their mates (oppositely charged carriers) in a pro-
cess called recombination. The net result of these
processes is that the carriers diffuse and/or drift
until they are trapped and (usually) recombined.
The free carriers produced during ionization re-
spond to an applied electric field by producing a
net drift current, the mechanism by which a mate-
rial conducts electricity. Therefore, ionization in-
duces a transient increase in conductivity.
Semiconductor devices employ both positively
and negatively charged carriers. The characteris-
tics of many such devices depend strongly upon
the instantaneous concentration of minority carri-
ers in various regions of the device. Since ionizing
radiation creates large (and equal) numbers of
When free carriers are created in a semiconductor
material and are trapped at impurity sites, many may
not undergo recombination with their mates, which
may be trapped elsewhere. In these cases, the mate-
rial properties may be altered semipermanently, even
though there is no net charge in the material. This
ionization effect is known as charge trapping.
The chemical effects of ionization occur during
the processes of trapping and recombination when
sufficient energy is available to disrupt chemical
bonds. When ionization is complete, permanent
changes of physical and/or electrical properties
may occur. The radiation dose required to cause
such effects is typically larger than that normally
encountered in TREE applications.
Displacement is an important phenomenon in
crystalline materials, and it is a very important
phenomenon in TREE because many electronic
devices (e.g., transistors, diodes, integrated cir-
cuits) are constructed from crystalline serniconduc-
tors - primarily silicon and germanium. Lattice
defects result from the displacement of atoms from
their usual sites in crystal lattices. The simplest
lattice defects, stable only at very low tempera-
tures, are extra atoms inserted between lattice po-
sitions (interstitial) and unoccupied lattice
positions (vacancies). At least part of the resultant
damage to the material is stable and accounts for
permanent property changes of irradiated crystal-
line materials.
The production of displacement damage in a
crystalline solid is a complex process. An abbrevi-
ated description of this process is given below:
1. Radiation of an appropriate form enters
the material, interacts with a lattice atom,
and imparts to it a certain energy.
2. The target (recoil) atom leaves its lattice
site, thus creating a vacancy, and collides
with other lattice atoms.
3. Other atoms are displaced from their sites,
creating yet more vacancies.
4. Eventually, most recoil atoms come to
rest in interstitial positions, while a few
fall into vacancies. Interstitials and va-
cancies are not stable at room temperature
and eventually disappear or form more
complex lattice defects.
5. The defects migrate through the crystal.
6. Eventually, the mobile defects are annihi-
lated by recombination of vacancy-inter-
stitial pairs, are immobilized by the
formation of stable defect clusters with
other impurities of lattice defects (either
present in the original material or created
by the irradiation), or escape to a free sur-
face.
7. Meanwhile, the physical properties of the
material are changed by the presence of
the defects.
1.4 Natural Space Radiation Environment
In this section, the earth's space radiation envi-
ronment is described in terms of trapped and
nontrapped charged particles as relevant to effects
on spacecraft electronics. The nature and magni-
tude of the spatial distribution and temporal varia-
tion in the trapped radiation environment are
presented. Transiting cosmic rays of galactic and
solar origin are described, and their interaction
with the earth's magnetic field is considered. In
terms of spacecraft electronics, accumulated dam-
age from electron and proton exposure will limit
system endurance. Transient effects from indi-
vidual high-energy protons or cosmic rays can dis-
rupt system operation, perhaps irreversibly.
The internal spacecraft radiation environment is
described in terms of shielding effectiveness
against the high-energy electrons, protons, and
cosmic rays of the external environment. Expo-
sure levels are presented in terms of ionizing radia-
tion dose and particle fluence to permit
comparison to electronic component damage sus-
ceptibility data. This will permit the assessment of
the potential frequency or probability of critical ef-
fects in the electronics. Of particular importance
are the limits in shielding effectiveness for high-
energy electrons, protons, and cosmic rays.
The interactions between the space radiation en-
vironment and spacecraft electronics include those
at the external surfaces as well as those within the
internal electronics. Important effects at the exter-
nal surfaces include degradation of solar cells and
charging of dielectric material, which can result in
transient-producing arc discharges. For these ex-
ternal effects, the characterization of the free-field
electron and proton environment as a function of
particle energy and time is important. The internal
spacecraft radiation environment is defined by par-
ticle transport through the spacecraft structure and,
when necessary, the shielding added to protect sen-
sitive electronic piece parts. Important effects on
the internal electronics are performance degrada-
tion resulting from energy deposition by accumu-
lated ionization in semiconductor materials,
accumulated atomic displacement damage in the
crystal semiconductor by high-energy protons, and
transient effects resulting from the ionization
tracks from the interaction of a single cosmic ray
or high-energy proton. Therefore, of particular in-
terest for effects on the internal electronics are the
total electron and proton exposure (i.e., fluence)
and the time-dependent rate of high energy protons
and cosmic rays (i.e., flux).
The earth's natural radiation environment con-
sists of electrons, protons, and heavy ions that are
either trapped by the earth's magnetic field, or that
are transiting through the domains of the earth's
artificial satellites. Trapped radiation and transit-
ing radiation environments are discussed below
[Subsections 1.4.1 and 1.4.21.
1.4.1 napped Radiation
As the earth sweeps through the solar wind, a
geomagnetic cavity is formed by the earth's mag-
netic field, as shown in Figure 1 - 1, which defines
the magnetosphere. The cavity is hemispherical on
PLASMASPHERE
Figure 1-1. The geometric cavity (Barraclough et al.,
the sun side, with a boundary at approximately 10
to 12 earth radii (Re = 6,380 km). On the night
side, it is cylindrical, approximately 40 Re in diam-
eter. Because of the sweeping action of the solar
wind, it extends over several hundred Re in the
antisolar direction. The main particle-trapping re-
gion, of specific interest here, is the cross-hatched
area labeled plasmasphere.
The total magnetic field of the magnetosphere is
defined in terms of two interacting and superim-
posed sources of internal and external origin. The
internal field of the earth is thought to be caused
by convective motion in the molten nickel-iron
core of the planet, and by a residual permanent
magnetism in the earth's crust. The external field
is comprised of the sum-total effect of currents and
fields set up in the magnetosphere by the solar
wind. The internal field component of the earth's
magnetic field exhibits gradual changes with time,
characterized as secular variations (Barraclough et
al., 1975; IAGA, 1986). These temporal effects
are also observed in the shrinking value of the
earth's dipole moment and the drift in the location
of the boreal (north) and austral (south) magnetic
poles.
1975; IAGA, 1986; Spjeldvik and Rothwell, 1983).
Superimposed on these slow internal changes
are cyclic variations in the external field, whose
magnitudes depend on the degree of perturbation
experienced by the magnetosphere. Specifically,
strong perturbations of the geomagnetic field are
present in the outer magnetosphere and depend on
local time (diurnal effects), season (tilt effects),
and solar wind conditions (including solar flares)
(Stassinopoulos and King, 1974). All of these af-
fect the magnetospheric current systems, which in
turn modify the local field values.
A characteristic of the geomagnetic field, of par-
ticular significance to space radiation effects in
electronics, is the Brazilian or South Atlantic
anomaly (SAA). This is primarily the result of the
offset of the dipole term of the geomagnetic field
by approximately 11 degrees from the earth's axis
of rotation and its displacement of about 500 km
toward the Western Pacific. The effect is an appar-
ent depression of the magnetic field over the coast
of Brazil. There, the Van Allen belt reaches lower
altitudes, extending down into the atmosphere.
The SAA is responsible for most of the trapped
radiation received in low-earth orbits (LEO). In
contrast, on the opposite side of the globe, the
Southeast-Asian anomaly displays correspondingly
stronger field values, and the trapped-particle belts
are located at higher altitudes.
1.4.1.1 napped Radiation Domains
The earth's magnetic field, above the dense at-
mosphere, is populated with trapped electrons, pro-
tons, and a small number of low-energy, heavy
ions. These particles gyrate around and bounce
along magnetic field lines and are reflected back
and forth between pairs of conjugate mirror points
(i.e., regions of maximum magnetic field strength
along their trajectories) in opposite hemispheres.
At the same time, because of their charge, elec-
trons drift eastward around the earth, while protons
and heavy ions drift westward. Figure 1-2 illus-
trates the spiral and drift motion of the trapped par-
ticles.
The magnetosphere can be divided into five do-
mains for populating or visiting particle species, as
shown in Figure 1-3. The strong dependence of
trapped particle fluxes on altitude and latitude is
expressed in terms of the McIlwain L parameter
(McIlwain, 1961), where L is a dimensionless ratio
of the earth's radius, approximately equal to the
geocentric distance of a field line in the geomag-
netic equator. Also shown in Figure 1-3 are the
domains mapped by using the dipole field equa-
tion:
R = L cos2 A,
(1.1)
(or R-L space), where R is the radial distance and
L is the invariant latitude. It should be noted that
the representation using L becomes increasingly
invalid for equatorial distances greater than four
times Re because of the more complex particle
motion in the geomagnetic field and the distortion
of the geomagnetic cavity by solar wind
interaction effects.
The indicated domain boundaries should be con-
sidered only as transitions, and not as actual lines.
These boundaries are assumed for modeling pur-
poses and, additionally, are used here for a qualita-
tive picture of the charged-particle distribution.
"Real" boundaries are diffused areas, varying with
particle energy, and fluctuating in position due to
magnetic perturbations, local time effects, solar
cycle variations (minimum and maximum activity
phases), and individual solar events.
MIRROR POINT
.....
" .
-... -...
...
. ..-, .....
Figure 1-2. Trapped particle trajectory and drift motion (Spjeldvik and Rothwell, 1983).
Electrons. Energetic Van Allen belt electrons
are distinguished into "inner zone" and "outer
zone" populations. The volume of space occupied
by the inner zone extends at the equator to about
2.4 Re. These domains are indicated in Figure 1-3
& 1-4 by region 1 for the inner zone electrons,
and by regions 2 through 4 for the outer zone elec-
trons. The L = 2.8 line is used to separate the in-
ner and outer zone domains, while the termination
of the outer zone at L = 12 is intended only to de-
lineate the maximum outward extent of stable, or
pseudoelectron, trapping. The region between L =
2.5 and 2.8 is called the "slot." During magneto-
spherically quiet times, its electron density is very
low. However, during magnetic storms, the elec-
tron flux in the slot may increase by several orders
of magnitude.
The inner zone electrons are less severe com-
pared to the outer zone electrons. Specifically, the
outer zone has peak fluxes exceeding those of the
inner zone by about an order of magnitude. Addi-
-2.8 1 -5.0 -12.0
I
I
I
1 3 5 7 9 11 13
L (earth radii)
INNER ZONE TRAPPED
ELECTRONS PROTONS
OUTER ZONE SOLAR FLARE
ELECTRONS PROTONS
tionally, the outer-zone spectra extend to much
higher energies (- 7 MeV) than the inner-zone
spectra (< 5 MeV). In this subsection, a detailed
description of both the external and internal radia-
tion environments is presented for LEO in the in-
ner zone, and for geostationary earth orbits (GEO)
within the outer zone.
Protons. Protons with energies greater than 10
MeV populate regions 1 and 2 with an approxi-
mate trapping boundary placed at L = 3.8, as
shown in Figure 1-3. In contrast to electrons, the
energetic trapped protons (E > 1 MeV) occupy a
volume of space that varies inversely and mono-
tonically with their energy, as shown in Figure
1-4. Consequently, these particles cannot be as-
signed to inner and outer zones. Figure 1-5 shows
the proton flux intensities as a function of radial
distance and energy. In low-earth orbits, the most
intense and penetrating radiation is encountered in
the form of protons in the SAA.
Figure 1-3. Charged-particle distribution in the magnetosphere (Stassinopoulos and Raymond, 1988).
solar cycle dependence is reflected by the average
-
-
- conditions for the solar minimum and solar maxi-
-
mum activity phases of the 1 1-year cycle.
-
-
The predictions of these models for LEO mis-
-
sions are presented in Figures 1-6 and 1-7. Figure
1-6 gives the integral proton spectra for a circular
-
500-km, 60-degree-inclination orbit, for both solar
-
-
- minimum and solar maximum conditions. The
-
z
relative hardness of the LEO proton spectrum
-
Z.
- should be noted. Between 50 and 500 MeV, the
w
proton flux decreases only by a factor of 4. Figure -
1-7 presents the comparable data for the trapped
- electron environment.
-
-
-
-
The geosynchronous integral electron spectra,
-
obtained from the AE8-MAX model, are plotted in
Figure 1-8. Worst and best cases are shown, cor-
responding to "parking" longitudes at 160W
(L = 7.0), and 70W (L = 6.6), respectively. The
flux ratio between the worst and best cases is about
2 3 4 5 6 7
GEOCENTRIC RADIAL DISTANCE ALONG EQUATOR
1.8 for electron energies greater than 1 MeV, and
(earth radii) 2.3 for electron energies greater than 2 MeV.
The proton spectrum at GEO, in contrast to that
Figure 1-4. Trapped proton population as a function
of energy (Stassinopoulos and Raymond, 1988).
of LEO, is very soft and essentially is depleted for
proton energies greater than 1.75 MeV. Thus,
trapped protons in GEO are stopped by very small
1.4.1.2 Trapped Radiation Models
material thicknesses (approximately 0.05 mm of
Available radiation measurements from space
al~minLIm) and are not of Concern to the internal
form the basis for models of the trapped electron
and proton environment. These models have been
1.4.1.3 Trapped Radiation Variations
developed by the U.S. National Space Science
Data Center (NSSDC) at NASA's Goddard Space
The trapped particle fluxes respond to changes
Flight Center. All models are constructed with
in the geomagnetic field induced by solar activity
and, therefore, exhibit a strong dynamic behavior,
several dozen data sets from a corresponding num-
especially in the outer belts. Satellite measure-
ber of satellites, providing a wide spatial and a
ments in geosynchronous equatorial orbits have
long temporal coverage.
revealed a complicated temporal pattern consisting
The most recent models, AP8 for Protons (Saw-
of the superposition of several cyclical variations
Yer and Vette, 1976) and AE8 for electrons in conjunction with sporadic fluctuations
(NASA, n.d.), permit long-term average predic- (Lanzerotti, Roberts, and Brown, 1967; Lin and
tions of trapped particle fluxes encountered in any Anderson, 1966; O'Br-en, 1963). The main per--
orbit; they currently constitute the best estimates odic variations include a diurnal cycle, which in
for the trapped radiation belts. However, statistics GEO is characterized by ~ r d e r - o f - ~ a ~ ~ i t u d e elec-
associated with random fluctuations and short-term tron flux changes, and the 11-year solar activity
cyclical variations have been averaged out. The cycle.
1 2 3 4 5 6 7
DIPOLE SHELL, L
Figure 1-5. Equatorial radial profiles for proton fluxes (Stassinopoulos and Raymond, 1988).
Sporadic magnetic storms in GEO can produce larly protons, occurs in the low-altitude regime of
a modulation of the electron flux above 50 keV by the magnetosphere. Here, during the active phase
an order of magnitude within a period of less than of the solar cycle, the increased energy output from
10 minutes (Lin and Anderson, 1966), and with a the sun causes the atmosphere to expand, thereby
corresponding decay in days. Substorms, which raising the density of the atmospheric constituents
are a common feature of the midnight-to-dawn normally encountered at heights between 200 and
sector of a GEO orbit, result in the injection of 1,000 km.
electrons with energies between 50 and 150 keV
The solar-cycle variations observed in some
from the magnetospheric tail region.
areas of the trapped particle domain are functions
Another important solar-activity-induced modu- of energy and magnetic parameter L. They gener-
lation of the trapped particle population, particu-
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ally have opposite effects on each particle specie,
Electron
I Intensities 1 Lower 1 Higher
particularly in the low-altitude regime:
1 t i e 1 Higher 1 Lower
Solar
Minimum
No solar-cycle changes of consequence have
been measured in the heart of the proton trapping
domain. No significant long-term variations, with-
in current models, occur in the electron popula-
tions at geostationary altitudes. However, in the
atmospheric cutoff regions, electron and proton
populations may vary by as much as a factor of 5.
1.4.1.4 Flux-Free Time
As mentioned previously, the SAA is a region of
trapped particle radiation close to the earth.
Hence, for low-altitude, low-inclination orbits, the
SAA is the most important factor in determining
the level of radiation exposure for spacecraft. For
LEO with higher inclinations ( > 30 degrees) the
protrusions of the outer-zone electron belts (the
electron "horns") in the midlatitude regions must
also be considered. Of particular importance is the
temporal distribution of the proton exposure,
which determines the maximum rate of potential
proton-induced single-event upsets (SEU) in elec-
tronics, as well as the periods during which no up-
sets are observed.
The intermittent exposure of LEO satellites to
the trapped Van Allen belt radiation is illustrated
for electrons in Figure 1-9 for a circular 900-km,
99-degree-inclination orbit during its worst pass
through the SAA. Note in Figure 1-9 that even in
a worst-case pass, there are time periods during
which instantaneous electron fluxes above 0.5
MeV are below 1 particle/cm2-sec. The same pe-
riods are the "flux-free time" (FFT) intervals,
which may occur over short orbit segments (partial
FFT per period) or over the entire length of a revo-
lution (total FFT per period). In terms of geomag-
Solar
Maximum
netic geometry, FFT establishes the duration for
which the trajectory lies outside the trapping do-
main of the corresponding particle species, evalu-
ated at the given energies.
1.4.1.5 Arti6cial Enhancement
A severe hazard for space missions could be in-
troduced by a high-altitude nuclear explosion.
Such an effect would result in the injection into the
magnetosphere of energetic electrons from the beta
0 1 2 3 4 5 6 7
ENERGY, E (MeV)
Figure 1-8. Geostationary electron spectra
(Stassinopoulos and Raymond, 1988).
NORTH
POLAR
EGlON
NORTHERN
HORN
Q)
ENERGY, E
U) (MeV)
>0.5
*
i
OUTER ZONE
EQUATORIAL REGION SOUTH
POLAR
REGION
ENERGY, E
(MeV)
>0.5
20 30 40 50
SOUTHERN
HORN
ENERGY, E
(MeV)
>0.5
NORTH
POLAR
REGION
NORTHERN
HORN
ENERGY, E
(MeV)
9.5
A
-
-
-
-
-
-
-
-
- -
-
-
-
-
-
- -
- -
-
-
-
-
- -
-
- -
EQUATORIAL REGION
-
GLOBALLY OPPOSITE SAA
-
-
-
OUTER ZONE
-
OUTER ZONE
-
- -
-
-
-
-
2
60 70 80 90 100 110 120
RELATIVE TIME (minutes)
Figure 1-9. Electron flux profile for a worst-case pass through the South American anomaly; circular 900-km,
99-degree-inclination orbit (Stassinopoulos and Raymond, 1988).
decay of fission fragments. Subsequent trapping
of the electrons in the magnetic field (Teague and
Stassinopoulos, 1972) could produce an enhance-
ment of the electron population by many orders of
magnitude.
The principal hazard would be to LEO missions
mainly because very stable trapping is expected,
with anticipated lifetimes of up to 8 years (Teague
and Stassinopoulos, 1972). Figure 1-10 shows the
isochronal contours for the trapped electrons re-
sulting from the Starfish atmospheric nuclear ex-
plosion over Johnston Island in the Pacific (July
1962). Typical nuclear enhanced electron doses as
a function of LEO altitude (60" inclination) are
shown in Figure 1- 1 1. Doses are given for 180
days behind a 100-mil aluminum slab shield.
Doses are given for 20 kt, 100 kt, and 1.5 - 15 Mt
nuclear detonations at optimum burst height over
the equator. Nuclear bursts over other regions pro-
duce similar enhancement but with doses lower
than those indicated in Figure 1-1 1 (Wenaas,
1991).
Depending on the location of the explosion, the
injection could also produce a temporary enhance-
ment of the electron environment at geostationary
orbits. At GEO, the trapping would be less stable,
with exponential decay periods of between 10 and
20 days. The apparent longevity (or conversely, the
YEARS
/-
4 . 5 C 3 ,
Figure 1-10. Isochronal contours for electron longevity
following the Starfish nuclear detonation in July 1962
(Teague and Stassinopoulos, 1972).
decay rate) of such fission electrons depends to a
large extent on the injection latitude and altitude;
that is, it is a function of the magnetic dipole shell
parameter L and, to a lesser degree, of magnetic
field strength (Stassinopoulos and Verzariu, 197 1).
An example of nuclear-detonation induced dose
enhancement at GEO orbits is shown in Figure
1- 12 for a 100 kt burst and nuclear-saturated elec-
tron belts. While significant enhancement of the
180-day dose is noted for the case of saturated
belts, near-earth nuclear detonations only add
small doses to the natural radiation environment
(Rogers, 1993).
For internal electronics, it is important to note
that both the total ionizing exposure level and ex-
posure dose rate are substantially increased by the
artificially enhanced environment.
CIRCULAR ORBIT ALTITUDE (km)
Figure 1-11. Electron dose (180 day) in LEO orbits as a
function of altitude enhanced by the nuclear detonations
shown (Wenaas, 1992).
100 KT (I80 DAYS) + NATURAL
1 o3
0 10 20 30 40 50
TANTALUM SHIELD THICKNESS (mil)
Figure 1-12. Ten-year doses in GEO orbit enhanced by a
100 kt nuclear burst with saturated belts. Doses are behind
a 100 mil aluminum slab shield augmented by the Ta shield-
ing shown (Rogers, 1993).
1.4.11,6 Emerging Radiation
In interacting with spacecraft materials, the elec-
trons and protons of the trapped radiation belts are
modified in intensity by shielding and in character
through the production of secondary radiation.
The secondary radiation can extend the penetration
of the primary radiation and lead to an increase in
dose deposition over that of the attenuated incident
radiation. The most significant secondary radia-
tion is the brernsstrahlung, or "braking radiation,"
produced in the deceleration of electrons penetrat-
ing the spacecraft. This continuous x ray spectrum
is emitted roughly in the direction of electron pen-
etration and its mean energy is about one-third of
the initial electron energy. The bremsstrahlung in-
tensity depends linearly on the atomic number (Z)
of the spacecraft material and on the square of the
initial electron energy. Bremsstrahlung from ener-
getic electrons populating the radiation belts is
very penetrating, and thus difficult to attenuate, es-
pecially with the low-Z materials commonly used
on spacecraft (e.g., aluminum). On the other hand,
these low-Z materials tend to produce less
brernsstrahlung.
Electrons and Bremsstrahlung. To illustrate,
Figure 1- 13 and 1- 14 show the merging electron
and bremsstrahlung spectra behind spherical alu-
minum shielding for the incident environment of a
circular 500-km, 60-degree inclination orbit. As
the curves of Figure 1-13 clearly indicate, the
trapped electrons are effectively attenuated by the
aluminum shield, and nearly all are stopped by
thicknesses greater than 0.2 g/cm2, even at the
highest electron energies. However, as shown in
Figure 1- 14, the bremsstrahlung flux levels for en-
ergies above 70 keV are not significantly affected
by the aluminum shielding from 0.1 to 10 g/cm2.
It is important to note, however, that above 100
keV, the photon fluxes are, on the average, over
three orders of magnitude lower than the incident
electron flux at corresponding energy levels.
Trapped Protons. The transport of trapped
protons is illustrated in Figure 1-15, which shows
the emerging proton spectra behind various spheri-
cal aluminum shield thicknesses for a circular 500-
km, 60-degree-inclination orbit. As shown, the
aluminum shielding is very effective for low en-
ergy protons, but ineffective for high-energy ( > 30
MeV) protons. The shielding effectiveness of low
proton energies is important in reducing ionizing
energy deposition in the internal electrons. On the
other hand, hardening the proton spectra provides
little help in reducing potential proton-induced
SEUs.
1.4.1.7 Ionizing Radiation Dose
To illustrate the ionizing dose exposure, daily
dose values for LEO and GEO are presented in
Figures 1 - 16 through 1 - 18. The materially attenu-
ated doses and fluxes presented were calculated
with state-of-the-art transport codes (Jordan, 1982;
Seltzer, 1980).
Daily silicon doses in LEO at 500-km altitude
and 60-degrees inclination for solar minimum and
maximum, are shown in Figure 1-16 for a two-
sided (4n) exposure of aluminum slab shields, and
for a solid spherical shield averaged over 15 orbits.
The electron dose includes the bremsstrahlung
contribution.
As discussed previously, the SAA is the primary
contributor to doses accumulated by spacecraft in
LEO. Figure 1-17 shows electron plus brems-
strahlung dose contours at an altitude of 500 km
for a spherical aluminum shield thickness of 0.2 gl
cm2. Superimposed on the world maps are the
worst-case passes thorough the SAA for 28.5-,
57-, and 90-degree-inclination orbits. As men-
tioned previously, for low-inclination orbits (< 45
degrees), there are periods when complete revolu-
tions are in flux-free time.
The corresponding electron-plus bremsstrahlung
daily dose for an aluminum shield of solid-sphere
geometry in GEO at the parking longitude, with
the lowest average flux (70W), is illustrated in
Figure 1 - 18 in the form of a dose-depth curve. For
the parking longitude with the large average flux
(160W), the dose behind a 2-g/cm2 shielding
thickness is a factor of about 1.7 higher; this is true
for all shield geometries.
The ten-year total doses for some typical LEO
and GEO orbits are shown in Figures 1-19 and
1-20. These curves are useful for estimating the
total dose encounters for typical circular and ellip-
tic orbits. These curves were calculated using the
AP8 and AE8 models for spherical (Figure 1-19)
and slab shielding conditions.
10" &
k i-I
-
i \ \
-
\ -
................................................. .... ........... ................... ............ 1010 SHIELD i.. \ INPUT ELECTRON , -
-
THICKNESS \'c\ SPECTRUM -
-
-
-
-
-
.............................................. ....................................................... ..................................................
103 - -
- I ""_
-
-
-
1 o2 T
l o- z 2 4 6 810-1 1 0 10'
ENERGY, E (MeV)
Figure 1-13. Emerging electron spectra behind various thicknesses of spherical aluminum shields; circular 500-km,
60-degree orbit at solar minimum, BL time = 1998.0 (Stassinopoulos and Raymond, 1988).
ENERGY, E (MeV)
Figure 1-14. Emerging bremsstrahlung spectra behind various thicknesses of spherical aluminum shields; circular
500-km, 60-degree orbit at solar minimum, BL time = 1998.0 (Stassinopoulos and Raymond, 1988).
1 oO 10'
ENERGY, E (MeV)
Figure 1-15. Emerging trapped proton spectra behind various thicknesses of spherical aluminum shields; circular
500-km, 60-degree orbit at solar minimum, BL time = 1998.0 (Stassinopoulos and Raymond, 1988).
10'
3 1
-
-
*\ i - TRAPPED PROTONS
-
\ i - - TRAPPED ELECTRONS -
;..\ - .... j . . . . . . AND BREMSSTRAHLUNG. -
-
6
-
4
-
-
-
(a) Solar Minimum
-
-
- TRAPPED PROTONS
-
- - TRAPPED ELECTRONS -
(b) Solar Maximum
Figure 1-16. Daily doses for LEO (500-km, 60-degree orbit); silicon target, aluminum shield
(Stassinopoulos and Raymond, 1988).
-
CONTOURS (rads[Al] x lo*)
-- ORBIT (degrees)
LONGI TUDE (degrees)
Figure 1-17. World map contours of total electron plus bremsstrahlung dose (radslpsec) at 500-krn altitude for a
spherical aluminum shield thickness of 0.2 g/cm2, BL time = 1964 (Stassinopoulos, 1990).
BREMSSTRAHLUNG j
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
SHIELD THICKNESS (@crn2) SHIELD THICKNESS (gcm2)
(a) Best Case (Parking Longitude 70W) (b) Worst Case (Parking Longitude 1 60W)
Figure 1-18. Daily electron doses for GEO for a silicon target behind solid-sphere aluminum shielding (Stassinopoulos
Raymond, 1988).
and
SPHERE RADIUS (mil)
Figure 1-19. Ten year total dose for various typical or-
bits at the center of aluminum sphere based on AP8 IAE8
models (Hopkins, 1993).
The topic of damage to semiconductor devices
resulting from both ionizing and non-ionizing ra-
diation events is covered in more detail in subse-
quent chapters of this handbook. However, a brief
discussion of these effects is provided here to as-
sist in understanding the discussion of both the
natural space radiation environment and nuclear
weapon effects on semiconductor devices.
1.4.1.8 Susceptibility of Electronics to
Permanent Damage
The basic permanent damage mechanisms in
semiconductor devices exposed to high-energy
electrons and protons are accumulated ionization
effects and atomic displacements in bulk semi-
conductors. Effects of electron exposure in virtu-
ally all modern microcircuits are dominated by
accumulated ionization. Definition of the internal
ionizing radiation environment in terms of rads(Si)
is generally adequate. Failure levels resulting from
mately 1,000 rads(Si) for commercial microcir-
cuits, or greater than 10 Mrads(Si) for hardened
microcircuits.
Effects of proton exposure over the energy
range of interest in the space environment include
both ionization and displacement damage
(Petersen, 198 1). Failure levels resulting from pro-
ton-induced displacement damage can be as low as
1 x 10lo particles/cm2 for sensitive bipolar analog
microcircuits, power transistors, or CCD imagers.
The definition of the proton environment for the
internal electronics should include both the proton-
induced ionization (in rads[Si]), and the internal
proton fluence and energy spectra for displacement
effects.
Single-Event Susceptibility of Electronics.
Single-event phenomena (SEP) in semiconductor
electronics will be discussed in detail in Chapter 3
of this handbook. However, for the purposes of
- -
accumulated ionization can be as low as approxi- this discussion, SEP is defined as the nonperma-
nent upset of the state of an electronic circuit (e.g,
1 iE 0 or 0 iE 1) caused by the deposition of a criti-
cal amount of charge at the information node (e.g.,
memory cell or a bistable flip-flop).
The high-energy protons of the trapped space
radiation environment can cause single-event ef-
fects (SEE) in modern semiconductor electronics.
The proton energy threshold for these effects is
approximately 10 MeV, with the cross section for
nuclear reactions increasing substantially at 30
MeV and above (Raymond and Petersen, 1987).
Typically, a nuclear reaction resulting in a single
event occurs on the order of once every 100,000
protons. In terms of microcircuit susceptibility, for
a 60-degree orbit, the maximum proton-induced
upset rate occurs in the heart of the proton-trapping
domain of the radiation belts at an altitude of ap-
proximately 2,600 km. It has been estimated that
for electronics with "typical" shielding, the SEU
rate could be as high as 0.1 upsethit-day for sus-
ceptible microcircuit technologies, decreasing by
at least five orders of magnitude for tolerant rnicro-
circuit technologies (Bendel and Petersen, 1983).
At low-altitude, low-inclination orbits, the
proton-induced SEU rate is determined by pas-
sages through the SAA. During FIT, the electron-
ics will be free from trapped-proton SEUs.
1.4.2 Transiting Radiation
The transiting radiation of the space radiation
environment is composed of a solar contribution
and a galactic contribution. Each is composed of
high-energy protons and heavy ions. In terms of
the spacecraft electronics, the dominant effects are
those associated with the ionization tracks of
single particles, as well as the effects of total accu-
mulated ionization. As with the trapped radiation
environment, the external environment will be pre-
sented, followed by a discussion of the internal
environment, and finally transiting radiation ef-
fects in spacecraft electronics will be addressed.
1.4.2.1 Solar Cosmic Rays
Solar Flare Protons. Disturbed regions on the
sun sporadically emit bursts of energetic charged
particles into interplanetary space. These solar en-
ergetic particle events (usually occurring in asso-
ciation with solar flares) are composed primarily
of protons, with a minor constituent of alpha par-
ticles (5 to 10 percent), heavy ions, and electrons.
The emission of protons from a solar energetic par-
ticle event can continue for as long as several days.
The time history of energetic solar flare particles
as they arrive at the earth after the occurrence of
the parent flare has several important characteris-
tics. First, the particles arrive in tens of minutes to
several hours (depending on their energy and point
of origin on the sun); second, they peak within 2
hours to 1 day; and third, they decay within a few
days to 1 week. It is important to note that the
most energetic protons arrive at the earth in about
10 to 30 minutes.
Solar energetic particle event phenomenology is
distinguished by ordinary events and anomalously
large events. Anomalously large events are quite
rare. Figure 1-21 shows the energetic solar flare
proton events since 1956. As shown, three anoma-
lously large events occurred during solar cycle 19,
one during cycle 20, and none in cycle 21
(Goswami et al., 1987). Anomalously large events
are those having proton fluences > 10l0 particles1
cm2. They usually occur near the first and last
year of the solar maximum phase. The prediction
of anomalously large events was initially based on
an empirical model (Stassinopoulos and King,
1974), and later on a probabilistic treatment in-
volving modified Poisson statistics (King, 1974).
A simple statistical predictive model for solar
flares is provided by SOLPRO (Stassinopoulos,
1975), which is based exclusively on satellite spec-
tral measurements that nearly cover solar cycle 20
entirely. This model predicts, for a given mission
duration and a specified confidence level, the mis-
sion-integrated proton fluence spectrum from ordi-
nary events and the expected number of
anomalously large events with their event-inte-
grated fluence spectra. In terms of proton fluence,
since anomalously large events are rare, small-
sample statistics are the only appropriate predic-
tion technique. Thus, for spacecraft mission
YEAR
19 20 21
SOLAR CYCLE
Figure 1-21. Solar flare proton events for solar cycles 19,20, and 21 (Stassinopoulos and Raymond, 1988).
durations longer than one year, ordinary event flu-
ences are insignificant because probability theory
predicts the occurrence of at least one anomalously
large event, even for a confidence level as low as
80 percent.
Solar Heavy Ions. For ordinary solar flare
events, the relative abundance of the helium ions
in the emitted particle fluxes is usually between 5
and 10 percent, while the fluxes of heavier ions are
very small and significantly below the galactic
background. However, during major solar events,
the abundance of some heavy ions may increase
rapidly by three or four orders of magnitude above
the galactic background for periods of several
hours to days. The increased flux of the heavy
ions can have serious consequences in terms of an
increased frequency of single-event effects within
the spacecraft electronics.
1.4.2.2 Galactic Cosmic Rays
The region outside the solar system in the outer
part of the galaxy is believed to be uniformly filled
with cosmic rays, which consist of - 85 percent
protons, - 14 percent alpha particles, and - 1 per-
cent heavier nuclei. The galactic cosmic rays
range in energy to greater than 10 GeVInucleon.
Figure 1-22 shows the spectral distributions for hy-
drogen, helium, carbon, and oxygen ions. The dif-
ferential energy spectra of the cosmic rays near the
earth tend to peak around 1 GeVInucleon. To-
ward lower energies, the spectral shape is de-
pressed by interactions with the solar wind and the
interplanetary magnetic field. This reduction in
flux becomes more pronounced during the active
phase of the solar cycle. The total flux of cosmic-
ray particles seen outside the magnetosphere at the
distance of the earth from the sun (i.e., 1 astro-
nomical unit) is approximately 4/cm2-sec (prima-
rily composed of protons). For all practical pur-
poses, the cosmic-ray flux can be considered as
omnidirectional, except for very-low-altitude or-
bits, where the solid angle subtended by the earth
defines a region free from these particles. Figure
1-23 shows the relative abundance of the galactic
cosmic-ray ions. A model for these particles is
provided in Adams, Silberg, and Tszo (1981).
1.4.2.3 Geonlagnetic Shielding
Low-altitude earth orbits are essentially shielded
from solar or galactic cosmic rays by the geomag-
netic field up to inclinations of about 45 degrees.
The earth's field acts as an energy filter, preventing
particles with less than given momentum values
from penetrating to certain altitude-latitude combi-
1 0-7
10-2 10-1 1 o0 I o1 1 02 I o3
KINETIC ENERGY (GeWnucleon)
Figure 1-22. Cosmic-ray spectral distributions
(Stassinopoulos and Raymond, 1988).
nations. Figures 1-24 and 1-25 show the total ion
energy required to penetrate the magnetosphere in
terms of the dipole parameter L. Figure 1-26
shows the effects of geomagnetic shielding on so-
lar flare protons for high-inclination (greater than
60 degrees) LEO. Figure 1-27 shows the effect of
shielding on cosmic-ray silicon atoms for LEO.
For GEO, magnetic shielding is relatively inef-
fective, and such orbits will be exposed to galactic
cosmic-ray hydrogen of energies greater than
about 60 MeV, and to heavier ions whose energy
exceeds 15 MeVInucleon.
1.4.2.4 Transport and Shielding
Transiting radiation and shielding evaluation
require consideration of shield geometries and evalu-
ation techniques, shield composition, target composi-
tion, and dose units.
Solar Flare Protons. Considerations of solar
flare protons transport are similar to those previ-
ously discussed for trapped protons [Subsection
1 o0
8
6
0 5 10 15 20 25 30
ATOMIC NUMBER (Z)
Figure 1-23. Relative abundance of nuclei in ga-
lactic cosmic radiation (Stassinopoulos and
Raymond, 1988).
R = (A/z)[T~ + 2r(rno~2)]1/2 in GeV
L = [14.9/~(10-3)]1/2 for R in MeV
Figure 1-24. Contours of total energy required to penetrate the magnetosphere (Stassinopoulos and Raymond, 1988).
1.4.1.6, "Emerging Radiation"]. The materially at-
tenuated emerging spectra reflect the shielding ef-
fect on the distribution of the solar flare protons, as
shown in Figure 1-28. The proton fluxes in the
0.1- to 10-MeV range emerging behind spherical
aluminum shields of 0.3- to 5-g/cm2 thickness are
substantial. Particularly relevant to single-particle
event effects in electronics is the linear energy
transfer (LET) in silicon, defined as the energy
deposition per unit length in the active region of
the semiconductor device. The LET spectrum for
one anomalously large event behind spherical alu-
minum shields of two thicknesses is shown in Fig-
ure 1-29 for the interplanetary solar flare proton
spectrum not attenuated by the magnetosphere.
Stopping powers (dE/dx) were calculated from the
classical equation (Bethe, 1920). The Bethe for-
mula is accurate to about 20 percent at a few mil-
lion electron volts per nucleon (Littmark and
Zeiger, 1980). The error decreases at higher ener-
gies, where the assumptions of the Bethe formula-
tion are increasingly valid. At energies below a
few MeV per nucleon, the error increases due to
unmodeled details of the energy-loss mechanisms.
In general, the ionization loss of a single proton
is insufficient to cause a single-event effect in a
semiconductor device. Observed single-event ef-
fects from proton exposures are the result of the
energy deposition of particles produced by nuclear
interactions of the incident proton with the target
nucleus. The proton threshold energy for these
nuclear interactions is approximately 30 MeV
(Bendel and Petersen, 1983).
Galactic Cosmic Rays. Figure 1-30 shows the
unattenuated interplanetary spectra for silicon
cosmic-ray ions, the magnetospherically attenuated
orbit-integrated spectra incident on the surface of the
spacecraft, and the shielded spectra of emerging par-
ticles behind selected thickness of spherical alurni-
num geometries for a 600-km, 57-degree-inclination
orbit. Differential particle fluxes are shown refer-
enced to the left ordinate. The LET spectrum of the
silicon ion as a function of energy is referenced to the
right ordinate. The LET spectrum is important in
defining the energy deposited by a single particle and
evaluating subsequent single-event effects in the
spacecraft electronics.
In passing through shielding material, nuclear
reactions are induced by heavy ions with energies
above an effective threshold of a few million elec-
tron volts per nucleon. These nuclear reactions
provide a source of secondary radiation, both
prompt and delayed. Above several hundred mil-
lion electron volts per nucleon, nuclear reactions
surpass atomic ionization as the main attenuation
mechanism in material. At higher energies, the in-
teraction of the incident particle tends to occur pri-
marily with individual nucleons in the target
t
- HYDROGEN
-- Z 2 2 (most cases)
(RATIO [ Z A ] ~ = 0.25)
----
Z = 3 LITHIUM
L \
(RATIO [ZA]* = 0.187)
1 o3
L (earth radii)
Figure 1-25. Total energy required to penetrate
the magnetosphere (Stassinopoulos and Ray-
mond, 1988).
nucleus, and can lead to the ejection of several en-
ergetic protons and neutrons. This spallation pro-
cess leaves the product nucleus highly excited,
with de-excitation occurring through the evapora-
tion of additional nucleons and the emission of
gamma rays.
E-
ATTENUATED ORBIT
(90 degrees at 500 krn)
F ----
ATTENUATED ORBIT
(60 degrees at 500 krn)
I- -- UNATTENUATED INTERPLANETARY 4
ENERGY, E (MeV)
Figure 1-26. Magnetospheric attenuation of solar
flare proton spectra for a 500-km high-inclination
LEO (Stassinopoulos and Raymond, 1988).
1 02
ENERGY, E (MeVlnucleon)
Figure 1-27. Magnetospheric attenuation of cosmic-ray silicon atoms for a 600-km LEO (Stassinopoulos and
Raymond, 1988).
ENERGY, E (MeVlnucleon)
Figure 1-28. Emerging solar flare proton spectra behind various spherical aluminum shield thicknesses; circular 500-
km, 60-degree-inclination orbit at solar minimum, BL time = 1998.0 (Stassinopoulos and Raymond, 1988).
.......
SHIELD'
THICKNESS
....... .......... . . . . (g,cm2) ""
LINEAR ENERGY TRANSFER (LET) (MeVIcm)
Figure 1-29. Integral LET spectra for the attenuated inter-
planetary spectrum during one anomalously large event;
solar flare protons behind spherical aluminum shields, nor-
mal incidence (Stassinopoulos and Raymond, 1988).
For 400-MeV protons incident on aluminum,
the average total nuclear emission is 4.8 nucleons,
including 2.8 spallation nucleons with an average
energy of 120 MeV (Haffner, 1967). The process
can generate a rich variety of residual nuclei, espe-
cially in heavier elements, as a result of the multi-
plicity of statistically possible reaction paths (i.e.,
the specific number of protons and neutrons emit-
ted). These product nuclei frequently are radioiso-
topes decaying by beta-ray emission with a variety
of lifetimes.
Several important features are illustrated by the
curves of Figure 1-30. First, there is substantial at-
tenuation by the earth's magnetic field of all par-
ticles in the energy range of 10 to 10,000 MeV/
nucleon. Second, there is an insignificant effect of
thickness of material shielding in the energy range
. . . . . . . . . . . . . .
1 0' 1 o2 10"
ENERGY, E (MeVlnucleow)
Figure 1-30. Galactic cosmic-ray solar spectra emerging behind spherical aluminum shields of various thicknesses; so-
lar minimum (Stassinopoulos and Raymond, 1988).
from about 90 to 3,000 MeVInucleon. Note that
there is no substantial decrease in flux, even for
aluminum shielding of 10 g/cm2 (approximately
1.5 inches at 3,000 MeVlnucleon). Third, there is
an unavoidable shield side effect of a significant
increase in the low-energy (0.8 to 50 MeV1
nucleon), high-LET fluxes for shield thicknesses
greater than 0.1 g/cm2 of aluminum. With increas-
ing shield thicknesses, the population of high-en-
ergy ions decreases slightly, but with a resultant
increase in the low-energy ions. Since the LET in-
creases with decreasing energy in this range
(heavy solid curve), the presence of the shield ac-
tually increases the severity of the environment to
the internal electronics.
1.4.2.5 Ionizing Radiation Dose
In general, the ionizing radiation dose from the
transiting radiation environment is insignificant
compared to the trapped radiation environment.
Particle fluxes from energetic solar flares are
heavily attenuated by the geomagnetic field, which
prevents their penetration to low orbital altitudes
and inclinations. For a 500-km, 30-degree-inclina-
tion orbit, some penetration occurs. In contrast, a
polar orbit experiences a substantial degree of ex-
posure at any altitude.
In GEO, the geomagnetic shielding is relatively
ineffective. Even so, the average yearly dose from
ordinary events behind a 2-g/cm2 spherical aluminum
shield is quite small, approximately 18 rads(Si). In
comparison, the event-integrated dose from an
anomalously large flare at parking longitude of 70W
would be approximately 600 rads(Si)/event for the
same shield and target, as shown in Figure 1-3 1. Tri-
pling the shield thickness to 6 g/cm2 would result in
300 rads(Si)levent.
1.4.2.6 Single-Event Susceptibility of Electronics
Single-event upset (SEU) effects in electronics
from the transiting space radiation environment
may be the result of either the energetic solar flare
protons or cosmic rays. The nature of trapped
proton-induced single-event effects (SEE) has
been discussed previously [Subsection 1.4.1.81. In
general, the SEU rate due to transiting protons is
small compared to that due to cosmic rays, except
for the occurrence of an anomalously large event.
To cover the occurrence of such an event during
the spacecraft mission, both the expected duration
and fluence of the anomalously large event must
be considered in the electronics design.
Generally, cosmic-ray induced SEE dominate
proton-induced SEE, both at altitudes below 1,000
km and above 4,000 km for 60-degree circular or-
bits. For lower inclination orbits, the cosmic rays
are shielded by the earth's magnetic field, causing
the cosmic-ray upset level to decrease compared to
the proton upset rate. Conversely, for higher incli-
nation orbits, the relative upset rate of the cosmic
ANOMALOUSLY LARGE EVENT
(PARKING LONGITUDE, 40W)
AVERAGE (I-YEAR) ORDINARY
EVENT
ORBITAL INCLINATIONS (degrees)
Figure 1-31. Unattenuated solar flare proton dose
emerging behind spherical aluminum shielding
(Stassinopoulos and Raymond, 1988).
rays increases. The variations in the spacecraft or-
bit, space radiation environment, and device sus-
ceptibility should be considered in estimating
specific cosmic-raylproton upset levels in support
of spacecraft electronics design. The specification
of the internal electronics environment should in-
clude the time-dependent proton flux and energy
spectrum, the cosmic-ray LET spectrum, and the
cosmic-ray spectrum by particle species and en-
ergy spectrum. The actual cosmic-ray spectrum
can be a valuable supplement to the LET spectrum
in those cases where more detail is necessary to
support experimental characterization in ground-
based laboratory facilities.
1.4.3 Conclusions
The richly diverse space radiation environment
has been described in terms of its nature and varia-
tions with respect to the susceptibility of spacecraft
electronics. The constraints of space radiation ef-
fects on spacecraft electronics design can be sig-
nificant, but with careful component selection,
shielding, and design, systems can be realized that
are both of high performance and long endurance.
This section specifically addresses the earth's
radiation environment, but magnetic fields and
trapped radiation belts are not unique to the Earth.
Jupiter, to be explored by the Galileo spacecraft,
has a trapped radiation environment that is much
more severe than that of Earth. Even in transit to
the outer planets and beyond, galactic cosmic rays
must be considered for their effects on electronics.
1.5 Systems Development Background
The purpose of this section is to provide a de-
scription of the various aspects of nuclear harden-
ing and survivability (NH&S) system develop-
ment. The various phases of system acquisition
will be discussed, emphasizing how system surviv-
ability is factored into the various acquisition
phases.
1.5.1 Hostile Threats
In developing a system for space, tactical, or
strategic use many hostile environments must be
sion. These environments encompass both the
nuclear and the nonnuclear. Nuclear environments
include the direct, or primary, radiation as well as
the secondary environments and phenomena. The
primary environments from a nuclear detonation
are the neutrons, gamma rays, x rays, and fission
products. Depending upon the scenario, these in
turn produce, electromagnetic pulse (EMP) effects,
high-altitude EMP (HEMP), magnetohydrody-
namic EMP (MMDEMP), source-region EMP
(SREMP), system-generated EMP (SGEMP), in-
ternal EMP (IEMP), electron-caused EMP
(ECEMP), and dispersed EMP (DEMP), blast,
shock, thermomechanical shock (TMS), and ther-
mal radiation. If the mission of the system is in
space, the natural radiations - electron, protons,
and cosmic rays -must be considered. For some
space systems, both the nuclear and the natural
space environments must be considered.
For some missions, other natural phenomena,
such as lightning, can be quite hostile. Other non-
nuclear environments that may need to be con-
sidered include laser, high-powered microwave
(HPM), electromagnetic interference (EMI), and
several forms of kinetic energy (KE).
1.5.1.1 Nuclear Space Radiation
The primary radiations from a nuclear detona-
tion manifest themselves in widely differing man-
ners, depending upon where the detonation occurs.
When the detonation is exoatmospheric, the radia-
tion output essentially consists of x rays, g a m a
rays, neutrons, and fission products. In this in-
stance, the x rays are the dominant output. Fortu-
nately, x rays can be effectively shielded. For a
space system with nuclear detonation survivability
requirements, the x rays are often shielded to a
level approximately equal to the level of the
gamma rays, which cannot be effectively shielded.
Neutrons are also effectively impossible to shield.
The primary radiations from an exoatmospheric
nuclear detonation, in order of concern for system
hardening in space, are x rays, gamma rays, neu-
trons, and enhanced trapped electrons (for satel-
mitigated so that the system can perform its mis- lites in some orbits). The secondary environments
created by the primary radiations include HEMP, anced approach to hardening. For example, for a
MHDEMP, SGEMP, and ECEMP. Another phe- ground-based system, there is little value in pro-
nomenon also associated with x rays is thermome- viding extreme hardening measures for nuclear ra-
chanical shock (TMS).
diation while ignoring hardening against EMP. A
complete discussion of hardness-verification and
If the nuclear detonation is endoatmospheric, the
hardness-assurance activities for these other threats
environments are somewhat changed. The x rays
are converted to airblast, but the gamma rays and
is beyond the scope of this chapter, but other re-
neutrons remain because of their extreme penetrat-
ports and guidelines are available for this purpose.
The important point is that the program manager
ing capability. The dominant environment now
and contractor ensure that comprehensive systems
depends upon parameters such as altitude and sys-
engineering analyses are performed to identify all
tem mission (manned or unmanned).
survivability requirements and assign a proper
1.5.1.2 Natural Space Radiation
level of hardening effort to each one.
For systems in space, the natural space environ-
ment, must be considered in addition to the radia-
tion from the nuclear detonation. The natural
radiations of interest are electrons, protons, and
cosmic rays. The electrons and protons exist in a
relatively wide range of energies.
1.5.3 Emphasis on Electronics
Although many design aspects must be consid-
ered when deriving the design specification for a
hardened system, it quickly becomes evident that
electronic devices must receive a great deal of at-
tention. Historically, it has been recognized that
-
The electron dose is dependent upon the orbit of
semiconductor devices are usually the items most
the spacecraft because the highest concentrations
sensitive to the hostile radiation environments. Ac-
of the electrons exist in the Van Allen belt, and the
cordingly, they receive attention because they are
exposure will depend upon the length of the time
necessary for generating the functions that enable
the spacecraft spends in these belts.
the system to operate and perform its mission.
Cosmic rays are usually very high-energy-ions
that cause single-event phenomena (SEP). Shield-
ing is not considered to be effective in eliminating
SEP, so other methods such as device-hardening
against SEP andor error detection and correction
(EDAC) must be utilized. For some space-based
systems, SEP is the foremost hardening consider-
ation.
1.5.2 Balanced Hardening Concept
It must be emphasized that a complete surviv-
ability program will generally include system
threats other than nuclear or space radiation. De-
pending upon the system and other circumstances,
these additional threat environments may be more
stressing to the system than radiation. The amount
of attention given to a particular threat environ-
ment should be both proportional to its relative
importance and in consonance with hardening ac-
tivities for other environments, necessitating a bal-
1.5.4 Life Cycle Survivability and Hardness
Survivability requirements do not cease with the
completion of system design and verification. Sur-
vivability must be actively considered throughout
the design's entire life cycle to ensure that the op-
erational system retains the desired attributes.
Department of Defense (DoD) programs are
considered to have life cycles composed of distinct
phases. This concept is useful for any system,
since it clearly defines milestones that must be met
to ensure proper review of design feasibility.
Just as programs have defined phases encom-
passing particular tasks, the survivability life cycle
may be viewed as a continuum of activities. Since
these activities are a function of the overall pro-
gram phase in which they occur, it is instructive to
view them in the context of the phases of a major
program and in relationship with each other. Fig-
ure 1-32 shows these relationships.
KEY HARDENING
ACQUISITION
ACTIVITIES
LIFE-CYCLE
PHASES I
LIFE-CYCLE
SURVIVABILITY
PLANNING
C
LIFE-CYCLE
DEV
SURVIVABILITY
IMPLEMENTATION
MAINTENANCE
SURVEILLANCE
OPERATIONAL
Figure 1-32. Life-cycle survivability program (Coppage, 1993).
The concept development (CD) phase requires
development of the environment specifications,
hardness criteria, and initial hardening concepts
that match the overall system concept.
The demonstration validation (DIV) phase
extends, refines, and verifies these items as the
system concept is validated. It may include a hard-
ness assessment of the preliminary design con-
cepts. Historically, when the demonstration of the
system concept was the focus of the DIV phase
with no attention to survivability, the hardening
program suffered or was more costly. Survivabil-
ity must be considered early in the CD phase.
Figure 1-32 shows hardness assurance (HA) oc-
curring in the production phase. In accordance
with its definition, HA activities assure production
of a system as robust as that verified during EMD
in the initial hardened design.
Figure 1-32 is greatly simplified; many other
functions necessary for hardening and HA occur
during the design phases shown in this figure. To
help clarify this point, Figure 1-33 adds hardening
and HA considerations along with system-develop-
ment milestones. Notice that these considerations
are present from the program initiations and con-
tinue throughout the life of the system.
The engineering and manufacturing develop- As stated at the outset of this section, it is also
ment (EMD) phase usually requires a large in- necessary to remember that the hardening and HA
crease in hardening efforts. Detailed design of a program must be a part of the overall system de-
hardened system and verification of the design velopment management structure. To emphasize
hardness are major activities. They are often ac- this point, Figure 1-34 provides another perspec-
companied by hardening trade-off studies and nu- tive of the activities needed to develop a hardened
merous hardness tests. system.
I PROGRAM INITIATION I
DESIGN REQUIREMENTS
I
1;q
DESIGN AND QUALIFICATION I
ASSURANCE I
HARDENING AND HA CONSIDERATIONS ADDED
Figure 1-33. Hardening and hardness assurance (HA) incorporated into normal system development tasks
(Coppage, 1993).
Finally, during deployment and operational use However, such a generalization requires that sys-
of the system, hardness maintenance (HM) and tems be separated into categories based on their
hardness surveillance (HS) are used to further use (e.g., tactical, space-communications, space-
guarantee the continuing hardness of the system strategic, interceptor missile, intercontinental bal-
once fielded. The HA procedures and controls listic missile [ICBM], strategic-manned, etc.).
must apply to the procurement of any repair parts Table 1-1 provides a summary of generic NH&S
used in HM. requirements for representative systems.
1.6 System Nuclear Hardening and
Survivability Requirements
This section provides a method for categorizing
various types of systems as a function of mission
and survivability requirements. This background
information should provide a relative indication of
the radiation-hardened microelectronic require-
ments for typical DoD systems.
1.7 Nuclear Threat Environments and
Nuclear Specification Development
This section explores in detail the development
of nuclear threat environments and nuclear specifi-
cation criteria. These two activities are part of the
conceptual and validation phases of the system ac-
quisition life cycle (Figure 1-34). Information that
should be provided by the government in the state-
Several general comments can be made con-
ment of work (SOW) of a procurement action is
cerning the NH&S requirements of systems and
outlined, and guidance is provided on the informa-
how these requirements translate to radiation-hard-
tion required to define the various radiation threats,
ened microelectronic component specifications.
(e.g., ionizing radiation dose, dose-rate upset).
I
DSARC REVIEW
SECDEF
OF INTEGRATED
TLE PLAN
I
I
PRODUCTION ACCEPTANCE TBE
A PROGRAM I Nl I ATl ON DECISION
FULL-SCALE DEVELOPMENT INITIATION
(RATIFICATION DECISION )
PRODUCTION DECISION
REFERENCES: DoD DIR5000.1
DoD DIR5000.3
Figure 1-34. System acquisition life cycle for a hardened system (Coppage, 1993)
The SOW for a survivable electronic system
must contain the nuclear hardness specifications
along with the system performance specification
and the other operating environments. The de-
scription of the nuclear weapon environments in
which the system must be designed to operate is of
overriding importance.
Usually, the electronic system developer need
not be concerned with calculating the nuclear envi-
ronment because the nuclear environment external
to the system of interest is specified by the procur-
ing agency. The translation of this information to
the internal system environment is usually the re-
sponsibility of the system developer.
1.7.1 Minimum Adequate Hardness
Specification
An adequate nuclear hardness specification for
an electronic system should include at least the fol-
lowing:
1. A physically meaningful (unambiguous)
definition of the external, or "free-
field," nuclear environments to be sur-
vived.
2. A definition of the ionizing radiation at-
tenuations and shielding, andlor buildup
factors that apply to the system, or a
definition of the modified nuclear envi-
ronment to be encountered by the sys-
1-33
Table 1-1. NH&S requirements for representative systems.
tem. Both may be needed if the system
being developed does not include its
own facility or its shielding as part of
the contracted effort.
3. A description of the system perfor-
mance requirements in each operational
mode at various times relative to the
exposure to the nuclear environment.
4. A statement concerning hardness verifi-
cation, qualification, and contract com-
pliance demonstration methods,
including system survival probabilities
and associated confidence levels.
5. Statements regarding HA requirements
in production and HM during and after
deployment. These may be preliminary
System Category
Space-Strategic
Space
Communications
Tactical and
Strategic-
Manned
statements calling for program plans to
be developed by some later scheduled
date.
6. A program plan establishing critical
milestones and data requirements.
Items 1 and 2 are nuclear hardness criteria and
the environment description; item 3 provides the
system performance requirements. The remaining
items assist in defining the hardness program.
1.7.2 Nuclear Environment Criteria
Development
During the conceptual phases of a survivable sys-
tem, the nuclear hardness criteria are developed and
updated by operations analysis procedures. The mis-
sion requirements, enemy capabilities, and system
Example
Systems
FEWS,
GPS,
MILSTAR
Brilliant
Eyes
USN UHF
and other
communica-
tion satellites
B 1 and B2 air-
craft
Ml Al tanks
SINCGARS
Threat
NWE and natural
space (ionizing rad-
iation dose, dose-
rate upset, single-
event phenomena,
neutron irradiation)
Natural space (ion-
izing radiation dose
and SEU)
NWE (ionizing rad-
iation dose, neutron
irradiation, dose-
rate upset)
Microelectronics
Requirements
State-of-the-art 1M RAM,
(32-bit microprocessors,
1OOkgate arrays, MIMIC
communications link,
discrete power transis-
tors, etc.)
Commercial near state-
of-the-art radiation-toler-
ant devices with some
specifically designed and
fabricated rad-hard rnicro-
electronics (64k SRAMs,
16-bit microprocessors,
20k gate arrays, GaAs com-
munication links)
Commercial microelectron-
ics suitable for reduced
threats (e.g., no transient
requirements); radiation-
tolerant devices satisfactory
for other threats (ULSIC
SRAMs and DRAMS, 32-bit
microprocessors, ULSIC
gate arrays)
Exemplary Radiation
Hardening Requirements
Ionizing radiation dose:
2 1 Mrad(Si)
Transient upset: > 1 x 10"
rads(Si)/sec (critical mem-
o ~ )
SEU: I 1 x 10-lo upset1
bit-day
Neutron irradiation:
2 1 x 1012 n/cm2
Ionizing radiation dose
2 100 krads(Si)
SEU: I 1 x 1C@ upsets/
bit-day
Ionizing radiation dose:
< 10 krads(Si)
Neutron irradiation:
- 10'2n/cm2
Transient upset: I 1 x lo9
rads(Si)/sec
SEU: (may be specified for
high-altitude aircraft)
concept are combined as shown in Figure 1-35. Sce-
narios that "tell the story" of the system deployment
are developed, estimating the results as a function of
tactics and the enemy threat.
MISSION
REQUIREMENTS
ENEMY
CAPABILITIES
I
I
THREATS
SYSTEM
CONCEPT
PERFORMANCE
COST AND OTHER
TRADE-OFFS
NUCLEAR
Figure 1-35. Simplified procedure for developing a nuclear
hardness specification.
As part of the operations analysis, performance
versus life cycle cost trade-off and feasibility stud-
ies are conducted. Nuclear hardness and surviv-
ability are among the trade-off parameters. The
goal of this procedure is the development of:
(1) the nuclear hardness specification requirements
for the systems, and (2) the supporting documenta-
tion and rationales for these criteria.
The establishment of nuclear hardness criteria
and nuclear specifications is a government respon-
sibility. Major system contractors frequently will
be involved in these early concept-formulation ac-
tivities, but their involvement is of a supporting
nature. In some cases, the system contractor will
develop the first proposed nuclear hardness speci-
fication, particularly if that contractor has a major
role in developing the system concept. In any
case, it is desirable for the contractor to influence
the preparation of the nuclear hardness specifica-
tion. It is to the contractor's advantage to assure
that the nuclear hardness impacts of his design ap-
proach are recognized by the procuring agency and
that appropriate consideration of those impacts are
reflected in the nuclear hardness specification. A
clear, firm specification forms the basis for fair
competitive bidding, bid evaluation, and objective
contractor performance compliance demonstration.
It is desirable that the operations analysis, which
is the basis for a nuclear hardness specification, be
documented and referenced, if not summarized, in
the specification. This permits an intelligent
evaluation of such issues as new system applica-
tion, survivability shortcomings, or updated threats
scenarios that arise during and after the system-
design phase of the development program.
The interaction between the nuclear environ-
ment specification, system-performance criteria,
and hardness-verification requirements deserves
emphasis. The hardening costs can be affected
strongly by specific demands on system perfor-
mance during and after nuclear exposure. There is
an important trade-off between the environment
specification and verification requirements; aug-
mented environment specifications (e.g., a contrac-
tually imposed safety margin) can be used to
simplify the verification requirements (e.g., quali-
fication tests), particularly the statistical aspects.
This procedure is effective for systems with the
lower-level criteria (tactical systems) in which unit
cost is a strong factor and the hardness reguire-
ments are well within the state of the art technol-
ogy.
1.7.3 Nuclear Envimnmepat Ds c ~pt i on
The nuclear weapon environment descriptions
are the maxima, and/or envelopes, of the external
nuclear environments the system must survive.
These are "free-field" and "external" in the sense
that they need not take account of system mitiga-
tion of this external environment. It is always un-
derstood that all environment levels lower than
those specified must also be survived. The most
important requirement for the environment de-
scription is that it be clear and complete, leaving
nothing substantial to interpretation. From the sys-
tem developer's viewpoint, it should define the en-
vironment in terms that can be correlated with system level (Level Z), operational consideration
known effects in the system so that it can serve as may require that only one of the major subsystems
a basis for contract compliance demonstration. survive x-ray flux (for example, Subsystem 1).
During the nuclear hardness specification refine-
The subsystem specification is then divided as nec-
ment in the contract definition phase, system and
essary at Level 2. Furthermore, at Level 3, the
subsystem functional allocations are tentatively
system analysis may show that Sub-subsystem 1
made by means of a system requirement analysis
does require an x-ray specification but that Sub-
(SRA). Additionally, during the full-scale develop-
subsystem 1A does not. The specification at this
ment phase, before preliminary design, the prime
level is again modified. This process continues
contractor or program manager may provide for a
until the lowest-level subsystem is reached.
number of subcontractors to develop specific sub-
systems. This subcontracting arrangement also
may be made before prime contract award. It is
the prime contractor's responsibility, with program
office approval, to interpret and redefine the
nuclear hardness specifications as applicable for
the subcontractors, so that the integrated system
will meet its requirements at all system levels.
The resulting nuclear hardness specifications to
be addressed by the subcontractors are still exter-
nal specifications as far as the subsystem is con-
cerned, but generally are not the free-field
environment. For example, when considering
TREE, the prime contractor must account for vari-
ous shielding interfaces that either attenuate or en-
hance nuclear radiation effects.
The hierarchy of the formulation of the sub- In addition to describing the radiation specification
system specification is shown generically in Figure that the subsystem in question must survive, the
1-36. The overall system specification (Level 1) prime contractor has the responsibility for defining
may include a requirement for withstanding, for the nuclear-induced environments at all subsystem
example, x-ray flux. However, at the major sub- interfaces, including such things as voltage transients
PERFORMANCE NUCLEAR AVAILABILITY TACTICAL
REQUIREMENTS ENVIRONMENT REQUIREMENTS EMPLOYMENT
SUBSYSTEM 1 SUBSYSTEM 2
SPECIFICATION SPECIFICATION
SUBSYSTEM
LEVEL 1:
WEAPON
, rANAi
LEVEL 3: SUBSYSTEM 1 SUB-SUBSYSTEM 2
SUB-SUBSYSTEM SPECIFICATION
-
OVERALL SYSTEM
SPECIFICATION
(1) PERFORMANCE SPECIFICATION
(2) AVAlLABlLITYIRELlABlLlTY
(3) NUCLEAR SPECIFICATION
RADIATION (GAMMA AND NEUTRON)
SHOCK PROFILE
CURRENT AND VOLTAGE PULSE (EMP)
SYSTEM
Figure 1-36. Weapon system specification tree.
at hard-wire (cable) interfaces, temperature transients
at subsystem enclosures, and structural-impulse reac-
tions that might be transmitted to various subsystems.
These are difficult to define at this early stage and are
frequently determined by the conservative application
of data from other systems and good engineering
judgment.
The parameters that must be specified to ad-
equately describe the most important nuclear envi-
ronments are discussed in Subsection 1.7.4. If
these guidelines are followed, a clear definition of
the nuclear hardness specification will result.
1.7.4 Nuclear Environment SprEcatEow at
the System
The nuclear hardness specification for an elec-
tronic system must include physically clear (unam-
biguous), quantified descriptions of all environ-
ments that can affect the system performance and
which the system is required to survive. The dif-
ference between the environment and the effects of
the environment must be made clear. For example,
neutron fluence and energy spectrum would be an
environment, while the damage-equivalent fluence
or an ionization dose value would be an effects-
type description. Eoth could be given, for reasons
to be discussed. The following subsections present
the minimum information required in a nuclear
specification of the design environment at the sys-
tem.
1.7.4.1 Neutrons
A neutron hardness specification for a system
should at least consist of the following:
1. A fluence value of neutrons above some
threshold energy (n/crn2).
2. A spectrum curve, table, or source de-
scription. Usually, the spectrum for all
neutrons above the threshold of 10 keV
is adequate for engineering purposes.
3. A time history of neutron flux and spec-
trum (if significant) for the scenario
(n/[cm2-sec]).
4. An effects equivalent fluence, consistent
with the physical fluence and spectrum
for the damage effects of interest or irn-
portance. The most common unit is the
1 MeV(Si) displacement equivalent flu-
ence. Alternately, the means whereby
the effects equivalent fluence is calcu-
lated from the spectrum can be speci-
fied.
The ionization effects of neutrons should also be
included in the description of the delayed ionizing
radiation environment.
1.7.42 G a m a Rays
It is adequate, and common practice, to spccify
prompt free-field g a m a rays as an electron equi-
librium absorbed dose, or dose rate, in silicon.
Dose rate should be specified either with a pulse
shape rads(Si)/s versus time) or a peak rate and a
pulse length for triangular or Gaussian representa-
tion.
B.7.4,3 X Rags
Because weapon-produced x rays interact quite
strongly with system enclosures, it is essential that
the description of a system's external free-field
environment be given in terms of the incident ra-
diation rather than energy disposition in electron-
ics. Therefore, a specification of the x-ray energy
fluence (cal/cm2), the time history of the x-ray flux
(cal/[cm2-sec] versus time), and x-ray energy spec-
tra are required. The energy spectrum is often de-
fined in terms of the photon output of one or more
blackbody spectra with a characteristic ternpera-
ture or energy. The system developer must deter-
mine the x-ray environment at specific points of
interest in dose terms (i.e., rads [Si] or caVg[Au])
considering the system shielding and recognizing
the nonequilibrium nature of the dose near inter-
faces.
Subcontractors or subsystem developers may
receive x-ray specifications in dose units wherein
the prime contractor has performed the needed
shielding calculation. It is vital that a clear distinc-
tion be made between electron equilibrium dose
and actual dose near an interface.
1.7.4.4 Ionizing Radiation Dose
Ionizing radiation dose is stated independently
in the nuclear hardness specification. Normally
units of rads(Si) are used for the descriptions since
no confusion arises in the interpretation of ab-
sorbed dose. Ionizing radiation dose is the sum of
all ionizing radiation doses in the system due to
neutrons, x rays, prompt gamma rays, delayed or
secondary gamma rays, fission-product gamma
rays, and trapped electrons (in some exoatom-
spheric situations). Electron ionizing dose is of
importance in satellites and space systems. In ad-
dition, due to total ionizing validation time depen-
dent effects (discussed in detail in Chapter 2), the
dose rate of the ionizing radiation source (e.g.,
NWE, etc.) would be identified.
1.7.4.5 Nuclear EMP
An EMP specification should contain exterior
free-field descriptions of the electric (E) and mag-
netic (H) fields in volts per meter and ampere-turns
per meter, respectively, as functions of time or fre-
quency, with polarization stated (or given as worst
case for the system developer to design against).
The E(t) and H(t) characteristics are different for
high-altitude bursts and ground-level or atmo-
spheric bursts, and a variety of threats may need to
be considered in the specification.
For subsystem specifications, coupled currents,
Thevenin or Norton equivalent sources, enclosure-
shielding attenuation factors, and line-filter attenu-
ations may be used to define the designer's tasks.
1.7.4.6 SGEMP
SGEMP may be specified in terms of external
impinging photon flux and energy spectrum, in
which case the system developer must account for
the effect in the enclosure design (materials,
shapes, shielding, etc.), and in selection of insensi-
tive components or configurations. Alternatively,
the procurement agency may specify the internal
fields, if they are calculable. The reader is cau-
tioned that SGEMP effects and coupling coeffi-
cients are sometimes poorly defined.
1.8 List of References
Adams, J.H., R. Silberg, and C.H. Tszo, 1981.
Cosmic Ray Effects on Microelectronics; Part I,
The Near-Earth Particle Environment, MR-4506,
Naval Research Laboratory, August 198 1.
Barraclough, D.R., R.M. Harwood, B.R. Leaton,
and S.R.C. Malin, 1975. "A Model of the
Geomagnetic Field at Epoch 1975," Geophys. J. R.
Astron. Soc., Vol. 43, p. 645, 1975.
Bendel, W.L., and E.L. Petersen, 1983. "Proton
Upsets in Orbit," IEEE Trans. Nucl. Sci., Vol.
NS-30, No. 6, pp. 4481-4485, December 1983.
Bethe, H., 1920. "Theory of the Passage of Fast
Corpuscular Rays Through Matter," Ann. Physik,
Ser. 5, pp. 5-325, 1920.
Coppage, EN., 1993. System Development
Hardness Assurance Guideline Document:
Nuclear and Space Radiation Aspects,
MIL-HDBK-817, 1993.
Goswarni, J.H., R.E. McGuire, R.C. Reddy, D. Lai,
and R. Jha, 1987. Solar Flare Protons and Alpha
Particles During the Last Three Solar Cycles, Los
Alamos Preprint LA-UR-87-1176, submitted to J.
Geophys. Res., 1987.
Haffner, J.W., 1967. Radiation and Shielding in
Space, Academic Press, New York, NY, 1967.
Hopkins, M., Aerospace Corporation, private
communication, 1993.
IAGA, 1986. "International Geomagnetic
Reference Field, Revision 1985," EOS, Vol. 67,
pp. 523-524, IAGA Division I, Working Group 1,
June 1974.
Jordan, T.M., 1982. "Adjoint Monte Carlo
Electron Shielding Calculati~ns,'~ANS Trans., Vol.
41, June 1982.
Kaul, D.C., et al., 1990. Capabilities of Nuclear
Weapons (U); Chapter 8 - Nuclear Radiation
Phenomena (U), DNA-EM- 1 -CH-8, Defense
Nuclear Agency, March 1990 (SRD).
King, J.H., 1974. "Solar Proton Fluences for
1977- 1983 Space Missions," J. Spacecraft and
Rockets, VoI. 1 1, pp. 401-408, 1974.
Lanzerotti, L.J., C.S. Roberts, and W.L. Brown,
1967. "Temporal Variations in the Electron Flux at
Synchronous Altitude," J. Geophys. Res., Vol. 72,
No. 23, pp. 5893-5902, December 1967.
Lin, R.P., and K.A. Anderson, 1966. "Periodic
Modulation of the Energetic Electron Fluxes in the
Distant Radiation Zone, J. Geophys. Res., Vol. 7 1,
No. 7, pp. 1827-1835, April 1966.
Littmark, U., and J.F. Zeiger, 1980. Handbook of
Range Distributions for Energetic Ions in All
Elements, Pergamon Press, New York, NY, 1980.
Mcllwain, C.E., 196 1. "Coordinates for Mapping
the Distribution of Magnetically Trapped Particles,
"J. Geophys. Res., Vol. 66, No. 1 1, pp. 368 1-369 1,
December 196 1.
NASA, n.d. AE8 Trapped Electron Model,
National Space Science Data Center, NASA-
Goddard Space Flight Center (unpublished report),
MD.
O'Brien, B.J., 1963. "A Large Diurnal Variation of
the Geomagnetically Trapped Radiation," J.
Geophys. Res., Vol. 68, No. 4, pp. 989-995,
February 1963.
Petersen, E.L., 198 1. "Soft Errors Due to Protons
in the Radiation Belt," IEEE Trans. Nucl. Sci., Vol.
NS-28, No. 6, pp. 3981-3986, December 1981.
Raymond, J.P., and E.L. Petersen, 1987.
"Comparison of Neutron, Proton, and Gamma Ray
Effects in Semiconductor Devices," IEEE Trans.
Nucl. Sci., Vol. NS-34, No. 6, pp. 1622-1628,
December 1987.
Rogers, C., Jaycor, private communication, 1993.
Sawyer, D.M., and J.I. Vette, 1976. AP8 Trapped
Proton Environment for Solar Maximum and Solar
Minimum, NSSDC 76-06, National Space Science
Data Center, Greenbelt, MD, December 1976.
Seltzer, S., 1980. SHIELDOSE: A Computer Code
for Space Shielding Radiation Dose Calculations,
NBS Technical Note 11 16, U.S. Dept. of
Commerce, National Bureau of Standards, May
1980.
Spjeldvik, W.N., and P.L. Rothwell, 1983. The
Earth's Radiation Belts, AFGL-TR-83-0240, Air
Force Geophysics Laboratory, Hanscom AFB,
MA, September 1983.
Stassinopoulos, E.G., 1990. "Radiation Envi-
ronment of Space," Microelectronics for the
Natural Radiation Environments of Space, IEEE
Nuclear and Space Radiation Effects Conference
Short Course, Reno, NV, July 1990.
Stassinopoulos, E.G., 1975. SOLPRO: A Computer
Code to Calculate Probabilistic Energetic Solar
Proton Fluences, NSSDC 75- 1 1, National Space
Science Data Center, Greenbelt, MD, April 1975.
Stassinopoulos, E.G., and J.P. Raymond, 1988.
"The Space Radiation Environment for
Electronics, Proc. IEEE, Vol. 76, No. 11,
November 1988.
Stassinopoulos, E.G., and J.H. King, 1974.
"Empirical Solar Proton Model for Orbiting
Spacecraft Applications," IEEE Trans. Aerosp.
Electron. Syst., Vol. AES- 10, No. 4, July 1974.
Stassinopoulos, and P. Verzariu, 197 1. "General
Formula of Decay Lifetimes of Starfish Electrons,"
J. Geophys. Res., Vol. 76, No. 7, pp. 1841-1 844,
March 197 1.
Teague, M.J., and E.G. Stassinopoulos, 1972. A
Model of the Stafish Flux in the Inner Radiation
Zone, NASAIGFSC X-60 1-72-487, NASA- God-
dard Space Flight Center, MD, December 1972.
Wenaas, E., Jaycor, private communication, 1993.
CHAPTER 2
IONIZING RADIATION EFFECTS*
2.1. Radiation Sources and Interaction With
Matter
When an integrated circuit (IC) is exposed to
a significant radiation environment, the electrical
properties of its active components usually will be
altered, resulting in circuit performance degrada-
tion or failure. In addition, for pulsed radiation,
radiation-generated photocurrents can lead to tran-
sient circuit upset. The primary goal of the radia-
tion effects community is to harden electronic
systems subjected to radiation to prevent degrada-
tion, failure, or upset. Hardening may be accom-
plished by several different ways: on the device
level processing, design, layout and material
choice (e.g., silicon-on-insulator vice bulk technol-
ogy are employed). On the system or subsystem
level power strobing, circumvention, EDAC and
design methods are used. In addition shielding can
be used at the device, subsystem and/or system
level.
In this chapter, the basic mechanisms of ionizing
radiation on material (Si, Si02, etc.) and devices
[metal-oxide-semiconductor (MOS) and bipolar
technologies] are discussed. In addition, a brief
discussion of ionizing radiation effects in gallium
arsenide (GaAs), the simultaneous effects of ioniz-
ing radiation and temperature, and reliability prob-
lems in MOS field-effect-transistors (MOSFETs)
will be presented.
The term "total dose," widely used to describe
ionizing radiation effects, is not quite correct be-
cause of time-dependent effects. In this handbook,
and particularly in this chapter, "ionizing radiation
dose" is used instead of "total dose."
2.1.1 Sources and npes of Radiation
Electronic systems may be exposed to a variety
of radiation sources and environments. Those envi-
ronments of the most interest are space radiation
and radiation from nuclear reactors and explosions.
These environments have been the primary drivers
of the work in radiation effects and hardening. The
specific types of radiation and the irradiation sce-
narios associated with each of these environments
differ widely. Therefore, when attempting to
harden a particular electronics system, it is impor-
tant to keep the specific application and potential
radiation environment in mind. For example, sys-
tems to be used in space may have to withstand
large radiation doses that are accumulated slowly
over long periods of time, whereas electronics to
be used in the vicinity of nuclear explosions must
be hardened against radiation delivered in very
short pulses at very high dose rates.
Other radiation sources to which electronic sys-
tems may be exposed include materials with radio-
active contaminants, such as uranium and thorium.
When incorporated into packaged ICs, these mate-
rials can produce isolated radiation events (e.g.,
alpha particle emissions), which can result in occa-
sional transient upsets similar to single-event
upsets (SEU) encountered in space radiation envi-
ronments. Other radiation sources are the various
irradiation tools used in the processing of modern
small-scale, high-density ICs, which include ion-
implantation machines, plasma-ion etching, and x-
ray and electron-beam lithography tools. It is
important that the radiation damage caused by
these tools be minimized during processing. Fi-
nally, the various radiation simulators used both to
study the fundamental nature of the interactions of
radiation with matter and to simulate various
*Much of the material presented in this chapter is derived from McLean and Oldham (1987).
aspects of threat radiation environments of interest
are discussed. These include such facilities as 6 0 ~ o
cells, x-ray irradiators, particle accelerators [e.g.,
linear accelerators (LINAC)], flash x-ray (FXR)
machines, and nuclear reactors.
The various radiation sources and/or environ-
ments give rise to a variety of irradiating species,
with a wide variation in energy spectrum and time
history. For example, nuclear explosions give rise
primarily to x-rays, gamma-rays and neutrons,
whereas the space environment consists essentially
of a low-level, constant flux of energetic charged
particles - electrons, protons, and heavy ions. The
various types of irradiating species can be grouped
into three major categories: (1) photons (x rays and
gamma rays); (2) charged particles (electrons, pro-
tons, alpha particles, and heavy ions); and (3) neu-
trons. Cosmic rays encountered in the space
environment consist of a variety of charged par-
ticles, generally with very high energies (>I00
MeV). The neutron energy ranges of interest are
the so-called high-energy range (tens of MeV
down to 10 keV) and the thermal range (-kT).
The interaction of radiation with solid-material
targets depends on a number of factors, namely, on
the mass, charge state, and kinetic energy of the
incident impinging particle, and on the atomic
mass, atomic number (charge), and density of the
target material. The specific types of interactions
that occur between the primary particles and target
atoms are listed below:
Photons (+ high-energy secondary
electrons)
- Photoelectric effect
- Compton scattering
- Pair production
Charged particles
- Rutherford scattering
- Nuclear interactions (heavy particles)
- Coloumb interaction
Neutrons
- Elastic scattering
- Inelastic scattering
- Transmutation reactions.
These are addressed in the subsections that follow.
Many references are available that discuss these
interactions in great detail. A list of these is pro-
vided in the bibliography in chapter 7.
2.1.1.1 Photon Interactions
Photons interact with target atoms through the
photoelectric effect, Compton scattering, and pair
production, each interaction producing energetic
free electrons. The energy range in which photo-
electric collisions dominate depends on the atomic
number (Z) of the material. Away from the electron
shell absorption edges (where the interaction prob-
ability increases abruptly with increasing photon
energy), the probability of a photoelectric interac-
tion decreases with increasing photon energy and
increases with Z. If the incident photon is energetic
enough to emit an electron from the K-shell, then
most (-80 percent) of the collisions are with M-
shell electrons. In the photoelectric process, the in-
cident photon energy is completely absorbed by the
emitted electron (photoelectron). If a K-shell elec-
tron is involved, then an L-shell electron will drop
into the remaining empty state. Either a character-
istic x ray or a low-energy Auger electron is emit-
ted from the L-shell, depending on the value of Z.
In contrast to the photoelectric effect, Compton
scattering does not involve complete absorption of
the incident photon. Figure 2-1 shows the region
where Compton scattering is dominant. The inci-
dent photon gives up a portion of its energy to
scatter an atomic electron, thereby creating an en-
ergetic Compton electron, and the lower-energy,
scattered photon continues to travel in the target
material.
The third type of photon interaction, pair pro-
duction, has a threshold energy of 1.02 MeV.
Above this energy, a photon striking a high-2. tar-
get may be completely absorbed and cause a
positron/electron pair to form. [A positron has the
same rest mass and charge as an electron, except
that the charge is positive.]
Figure 2- 1 illustrates the relative importance of
the three photon interactions as a function of Z and
photon energy. The solid lines correspond to equal-
interaction cross sections for the neighboring ef-
Figure 2-1. Relative importance of three photon interactions as a function of atomic number and
photon energy (Evans, 1955).
fects. For silicon (Z = 14), the photoelectric effect Target material ionization is a major conse-
dominates at energies below 50 keV and pair pro- quence of charged-particle interactions, especially
duction dominates at energies above 20 MeV. Over for electrons and the lighter charged ions (protons,
-
the broad intervening energy range, Compton scat-
tering dominates. In all three cases, however, the
essential result of the photon interactions is the
production of energetic secondary electrons (and
positrons at very high photon energy), which then
undergo subsequent charged-particle interactions.
In other words, the primary energy transfer from
the incident photons to the target occurs via the
secondary electron interactions.
2.1.1.2 Charged-Particle Interactions
Charged particles incident on a target interact
primarily by Rutherford scattering and Coulomb
interaction. Rutherford scattering can cause both
excitation and liberation (ionization) of atomic
electrons. If their energies are high enough to over-
come the Coulomb repulsion of the target nucleus,
protons and other nuclear particles can undergo
nuclear reactions with the target nucleus. For ex-
ample, a proton can be absorbed by the nucleus to
form a compound nucleus that can then, depending
on the proton's energy, emit one or more neutrons,
an alpha particle, or other nuclear particles.
alphas). In semiconductors and insulators, ioniza-
tion results in excess nonequilibrium densities
of electrons and holes. The actual ionization
processes associated with the passage of a single
energetic charged particle through a solid is ex-
ceedingly complex, generating a number of high-
energy secondary electrons with various energies
and momenta, which subsequently produce further
ionization, and so on in a cascade process. How-
ever, most of the final ionization events and most
of the energy transfer occur through a single type
of intermediate process involving the collective
motions of many valence electrons in simple oscil-
latory motion against the background of positive
ionic cores. (Because of the much larger masses,
the ion cores can be considered stationary relative
to the oscillating electrons.) These plasma vibra-
tions, or plasmons as they are called in quantum
mechanics jargon, are induced by the long-range
nature of the Coulomb interaction, which extends
over regions containing many atoms. The plasmon
energies, corresponding to the resonance frequency
of the oscillations, are typically in the range from
10 to 20 eV for most solids, depending upon the
number density of valence electrons. Following its
creation, a plasmon decays rapidly (<1 psec) via
excitation of a single electrodhole pair across the
bandgap. The excess kinetic energy carried by the
individual electrons and holes may result in one or
two additional ionization events (depending upon
the bandgap width), with the remainder of the en-
ergy being quickly dissipated as thermal lattice
motion.
2.1.1.3 Neutron Interactions
Neutrons incident on a target undergo the fol-
lowing nuclear interactions: elastic scattering, in-
elastic scattering, and transmutation. In an elastic
collision, the neutron gives up a portion of its en-
ergy to an atom of the target material, and can dis-
lodge the atom from its lattice position. This
process will occur as long as the imparted energy
is greater than that required for displacement (-25
eV for most materials). The displaced atom is re-
ferred to as the primary recoil atom (or primary
knock-on atom, PKA); it subsequently will lose
energy to ionization and can also displace other
lattice atoms.
Inelastic neutron scattering involves capture of
the incident neutron by the nucleus of the target
atom with subsequent emission of the neutron at a
lower energy. Kinetic energy is lost in this process
and the target nucleus is left in an excited state.
The excited nucleus returns to its original state by
the emission of a gamma ray. The kinetic energy of
the emitted neutron is reduced, compared to the
incident neutron, by the energy of the gamma ray.
Inelastic neutron scattering can also cause dis-
placement of the target atom to occur.
Transmutation involves capture of the incident
neutron by the target nucleus and subsequent emis-
sion of another particle, such as a proton or an al-
pha particle. The remaining atom is thereby
transmuted, i.e., converted from one element into
another. The nuclear particle and the recoiling re-
sidual nucleus emitted from the transmutation re-
action can also produce displaced atoms.
2.1.2 Ionization and Atomic Displacemenb
In spite of the seemingly complex interactions
of radiation with matter, with the various depen-
dencies of the interactions on the properties of the
incident particle and target materials, in the end
two essential effects on solid-state electronics are
produced: (1) ionization (generation of electron1
hole pairs), and (2) displacement damage (dislodg-
ing atoms from their normal lattice sites). As pre-
viously stated, particles passing through electronic
materials generally deposit a portion of their en-
ergy into ionization and the remainder into atomic
displacements. However, for most practical pur-
poses, the situation is even simpler than this state-
ment indicates. Specifically, for charged-particle
irradiation, the primary modes of electronic device
degradation occur as a result of ionization, even
though a certain amount of atomic displacement
can occur in general, especially for the heavier
ions. Similarly, for high-energy neutron irradiation,
the primary mechanisms for device degradation
are attributed to atomic displacement damage,
even though considerable ionization can be associ-
ated with neutron interactions. This simplified situ-
ation is summarized in Figure 2-2.
It must be recognized, however, that this is
a simplification that applies to the commonly
observed failure or degradation modes of most
electronic devices. To be sure, there are situations
or pa.rticular devices in which neutron-induced
ionization can be significant, or in which displace-
PRIMARY EFFECTS
---- SECONDARY EFFECTS
Figure 2-2. Schematic indicating primary radiation
effects and secondary effects in electronic materials
(McLean and Qldham, 1987).
ment damage associated with energetic charged-
particle irradiation can be significant. For the top-
ics to be covered here, ionization damage can
essentially be associated with charged particles and
displacement damage with neutrons.
2.1.3 Radiation Exposure Terminology
The commonly used terminology and units
of radiation exposure and damage are presented
here to enable quantification of the subsequent top-
ics of this chapter. Table 2- 1 highlights some of the
important terminology and units of radiation
exposure.
Flux is simply the particle current density inci-
dent on a particular area element expressed in
number of particles/cm2-sec. Particle fluence is
just the time integral of the flux over some period
of time (e.g., over the time of a radiation pulse)
expressed in units of particles/cm2. The energy
spectrum is simply the distribution of a particle
fluence (or flux) over energy, e.g., particles/cm2-
MeV.
Table 2-1. Important terminology and units of
radiation exposure.
Neutron exposure of a sample is commonly
given in terms of the neutron fluence (n/cm2).
However, the amount of displacement damage
from neutrons in a given material varies signifi-
cantly with neutron energy. Therefore, in order to
allow meaningful comparisons between experi-
ments using different neutron energy spectra, neu-
tron fluences are often expressed in terms of
"normalized to" an equivalent 1-MeV neutron
fluence, which is that fluence of 1-MeV neutrons
that would produce the same electronic effect as
the neutron spectrum used in a particular study.
. ... . . . . . . . . . . . . . .............................................................. . . . . . . . . . .
. .
. . . . . . . . . . .
::. .:.':..'.: '.: " '
. . . . . . . . . . . . . . . . .
: : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .._....... ....................................
.,;: p.:bg,,g i66$.:wi ~ i & ..:;.:;:
. . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flux
Fluence
Energy spectrum
Neutron fluence
1-MeV equivalent neutron
fluence
Ionizing radiation
Stopping power (linear
energy transfer, p-l dE/dx)
Absorbed ionizing
radiation dose (D, or y)
Ionizing dose rate ( j , or A)
For charged-particle exposure, the amount of
energy that goes into ionization is given by the
stopping power, or the linear energy transfer (LET)
function p-I dE/dx, commonly expressed in units
of ~ e ~ - c m ~ / ~ . The stopping power has been tabu-
lated for a number of target materials as a function
of incident particle energy and atomic number. An
example of the stopping power for electrons
(Berger and Seltzer, 1966) and protons (Janni,
1966) incident on silicon is shown in Figure 2-3.
The absorbed ionizing dose (D, or y) is the integral
over energy of the product of the particle energy
spectrum and the stopping power. The commonly
used unit of absorbed ionizing dose is the rad (ra-
diation absorbed dose), where 1 rad is equal to the
absorbed energy of 100 ergslg of material. As a
result, the energy loss per unit mass differs from
one material to another, the material in which the
dose is deposited must be specified when this unit
is used, e.g., rads(Si) or rads(Si02). The Systkme
International (or metric) SI unit of absorbed dose is
the gray (Gy), which is equal to an absorbed en-
ergy of 1 Jlkg, or 100 rads. However, the gray is
rarely used by the radiation effects community. Fi-
nally, the ionizing dose rate ( j ) is usually ex-
pressed in rads(M)lsec, where M represents the
target material of interest (e.g., Si, SO2).
. . . . . . . . . . . ..........
..... . . . . . . . . . . . ...... . . . . . . . . . . . . . ..........................
...-...
. . . . . . . . . . . . .
_ :
.....
. . . . . . . . . . . . . .... ........................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
;:;;:i;,;~~,;;,yu~i&~~fM;~g mj:;L ,:;;:::
......
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . .
particles/cm2-sec
particles/cm2
particles/cm2-~eV
n/cm2
nlcm2
~ e ~ - c m ~ / ~
r a4Wa
rad(M)lsec
2.1.4 Overview of Primary Radiation Effects
on Electronic Materials
Note: As discussed above, the dominant effects result-
al rad = 100 ergs/g = 0.01 Jkg [SI units: 1 gray (Gy) =
ing from the interaction of radiation with elec-
100 rads = 1 Jkg]. M represents the target material of tronic materials are ionization (primarily
interest, typically silicon (Si) or silicon dioxide (SiO2) associated with charged-particle interactions) and
for electronic components.
atomic displacement damage (primarily associated
with high-energy neutron exposure). The major
consequences of these effects are discussed here;
the effects of atomic displacement damage are dis-
cussed in Chapter 4.
Figre 2-3. Stopping power versus particle energy for
electrons and protons incident on silicon (Berge: and
Seltzer, 1964; Janni. 1965).
[Figure 2-4(c)] until they either undergo recombi-
nation elsewhere in the material, or are trapped at
a localized trap (defect) site, or are collected at an
electrode.
If an electric field is present, there will be net
charge separation and, therefore, an electric cux-
rent. These radiation-induced photocurrents can
be a major problem in semiconductors, resulting in
circuit upset of burnout. Associated with the pas-
sage of even a single energetic heavy particle (al-
phas, heavy ions), sufficient ionization may occur
such that the current or collected charge may cause
BAND
(a) Ionization Event
Figure 2-4 is a schematic of the ionization pro- 1 Q - F
cess i~ semiconductors and insulators. In Figure
2-4(a). an elsctroaz in the valence band is excited:
across the bandgap into a condvction band state,
either as a direct result of interaction with an ener-
getic charged particle or as the result of the decay
of a plasmon excitation (the collective oscillation
of a large number of valence-band electrons). Very
rapidly (on the order of a picosecond), the excited
electron in the conduction band and the hole left
behind in the valence band lose their excess kinetic
cinity of the conduction- and valence-band edges,
1
respectively. Then, except for some fraction (small
energy [Figure 2-4(b)] through lattice scattering
and are "therrnalized" in energy, falling to the vi-
in semiconductors, possibly large in insulators) of Figure 2-4,. Schematic of ionization process in semi-
the electronlhole pairs, which undergo what is
conductors and insulators; ionization leads to transient
called initial recombination, the electron and hole
photocurrents and buildup of trapped charge (space-
charge effects). [Effective measure of damage is charge
will be free to diffuse and drift (if electric fields are
yield per dose (electronlhole pairs per rad).l
present) away from their point of generation
(McLean and Oldham, 1987)
(b) Thermalization (c) Charge Separation
and Drift
an upset. In this case, upsets are referred to as
single-event upsets, as opposed to bulk-ionization-
induced photocurrents upsets. The currents associ-
ated with a single particle may also induce current
latchup in some cases. Latchup is a specific type of
device failure mode which is caused by the activa-
tion of a parasitic silicon-controlled-rectifier (SCR)
structure contained in CMOS and some bipolar cir-
cuits. This SCR structure can only be deactivated
by the removal of the excitation voltage. Prolonged
activation of the SCR structure can result in circuit
failure. Latchup can be caused by either dose-rate
induced photocurrents or the charge deposited by a
single ion strike. These problems are increasing in
importance as the sizes of devices are scaled down,
thus requiring less charge to cause upset.
In insulators (e.g., Si02), radiation-induced pho-
tocurrents are generally not a problem because of
the much lower carrier mobilities and lower num-
bers of electron/hole pairs created. However, insu-
lators generally contain relatively large densities of
charge-trapping centers, where the radiation-in-
duced charges can be trapped for long periods of
time. The trapped charges can then generate inter-
nal space-charge electric fields, which in turn can
lead to voltage offsets or shifts in device operating
characteristics. If sufficient space-charge fields are
generated, device failure may result. This is a ma-
jor radiation effects problem in MOS devices. In
addition, internal space-charge fields due to
trapped charge in field oxides and passivation insu-
lators can turn on parasitic current leakage paths in
adjoining semiconductor materials. As device di-
mensions are scaled down, this also will become
more of a problem in both MOS and bipolar tech-
nology circuits.
The amount of damage due to ionization is di-
rectly related to the charge yield per unit dose, i.e.,
number of electronlhole pairs generated per rad.
This is true both for the magnitudes of the induced
photocurrents (for pulsed irradiation) and for the
amount of trapped-charge buildup for ionizing ra-
diation dose effects. Table 2-2 lists the average
ionization energy (Ep) required to generate a single
electron/hole pair for several important electronic
materials, as well as the initial charge pair density
per rad (go) deposited in the material. The latter
quantity is obtained simply from the product of the
material density and the deposited energy per rad
(1 rad = 100 ergslg = 6.24 x 1013 eV1g) divided by
Ep. AS noted earlier, in wide-bandgap insulators
such as Si02, significant initial (or immediate) re-
combination of the electronlhole pairs can occur
before they can separate. The actual charge yield
for charged particles is a function of the electric
field and the line density of electron/hole pairs
(number created per track length of the incident
particle); the value of go listed in Table 2-2 corre-
sponds to the yield in the high field limit. For pho-
tons, the charge yield depends primarily on photon
energy and the electric field.
Table 2-2. Electronlhole pair generation energies
and pair densities generated by 1 rad (Srour,
1982 and 1983).
Pair Density
Pair Generation Generated
Energy, Ep per rad, go
Material (ev) (pairs/cm3)
Silicon 3.6 4.0 x l0l3
Silicon dioxide 17 8.1 x loi3
Gallium arsenide -4.8 -7 x loi3
Germanium 2.8 1.2 x l0l4
The primary effects of ionizing radiation on
electronic materials discussed here are summarized
below:
Ionizing radiation dose (D): charge
buildup effects (rads[Si] or rads[Si02])
- Voltage offsets
- Induced parasitic leakage currents
- Speed (mobility) degradation
Transient radiation effects: induced
photocurrents or particle ionization
- Transient upset ( j ) due to bulk
semiconductor ionization (rads[Si]/sec)
- Single-event upset due to energetic
heavy ions (errorshit-day)
- Latchup
- Burnout 2.1.5 Characteristics of Specific Radiation
- Gate rupture.
The overall content of this list resembles the
general form of a radiation specification that may
be imposed on an electronic system required to
operate in a given radiation environment. That is,
the system may be required to survive or to be
hardened against failure for given values of ioniz-
ing radiation dose (rads[Si]) or rads(Si02]), dose
rate (rads[Si]/sec), and SEU, usually expressed in
terms of some maximum error rate per bit for the
threat environment (e.g., errorslbit-day). Typical
target values for radiation-hardened circuit are ion-
izing radiation dose to 1 Mrad, dose rate to lo9
radslsec, and SEU to errorhit-day.
Environments
When defining a radiation survivability specifi-
cation for an electronic system, the potential radia-
tion environment must be considered. Some
pertinent information concerning the three radia-
tion environments of most practical interest (space,
nuclear explosions, and nuclear reactors) is given
in Table 2-3, (1) summarizing the quantitive char-
acteristics of the various environments, (2) indicat-
ing the primary failure mechanism of ICs exposed
to these environments, and (3) noting some of the
radiation effects data. The various failure mecha-
nisms are discussed in some detail in the remainder
of this chapter.
Table 2-3. Characteristic radiation output and pertinent features of natural space, nuclear explosions, and nuclear reactors.
Nabrat Space Nuclerr Explosion Nuclear We ~ ~ f s r
I
Low ionizing dose rate
(<<I radfsec)
Ionizing radiation dose
(2 lo5 rads)
Environment
High-dose-rate gamma flux
( j 2 lo8 radstsec)
Ionizing radiation dose
(21 o4 rads)
Steady-state neutron flux
Low to moderate ionizing
dose rate (gamma rays)
High-energy electrons and Delayed high-energy neutron flux
protons trapped in the earth's (fluence >loi3 n/cm3)
magnetosphere
Galactic Cosmic Rays (GCR) -
(electrons, protons, heavy ions)
Solar Enhanced Particles (same as GCRs)
Primary Failure Mechanisms
Ionizing-radiation-dose-induced Ionizing-radiation-dose-induced Displacement damage
charge buildup charge buildup
Single-event effects Transient-photocurrent-induced upset Ionizing-radiation-dose-induced
and burnout charge buildup
Neutron displacement damage
Test Simulators
Low-dose-rate ionization sources: Ionization sources: flash x ray, Nuclear reactor
6 0 ~ o , x-ray tester LINAC electron beam (for dose rate); Moderate-dose-rate ionization
%o, x-ray tester (for ionizing data) sources: 6 0 ~ o , x-ray tester
High-energy particle sources: Neutron source: nuclear reactor
proton and heavy-ion beams
2.2 Basic Mechanisms of Ionizing Radiation
Effects on Electronic Materials and Devices
In Section 2.1 it was noted that one of the major
effects associated with radiation-induced ioniza-
tion in electronic materials is trapped-charge
buildup, which induces internal space-charge fields
that interfere with the normal (designed) opera-
tions and control of devices. This problem is pri-
marily associated with the insulating films used in
modern IC technologies. The primary focus of
work in this area over the past 20 years has ad-
dressed MOS technologies because of the impor-
tance of the charge-trapping effects in the thin
silicon dioxide films employed in these technolo-
gies, both as gate oxides over the active semicon-
ductor channel region and as isolation or
passivation oxides. However, as device dimensions
shrink, the ionizing radiation dose problem is of
increasing concern for the bipolar technologies as
well, in connection with trapped-charge-induced
leakage paths near isolation or passivation oxides.
For the purposes of discussing the pertinent phys-
ics, the ionizing radiation dose charging problem
in Si02 gate oxides of MOS structures will be ad-
dressed. The basic mechanisms underlying charge
trapping are the same in both gate and field passi-
vation oxides, differing only in the circuit manifes-
tations. In addition, a brief discussion of induced
leakage current problems for both MOS and bipo-
lar structures will be presented. In general, charg-
ing of the oxide regions can occur both within the
bulk of the oxide films as well as at the interfaces
between the oxides and the semiconductor regions.
Figure 2-5 shows a simple schematic of a
MOSFET, in this case an n-channel device using a
p-type Si substrate. When a bias potential is ap-
plied to the gate contact, an electric field exists
across the gate-oxide region and into the silicon
(Si) surface region immediately below the gate re-
gion. If the gate bias is sufficiently large and posi-
tive (for n-channel operation), the majority carriers
(holes in p-type Si) will be repelled from or de-
pleted in this surface region, and minority carriers
(electrons) will be attracted to this region, forming
what is called an inversion layer.
Additionally, if a potential difference is subse-
quently applied between the source and drain con-
tacts [n+-doped regions in Figure 2-51, the
inversion layer provides a low-resistance current
channel for electrons to flow from the source to
the drain. The device is then said to be turned on
[Figure 2-5(a)], and the control-gate bias potential
at which the channel just begins to conduct appre-
ciable current is called the turn-on voltage, or
threshold, of the device.
GATE FIELD
OXIDE OXIDE
CONDUCTING INVERSION
CHANNEL (POSITIVE VG)
p-TYPE SILICON
b
SUBSTRATE
(a) Normal Operation
GATE FIELD
OXIDE OXIDE
POSITIVE OXIDE CHANNEL TURNED
TRAPPED CHARGE ON (VG = 0)
p-TYPE SILICON
b
SUBSTRATE
(b) Post-Irradiation
Figure 2-5. Schematic of n-channel MOSFET illus-
trating the basic effect of ionizing-radiation-dose-in-
duced charging of the gate oxide (McLean and Oldharn,
1987).
The ionizing radiation dose problem that occurs initial processes of pair creation and prompt re-
in this structure is then due to the radiation-in- combination, which determine the actual charge
duced charging (normally positive) in the thin (hole) yield in the Si 02 film and consequently the
gate-oxide region, which generates additional initial (maximum) voltage shift, constitute the first
space-charge fields at the Si surface. These addi- major factor of the MOSFET response.
tional induced fields result in voltage offsets, or
shifts, in the turn-on voltages of the devices, which
lead to circuit degradation and failure. For ex-
ample, for sufficiently large amounts of trapped
positive charge for the device shown schematically
in Figure 2-5, the device may be turned on even
for zero applied gate bias [Figure 2-5(b)]. In this
case, the device is said to have failed by "going
into depletion mode."
2.2.1 Radiation Response of MOS Structures
Figure 2-6 shows a schematic energy band dia-
gram for an MOS structure where positive bias is
applied to the gate, so that free electrons in the ox-
ide layer will be swept toward the gate and holes
will be attracted to the Si substrate. (In an energy
band diagram - essentially equivalent to a poten-
tial energy diagram - electrons tend to fall down-
hill, whereas holes will float upward.) Also
indicated in Figure 2-6 are the four basic processes
contributing to the radiation response of such a
system.
The part of an MOS structure that is most sensi-
tive to ionizing radiation is the oxide insulating
layer (Si02), which in present-day devices is gen-
erally less than 100 nm thick. When the radiation
passes through the oxide, the deposited energy cre-
ates electronlhole pairs. In Si02, the radiation-gen-
erated electrons are much more mobile than the
holes, and they are swept out of the oxide (col-
lected at the gate electrode) in times on the order
of picoseconds (Hughes, 1973). However, in that
first picosecond or two, some fraction of the elec-
trons and holes will recombine. This fraction de-
pends greatly on the applied field and on the
energy and type of the incident particle. The holes
that escape initial recombination are relatively im-
mobile and remain behind near their points of gen-
eration, causing negative voltage shifts in the
electrical characteristics of MOS devices, e.g., in
threshold voltage (VT) for MOSFETs, or in
flatband voltage (Vfb) for MOS capacitors. These
Over a period of time extending typically, at
room temperature, from lop7 second to the order
of seconds (but much longer at lower tempera-
tures), the holes undergo a rather anomalous sto-
chastic hopping transport through the oxide in
response to any electric fields present [shown mov-
ing toward the Si substrate for the gate bias situa-
tion depicted in Figure 2-61. This hole transport
process, which is very dispersive in time, is the
second major factor of the MOS response. The
holes that reach the silicon substrate through the
transport process and undergo recombination give
rise to a short-term recovery in initial voltage shift.
The transport process itself is sensitive to a number
RADIATION-INDUCED
INTERFACE TRAPS
WITHIN Si BANDGAP
(4)
I
' (3)
DEEP HOLE
TRAPPING
NEAR Si/Si02
INTERFACE
/ HOPPING TRANSPORT
OF HOLES THROUGH
(1 LOCALIZED STATES IN
ELECTRONJHOLE Si02 BULK
PAIRS GENERATED
BY IONIZING
RADIATION
Figure 2-6. Schematic energy band diagram of Si02
MOS structure for positive gate bias (Srour, 1983).
of variables, including applied voltage, tempera-
ture, oxide thickness, and (to a lesser extent) oxide
process parameters (e.g., anneal temperature, etc.).
When the holes reach the Si 02 interface (for
positive applied gate bias), some fraction is cap-
tured in long-term trapping sites and causes a rem-
nant negative voltage shift that is not sensitive to
the silicon surface potential and persists in time for
hours to years. This long-lived radiation-induced
voltage shift component is the most commonly
observed form of radiation damage in MOS de-
vices. The long-term trapping of holes near the
Si02/Si interface, as well as their subsequent an-
nealing in time, constitutes the third major factor
of MOS response indicated in Figures 2-6, 2-7,
and 2-9. Hole trapping and annealing are very sen-
sitive to the processing of the oxide and to other
variables, such as field and temperature.
The fourth and final component of MOS re-
sponse is that of a radiation-induced buildup of in-
terface traps right at the Si02/Si interface. These
are localized states with energy levels within the Si
bandgap. Their occupancy is determined by the lo-
cation of the Fermi level; consequently, the radia-
tion-induced interface traps give rise to a voltage
shift component that depends on the silicon surface
potential. In general, there can be both prompt in-
terface traps, present immediately after a radiation
pulse, as well as a delayed time-dependent buildup
of states, which can continue for thousands to tens
of thousands of seconds at room temperature. Both
the magnitude and nature (relative ratio of prompt
and delayed components) of the interface traps are
also highly dependent upon oxide processing, as
well as upon other variables such as temperature
and applied field (both magnitude and polarity).
A major electrical consequence of the radiation-
induced charging of the Si02 film (including trans-
porting holes, trapped holes, and interface traps) is
a shift in pertinent voltage operating points for
devices, such as in the threshold voltage VT for a
MOSFET. The threshold voltage is written:
where V; is the threshold voltage before irradia-
tion and AVT(t) is the time dependent voltage shift
following radiation exposure. The pre-irradiation
threshold voltage is defined and its explicit expres-
sion is given in any textbook discussing MOS tran-
sistors (e.g., Sze, 1981). It depends upon
temperature, gate-semiconductor work function
difference, substrate doping density, oxide layer
thickness, and substrate bias. There are also contri-
butions to VT from any fixed oxide charges and in-
terface traps existing before irradiation.
Based on Figure 2-6 and its discussion, the ra-
diation-induced threshold voltage shift can be sub-
divided into three components:
where V,,(t) is the (short-term) contribution from
the radiation-generated mobile holes transporting
in the oxide bulk, VoJt) is due to the deep trapped
holes near the interface, and Vit(t) is the contribu-
tion from the charged interface traps. Note that all
three components are generally time dependent.
They are given explicitly as:
where q is the electronic charge, Cox is the oxide
capacitance per unit area (Cox = ~~,/t,,), and to, is
the oxide thickness (the subscript ox is the dielec-
tric constant of the oxide). In Equation 2.3a, nh(x,t)
is the space- and time-dependent density of free
(mobile) holes, and distance x in the oxide is
measured relative to the gate/Si02 interface. In
Equation 2.3b, No,(t) is the radiation-induced areal
density of deep trapped holes near the Si02/Si in-
terface; it is time dependent both because of its
time-dependent buildup as the transporting holes
reach the interface and because of its long-term
annealing, which can extend out to years. In Equa-
tion 2.3c, the sign of the radiation-induced inter-
face trapped charge Qit(t) is unspecified because it
can contribute either a net negative or net positive
charge, depending on the position of the Fermi
level at the Si surface at inversion. [Usually, Qit is
negative for n-channel and positive for p-channel
devices.] In general, a voltage offset is simply pro-
portional to the first moment of the induced oxide
charge relative to the gate interface. For the mobile
hole distribution, Equation 2.3a retains this defini-
tion explicitly, since the transporting holes can be
distributed through the bulk of the oxide. For both
the long-term trapped holes and interface traps,
(x) = to,, with the resulting simplifications exhib-
ited in Equations 2.3b and 2 . 3 ~ . Positive charge in-
duces a negative shift in VT, and negative cha.rge
induces a positive shift.
To further aid in understanding some of the ba-
sic processes involved in the time-dependent re-
sponse of MOS structures, Figure 2-7 illustrates
the positions and magnitudes of the radiation-in-
duced charges in the Si 02 before and after an in-
finitesimally short radiation pulse. The processes
depicted here include charge generation and initial
recombination, hole transport, and long-term hole
trapping. The annealing of the trapped holes and
interface trap buildup are not included. Figure 2-8
illustrates the corresponding capacitance-voltage
(C-V) curves schematically for an MOS capacitor
for the times indicated in Figure 2-7.
The pre-irradiation condition (t = O-) is depicted
in Figure 2-7(a) (no oxide charges), and the corre-
sponding C-V curve is indicated by the t = 0-
curve of Figure 2-8. At t = O [Figure 2-7(b)], the
radiation pulse occurs, generating electronlhole
pairs across the oxide bulk. In a time on the order
of picoseconds (t = 03), some of the electrodhole
pairs will recombine [Figure 2-'7(c)], and the rela-
tively highly mobile electrons will be transported
toward the gate and be collected [Figure 2-7(d)].
The corresponding @-V curve is shifted far to the
left in the negative voltage direction, as indicated
by the curve labeled t = O+ in Figure 2-8. The mag-
nitude of the flatband voltage shift Vfb(O+) is maxi-
mum at this time. Then the holes begin their
relatively slow hopping transport toward the Si02/
Si interface, where some fraction of them is cap-
tured in the long-term trapping sites. Figure 2-7(e)
shows the intermediate situation at t = t l , where
some holes are still being transported, some have
reached the substrate and undergone recombina-
tion, and some have been trapped near the inter-
face. Since a less positive charge remains in the
oxide, the C-V curve has partially annealed back at
t = tl in the positive voltage direction from its ini-
tial shifted position at t = Q3. The final charge con-
figuration (t = t2) after completion of the hole
transport is depicted in Figure 2-7(f), where only
the long-term, trapped holes remain near the SiQ2/
Si interface, giving rise to a long-term fiatband
voltage shift in the C-V characteristic, as indicated
by the t = t2 curve of Figure 2-8.
SEMlCONDUCTOR (Si)
(a) t = 0- (Pre-Irradiation) (b) t = 0 (Ioninzing Burst)
+ - + - - + - + + + +
-
- + + + OXIDE (s~o*) + + +
- I + -
+ i
I I
SEMICONDUCTOR (Si)
- - .
IL -
-
-
-
L-.----- -
-
(c) t = O+ (After Initial (d) t = O+ (ARer Electron
Recombination) Transport)
I I
- -
w/fl/wa -- METAL y / / mf l &
- - ----
+ + + + OXIDE (Si02)
+ +- + + , - . t + - + -t-_.
SEMICONDUCTOR (Si)
4
- -
I-
- -
(e) t = tll (Hole Transport (f) t = t2 (Afier Hole
in Proqress) Transport)
Figure 2-7. Illustration of recombination, transport,
and trapping of carriers in SiQ2 films (Srour, 1983).
ACCUMULATION
INVERSION
--
VOLTAGE
Figure 2-8. Capacitance-voltage curves corresponding
to the conditions illustrated in Figure 2-7 (Srour, 1983).
The overall actual situation is even more com-
plicated than Figures 2-7 and 2-8 indicate. In gen-
eral, long-term annealing of the deeply trapped
holes is possible via tunneling of electrons from
the Si substrate, which gives rise to a much slower
recovery of the C-V curve near the pre-irradiation
curve. In addition, radiation-induced interface traps
can be present both immediately after irradiation (t
= 0+) as well as continuing to build up over long
time periods. The interface traps not only contrib-
ute to the shift of device characteristics, but they
also cause a distortion (stretchout) of the C-V or
current-voltage (I-V) curves because the charge
state of the traps is dependent upon the surface
potential (and hence upon the applied bias).
A schematic, time-dependent recovery curve in
Figure 2-9 depicts the radiation-induced shift in
threshold voltage as a function of log-time from
to lo8 seconds for a radiation-hardened n-
channel MOSFET under positive gate bias at room
temperature after exposure to a 1-psec ionizing ra-
diation pulse. This figure is schematic in that real
data are not shown (over the enormous time re-
gime depicted), yet it is basically representative of
the composite response of an actual hardened n-
channel device. The figure relates the major fea-
tures of the response of each of the primary
processes indicated in Figure 2-6. The initial shift
AVT at second, which is also the maximum
shift, is determined mainly by the electronlhole
pair creation in the Si02 bulk and by the initial re-
combination processes. (However, some contribu-
tions from annealing by hole transport are possible
during the pulse and from prompt interface-state
production, which is low for a hardened oxide.)
The short-term annealing shown occurring out to
about second is due to the hole transport pro-
cess. The shift occurring at 1w2 second is prima-
rily due to the deep hole trapping near the Si02/Si
interface, which then anneals out slowly in time
(approximately linearly with log-time), essentially
out to infinite time [to lo8 seconds in Figure 2-91,
The solid curve in Figure 2-9 corresponds to
transport, trapping, and annealing of holes alone.
In this situation, annealing includes: (1) short-term
recovery, which occurs when the untrapped holes
reach the substrate and recombine; and (2) long-
term annealing (e.g., tunneling, etc.). In addition to
long-term annealing of trapped holes, however, a
buildup of radiation-induced interface traps may
LONG-TERM RECOVERY
WITH INTERFACE
TRAP BUILDUP
ANNEALING/
LONG-TERM RECOVERY
(2)
I It-- HOLE TRANSPORT/
I I
SHORT-TERM RECOVERY
INITIAL HOLE YIELD/
INITIAL AVT
10-6 l om4 10-2 100 102 104 106 108
TIME AFTER RADIATION PULSE (seconds)
Figure 2-9. Schematic time-dependent threshold-volt-
age recovery of an n-channel MOSFET following
pulsed irradiation, relating the major response features
to underlying physical processes (McLean and Oldham,
1987).
occur, typically in the time regime between
and lo3 seconds, as indicated by the dashed curve
in Figure 2-9. [For an n-channel device, the inter-
face-state contribution to AVT is positive, corre-
sponding to a net negative interface trapped charge
at the threshold voltage.] If the interface trap con-
tribution is relatively large, the threshold voltage
may actually recover past its preirradiation value
(i.e., AVT positive), a phenomenon known as su-
per-recovery, or rebound. This effect can also lead
to circuit failure if it is sufficiently large. If a rela-
tively large component of prompt interface traps is
produced, then there would simply be an additional
upward translation of the solid and/or dashed
curves for all time. Again, because of the trapped
positive charge annealing, super-recovery could
occur.
In any case, because of the several different
physical processes involved, each having different
characteristic times, it is apparent that the overall
time history of the recovery can be fairly complex,
with important implications for testing procedures,
hardness assurance, and resource prediction.
In the simplest terms, it must be possible to extract
from test data - usually over a very limited time
regime and for a limited range of experimental
conditions - the expected performance of an IC
in a particular threat environment, which may in-
volve a completely different time regime (perhaps
orders of magnitude shorter or longer). Before ad-
dressing these issues, the basic physical processes
responsible for the complex time history depicted
in Figure 2-9 are discussed in further detail.
2.2.2 Physical Pr~~~cesses Underlying the
Radiation Rmpom of M0S Devices
In this subsection, more detail is given for each
of the physical mechanisms described in Subsec-
tion 2.2.1 and displayed schematically in Figure
2-9. The intent is to provide the user with some fa-
miliarity with these processes by summarizing
their major characteristics and indicating the main
concepts used in their model descriptions.
2.2-2.1 Initial Mole Yield
The initial hole yield in the oxide determines the
initial (maximum) voltage shifts of MOS devices
and sets the scale for the amount of damage (at any
time) due to ionizing radiation. The two major fac-
tors that determine the initial hole density are the
electronlhole pair creation energy and the field-de-
pendent fraction of holes that escape the initial re-
combination processes. The initial value of the
threshold voltage shift is then simply related to the
initial hole density via the dose and geometric (ox-
ide thickness) factors.
The electron/hole pair creation energy Ep for
Si 02 was determined by Ausman and McLean
(1975) to be 18 + 3 eV, based on the analysis of
experimental data of Curtis, Srour, and Chiu
(1974). This result has since been independently
confirmed by others (Boesch and McGarrity, 1976;
Sanders and Gregory, 1975), including a later,
more accurate set of measurements and analysis by
Benedetto and Boesch (1986), which establishes
En to be 17 k 1 eV.
r
From the value of Ep, the initial electron/hole
pair density per unit dose is easily determined to
be 8.1 x 1012 ~ r n - ~ / r a d ( S i ~ ~ ) . This initial density,
however, is quickly reduced by the initial recombi-
nation processes (occurring in picoseconds) before
the electrons are swept out of the oxide and col-
lected. The fraction of holes escaping initial re-
combination fy(Eo,), which determines the final
hole yield, is determined mainly by two factors:
(1) the magnitude of the oxide electric field E,,,
which acts to separate the charge pairs; and (2) the
initial line density of electrodhole pairs created by
the incident radiation particle. The pair line den-
sity, which is determined by the linear energy
transfer (LET) and therefore a function of the inci-
dent particle type and energy, is inversely propor-
tional to the average separation distance between
electron/hole pairs. Obviously, the closer the aver-
age spacing of the pairs, the more recombination
that occurs for a given field and the less the final
yield of holes.
The initial recombination problem has not been
solved analytically for arbitrary pair line density.
However, analytic solutions do exist in the limiting
cases, namely, where the charge pairs are far apart
(geminate model) and the opposite, where the elec-
tronlhole pairs are very close together (columnar
model). The characteristic distance scale that dis-
tinguishes these cases is the thermalization radius
of a single electronlhole pair, i.e., the average sepa-
ration distance between an electron and hole of the
same pair after they have dissipated their excess
kinetic energy and reached thermal equilibrium
energies. For SO2, the average thermalization dis-
tance is about 8 nm (Ausman and McLean, 1975;
Oldham, 1985).
Figure 2-10 illustrates schematically the two
limiting cases for which recombination models
have been solved. For the geminate case [Figure 2-
10(a)], the separation distance between pairs is
much larger than the thermalization distance. Un-
der such circumstances, only the recombination
between the individual members of the same pair
needs to be considered; i.e., it is only necessary to
calculate the recombination probability of a single
isolated charge pair whose members are attracted
while, at the same time, they undergo both a drift
motion (in opposite directions) in response to the
local electric field and a random diffusive motion
driven by the thermal fluctuations of the system.
Columnar recombination [Figure 2- lO(b)] oc-
curs when the average pair separation distance is
much less than the thermalization distance. In this
case, the individual electronlhole pairs lose their
identity, and recombination must be considered
between many electrons and holes lying in a
cylindrical distribution around the track of the
incident particle. Obviously, the probability of
recombination of an individual carrier in this case
is significantly greater than in the geminate model
because of the enhanced probability of recombina-
tion encounters between opposite charges.
These models have been successfully applied to
the initial recombination process in thermally
grown Si 02 films in recent years. For example,
low-LET particles, such as high-energy electrons
(including the high-energy secondary Compton
electrons from 60~o-garnma interactions), generate
a sparse density of charge pairs along their tracks
(for a 1-MeV electron, the average pair separation
distance is about 50 nm), and the geminate model
fits the results very well. On the other hand, very-
high-LET particles, such as protons, alpha particles
/
1
I
4-L-
ESCAPE \ CAPTURE
\
\
\
'.
.-
(a) Geminate Model - Separate Electron/Hole Pairs
4 1- PAIR SEPARATION DISTANCE
(b) Columnar Model - Overlapping ElectronIHole Pairs
Figure 2-10. Schematic diagrams indicating limiting
pair separation distances for the geminate and columnar
recombination models (McLean and Oldharn, 1987).
and other heavier ions, generate high pair density
along their tracks (for example, a 1-MeV proton
generates, on average, an electronhole pair about
every 0.3 nm), and the columnar model success-
fully describes the experimental results. Many situ-
ations of practical interest fall in the transition
region between these two models for the limiting
cases of pair separation distance. However, the ex-
perimental results reflect a smooth continuous
transition between the limiting cases. That is, inter-
mediate cases show increasing columnar behavior
(stronger recombination) as the density of electron1
hole pairs is increased. Figure 2-1 1 is a compila-
tion of a number of experimental results (Ausman
and McLean, 1975; Benedetto and Boesch, 1986;
Boesch and McGarrity, 1976; Curtis, Srour, and
Chiu, 1974; Oldham and McGarrity, 1981) of the
fractional hole yield fy versus electric field for a
number of particles spanning the range from low
to high LET. For these particle sources at a field of
1 MVIcm, the yield varies from almost 90 percent
for low-LET particles (12-MeV electrons and
6 0 ~ o ) to only about 6 percent for the high-LET
2-MeV alpha particles. This figure clearly shows
that recombination is a real and often important
effect when MOS responses to different radiation
sources are compared.
Finally, knowing the initial pair volume density
per rad (go = 8.1 x 1012 ~ m - ~ / r a d [ ~ i ~ ~ ] ) and
the fractional hole yield after recombination
fy(Eox) [from Figure 2- 1 11, the initial threshold
(or flatband) voltage shift is easily obtained.
Assuming a uniform generation density across
the oxide layer, the total initial areal charge
density of holes that escape recombination is
Qh = q go to, fy(Eox)D, where to, is the oxide
thickness and D is the dose in rads(Si02). The
initial threshold shift is related to Qh as:
AQh
AV, (Of) = -
2c ox
0
0 1 2 3 4 5
ELECTRIC FIELD (MeVIcm)
Figure 2-11. Experimentally measured fractional hole
yield versus electric field (in SO2) for several incident
particles WcLean and Oldham, 1987).
where Cox = ~ ~ ~ / t ~ , . The factor of 2 comes from
the fact that the centroid of a uniform charge den-
sity is to,/2, and a negative voltage shift is indi-
cated corresponding to the positive sign of the
induced charge. Finally, substituting for the con-
stant factors in Equation 2.4:
-8 2
-AV,(O+) = 1.9 x 10 tox f,(Eox)D . (2.5)
Here, the units of VT are volts if to, is expressed in
nanometers, and D is in rads(Si02). Equation 2.5
explicitly shows the dependence of the initial volt-
age shifts on oxide thickness squared, indicating a
significant improvement in the radiation suscepti-
bility of devices having thinner gate oxides.
2.2.2.2 Hole %ansp&
The transport of the holes through the SiQ2 ox-
ide layer to the silicon substrate and their subse-
quent recombination there, which is responsible
for the early-time recovery of VT [Figure 2-91, has
been studied extensively by several groups, includ-
ing Boesch et al. (1975). This process has been
found to exhibit some rather unusual properties;
the principal ones are listed below:
1. It is highly dispersive in time, taking
place over many decades in time fol-
lowing a radiation pulse.
2. It is universal in nature, meaning that
changes in temperature, field, and thick-
ness do not affect the shape or overall
dispersion of the recovery curves when
plotted in terms of log-time. Changes in
these variables affect only the time scale
for the recovery.
3. The transport is field activated.
4. At temperatures above about 14QK, the
transport has an Arrhenius-type tem-
perature activation dependence; below
14QK, the transport essentially be-
comes thermally nonactivated.
5. The characteristic recovery time, or hole
transit time, has a strong superlinear
power-law dependence on oxide thick-
ness.
Many of these features, such as the dispersion
in time, universality, and superlinear thickness de-
pendence, can be directly attributed to a wide dis-
tribution of transit times of the individual holes
through the material. The wide distribution of tran-
sit times is a result of a broad distribution of indi-
vidual (microscopic) event times, which extend
into the time range necessary for the fastest carri-
ers to transit through the sample. In essence, while
some carriers transit the sample very rapidly via a
succession of rapid events (i.e., hops), other carri-
ers are immobilized at some point for times on the
term polaron refers to the situation where the
charge carrier (hole in our case) strongly interacts
with the surrounding medium, inducing a signifi-
cant distortion of the lattice or atom network in the
immediate vicinity of the carrier (also sometimes
referred to as self-trapping of the carrier).] As the
carrier moves through the material via hopping, it
carries with it the accompanying lattice distortion.
The strongest evidence for the polaron hopping
mechanism is the transition from thermally acti-
vated behavior above -140K to an essentially
nonactivated transport at lower temperature.
order of, or greater than, the transit time of the
some of the salient features of hole transport are
fastest carriers. Such broad distributions of event
illustrated by the data sets shown in Figures 2-13
times can be envisioned in two
and 2-14. Figure 2-13 shows the effect of tempera-
situations. First, in hopping transport, small fluc-
ture and Figure 2-14 the effect of oxide electric
tuations (due to disorder) in either the intersite
field, These data are measurements of the flatband
hopping distance or in activation energy, or even in
voltage shift versus log-time from 10-4 to 103 set-
bond can produce large in the following pulsed 12-MeV electron (LINAC)
transfer
and hence lead to large
irradiation of MOS capacitors. The data in these
variations in hopping times. Second, for transport
figures are well normalized to the initial
mediated in which the AV,(O+) immediately after the radiation pulse,
carriers move via normal band conduction between
The initial shifts are not those at the earliest mea-
trapping events, in the
surement (-104 second), but rather are the calcu-
trap energy level can lead to a broad distribution of
lated shifts before any transport occurs. The actual
times from the These
values of AVm(O+) vary with dose, field, and thick-
are indicated schematically in Figure 2-12.
ness as described in Subsection 2.2.2.1. The data
The specific intersite hopping transfer mecha- are plotted in the negative direction because the
nism seems most likely to be small polaron-like voltage shifts are negative, indicative of net posi-
hopping of the holes between localized, shallow tive charge induced in the oxide layer. Figure 2-13
trap states having a random spatial distribution but shows the response for a series of temperatures
separated by an average distance of 1 nm. [The between 125K and 293K at a single oxide field
(a) Trap-Modulated Transport (b) Hopping Transport (Tunneling)
(Valence-Band Conduction)
Figure 2-12. Schematic diagrams of the trapped-modulated and hop-
ping transport models, both of which lead to large dispersion in carrier
transit times (McLean and Oldharn, 1987).
of 1 MVIcm. The strong temperature activation
above 141K is apparent; in fact, plotting the time,
say, at which half-recovery occurs versus 11T
(Arrhenius-type plot) yields a straight line, the
slope of which yields an activation energy of -0.60
eV. Figure 2-14 shows the response at a constant
temperature of 79K with oxide field as a param-
eter in the range from 3 to 6 MVIcm.
The large amount of time dispersion is apparent
in both Figures 2-1 3 and 2- 14, with the recovery
taking place over many decades in time (approxi-
mately 8 to 10 decades from start to finish). The
universal feature of the transport is also evident in
the data in that changes in an external parameter
[temperature in Figure 2-13 and field in Figure
2-14] do not seem to have much effect on the
shape of the recovery curves when log-time plot-
ted. Rather, the major effect of changes in these
parameters is simply to produce a rigid translation
of the curves along the log-time axis; that is, only
the time scale for the transport is affected and not
the amount of dispersion. In fact, if these data are
replotted in time units scaled to a characteristic re-
covery time (e.g., half-recovery time), the data for
different parameter values essentially trace out the
same universal curve. This is shown in Figure
2-15 for the temperature data of Figure 2-13,
where the data for all temperatures in terms of
scaled time trace out a universal curve over ten or
more decades in time. In several instances, data
points from as many as five temperatures overlap
to a considerable degree in the same region of
scaled time.
The almost complete flatband recovery at late
times and high temperatures in Figure 2-13
indicate very little long-term, or permanent, trap-
ping of holes in this particular sample; a trapping
fraction of < 2 percent is indicated by these data.
Hence, this particular oxide is a "good" (i.e., clean,
radiation-hard) oxide in which to analyze the hole
transport, not complicated by effects associated
with deep hole traps. Be aware that the deep hole-
trapping fraction can vary greatly among different
oxides, so care must be exercised when quantita-
tively characterizing hole transport properties if the
trapping fraction is large.
Figures 2- 13 and 2- 14 indicate that little trans-
port or recovery occurs at the lowest temperatures
until relatively long times on the scale of the ex-
periments. For example, at 80K and for Eox = 3
MVIcm, the recovery begins only after 10 seconds
[Figure 2-14]. In fact, for Eo, < 2 MVIcm, essen-
tially no recovery takes place at 80K for times on
the order of thousands of seconds; the holes remain
frozen in place very near their point of generation.
TIME AFTER PULSE (seconds) TYME AFTER PULSE (seconds)
Figure 2-13. Normalized flatband voltage recovery data Figure 2-14. Normalized flatband voltage recovery data
following pulsed 12-MeV LI NK electron irradiation of following pulsed LINAC electron-beam exposure for
96.5-nm oxide MOS capacitor under 1-MVIcm oxide 96.5-nm oxide MOS capacitor at 80K and for oxide
field for various temperatures (Boesch et al., 1978). fields from 3 to 6 MVIcm (McGanity et al., 1978).
This feature has been used in studies of the charge charge (electron) trapping and interface-state
yield in Si02 (Boesch and McGarrity, 1976; buildup effects, unless specific device-processing
Oldham and McGarrity, 1983; Sanders and Gre- changes are made to alter the oxide and conse-
gory, 1975). It also has severe implications for the quently reduce the hole trapping or enhance the
operation of Si02 MOS devices at cryogenic tem- other effects.
peratures if they &e exposed to ionizing radiation.
Indeed, there would be no short-term recovery of
the devices, as is the case at room temperature
[Figure 2-91; the threshold voltage shift would re-
main essentially at its maximum initial value for
all practical times.
2.2.2.3 Deep Hole napping and Annealing
Following exposure to ionizing radiation and af-
ter the radiation-generated holes have been trans-
ported through the oxide, MOS structures typically
exhibit a negative voltage shift component AVO, in
their electrical characteristics (e.g., V , V,) that is
not sensitive to silicon surface potential and per-
sists for hours to years. This long-lived radiation
effect component is the most commonly observed
form of radiation damage in MOS devices and is
attributed to the long-term trapping of some frac-
tion of the radiation-generated holes in the oxide
layer within -10 nm of the Si02/Si interface. This
effect generally dominates other radiation damage
processes in MOS structures, including negative
Again, it must be stressed that radiation effects
involving interface phenomena in general (hole
trapping and long-term annealing [removal] of
trapped holes, interface trap buildup) are all highly
dependent upon oxide processing. The different
effects vary by orders of magnitude for these phe-
nomena among oxides of varying processing histo-
ries, in contrast to the bulk phenomena of charge
pair generation, recombination, and hole transport,
in which remarkably little variation is observed
among thermal oxides of greatly different process-
ing. Consequently, in terms of minimizing long-
term damage effects associated with the interface
phenomena, proper control of oxide (circuit) pro-
cessing has been, and continues to be, a major
thrust of radiation-hardening efforts.
The effect of processing on the fraction of holes
that undergo deep, long-lived trapping is illustrated
by the data shown in Figure 2-16. Here, the thresh-
old voltage shifts versus ionizing radiation dose are
plotted for two n-channel devices where the radia-
+
= 0
2
s -
n
>-
0.25
L
x
cn
w TEMPERATURE
0
a
3 0.50
0
z
a
m
3 0.75
L
O
W
!
4
a
5 1.0
p 10-8 106 10-2 100 102 1 04 106
SCALED TIME, tltlI2
Figure 2-15. Normalized flatband voltage recovery data of Figure 2-13 (E,, = 1 MVIcm) replotted with time scaled to half-
recovery time, illustrating the universality of response with respect to temperature (McGarrity et al., 1978).
tion hardness was varied by changing the high-
temperature processing. The dose rate was 8 x 10"
rads/min, and the measurements were obtained
within 10 minutes of the exposure at each dose.
Clearly, at each dose there is roughly an order-of-
magnitude difference in the threshold voltage shift,
which in turn is most likely due to an order-of-
magnitude difference in the number of hole traps
present in the two oxides. In genera!, the fraction
of radiation-generated holes that undergo long-
term deep trapping has been found to vary from as
little as 1 or 2 percent for a good, hardened oxide,
to the order of 10 to 20 percent for good-quality
commercial oxides, and to as much as 50 to 70
percent in very soft commercial oxides.
Evidence concerning the location of the trapped
holes is contained in Figure 2-17, which shov~s
long-term flatband voltage shift AVfi measured in
MOS capacitors on n-type silicon irradiated to 1
Mrad(SiQ2) at gate voltages from -10 to +-I0 volts.
The flatband shift for negative gate voltage VG in-
positive oxide charge must be fairly mobile since it
apparently moves rapidly toward, and is trapped
near, the Si02/Si interface under positive bias and
moves toward the gate under negative bias. If bulk
trapping were involved rather than trapping near
the interfaces, the shifts for positive and negative
polarity for the same Geld magnitude would not
differ nearly as much as the data in Figure 2-17. A
great amount of other work indicates that the loca-
tion of the long-term tiappecl holes under positive
gate bias is generally within -10 nm of the Si02/Si
interface (Grove and Snow, 1966; Oldham, Lelis,
and McLean, 1986).
In addition to the location of the trapped holes in
the oxide within -10 nm of the Si02/Si interface
and the fact that the hole-trapping fraction is
highly dependent on processing, other pertinent
pieces of information concerning the characteris-
tics of the hole traps - obtained from the work of
many investigators over the years - include the
following:
cludes contributions from both the oxide-trapped
1. The number density of the hole traps
charge and radiation-generated interface states, but
typically lies in the range from 1016 to
the response is dominated by the trapped-hole
l0I9 cmp3 (Eoesch e l nl., 1984; Grove
component. The shift under positive VG is much
and Snow, 19666, with the correspond-
greater than that observed at equivalent nega.tive
ing areal density ranging from 1012 to
VG. From similar data, it has been inferred that the
1013 c m2 .
IOMlZlNC RADIATYON DOSE (rads[Si]) GATE VOLTAGE, VG (volts)
Figure 2-16. Effect of processing on hole trapping; Figwe 2-17. Bias dependence of radiation-induced volt-
threshold voltage shift versus ionizing radiation dose for age shift; flatband voltage shift versus gate voltage for an
two n-channel MOSFETs (VG = +10 volts) receiving MOS capacitor following a I -Mrad (SiQ2) exposure (b,
different high-temperature processing (Derbenwick and
= 70 nm) (Derbenwick and Gregory, 1975).
Sanders, 1977).
2. The cross section for hole trapping is
usually found to be around 5 x 10-l4
cm2 for a 1-MVIcm oxide field (Aitken
and Young, 1977; Boesch et al., 1986).
3. The cross section decreases as E;:' ~ for
fields above 1 MVIcm in magnitude
(Boesch and McLean, 1985; Dozier and
Brown, 1980; Tzou, Sun, and Sah,
1983). For the data shown in Figure 2-
16, the increase in Vfb as the bias is in-
creased from zero is attributed to the
increased yield of holes with increasing
field; but the flattening of the curve for
larger positive bias (and sometimes a
turnaround has been observed) is prob-
ably due to the decreasing cross section
for hole capture as the field increases
above 1 MVIcm.
4. It is commonly observed (Boesch and
McGarrity, 1976; Boesch et al., 1986;
Churchill, Collins, and Holmstrom,
1974; Collins, Holmstrom, and
Churchill, 1979; Hughes and Seager,
1983) that the total number of trapped
holes Not tends to a saturation level in
the 1- to 10-Mrad dose range. Depend-
ing on specific circumstances, this is
due to one or more operating factors,
including trap filling (hard saturation),
large space-charge effects to the point of
field reversal in some regions of the
oxide layer, and recombination of the
trapped holes with radiation-generated
electrons moving through the trapped-
hole distribution.
5. Based upon an increasing accumulation
of electron spin resonance (ESR)
spectroscopy data (Lenahan and
Dressendorfer, 1983; Marquardt and
Sigel, 1975; Sigel et al., 1974), the mi-
croscopic structure of the trapped holes
seems to be the so-called E; center,
which is a trivalent silicon defect associ-
ated with an oxygen vacancy in the
Si02 structure (Feigl, Fowler, and Yip,
1974; Griscom, 1984; Silsbee, 196 1).
In essence, present evidence suggests the fol-
lowing model for the hole-trapping process. The
Si02/Si interface region of MOS structures is char-
acterized by high local strain and a deficiency of
oxygen atoms, resulting in a number of strained Si-
Si bonds (instead of normal Si-0-Si bonding con-
figurations). A hole encountering such a strained
bond may break the bond and recombine with one
of the bonding electrons. The resulting positively
charged structure relaxes to the E; center configu-
ration, with one of the Si atoms retaining the re-
maining electron from the broken bond and the
positive charge residing with the other trivalent Si
atom. Figure 2-18 shows a simple schematic of the
trapping process.
(a) Strained Si-Si Bond (b) Relaxed E; Center
(Oxygen Vacancy) Configuration After
Hole Capture
Figure 2-18. Schematic of hole-trapping process
(Boesch, n.d.).
Regarding the question of the long-term stability
of the deeply trapped holes, it is to be noted that
the holes in deep traps in the Si02 layer of an
MOS structure after irradiation are not truly "per-
manently" trapped. Instead, they are observed to
disappear from the oxide over times from rnillisec-
onds to years. This discharge of the trapped holes,
as commonly observed at or near room tempera-
ture, is the major contributor to the so-called
"long-term annealing" of radiation damage in
MOS devices. The annealing of the trapped holes
has two manifestations that may reflect different
hole-removal processes. The first is the slow, bias-
dependent recovery of AVO,, typically observed at
normal device operating temperatures (-55 to
125"C, for instance). Aspects of this process have
been described through a tunneling model. The
second is the relatively rapid and strongly tempera-
ture-dependent thermal detrapping or recombina-
tion of the holes observed when MOS structures
are deliberately subjected to thermal annealing
cycles at elevated temperatures (150 to 350C).
This process has been described through a thermal
detrapping model. The focus of the discussion here
is restricted to the "tunnel anneal" process, impor-
tant at normal operating temperatures.
Figure 2-19 presents typical results for the time
dependence of hole annealing at room temperature.
Midgap voltage shift, AV (-VoJ, is plotted as a
mg
function of time after irradiation for three n-chan-
nel MOSFET samples with different dry-oxide
processing. The discharge of the trapped holes is
roughly linear in log(t). This behavior is a hallmark
of the hole-annealing process and has been used in
convolution schemes for predicting the response of
MOS devices under low-dose-rate irradiation con-
ditions (Derbenwick and Sanders, 1977; Winokur,
1982; Winokur, Kerris, and Harper, 1983). Note
that the three devices shown in Figure 2-19 have
been irradiated to different doses to achieve
roughly comparable shifts for the first measure-
ments (20 krads for the soft samples, 90 krads for
the intermediate samples, and 1 Mrad for the hard
samples).
A SOFT (20 krads)
TUNNEL MODEL RESULTS
TIME AFTER IRRABBAT3QN (seconds)
Figure 2-19. Long-term annealing data for three
MOSFETs of varying radiation hardness; devices re-
ceived the doses indicated to produce comparable initial
shifts (Oldham, Lelis, and Mckan, 1986).
Several investigators have suggested a tunneling
process to explain the log(t) recovery and other as-
pects of hole annealing in MOS structures
(Benedetto et al., 1985; Boesch et al., 1978;
Manzini et al., 1983; Oldham, Lelis, and McLean,
1986; Saks, Ancona, and Modolo, 1984). These
models assume that electrons from the silicon sub-
strate tunnel to, and recombine with, the trapped
holes in the distribution of traps near the Si02/Si
interface, as illustrated by the schematic diagrams
in Figure 2-20. [Equivalently, the holes can be
thought of as tunneling from the traps to the silicon
valence band.] As a consequence of the exponen-
tial decay of the tunneling probability with dis-
tance into the SO2, at a given time t the hole traps
are emptying from the silicon at a depth X,(t) that
increases logarithmically with time (McLean,
1976; Ross and Wallmark, 1969):
where p is the tunneling barrier height parameter
and to is the time-scale parameter. For distances
only slightly greater than X,, essentially all the
traps remain full at time t; for distances only
slightly less than X,, essentially all the traps have
been emptied by tunneling. Thus, hole removal
proceeds via a "tunneling front" that moves into
the oxide with a "velocity" AX, = 1.151j3 per
decade in time. [Manzini et al. (1983) and
Benedetto et al. (1985) have found AX, to be
(a) t < to
(b) Z >> to
Figure 2-26. Schematic of trapped-hole removal by
electron tunneling from silicon substrate (McEean and
Oldham, 1987).
about 0.2 nm per decade.] For X, << to, and a
uniform distribution of traps in the oxide within
tunneling distance of the silicon, the resulting
trapped-charge loss (and hence the decrease in
AVO,) at a given time due to the tunnel anneal is
then proportional to X,; i.e., AVot decreases as
Cn(t). Thus, the tunneling model explains qualita-
tively the observed approximate log(t) anneal of
the trapped holes.
What this simple model fails to do is describe
the observed responses in detail. As shown in Fig-
ure 2-19, the annealing curves are not completely
linear; the rate of annealing tends to decrease with
time. This is to be expected, since the rate of an-
nealing should approach zero as the amount of
charge left to be removed (remaining AVot)
approaches zero. The simple log(t) anneal arises
from the assumption that the trapped holes are dis-
tributed uniformly into the oxide from the silicon
interface. In reality, the hole trap density generally
falls off with distance from the silicon. Oldham,
Lelis, and McLean (1986) assumed an exponential
falloff in occupied hole-trap density from the inter-
face and incorporated this form into the appropri-
ate expressions from tunneling theory, yielding the
solid-line fits to the data as shown in Figure 2-19.
An important conclusion from this analysis was
that the trapped-hole distribution lies close to the
Si02/Si interface in hard oxides (i.e., the distribu-
tion falls off relatively sharply from the interface),
whereas it extends deeper into the oxide bulk for
the soft oxides. This is apparently related to the
size of the strained, oxygen-deficient region near
the interface, a property highly dependent upon
processing conditions. The fact that the tunneling
rate depends exponentially on tunneling distance
then explains the many orders of magnitude varia-
tion in long-term annealing rates among different
oxides (Johnston and Roeske, 1986).
from the field modification of the tunneling poten-
tial barrier height; a positive electric field has the
effect of lowering the barrier to tunneling and
thereby increases the rate of annealing.
2.2.2.4 Radiation-Induced Interface 'haps
Interface traps Nit are localized electronic states
located at or very near the Si02/Si interface, hav-
ing their energy levels distributed within the Si
bandgap. They can exchange charge with the Si
conduction and valence bands. Their occupancy, or
charge state, depends upon the position of the
Ferrni level at the interface, i.e., upon the value of
the surface potential. The major effects of Nit in
MOS systems are to (1) produce distortions in de-
vice characteristics (e.g., C-V or I-V) as the gate
bias is varied, (2) shift the threshold voltage due to
the net interface trapped charge at the turn-on or
inversion point, and (3) introduce additional Cou-
lomb scattering centers for carriers moving in the
surface channel of a MOSFET, which degrade the
carrier mobilities. Before irradiation, the area den-
sity of interface traps in good, modern devices is
5101 cm-*; for such a density, Nit effects nor-
mally are not much of a problem.
Upon irradiation, however, interface traps can
build up to a significant level, resulting in discern-
ible effects in devices. In general, two components
of radiation-induced interface traps have been ob-
served: (I) a prompt component present at the ear-
liest measurements following an irradiation, and
(2) a time-dependent component that can continue
building up for thousands of seconds. The relative
ratio of the two components can vary greatly, with
one or the other dominating in a particular system.
As a general statement, the delayed time-depen-
dent Nit seems to dominate in metal (aluminum)
gate devices (Winokur, McGarrity, and Boesch,
1976; Winokur et al., 1977; Winokur et al., 1979;
Winokur and Boesch, 1980; Winokur, McLean,
Additional aspects of the tunnel-anneal process
and Boesch, 1986), prompt Nit dominates in thick,
are its dependencies upon temperature and oxide
steam oxides (as used as field oxides) (Boesch,
field. The temperature effect seems to be ad-
1982; Boesch and Taylor, 1984), and both compo-
equately explained (Manzini et al., 1983) by a lin-
nents seem to be present in more or less compa-
ear temperature dependence of the trap energy rable amounts in polysilicon gate devices
levels, Et(T) = E: - bT, where E! = 3.6 eV and b (Schwank et al., 1986) that are more representative
= 2.0 meVI0K. The electric field dependence arises of present-day technology.
An example illustrating the effect of the time-
dependent Nit buildup is shown in Figure 2-21,
which displays C-V traces of an aluminum-gate,
dry-oxide MOS capacitor, both before irradiation
and for a series of times from 0.04 to 400 seconds
following a pulsed 200-krad(Si02) LINAC elec-
tron beam exposure. At the first measurement fol-
lowing irradiation (0.04 second), the C-V curve is
simply shifted along the negative voltage axis
without any discernible change in its shape com-
pared to the pre-irradiation trace, indicative simply
of a positive charge being induced in the oxide.
The 0.4- and 4-second curves show a rigid shift
back in the positive voltage direction with little
tween 1 and 6 MVIcrn, from 2 x lo0 to almost 105
seconds following pulsed LINAC irradiation. Note
that the final Nit levels in this case are almost
solely due to the time-dependent buildup process.
There is obviously a strong field dependence on
both the rate of buildup and the final value of Nit.
For all fields, the buildup apparently begins on the
order of seconds (the point at 1 second on Figure
2-22 is also the pre-irradiation Nit value), continu-
ing for several hundred seconds at the highest field
(6 MVIcm) before leveling off. For the lower field
values (I and 2 MVIcm), the generation rate is
much lower, but Nit is still seen to be increasing
even at the latest measurement times.
change in because of a of the
In Figure 2-23, the field dependence of the ra-
end of the transPoit Process and the
diation-induced interface trap buildup is
trapped-h01e
the significant
for three types of MOS capacitors: (1) aluminum
stretchout seen to occur between 4 and 40 seconds
gate, (2) polysilicon-gate samples receiving fitypi-
becomes even greater at 400 seconds. This distor-
cal Si-gate processing,,, and (3) special ..hardened"
tion is directly attributed to the delayed buildup of
Si-gate capacitors. Plotted in the figure is the in-
radiation-induced Nit.
crease in interface trap density between midgap
Figure 2-22 shows the time-dependent buildup and inversion following 1-Mrad(Si02) irradiation
of interface trap density (for states with energies as a function of oxide electric field for both posi-
between midgap and inversion) for Al-gate, wet- tive and negative polarities. ANi, contained both
oxide capacitors for a series of oxide fields be- prompt and delayed time-dependent components
APPLIED VOLTAGE (volts)
Figure 2-21. High-frequency 1-MHz C-V curves of MOS Al-gate capacitor at several times following pulsed electron beam
irradiation (Winokur, McGanity, and Boesch, 1976).
for the Si-gate samples. In all three samples, ANit
is much less under negative bias polarity than posi-
tive polarity [note the log scale for ANit]. The Nit
buildup for the Al-gate capacitors increases with
increasing positive field, in general agreement with
the earlier data of Figure 2-22. However, the Si-
gate capacitors exhibit a rapid increase in Nit pro-
duction for positive fields up to -1 MVIcm, which
peaks in the range from 1 to 2 MVIcm but then
drops off somewhat at higher fields. It is clear that
DOSE = 0.8 Mrad
0O2 6 ~ ~ 1 102 103 104 105
TIME AFTER PULSE (seconds)
Figure 2-22. Integrated interface trap density between
midgap and inversion surface potentials as a function of
time following pulsed electron-beam (LINAC) exposure
for several oxide field values; 0.8-Mrad dose, wet-oxide
A1 gate, to, = 96.5 nm (Winokur et al., 1977).
AI-GATE
I
E
TYPICAL Si-GATE
0
V
C
.-
Z
1010
- 3 - 2 - 1 0 1 2 3 4 5
ELECTRIC FIELD (MVIcrn)
Figure 2-23. Oxide field dependence of radiation-in-
duced interface trap buildup following 1-Mrad (Si02) ir-
radiation in three MOS capacitors having different gate
structures (Winokur et al., 1985).
some qualitative differences exist in the mecha-
nisms of Nit buildup in Al-gate and Si-gate sys-
tems. These differences are not understood at the
present time, although they are likely to be associ-
ated with differences in the nature of the genera-
tion mechanisms for the prompt and delayed
time-dependent components. Note also in Figure
2-23 that for normal operating fields of 1 to 2 MVI
cm, ANit for the typical commercial Si-gate pro-
cess is about five times greater than that for the Al-
gate samples. This increased ANit is commonly
observed for Si-gate technologies.
The discussion thus far has attempted to illus-
trate some of the major observations that have been
made concerning the buildup of radiation-induced
interface traps, such as the existence of prompt and
delayed time-dependent components, the strong
bias polarity effect, the dependence on the magni-
tude for positive fields, and the strong dependence
on oxide processing, including the differences be-
tween aluminum-gate and polysilicon-gate struc-
tures. At the present time, the precise mechanisms
responsible for the interface trap buildup are not
well understood, and, in fact, the general area of
Si02/Si interface traps and their generation under
various stresses (radiation, high electric fields, hot-
carrier injection, etc.) is a complex subject of in-
tense current interest and debate. However, some
observations concerning these phenomena include:
1. There is much evidence that Nit buildup is
associated with the hole transport, trap-
ping, and annealing processes (Boesch et
al., 1986; Lai, 1983; McGarrity et al.,
1978; Winokur, McGarrity, and Boesch,
1976; Winokur et al., 1976, 1977, 1979;
Winokur and Boesch, 1980; Winokur,
McLean, and Boesch, 1986).
There may also be a strong correlation of
the buildup with hydrogen or water con-
tent of the oxide; in fact, arguments have
been made that the time-dependent
buildup is associated with the release
(during the hole-transport phase) and dif-
fusion of hydrogen, or a water-related
species, from the oxide bulk to the inter-
face (Brown, 1985; Griscom, 1985;
McLean, 1980; Revesz, 1977; Sah, 1976;
Svensson, 1978).
3. The amount of interfacial strain,
which is highly variable with processing,
seems to be an important factor (EerNisse
and Derbenwick, 1976; Grunthaner,
Grunthaner, and Maserjian, 1982; Toyo-
kawa et al., 1986; Winokur, McLean, and
Boesch, 1986; Zekeriya and Ma, 1984).
4. The rate of buildup of the time-dependent
Nit component increases with tempera-
ture; however, the final density at long
times is essentially independent of tem-
perature (Mckean, 1980; Winokur et al.,
1977, 1979).
5. Annealing of interface traps has not been
observed at normal operating tempera-
tures (Reed and Plummer, 1986); signifi-
cant annealing occurs only for T > 150C.
6. In many cases, a sublinear dependence of
DN,, on dose (-D2I3) has been observed,
particularly for the delayed time-depen-
dent component (Dozier and Brown,
1983; Naruke et al., 1983; Winokur et al.,
1977; Winokur and Boesch, 1980).
7. The magnitude of Nit buildup is generally
observed to decrease with decreasing ox-
ide thickness (Boesch et al., 1978; Ma,
1975; Ma and Barker, 1974; Naruke et al.,
1983; Saks, Ancona, and Modolo, 1986;
Viswanathan and Maserjian, 1976).
8. The energy distributions of radiation-in-
duced interface traps are commonly ob-
served to be U-shaped, with a minimum
near midgap and rising toward both the
conduction and va.lence band edges (Sah,
Sun, and Tzou, 1982; Winokur, McCarrity,
and Boesch, 1976; Winokur et al., 1977).
However, the existence of intermediate
structures, such as peaks, is the subject of
debate (Knoll, Braunig, and Fahmer, 1982;
Lenahan and Dressendorfer, 1984; Ma,
1975; Poindexter et al., 1984).
9. The interface traps seem to be arnphoteric
in nature, that is, they have a net negative
charge (acceptor-like) when the Fermi
level EF at the surface is in the top half of
the Si bandgap; they have net positive
charge (donor-like) when EF is in the bot-
tom half of the bandgap; and they are
charge neutral when EF is near midgap
(Knoll, Braunig, and Fahmer, 1982;
Lenahan and Dressendorfer, 1984; Ma,
Scoggan, and Leone, 1975; Poindexter et
al., 1984).
10. Since the radiation-induced interface traps
lie at or very near the Si02/Si interface,
they introduce additional scattering ten-
ters for the conducting channel carriers in
MOSFETs, especially when charged;
these are in addition to the normal scatter-
ing from surface roughness, ionized
dopants or other impurities in the surface
region, and lattice vibrations (phsnons).
2.3 Ionizing Radiation Dose Effects om
Sedcondaactoi~ Devices
The purpose of this section is to provide a brief
summary [paraphrased from Rose, 19841 of the
effect of ionizing radiation dose on a variety of
semiconductor devices, e.g., diodes, transistors,
MOS digital integrated circuits, and both linear
and digital bipolar integrated circuits. In addition,
a number of examples concerning the ionizing ra-
diation dose hardness of these types of devices will
be provided. The information presented here can
be used as part of the semiconductor device selec-
tion criteria (e.g., technology and operating mode)
for different applications (e.g., space satellite, stra-
tegic or intercepter missile, etc).
2.3.1 Effects on Diodes
2.3.6.8 Cow~entiomall Diodes
Ionizing radiation dose effects in switching and
rectifying diodes appear as a change in the fornard
voltage VF, leakage current f R, and the breakdown
voltage VB. Parameter changes are not linear with
cumulative dose. In general, the parameter changes
are barely detecta.ble at 10 krads(Si). At 100
krads(Si), the usual parameters of design impor-
tance, AVF and AIR, are less than 50 mV and 10
PA, respectively.
2.3.1.2 Voltage-Reference Diodes
The parameter of interest voltage-reference di-
odes is reference (or zener) voltage VZ. Figure
2-24 is a normalized scatter plot of change in zener
voltage as a function of ionizing radiation dose. It
can be seen that insignificant changes occur up to
lo2 krads(Si); between lo2 and lo3 krads(Si),
changes of 0.1 to 1 percent are typical. The mecha-
nism for the change is creation of inversion layers,
which are dependent on doping concentration lev-
els. Therefore, diodes that are heavily doped and
have low breakdown voltages are not as sensitive
to ionizing radiation dose as lightly doped devices
with high breakdown voltages.
IONIZING RADIATION DOSE (krads[Si])
Figure 2-24. Normalized reference voltage change AVZ
for zener diodes at 25OC versus ionizing radiation dose
[AVZ(D) is the average change in VZ for the given test
sample] (Rose, 1984).
2.3.1.3 Microwave Diodes
Microwave diodes are inherently hard to ioniz-
ing radiation dose. Most device pre-irradiation pa-
rameters are unaffected at dose levels below lo6
rads(Si) and show only small changes (a few per-
cent) between lo6 and lo7 rads(Si).
2.3.2 Effects on Junction Field-Effect
Transistors
The primary effect caused by ionizing radiation
dose on junction field-effect transistors (JFETs) is
increased leakage current between the reverse-bi-
ased gate and drain. This increased leakage current
is caused by ionization-induced surface charge
within the oxide. This surface charge, if suffi-
ciently great, can invert the region. In the case of a
heavily doped p-region, the oxide may saturate be-
low a level sufficient to invert the surface. This
saturation effect results in an increased reverse cur-
rent, effectively shunting the bulk channel and
causing pinch-off to appear less complete. The in-
creased leakage current is similar to increased re-
verse leakage within pn diodes and therefore has
comparable failure levels. Typical changes in in-
creased leakage currents may be of one or more
orders of magnitude between lo6 and lo9 rads(Si).
However, even these large changes may not sig-
nificantly affect circuit operation. For most appli-
cations, JFETs are inherently hard to ionizing
radiation dose levels up to lo7 rads(Si).
2.3.3 Effects on Bipolar Tkansistors
Bipolar transistors experience changes in their
forward current gain hEE, leakage currents IcBO
and IEBO, and saturation voltage VCE(,,) when
exposed to ionizing radiation. The ionizing radia-
tion dose causes leakage currents to increase,
thereby degrading hFE. Gain degradation is a func-
tion of collector-base bias voltage, as shown in
Figure 2-25 for npn and pnp transistors. Low-cur-
rent, high-gain transistors are more vulnerable to
ionizing radiation effects than other transistors be-
cause surface current effects are more significant at
low collector currents. The variation of hFE as a
function of collector current and ionizing radia-
tion dose is given for 2N2222A transistors in
Figure 2-26. The error bars shown in the figure are
due to the variation of hFE degradation from batch ionizing radiation dose. These are generally of
to batch of the same part. Figure 2-27 shows data. lesser significance, reflecting average changes of
for 2N2102 transistors taken from five different about 1 percent at lo5 rads(Si) as shown in
batches during a single day's run. In addition to Figures 2-28 and 2-29.
h, , VCE(,,) and Iceo will both be affected by
-.<?:\\
PASSIVE
--
.\ \?,
VCB = 10 volts, IE = 0.01 rnb ,:.\ . . . . . \ .<\
----
VCB = l o volts, IE = 1 rnA .\ --J
-
- - -
VCB = 10 volts, IE = 50 rnA
- Ll l LU LLLU
PRERAD 1 o4 1 o5
IONIZING RADIATION DOSE (rads[Si]]
(a) npn Transistor 2N2102 (b) pnp Transistor 2N3799
Figure 2-25. Ionizing-radiation-dose-induced hE degradation dependence on irradiation bias condition (Wolmes-Siedle md
Zaininger, 1968).
IONIZING RADlATiON DOSE (rads[Si]]
Figure 2-27. hE degradation for five identical 2N2102
transistors from same day's production (Holmes-Siedle
and Zaininger, 1968).
IONIZING RADlATlON DOSE (rads[Si])
Figure 2-26 hE degradation for 2N2222 transistors
(combined data of 34 devices for all tests by same
manufacturer); VCE = 20 volts (Price et al., 1982).
10-4
lo0 * 4 6 8101 lo2 1 o3
IONIZING RADIATION DOSE (krads[Sil)
Figure 2-28. Normalized saturation voltage change AVCE(SAT) for general-purpose transistors at 25C versus ionizing
radiation dose [AVCE(SAT)(D) is the average change in VCE(SAT) for the given test sample] (Rose, 1984).
2.3.4 Effects on MOSFETs changes in the MOS transistors and ICs [as dis-
MOS devices are generally the most sensitive
cussed in Section 2.21. The effects on individual
electronic devices to ionizing radiation dose due to
transistors are discussed here while these effects on
ionization-induced trapped charge in oxide and the
MOS ICs are discussed in Section 2.5.
generation of interface states, both of which cause
. . . . . . . . . . . . . . . . . . . . . . . .
4 6 8104
IONIZING RAD1ATiON DOSE (krada[Si])
Figme 2-29. Normalized change in collector base cutoff current BCBO for general-purpose transistors at
izing radiation dose [AIcso(D) is the average change i n Icso for the given test sample] (Rose, 1984).
25C versus ion-
The primary effect on MOS transistors is the tion-induced change in threshold voltage VT for
buildup of trapped charge in the gate oxide, which these types of devices varies greatly, as seen in
results in a threshold voltage shift. One of the cur- Figure 2-30, with some devices exceeding the typi-
rent applications for MOSFETs is as a power cal maximum gate threshold voltage near BO*
switch for povrer-conditioning circuits. The ioniza- rads(Si). Other devices showed much less degrada-
tion and were still within the manufacturer's speci- fectively, the ionizing radiation dose degrades the
fication beyond lo5 rads(Si). These and similar equivalent transistor gains, which in turn require
data indicate the dependence of bias, process, and high gate trigger current IGT. The observed failure
circuit design on the failure level for MOSFETs. threshold (50 percent increase in IGT) has been in
Proper design and part selection, however, will
the range of lo4 to lo5 rads(Si), making SCRs one
permit the usage of MOSFETs in circuits with ion-
of the most sensitive discrete devices to ionizing
izing radiation dose requirements up to lo6
radiation dose as well as to dose-rate and displace-
rads(Si).
ment damage effects.
Some MOSFET devices particularly those used
2.3.6 Effects On Integrated Circuits
for high-voltage switching applications exhibit 2.3.6.1 Bipolar Linear lcs
strong rebound effects, i.e., post-irradiation biased
Bipolar linear ICs are moderately sensitive to
can produce significant changes in the
ionizing radiation dose effects. Offset voltage Vos,
post-radiation threshold voltage. These effects can
offset current Ios, bias current Ib, and open-loop
produce significant threshold shifts that are evident
voltage gain A\aL are some of the key parameters
long after the radiation exposure is Fur-
of operational amplifiers and comparators affected
thermore, these devices exhibit large variations in
by ionizing radiation, The for the
response when irradiated at different dose rates.
appearance of parameter changes is about
Irradiated at different dose rates. Irradiation at low-
krads(Si). Figure 2-3 depicts these parameter
(satellite applications) can produce large
variations for a linear IC, In general, bias current
threshold voltage changes.
changes are more pronounced than changes in
2.3.5 Effects on Four-Layer Devices
other parameters. Usually, the mean AIb (10 krads)
is a small fraction of Ib (maximum). There are,
Ionizing radiation dose will have essentially the
however, isolated cases where significant changes
same effect as neutrons on four-layer devices. Ef-
10
1 I l l l l l I I I
are observed at low doses. For example, the
LMl 1 l F has a specification maximum Ib of 100
nA at 25C and a measured mean AIb of 98.6 nA
at 10 krads(Si).
As with bipolar digital ICs, linear ICs built us-
ing oxide isolation exhibit significant leakage
currents and failures at >10 krads(Si). Bipolar
regulator ICs suffer from a loss of precision when
their loop gains are degraded. Regulation changes
are, however, barely detectable at 10 krads(Si).
Radio Frequency (rf) bipolar linear ICs are less
sensitive to ionizing radiation dose degradation;
greater than 100 krads(Si) are required to produce
observable effects.
rads(Si). Emitter-coupled logic (ECL) circuits re-
main hard to levels in excess of lo7 rads(Si). The
approximate failure threshold ranges for these vari-
ous technologies are shown in Figure 2-32.
2.3.6.3 MOS Digital ICs
MOS digital IC devices are most sensitive to
ionizing radiation dose effects. The sensitivity is
dependent on the particular MOS technology, com-
plexity of the device, time history profile of ioniz-
ing radiation dose threat, bias, circuit performance
requirements, and manufacturing process. The ra-
diation response of MOSFETs and MOS ICs is
discussed elsewhere in this chapter [see Sections
2.4 and 2.51 and will not be repeated here. How-
2.3.6.2 Bipolar Digital ICs ever, a few comments are appropriate:
Bipolar digital ICs, including all forms of tran- * Many commercial parts that are not ex-
sistor-transistor logic (TTL) are relatively insensi- plicitly designed to be radiation-hard
tive to ionizing radiation dose effects. Most TTL
are indeed radiation-resistant, i.e., fail-
ICs operate within their specification limit after
ure levels 2100 krads(Si02), and thus
lo6 rads(Si). Bipolar devices built utilizing oxide
are suitable for either tactical or limited
isolation (LOCUS), such as Fairchild Advanced
Schottky TTL (FAST), are susceptible to failure at
levels not much greater than 10 krads(Si). The fail-
ures are a result of isolation leakage, and although
process solutions are known to exist none have
been incorporated by semiconductor manufactur-
ers. However, advanced bipolar technologies like
advanced low-power Schottky (ALS), current-
mode logic (CML), and double-diffused have
shown no appreciable degradation, even after lo6
VOLTAGE GAIN
OFFSET VOLTAGE
103 2 4 6 alO4 lo5 1 o6
IONIZING RADIATION DQSE (rads[Si])
Figure 2-31. Linear IC parameter variations with
ionizing radiation dose (Rose, 1984).
nonstrategic space applications.
The trend to smaller feature size and in-
creased integration density has im-
proved the gate threshold voltage
radiation response (due to thinner gate
oxides) but degraded the leakage
current response due to field oxide
sensitivities.
Insulating substrate technologies [e.g.,
silicon-on-sapphire (SOS), and silicon-
on-insulator (SOI)], while demonstrat-
ing superior dose-rate and SEU
response, have manifested several new
ionizing radiation dose failure modes.
These include side-wall leakage for
mesa-type structures and back-channel
leakage. Also, for planar designs, the
more traditional tub-to-tub leakage
(e.g., field-oxide inversion) and field-
oxide (bird's beak) leakage paths still
exist.
A brief comparison of various MOS integrated
circuit ionizing radiation dose failure threshold
ranges is shown in Figure 2-33.
Figure 2-32. Ionizing radiation dose thresholds for digital bipolar integrated circuits (Rose, 1984).
TECHNOLOGY
STANDARD TTL
LOW-POWER SCHOTTKY TTL (LSTTL)
RAD-HARD LSTTL
FAIRCHILD ADVANCED STTL
ADVANCED SCHOTTKY LOGIC (ASL)
INTEGRATED SCHOTTKY LOGIC (ISL)
EMITTER-COUPLED LOGIC (ECL)
Figure 2-33. Ionizing radiation dose thresholds for MOS technologies (Rose, 1984).
MANUFACTURER IONIZING RADIATION DOSE (rads[Si]) 1
1 04 105 106 107 108
TECHNOLOGY
BULK CMOS
RAD-HARD CMOS
HCMOS
CMOSISOS
RAD-HARD CMOSISOS
RAD-HARD CMOSISOI
HMOs l
HMOs II
HMOs Ill
DMOS
MNOS HARDENED
MNOS COMMERCIAL
VARIOUS
VARIOUS
VARIOUS,
TEXAS INSTRUMENTS,
HARRIS
FAIRCHILD,
MOTOROLA,
SlGNETlC
TEXAS INSTRUMENTS
RAYTHEON
VARIOUS
m
0
i ) ,
.I
. -
I ;
MANUFACTURER I IONIZING RADIATION DOSE (rads[Si]) 1
06 1 02 103 1 04 1 05 1
:
VARIOUS
SANDIA, HARRIS,
IBM, HONEYWELL
NATIONAL, MOTOROLA,
OTHERS
HARRIS
HARRIS, MARCONI
UNITED TECHNOLOGIES,
HONEYWELL, TEXAS
INSTRUMENTS
INTEL
INTEL
INTEL
NEC
SANDIA, NCR, SPERRY
I
I
0 :
0:
I
0
=
:I !
1
I:
2.4 Mebll-Oxide-Semiconductor Field-ERect
Tramistor Ionizing Radiation Dose
Response
In Subsection 2.1.2, the basic mechanisms of
ionizing radiation effects were discussed. Building
on the information provided there, this section ad-
dresses ionizing radiation effects on MOSFETs.
Basically, the effects of ionizing radiation on
MOSFETs result in:
- Threshold voltage (VT) shifts
Induced leakage currents
Reductions in mobility.
Each of the effects is discussed below. In
addition, second-order effects (i.e., hot-carrier
degradation and surface recombination velocity)
are discussed.
2.4.8 Thmhold Voltage Shifts
As previously stated, the radiation-induced re-
sponse is a summation of a variety of basic pro-
cesses: initial hole yield, hole transport, deep hole
trapping, short- and long-term annealing, and inter-
face trap buildup. Chara.cteristic time regimes are
associated with each of these processes and each
process is also a function of bias, temperature, ox-
ide thickness, etc. Figure 2-34 depicts the time-de-
pendent, radiation-induced threshold voltage
response for an n-channel MOSET, with the vari-
ous characteristic time regimes (at room tempera-
ture) explicitly noted, and illustrates the various
long-term recovery behaviors (recovery without
ANit, with prompt ANit, and with time-dependent
ANit buildup). This overall effect is summarized by
0
V)
.w
.-
C
3
2 TRAPPED HOLE
2
4-
.-
-e
m
V
+
>
a
HOLE TRANSPORT
AND TRAPPING,
PROMPT Nil BUILDUP
u I I 1 1 1 1 I l i I -. .
u - - --
106 10-6 100 I (a2 I o4 I 06 I 08 I ~ l o I 01'
TIME AFTER RWDIQ.TION PULSE (seconds)
Figere 2-34. Schematic time-dependent threshold voltage recovery of an n-channel MOSET following pulsed irradiation,
indicating the room-tempzature time regimes associated with the various basic physical processes and possible long-term
responses (McLean and Oldham, 1987).
Equation 2.9. The influence of intriusic (e.g., oxide
morphology, etc.) factors in conjunction with
extriusic effects (e.g., bias, temperature, etc.)
greatly complicates issues dealing with radiation
testing, hardness assurance, and response predic-
tion of circuits in a radiation environment. The re-
sult of the trapped positive charge (holes) for the
n-channel MOSFET is to lower the threshold volt-
age, i.e., it drives the device into depletion, as
shown in Figure 2-35(a), which depicted by a shift
to the left for the threshold voltage and an increase
in drain current ID. In this case, a shift to the left
indicates that a lower gate voltage is required to
turn on the MOSFET. However, as interface trap
density begins to increase the negative charge asso-
ciated with this effect for n-channel devices, sub-
tracts from the positive charge (hole traps) and the
threshold voltage begins to turn around:
AVT = AVot - AVit .
(2.9)
The overall effect for the p-channel MOSFET is
somewhat different. For this device, the trapped
positive charge increases the threshold voltage,
i.e., it drives the device into accumulation, as
shown in Figure 2-35(b), and is also depicted by a
shift to the left for the threshold voltage. However,
in this situation, a shift to the left results in lower
drain current since this change in VT implies that a
higher (more negative) gate voltage is required to
turn on the MOSFET. As the interface state density
increases, the threshold voltage continues to in-
crease. This occurs due to the amphoteric nature
of interface traps or states, where, for a p-channel
device, these traps have a positive charge. Thus,
the p-channel device final threshold voltage will be
the result of the sum of the trapped holes and inter-
face states. This result differs from that for the
n-channel device, where the final threshold voltage
is the result of the difference between the trapped
holes (positive charge) and the interface state den-
sity (negative charge).
2.4.1.1 Rebound Effects (Super-Recovery)
A more detailed discussion of the rebound
(super-recovery) effect is presented here. Deeply
trapped holes (ANot) anneal out over very long pe-
riods of time. Interface traps (ANit) have not been
observed to anneal out at normal operating tem-
peratures. Furthermore, ANit may continue to build
up over time. Since, for an n-channel device under
positive bias, the interface traps contribute net
negative charge and therefore a positive contribu-
tion (AVit) to the threshold voltage, these factors
taken together may give rise to the phenomenon
called super-recovery (Johnston, 1984), or rebound
(Schwank et al., 1984). Namely, at the end of an
0
-1 8 -1 4 -1 0 -6 -2 2 -16 -1 2 -8 -4 0 4
GATE VOLTAGE, VG (volts)
(a) n-channel; to, = 1,000 A
(Substrate NA = 1 x lo1 6,
(b) p-channel; to, = 1,000 A
(Substrate ND = 5 x 1 o1 5,
Figure 2-35. Radiation-induced threshold shift in enhancement MOSFET drain current versus gate voltage characteristics
(King, 1979).
irradiation, the threshold voltage for an n-channel
MOSFET is generally shifted negatively, since the
(negative) voltage contribution AVot from the
trapped holes usually dominates AVi,, at least for
doses up to about 1 Mrad. However, as annealing
of the trapped holes occurs and/or further buildup
of the interface trapped charge occurs, the thresh-
old voltage may actually anneal back to and past
its initial pre-irradiation value; i.e., AVT may go
positive at some late time after cessation of the ra-
diation. If the positive voltage excursion is suffi-
ciently large, circuit failure may result frorn this
effect. Super-recovery is clearly demonstrated by
the data shown in Figure 2-36. Here, the threshold
voltage of a polysilicon-gate n-channel MOSFET,
as well as the separate components AVit and A h p
are plotted against time after exposure to 1 Mrad
6 0 ~ o irradiation that is completed in 1 hour. A gate
bias of +10 volts was maintained during both irra-
diation and the anneal time. Data are shown for
two temperatures, for 25C and for 125C (which
accelerates the rate of hole annealing). At neither
temperature is any annealing of AVi, observed, but
rather some slight increase in AVit after cessation
of the irradiation is discernible. The important
point, of course, is that VT, which is initially is
shifted negatively by about 1 volt at the end of the
irradiation, returns in the positive direction far past
its pre-irradiation value. In fact, after 100 hours of
annealing at 125"C, AVO, is completely annealed,
leaving a final positive VT shift of +2.5 volts, due
entirely to interface trapped charge (most of which
was already present at the end of irradiation).
. -
Some interesting possibilities are associated
with this effect. For example, a device may ini-
tially be in failure at the end of an irradiation be-
cause of a sufficiently large negative voltage shift;
then, as the trapped holes anneal, the device may
begin operating normally at some time and con-
tinue operating until the device fails again frorn too
great a positive threshold voltage shift. Some hard-
ening schemes in the past have attempted to rely
on the compensation of trapped positive (hole)
charge by net negative interface trapped charge.
However, this type of hardening fix is risky at best,
PRERAD 810-1 1 o0 10' 1 o2
TIME (hours)
Figure 2-36. Threshold voltage shift of n-channel MOS transistor during 1 Wad 6 0 ~ o irradiation and subsequent anneal;
VT separated into shifts due to interface trapped charge (Vi,) and oxide trapped charge (V,,) (Schwank et al., 1984).
because the utmost control must be maintained
over the oxide processing to avoid excessive radia-
tion-induced Nit and consequent failure by rebound
at long times. Such careful control of the process-
ing is usually not possible in the long run for pro-
duction lines. The optimum hardening approach is
to minimize both ANot and ANit (Winokur et al.,
1985). [A discussion of the implications of the
behavior on testing considerations is provided in
Chapter 6.1
2.4.1.2 Apparent Dose-Rate Effects
A related problem area is that of an apparent
dose-rate effect (McLean and Oldham, 1987) on
device response; i.e., measurements of device re-
sponse (e.g., AVT) at the end of irradiation to a
fixed total dose, but delivered at different dose
rates, usually will show different results. This is
clearly a result of the complex time history of the
response in which, for example, different amounts
of trapped-hole annealing will occur during irra-
diation for different exposure times (to the same
dose). To deal with this problem, the techniques of
linear response theory have been used in the past.
This type of analysis is valid as long as the system
response is linear in dose. If the impulse response
function AVR(t) is known (say, the threshold volt-
age response to an infinitesimally short irradiation
pulse), then the general response to an arbitrary
irradiation described by the dose-rate function j(t)
may be obtained through the convolution integral:
A simple example for which this technique has
been applied (Derbenwick and Sanders, 1977;
Winokur, 1982; Winokur, Kerris, and Harper,
1983) is that for linear (log-time), trapped-hole
annealing. In general, this approach has limited
quantitative utility because of its nonlinear re-
sponse, as discussed below.
2.4.1.3 Trapped-Hole Saturation Effects
The effect of trapped-hole saturation on radia-
tion-induced threshold voltage shifts is discussed
in this section. Subsection 2.4.1.2 [above] noted
that apparent dose-rate effects, such as varying
amounts of trapped-hole annealing during irradia-
tion exposure, can sometimes be handled with the
convolution integrals of linear response theory.
This approach is valid as long as the system re-
sponse is linear in dose. Unfortunately, this is not
always the case for situations of practical interest.
For example, the number of trapped holes ANo,
tends to saturate for moderate to large dose rates at
doses in the range from 1 to 10 Mrads(Si02)
(Boesch and McGarrity, 1976; Boesch et al., 1986;
Churchill, Collins, and Holmstrom, 1974; Collins,
Holmstrom, and Churchill, 1979; Hughes and
Seager, 1983). This saturation may be due to one
or more factors, including hard saturation due to
trap filling, space-charge effects, or a balance be-
tween hole trapping and hole removal through tun-
nel anneal or recombination with radiation-induced
electrons. An example of such an effect is illus-
trated by Figure 2-37, in which the threshold volt-
ages for n- and p-channel MOSFETs are shown
plotted versus ionizing radiation dose. The thresh-
old voltage for the n-channel device first shifts
negatively as the positive charge buildup due to
trapped holes dominates the response. However, at
doses >1 Mrad, a turnaround is observed, with VT
shifting back in the positive direction at increasing
IONIZING RADIATION DOSE (rads[Si])
Figure 2-37. Threshold voltage versus ionizing radia-
tion dose for irradiated n- and p-channel MOSFETs, il-
lustrating the effect of hole-trapping saturation and
continued interface trap buildup in n-channel devices
(McLean and Oldham, 1987).
dose levels. This turnaround behavior is due to
saturation of the trapped-hole density, while at the
same time the interface trapped charge (negative
for n-channel) continues to increase. For the
p-channel device under negative gate bias, the in-
terface states also contribute net positive charge,
and there is a continued negative shift with dose in
its threshold voltage.
2,4.2 IonEzing Radiatim Dose GB~ssif cathx
Schem2
Since a variety of MOSFET responsss are pos-
sible due to the relative density of holes to inter-
face states; a scheme to categorize the possible
transistor responses has been developed by Bossch
(1986). The scheme, depicted in Table 2-4, classi-
fies oxide response as being one of four quaditalive
0 0
typss, bzsed, first, on lovr AN,, or hioh AN,, and,
8 -
secondly, on whether .ANit << AN,, or ANi, is
0 0
" ANo:. Here, is the oxide trapped-hole den-
sity present at the earliest measurement times of
interest, before appreciable trapped-hole annealing
0
occurs. Note that categories for ANit >> ANot are
not included since this case is not observed in prac-
tice. Thc tabls contains the general qualitative fea-
tures of the response in each cass. In practice,
Table 2-4,. Categorization matrix of possible ionizing
radiatior, dose response t y p ~s for MOS devices, indicat-
ing q~alitative features of response for each type
(Eoesch, 1986).
Category 1 Category 3
No super-recovesy Some super-recovery
Moderate log(t) Complex time history
recovery
Negligible mobility Some mobi!ihy
degradation degradation
Hard Ha d
Category 2 Category 4
No super-recovery Large super-recovery
Mkal: loglt) recovev Complex time history
Possible mobility Severe mobility
degradaf or, degadadon
Soft S o t
some oxides will fall into the grey zones between
the categories, a problem inherent in any classifica-
tion scheme.
2.4.3 Honking Radiation-Dlsse-Induced
Leakage Currents
The discussion of the physical mechanisms
underlying the radiation response of MOS devices
has focused on the gate-oxide layer and on the
consequences of trapped-charge buildup in these
layers, primarily that of induced shifts in threshold
voltages. However, identical physical processes
leading to charge buildup also occur in the thicker
oxides used in ItC technologies. Instead of voltage
shifts, the effects of charge buildup in these oxides
in circuit operation involve the generation of unde-
sirable parasitic current leakage paths. Specifically,
charge buildup in field-, passivation-, or isolation-
oxide regions can induce the formation of inver-
sion channels in the surface regions of adjoining
semiconductor regions, which, in the presence of
any potential gradients (e.g., fringing fields), will
result in parasitic current leakage paths. Leakage
paths can be important failure modes, not only in
bulk MOS technologies, but also in SOS and SO1
structures, and even in bipolar technologies a.s
well. Figure 2-38 is a schematic showing a pos-
sible induced leakage path in an MOS device
structure. Shown are top [Figure 2-38(a)] and
cross-section [Figure 2-38(b)] views of the device,
indicating the various regions of the device. In par-
ticular, the field-oxide region covers the Si sub-
strate outside the gate-oxide and normal
source-drain channel regions. If sufficient radia-
tion-induced chasge buildup occurs in the field-ox-
ide region, especially nesK the Si substrate, then an
inversion layer can be formed in the substrate, as
indicated in Figure 2-38(b), even with the normal
channel turned o f . This induced claannel region
under the field oxide then ogers a low-resistivity
current ledcage path between the source and drain
around the edge of the gate-oxide (normal channel)
region, as shown in; Figure 2-381(a). Note thai the
charge build~ip in the field oxide near the substrate
interface proceeds in exactly the same manner as
in the gate oxide; namely, in response to positive
voltages applied to the gate contact lines (or other
metal strip lines) over the field oxide, which drive
the radiation-generated holes down toward the
field-oxideISi interface [Figure 2-38(b)]. Because
the field-oxide layers are much thicker than the
gate-oxide layers, the field magnitudes are much
lower (-lo5 Vlcm, rather than lo6 Vlcm) in the
field-oxide regions; however, the basic processes
leading to the buildup are the same. Furthermore,
the charge-generation volumes are considerably
larger.
The schematic diagrams shown in Figure 2-38
do not accurately reflect the MOS structures of
present-day technology, but the basic principle of
the induced leakage current is nevertheless valid.
Figure 2-39 shows a cross section of a more
modern recessed field-oxide MOS structure. The
leakage paths between source and drain in these
structures are thought to be in the Si substrate
under the so-called "bird's beak" region of the
recessed field oxide, which is immediately adja-
cent to the gate-oxide channel region.
/ THIN GATE OXIDE Nw
k\ \ \ \ \ F n+ DRAIN G\\\\P
(a) Top View: Radiation-Induced Current Leakage
Path due to Positive Charge Buildup
- -
/ GATE METAL
GATE OXIDE
NORMAL CHANNEL REGION^ '---%-------
INVERSION LAYER
(+ BIAS)
p-SILICON
\- - - - - - - - -
(b) Cross Section: Field-Oxide/Substrate Interface
Figure 2-38. Schematic of MOS device structure
(McLean and Oldham, 1987).
POLYSlLlCON
RECESSED
GATE
- BIRD'S BEAK 1 OXIDE
"NORMAL" REGION
FIELD-OXIDE CHANNEL
REGION
\
REGION POSITIVE TRAPPED-
CHARGE INDUCED
CURRENT LEAKAGE PATH
Figure 2-39. Modem, recessed field-oxide MOS struc-
ture indicating charge buildup and induced current leak-
age paths i n the bird's beak regions of the device
(McLean and Oldham, 1987).
Typically, the induced leakage currents under
field oxides are studied with the aid of special test
field-oxide transistors, in which the field-oxide
material is used as a gate oxide in a normal MOS
transistor configuration. Some post-irradiation sub-
threshold leakage current measurements are shown
in Figure 2-40 for a device with a channel length
of 1.0 pm and a channel width of 50 pm. Results
are shown after each of a series of 10-krad(Si02)
LINAC pulses. Increases in leakage currents by at
least several orders of magnitude are obtained. As
GATE VOLTAGE (volts)
Figure 2-40. Radiation-induced increase i n subthresh-
old leakage currents i n n-channel field-oxide transistor
test structure subjected to a series of 10-krad(Si02)
pulses; VDD = 5 volts (Boesch, n.d.).
channel length is reduced, the fringing fields in the
field region between source and drain in an actual
device configuration increase, which results in in-
creased leakage currents.
As shown in Figure 2-38, the ionizing radiation
dose hardness of the MOSFET is limited by the n-
transistor leakage due to the positive charge accu-
mulation in the field oxide. A method to mitigate
this radiation-induced leakage path is shown in
Figure 2-41, where boron has been implanted un-
der the bird's beak region to prevent inversion; i.e.,
p-type material becomes n-type due to positive
charge accumulation, and the source-to-drain leak-
age path is cut off. The use of a boron (p-type)
implant is used in a variety of ways to supress ra-
diation- induced leakage.
Finally, insulating substrate technologies such as
SOS and SO1 suffer from so-called radiation-in-
duced back-channel leakage. Figure 2-42 shows a
simple schematic of an SOS structure [it could
well be an SO1 structure], indicating radiation-in-
duced positive charge buildup in the sapphire sub-
strate immediately under the active p-Si layer. The
normal device channel occurs in the p-Si region
next to the gate-oxide region. However, because of
the positive charging of the sapphire substrate, an
inversion layer can be induced on the back side of
the p-Si region, resulting in back-channel leakage
between source and drain. Figure 2-43 depicts the
three components of an I-V curve for a mesa-type
MOSFET structure used for SOS and many SO1
designs. The normal I-V response of the
p+ DRAIN
SOURCE
FIELD IMPLANT
RS SIDE WELL
Figure 2-41. Cross section of hardened transistor demonstrating radiation-induced leakage path mitigation via boron
implantation.
NORMAL GATE
CHANNEL REGION
? "0s POLY-si
INDUCED BACK- \
CHANNEL LEAKAGE
TRAPPED POSITIVE
PATH
CHARGE
SAPPHIRE
Figure 2-42. Schematic diagram illustrating back-chan-
nel current leakage in silicon-on-sapphire MOS transis-
tor (McLean and Oldham, 1987).
MOSFETs is shown by the top transistor curve on
the figure. [The effects of radiation on this compo-
nent of the I-V response were discussed in Subsec-
tion 2.4.1 .] However, two other radiation-induced
BODY TIE
9 ""i
leakage paths and their effect on the I-V response
are also shown in Figure 2-43. The back-channel
leakage component has been discussed previously
and is shown explicitly here. This component does
not, in general, change the overall shape of the I-V
response curve. However, the "floor" of the re-
sponse is translated upward, i.e., the minimum
value of leakage current will be higher after irra-
diation. The primary difference between the insu-
lating substrate and bulk MOSFET configurations
is the leakage current path identified as the side-
wall transistor. This path is extremely complex and
can be delineated into top, intermediate, and bot-
tom or lower-edge side wall. This delineation is
important since somewhat different radiation-hard-
ening methods must be employed to mitigate each
of these components. The most difficult of these
three leakage paths to resolve has been the bottom
or lower-edge side-wall component, which results
from an interaction between the back channel and
TOP
TRANSISTOR
SIDE-WALL
TRANSISTOR
v
BACK
CHANNEL
COMPOSITE
Figure 2-43. I-V curve components for an SO1 transistor.
the lower edge, i.e., charge sharing (Schrankler et
al., 1985). Hence, charge accumulation at the back
channel will impact the hardness of the lower-edge
parasitic transistor.
Also, the ability to "dope" the edge (with boron
for example) to prevent inversion can be compro-
mised by material defects along the edge-substrate
boundary that are caused by normal semiconductor
processing, e.g., mesa formation by reactive ion
etching. One method successfully employed for
SO1 MOSFETs to eliminate bottom side-wall leak-
age is to provide source-to-body ties on either side
of the source [see Figure 2-43]. This is accom-
plished by use of a boron p-plug that contacts the
buried layer. These ties are also required to elirni-
nate floating-body effects (kinks) in SO1
MOSFETs and improve transient upset hardness. It
should be noted that this body-tie-to-source con-
figuration is not employed in SOS technology.
These effects are discussed in Chapter 3. In addi-
tion, the use of body ties is limited to MOSFETs,
where the source and drain regions are defined.
Thus, for pass-gate MOSFETs, which are bidirec-
tional in that a signal can be transmitted from ei-
ther end, source-to-body ties [shown in Figure
2-43] cannot be used and other radiation-hardening
solutions must be employed. It is beyond the scope
of this chapter to provide a complete discourse on
the various methods used to obtain ionizing radia-
tion dose hardness, but abbreviated information is
provided here to indicate the scope and magnitude
of this problem.
2.4.4 Gate-Oxide Radiation-Hardening
Methods
Traditionally, gate-oxide radiation hardening,
manifested as a reduction in the radiation-induced
threshold voltage shift, is obtained by various pro-
cessing methods, which include:
Modifications to the gate-oxide process,
such as controlling the amount of hy-
drogen in the ambient atmosphere, pro-
cessing at temperatures below 900C,
use of specific chemical contaminants
to provide recombination centers, and
strict controls on process cleanliness
* Limiting post-gate process temperatures
and eliminating other steps that could
damage the gate oxide, e.g., post-gate
fabrication channel implantation.
In addition, the current trend toward thinner gate
oxides has also aided the hardening of gate oxides.
Moreover, as gate-oxide thickness to, approaches
the range of 150A or less, it is anticipated that the
primary concern in this area will be gate-oxide in-
tegrity and long-term reliability instead of radia-
tion hardness. The following discussion expands
on the effects of scaling on the radiation-induced
response of gate oxides. Several benefits are
gained when the gate-oxide layer is thinned. First,
the initial shifts (AVT) are reduced according to
t and the long-term hole trapping No, scales
accordingly in the linear regime. Second, the short-
term recovery time (hole transit time) decreases as
- t:, . Third, the recovery time is further decreased
if the gate potential is held constant as the gate-
oxide thickness is reduced, resulting in a larger
oxide field (Eox - VG/to,). The combined effect of
all three factors is dramatically illustrated by the
flatband voltage recovery data shown in Figure
2-44 for t hee thicknesses of as-grown oxide (37.6,
56.6, and 96.3 nm) exposed at 220K to pulsed
LINAC irradiation under constant 10-volt applied
gate bias. The vertical slash masks indicate the 75-
TIME AFTER PULSE (seconds)
Figure 2-44. Flatband voltage recovery data at 220K
for three as-grown oxide MOS capacitor thicknesses un-
der constant 10-volt applied gate bias [vertical bars indi-
cate 75 percent recovery point] (Boesch et al., 1978).
percent recovery point in each case. (These data
are not normalized, so that the t2 reduction in the
initial flatband voltage is also included). Under
these conditions, thinning the oxide by a factor of
-2.5 leads to more than an order-of-magnitude re-
duction in the shifts for the entire time regime of
the measurements.
Considering the effect on long-term deep hole
trapping, first of all, AVO, obviously scales in the
same manner (-&) as the initial shift. Next, if
gate bias is constant, then the fraction of hole trap-
ping decreases as E;:'~ for fields above 1 MVIcm;
furthermore, the long-term annealing rate is some-
what enhanced with increasing field. But consider
the scaling of to, down to and below 10 nm. For
temperatures below - 150C, the tunneling of elec-
trons from the Si substrate into the Si02 (where
they recombine with the trapped holes) seems to be
the process responsible for the long-term annealing
of the oxide positive trapped charge. Referring to
Figure 2-45, the time-dependent tunneling distance
Xm(t) associated with the tunnel annealing process
lies in the range from 2 to 4 nm for practical times
of interest - say from to lo1 seconds. Hence,
for oxides with to, < 10 nm, enhanced hole re-
moval can be expected to occur by electrons tun-
neling into the oxide from the gate electrode as
well. In fact, the tunneling parameters would be
roughly the same for polysilicon-gate material as
for the Si substrate. This possibility of enhanced
Figure 2-45. Model schematic of trapped hole removal
in thin gate-oxide MOS structures by electron tunneling
from both Si substrate and poly-Si gate (Benedetto and
Boesch, 1986).
POLY-Si
GATE
recovery by trapped hole recombination with tun-
neling electrons from both electrodes is indicated
schematically in Figure 2-45.
It is quite clear from this discussion that very
significant gains can be made in the radiation per-
formance of MOSFET devices by thinning the
gate-oxide layers. Unfortunately, as circuit integra-
I
t
I
I sio2 , b
I + +I
I
1 + 1
+I
e - d + + -
I
I+ +I
1 + 1
I + +I
I
1 + I
I + +I
1 + 1
tion density increases the gains realized in gate
si
e-
oxide radiation response must be tempered against
increased issues with isolation density. This will
require the development of new processing and de-
sign technology to mitigate these radiation induced
failure modes, e.g., source-to-drain leakage along
side walls, back channels, etc.
2.4.5 Ionizing Radiation Dose Effects on
MOSFET Mobility
In general, effective MOSFET channel mobility
tends to decrease with increasing radiation dose,
OXIDE THICKNESS, to, (nm)
103 - I
Figure 2-46. Threshold and flatband voltage shifts per
Mrad(Si02) at 80K (Boesch and McGarrity, 1976;
Benedetto et al., 1985; Saks, Anacona, and Modolo,
1984).
- k
- - CAPACITOR AVfb DATA
-
(Eox = +2.0 MVIcrn)
-
--
102 =..
MOSFET AVT DATA
-
- (Eox = +1.0 MVIcrn)
-
h
" 101
- ...............
E
-
'0
-
e
-
2 - -
e loo - - -
...............
I
rn
- -
W
- -
(3
u - -
/
5 lV1 .. .../.. .
= /
/
-/
-
-
Plummer (1980), Galloway, Gaitan, and Russell
(1984), and Galloway, Wilson, and Witte (1985), it
was shown by Sexton and Schwank (1985) that
mobility degradation can be fitted (over a wide
range of experimental conditions) by the empirical
relationship:
(2.1 1)
where po is the pse-irradiation value and a = (8 f.
2) x crn2. Mobility degradation, measured
TIME AFTER PULSE (seconds)
following irradiations of both n- and p-channel
transistors under all bias conditions, is plotted in
Figure 2-47. Recovery of threshold voltage shift and
transconductance change following pulsed e-beam irra-
Figure 2-48. From first principles, radiation-in-
diation at 77K for a M Q S ~ T with a 5.3-nm gate oxide
duced decreases in mobility lead to reductions in
(Benedesto et al., 1985). subthreshold slope, transconductance, transistor
drive, circuit speed, etc. The effect of a reduction
which causes a decrease in current drive capability.
in mobility, as previously stated, is to reduce the
Initial work in this area suggested that reductions
current drive capability (for a given VG - VT) Of a
in mobility were due to increased lattice and Cou-
transistor. This can be seen from:
lomb scattering by charged interface traps and that
the average surface mobility was proportional to
Wk'
INit. Following the earlier work of Sun and
1 - -[2(vG - v7)vD - v:]
- Leff 9 (2.12)
Figure 2-48. Normalized effective channel mobility as a function of radiation-induced interface trap density (Sexton and
Schwank, 1985).
where:
W = channel width
k' = (ueffCo,)/2
Leff = effective channel length
VG = gate voltage
VR = threshold voltage
VD = drain voltage.
This effect is shown in Figure 2-49.
VG - VT (volts)
Figure 2-49. Ionizing radiation dose degradation of the
parameter k' as a function of voltage for n- and p-chan-
nel transistors (Ports, 1980).
2.4.6 Other MOSFET Ionizing Radiation
Dose Effects
Another consequence of interface trap buildup
with irradiation is that the surface recombination
velocity increases (Sivo, Hughes, and King, 1972;
Snow, Grove, and Fitzgerald, 1967; Zaininger
and Holmes-Siedle, 1967), leading to larger sur-
face generation currents where junction edges are
passivated by oxides; this effect is illustrated in
Figure 2-50. Thus, junction leakage currents will
tend to increase with radiation dose.
A second-order effect of radiation on transistor
response occurs in the area of hot-carrier degrada-
tion. It has been shown that radiation increases the
number of electron traps in an oxide. Trapped
holes also exist after irradiation and it has been
suggested that the recombination of electrons with
previously trapped holes can lead to interface
traps. Thus, it might be expected that after irradia-
tion the hot-carrier response of MOS devices
might be significantly worse than before irradia-
tion, since a larger percentage of the electrons in-
jected into the oxide as hot carriers might be
trapped; also, interface traps might be more easily
created. In support of this conjecture, larger posi-
tive threshold voltage shifts with hot-carrier stress
have been reported for irradiated devices compared
to virgin devices. Transistors with lightly doped
drains to minimize hot-carrier effects were also
shown to be degraded more by hot-carrier stress
after irradiation than before. For devices that had
been fabricated to be radiation-hard, the effect of
irradiation on hot-carrier sensitivity was much
smaller. In another study of radiation-hardened de-
vices, the maximum linear transconductance deg-
radation under hot-carrier stress was shown not to
have been changed by previous irradiation. It then
appears that by proper processing techniques the
impact on subsequent hot-carrier degradation can
be minimized.
IONIZING RADIATION DOSE (rads[Si])
Figure 2-50. Surface recombination velocity of a de-
pleted surface as a function of ionizing radiation dose
[prerad value of S = 5 cmlsec] (Snow, Grove, and
Fitzgerald, 1967).
2.5 Metal-Oxide-Se~conductm Integrated
Circuit Ionizing Radiation Dose Response
In theory, the response of an IC to ionizing ra-
diation dose should be predictable from a knowl-
edge of individual transistor response. This section
will build on the discussions of Subsections 2.3.3
and 2.3.4, which address the radiation response of
individual bipolar and MOS transistors. In prac-
tice, making a quantitative estimate of the response
of a complex IC is a formidable task because the
transistors that comprise it can be biased at various
potentials. The shifts in the transistor parameters
depend on the applied bias (both pre- and post-
irradiation) and the radiation dose rate, and the cir-
cuit response depends on these various cornbina-
tions. Thus, in lieu of attempting to predict (or
simulate) the complete I&: response, critical param-
eters or timing paths will be identified and sirnu-
latedltested for worst-case conditions (Bhuva,
Paulos, and Diehl, 1986).
The circuit parameters that are altered by ioniz-
ing radiation dose include power-supply currents,
signal propagation times, input and output voltage
levels, current drive capability, minimum and
maximum functional frequencies, minimum
power-supply voltage, and noise margin.
In addition, ionizing radiation dose can make
circuits more susceptible to failure or further deg-
radation caused by other environments, e.g., tem-
perature, single-event upset, and transient radiation
upset. Subsequent sections of this chapter will pro-
vide examples and further discussion of the effects
of ionizing radiation dose on the above-noted
circuit parameters.
2.5.1 Po+ver-Supply Current
The power-supply current IDD when a CMOS
circuit is in standby mode is an important param-
eter of interest for many systems. IDD increases
markedly as the leakage current of individual
transistors increases. In particular, the leakage
current of an n-channel transistor will increase
as its threshold voltage tends tovrrard depletion
mode with radiation, as shown in Figure 2-5 1.
An increas~, in leakage current when the transistor
gate voltage is zero (and thus the transistor is OFF)
translates directly into the static power-supply
current IDD as shown in Figure 2-52. Leakage
current tends to decrease with time after irradiation
as the n-channel threshold voltage increases. Leak-
age current also depends on the dose rate at which
the radiation is received (since the negative n-chan-
nel threshold voltage shift is less at lower dose
rates), as illustrated in Figure 2-53 for a I-kbit
S R M. Other leakage currents (such as those from
field-oxide regions) may in some circumstances
also contribute to the overall circuit leakage. In
addition to large changes in the standby current,
significant changes can also be observed in the op-
erating current of the part.
GATE SOURCE VOLTAGE, VGS (volts)
Figwe 2-51. n-channel transistor subthreshold current
characteristics; x indicates zero gate voltage intercept
(Sexton and Schwank, 1985).
As stated, the response of an IC to ionizing
radiation dose also depends on the state in which
the circuit is irradiated. An example of this depen-
dence is illustrated in Figure 2-54., which depicts
the results of a test scenario designed to produce
worst-case post-radiation power-supply leakage. In
this example, worst-case ledcage is engendered by
irradiating a memory with one stored pattern (a19
ones) and measuring the post-irradiation leakage
measured with its complement (all zeroes). During
irradiation, the n-channel transistors that are ON
DRAIN SOURCE CURRENT, IDS (amperes)
Figure 2-52. Integrated circuit standby power-supply
current correlated with zero gate voltage transistor inter-
cept [Figure 2-51] (Sexton and Schwank, 1985).
have a maximum threshold voltage shift. The "not"
pattern used for leakage current measurement will
then cause the transistors that were biased ON dur-
ing irradiation to be OFF so that subthreshold leak-
age (and parasitic field leakage) will be measured.
a 2 t i COMPLEMENT i
C ' -I
G'
z
W
a
a
2
lo;
n
5
U)
DOSE (rads[Si])
-
- - -
=... . . . . . . . . . . . . . . . . . .;. . . . . . . . . . . . . . . . . . . . . . . . .i. . . . . . . . , . . . . . . . . . . , --
-
6 1
i ALLZEROES
4:
Figure 2-54. Standby power-supply current for a 16-kbit
CMOS SRAM as a function of ionizing radiation dose
for a test pattern that is the complement of that stored
during irradiation; a noncomplemented pattern (all ze-
roes) is shown for comparison (Passow et al., 1986).
One final subject in this area is the effect of dose
rate on ionizing radiation dose. This effect occurs
because ( I ) at low dose rates, rebound, or recovery
(gate-oxide positive charge annealing and interface
state growth) occurs, causing circuit failures due to
mobility-related issues (e.g., timing); (2) as the
-
-
@ DOSE RATE = 5,000 rads(Si)/min =
@ DOSE RATE = 850 rads(Si)/min 1
DOSE RATE = 300 rads(Si)/min
-
-
-
-
-
-
-
-
IONIZING RADIATION DOSE (krads[Si])
Figure 2-53. Standby power-supply current for a 1-kbit CMOS SRAM as a function of ionizing radiation dose
(Abare, Huffman, and Moffett, 1982).
dose rate increases, the recovery is less complete
and oxide trapped charge partially compensates the
interface state (positive shift); and (3) as the dose
rate continues to increase, the oxide trapped charge
dominates and current-leakage-type failures result.
This composite effect is depicted in Figure 2-55.
700
I I l l l l l l l I I1111111 I I1111fl
10-2 10-1 1 00 10' I 02 I o3
DOSE RATE (radsbsiysec)
Figure 2-55. Ionizing radiation dose to cause failure for a
Sandia SA3001 2-kbit CMOS S U M as a function of
dose rate. [Solid lines indicate the dose at each dose rate
that will cause the indicated change in power-supply cur-
rent (IDD) or read access time (tRD) Dashed line indicates
the ionizing radiation dose at which the circuit will un-
dergo a change of 1 mA in leakage current or a 6-nsec
increase in read access time.] (Winokur et al., 1986).
2.5.2 Circuit Timing Parameters
As discussed in Subsection 2.4.5, the effective
transistor channel mobility decreases with
increasing ionizing radiation dose. This effect, in
conjunction with threshold voltage changes, im-
pacts the time it takes to propagate a signal through
a circuit.
The effect of radiation on the speed of CMOS
integrated circuits can depend on the details of cir-
cuit fabrication, i.e., the various processes used in
circuit manufacture. For fabrication processes that
result in very little mobility degradation with radia-
tion, the negative threshold voltage shift of the n-
channel transistor can actually lead to improved
performance in some parameters for some radia-
tion dose levels. An example of this type of re-
sponse for the read access time of a 16-kbit SRAIM
is shown in Figure 2-56. Over the dose range mea-
sured, the access time improves with radiation at
all dose levels. (However, other parameters, such
as power-supply leakage current, may still be de-
graded with radiation.)
For processes that have a larger interface trap
buildup with irradiation, and thus more mobility
degradation, the speed of the circuits tends to de-
grade with radiation. An example of this type of
response for the read access time of another 16-
kbit SRAM is shown in Figure 2-57, where the ac-
cess time increases monotonically as the dose
increases and as the devices rebound following the
200-krad(Si) irradiation.
IONlZDNG RADIATION DOSE (rads[Si02])
Figure 2-56. Read access time for a 16-kbit CMOS
SRAM as a function of radiation dose for three power-
supply voltages (Passow et al., 1986).
PRERAD 3 x 104 105 2 x 105 REBOUND
IONIZING RADIATION DOSE (rads[Si])
Figure 2-57. Read access time for a 16-kbit CMOS
SRAM as a function of radiation dose and after rebound
(a post-irradiation biased anneal) (Jones, n.d.).
Another response observed is intermediate be-
tween those shown in Figures 2-56 and 2-57, viz.,
the access time might improve at low ionizing ra-
diation doses but be degraded at high ionizing ra-
IONIZING RADIATION DOSE (krads[Si])
Figure 2-58. Normalized read access time for a Ckbit
CMOS SRAM as a function of radiation dose
(Gingerich et al., 1984).
diation doses. This is shown for measurements
made soon after the completion of an irradiation in
Figure 2-58.
The elapsed time from completion of irradiation
to measurement of circuit parameters may affect
measured response, as illustrated in Figure 2-58. If
measurements are made many hours after the
completion of the irradiation, the access time may
degrade monotonically with radiation dose. The
degradation observed for a particular ionizing ra-
diation dose may depend on the dose rate of the
radiation, as illustrated in Figure 2-59 for a 2-kbit
SRAM. Here, the increase in read time is greater
for radiation at the lower dose rate. Other RAM
timing parameters, such as minimum write pulse
width, generally show trends similar to the read
access time for all of the above circumstances.
These differing characteristics in timing re-
sponse can be due to differences in the way in
which the circuits were biased during irradiation,
in the manner in which the circuits were fabri-
cated, in the time between completion of the radia-
tion and testing of the circuit, and in the radiation
dose rate. However, they can be understood
in terms of the differing individual transistor
responses that occur as a function of dose, time,
and dose rate, as discussed in previous sections.
Logic circuits may also show significant perfor-
mance degradation with radiation. The maximum
functional frequency for an 8-bit microprocessor as
a function of radiation and rebound for two differ-
ent processes is shown in Figure 2-60. Note that
during the rebound test one of the microprocessors
failed after a 50-hour anneal, indicating the impor-
tance of this type of testing for simulating space
environments.
2.5.3 Input and Output Voltage and Current
Parameters
Input voltage switching points (such as VIL and
VIH) also change during irradiation, as would be ex-
pected since these parameters are closely linked to the
threshold voltages of the transistors in the input stage.
An example of the changes observed in input circuits
for both CMOS and TTL input levels during irradia-
tion and during a subsequent unbiased room-tempera-
ture anneal is provided in Figure 2-6 1. In this ex-
ample, the switching levels decrease with radiation
Figure 2-59. Change in read access time for a Zkbit
CMOS SRAM as a function of dose for two dose rates
(Winokur et al., 1986).
TIME (hours)
IONIZING RADIATION DOSE (rads[Si])
Figure 2-60. Maximum functional frequency for a microprocessor as a function of dose and anneal time for parts fabricated
with two different processes (Sexton, n.d.).
3.0
2.6
-
In
C
-
0
>
y 2.2
W
>
!3
+ 1.8
3
n
z
1.4
1 .o
P R
IONIZING RADIATION DOSE (radsfSi]) POST RADIATION (hours)
Figure 2-61. Input voltage switching points for CMOS and TTL buffers as a function of dose and post-radiation unbiased
anneal at room temperature (Schroeder, Gingerich, and Bechtel, 198e).
Figure 2-62. n-channel output buffer current drive as a function of radiation dose and post-irradiation biased
anneal for parts fabricated with two different processes (Sexton, n.d.).
PRERAD lom1 1 o0 1 o1 1 o2
10.0
I 03
,
I I1111
9.0 -
i VDD = 9 volts -
...................... 8.0 - <.
z
E 7.0 -
-
Y
3
0 6.0 - ...................... ;.
-
G
since the n-channel threshold voltage changes; the
switching levels increase during the anneal as the
transistor threshold voltages recover toward their pre-
irradiation values. Output drive is directly linked to
the degradation in individual transistor performance
and thus shows similar response to that of a discrete
transistor. An example of the degradahon in nchannel
output drive for two different processes as a function
of radiation dose and rebound is shown in F i p 2-62.
Because of shifts in transistor threshold volt-
ages, the minimum power-supply voltage at which
circuits will operate (which must be greater than
the magnitude of the n- and p-channel threshold
voltages for a CMOS circuit) can change with ra-
diation, often increasing as the dose increases. An
example of this for a CMOSISOS static shift reg-
ister is given in Figure 2-63.
-
...........................
-
ANNEAL
125" C
b
....................................
-
z
q 5.0
K
3
4.0
3
a
5 3.0
0
2.0
1.0
0
2.5.4 Minimum and Maximum Frequency
Parameters
PRERAD *lo5 lo6 1 0 '
IONIZING RADIATION DOSE (rads[Si])
-
- ...................... i .......................... : ...........................
-
4 : IRRADIATION
..............................................................................
- 1
-
IIII
Dynamic circuits can experience an increase in
minimum functional frequency due to increased
transistor leakage, in addition to the normal de-
crease in maximum functional frequency. This ef-
fect for a CMOSISOS dynamic shift register is
n MAXIMUM
IONIZING RADIATION DOSE (rads[Si])
Figure 2-63. Maximum and minimum power-supply
voltages at 5 MHz for a 64-bit, clocked CMOSISOS
static shift register as a function of radiation dose
(Hatano and Doi, 1985).
illustrated in Figure 2-64. This effect is also ob-
served with commercial microprocessors (which
often contain dynamic nodes), causing them to be
more radiation-tolerant when operated at high
clock frequencies compared to low clock frequen-
cies. Similarly, the increase in leakage with radia-
tion leads to a decrease in hold time (or decrease in
required refresh period) for dynamic RAMS
(Myers, Danziger, and Soulanille, 1987; Sabnis,
Nelson, and Billig, 198 1).
IONIZING RADIATION DOSE (rads[Si])
Figure 2-64. Maximum and minimum functional fre-
quency at 5 volts for a clocked CMOSISOS dynamic
shift register with on-chip clock driver circuits as a func-
tion of radiation dose (Hatano and Doi, 1985).
2.5.5 Operating Margins Versus Ionizing
Radiation Dose
In general, ionizing radiation dose tends to re-
duce operating margins in an MOS integrated cir-
cuit. Circuits designed for radiation hardness must
account for more marked shifts, larger spreads, and
greater nonuniformities in device parameters than
those designed for operation in less severe environ-
ments. As an example of some of the factors in-
volved in these effects, a few of the considerations
pertaining to a static memory circuit will be dis-
cussed. The internal operating margins for sense
circuitry in memories tend to decrease with in-
creasing radiation dose. Figure 2-65 shows the
main factors that determine the internal operating
margins for the sense amplifier in a memory utiliz-
ing a CMOS memory cell with p-channel access
I THRESHOLD VOLTAGE I
1 05 106
IONIZING RADlATiOM DOSE (rads[Si])
Figure 2-45. Principal features determining internal op-
erating margins for a sense amplifier in a static memory
circuit (Haraszti, 1978).
transistors and illustrates the changes that can oc-
cur as the dose increases. Initially, the margin for
the sense amplifier to read a "1" is about 2 volts
(from 6 to 8 volts) and that for reading " 0 is about
1.7 volts (from 3.3 to 5 volts). Radiation-induced
leakage currents reduce the logic "1" level and
increase the logic "0" level in the cell by the
amounts shown. With p-channel access transistors,
the zero input to the sense circuitry is increased by
the p-channel threshold voltage ( ~1 . 9 volts pre-ir-
radiation), which gets larger in magnitude as dose
increases. Imbalances caused by offsets in the
sense amplifier, and nonsymmetrical leakages and
threshold voltages caused by the different shifts
with radiation of transistors biased differently, can
also serve to reduce the logic "1" level and in-
crease the logic "0" level as dose increases. Charge
transfer from the data and sense lines can cause
transient reductions in the logic margin and must
be considered for high-speed memory operation.
Variations in the precharge voltage from pro-
cess, temperature, and radiation shifts can also re-
duce the " 0 and "1" margins. For this example,
these various factors all combine to reduce the
margin of the sense amplifier to reading the logic
states "1" or "0" to almost zero at lo6 rads(Si); at
this point, the sense amplifier will cease to be able
to read the memory-cell contents correctly. This
example assumed that both circuit- and process-
hardening techniques were employed; with
unhardened circuit design, the sense amplifier
would be expected to fail from reduced operating
margin at less than 20 krads(Si) (Haraszti, 1978).
In addition to these effects on the sense amplifier
circuitry, the fact that the transistors within the
memory cell itself are biased differently during ir-
radiation can lead to imbalances and preferred
states from the memory cell. These internal imbal-
ances cause the cell to be more vulnerable to upset
by certain signals generated during the normal op-
eration of the memory, which can lead to "read dis-
turb" errors or other failure modes (Fleetwood et
al., 1986; Fleetwood and Dressendorfer, 1987).
The general reduction in operating margins
caused by irradiation of integrated circuits means
that the noise margins are reduced, thereby making
the circuits more susceptible to noise spikes caused
by internal circuit operation or sources external to
the integrated circuit.
2.5.6 Summary
As can be seen from the various examples pro-
vided in this section, the effect of ionizing radia-
tion dose on MOS technology microelectronic
devices is a relatively complex interaction of the
irradiation level, dose rate, static and dynamic con-
ditions of the circuit (both during and after irradia-
tion), temperature, device processing, etc. In
addition, a number of device parameters (e.g . ,
leakage current, operating speed, input and output
characteristics, etc.) must be considered separately
to ascertain the effects of the irradiation on a spe-
cific device.
Also, although a device may be subject to para-
metric failure (e.g., leakage current specification is
exceeded), functional failure may not occur until
significantly higher levels (order of magnitude) of
radiation are incurred. This fact exacerbates the
problems associated with the determination of the
level at which individual circuits cause system fail-
ure and must be addressed by the system designer.
As an indication of the complexity of the inter-
action of ionizing radiation dose with rnicroelec-
tronic devices, the effect of dose rate on failure
levels is shown in Figure 2-66. The basic explana-
tion for this effect is:
1. At low dose rates ( ~10- I radlsec), the
generation of interface state and anneal-
ing of trapped charge in the gate oxide
dominate device response.
2. At mid-range dose rates (10-I to lo0
radsec), gate-oxide trapped charge and
interface state generation (negative
charge) compensate.
3. At high dose rates (>lo0 radsec), gate-
oxide trapped-charge-induced failure
modes dominate.
Three general classes of devices are generally
encountered during the development of a system.
These are: (1) radiation-hardened devices (e.g.,
space system applications), where trapped charge
is generally the most significant problem and little
interface state generation occurs; (2) radiation-re-
sistant devices (not specifically fabricated for
radiation robustness, but capable of operating at
levels between 20 and 100 krads), where both
charge trapping and interface state generation oc-
cur, but where charge trapping dominates (super-
recovery is not generally expected); and (3) soft or
commercial circuits capable of operation below 20
krads, where significant charge trapping and inter-
face state generation should be anticipated in a ra-
diation environment of 10 to 20 krads.
2.6 Ionizing Radiation Dose Effects on
Biplar Transistors
Prior to the introduction of MOSFETs, bipolar
semiconductors were the dominant solid-state
technology. Thus, this type of device is widely
used in all types of military systems. However,
since the introduction of CMOS technology a dra-
matic shift away from the use of bipolar integrated
circuits has occurred. This shift can be attributed to
the fact that CMOS devices require less power and
can provide higher levels of integration density
than bipolar devices.
Despite the attributes of CMOS technology, bi-
polar ICs are still used to some degree in almost all
systems due to the face that bipolar devices are ca-
pable of operating at higher speeds and can pro-
vide larger current drive than MOS technology de-
vices. Also, bipolar devices are more suitable for
implementing precision linear functions. In addi-
tion, the recent development of BICMOS, a class
of integrated circuits that combines both bipolar
and CMOS technology in a single circuit, permits
the simultaneous optimization of both operating
speed and power consumption. BICMOS technol-
ogy has served to further perpetuate the life of bi-
polar technology through a number of new
applications, e.g., very-high-speed cache memory,
analog-to-digital converters, etc. Thus, despite the
transcendence of CMOS technology for digital ap-
plications, the continuing use of bipolar technol-
ogy for military applications is still of concern to
designers. The effects of radiation on bipolar semi-
conductor devices are addressed here.
In general, ionizing radiation dose will affect
bipolar devices in two ways: (1) reduction in cur-
rent gain (p or hm), and (2) increased leakage cur-
rents. In addition, at extremely high levels of
ionizing radiation (e.g., >>1 Mrad[Si]) bulk dis-
placement damage (electron-induced atomic dis-
placements) can occur. Electron displacement is
similar to neutron displacement; since the effects
of neutron irradiation are discussed in Chapter 4,
no further discussion is provided here for bulk dis-
placement damage.
DATA DISCONTINUITY -
FAILURE CRITERION:
FAILURE DUE
10-3 10- lo0 lo1 l o2 1103 104 105
IONIZBNG RAQlATiON DOSE RAPE (rads[SiYss;"c)
Figure 2-66. Dependence of circuit ionizing radiation dose failure level on dose rate (Johnston, 1984).
2.6.1 Current Gain Degradation
Basically, there are two distinct types of bipolar
transistors. The first type of transistor is manufac-
tured with a crystalline emitter in a planar structure
[Figure 2-67]. However, advances in bipolar tech-
nology have led to the introduction of polysilicon
(poly-Si) emitter devices [Figure 2-68], which
have improved packing density and faster switch-
ing speed than the crystalline emitter transistors.
From these cross-section sketches, it can be seen
that the physical structure of the two types of tran-
sistors differ significantly, resulting in differences
in their response to radiation. Although a detailed
explanation of bipolar transistor operation is be-
yond the scope of this handbook, a variety of text
books on this subject are available (e.g., Burger
and Donovan, 1968; Messenger and Ash, 1986).
Ionizing radiation gain degradation in bipolar
transistors has been studied extensively for crystal-
line emitter transistors (Gauthier and Nichols,
1983; Johnston and Plaag, 1987). Gain degradation
has been determined to be the result of an increase
in base current IB due to (1) an increase in the sur-
face recombination velocity caused by interface
traps in the insulating oxide where the base and
emitter-base depletion regions reach the surface,
and (2) spreading of the field-induced depletion
layer in the base region caused by oxide trapped
charge. The oxide used to isolate the base and
emitter contacts (called a spacer oxide in
polysilicon transistors) is susceptible to the buildup
of oxide trapped charge and interface states (Hart
et al., 1978). Moreover, interface states can de-
EMITTER BASE
COLLECTOR n+
Figure 2-67. Crystalline emitter transistor cross section (Enlow et al., 1991).
h\\\\\\\\\\\\
n+
p+ W- n
COLLECTOR n+
Figure 2-68. Polysilicon emitter transistor cross section (Enlow et al., 1991).
grade the current gain b by increasing the surface
recombination velocity S in both the base and
emitter-base junction regions. The effect on bipolar
transistor gain due to increased surface recombina-
tion velocity can be understood from Equation
2.13, which indicates that as S increases, P
decreases
where S and p are as defined above and
not present in polysilicon emitter transistors since
the heavily doped extrinsic base region layer [p+-
region shown in Figure 2-68] prevents any signifi-
cant spread in the field-induced depletion layer
(which can result from the trapped-charge buildup
in the oxide). In crystalline emitter transistors,
however, both effects are present due to the more
lightly doped base region, resulting in an improve-
ment in the performance of polysilicon emitter
devices over the crystalline devices, as shown
in Figure 2-69. ,Additionally, it has been noted
(Jenkins et al., 1991; Nowlin et al., 1991) that
As
- -
surface ~ecombination area
ionizing radiation dose causes an increase in
W
-
- base width the base current. This is consistent with the
-
DB - base doping
-
A, - emitter area
GB
-
- base conductivity
GE
-
- emitter conductivity
LE
-
- emitter diffusion length
LB
-
- base diffusion length.
In addition, oxide trapped charge can deplete the
lightly doped base regions near the oxide, increas-
ing Shockley-Hall recombination. This trapped
charge can eventually lead to conduction between
the collector and emitter with no base drive. The
base current can be depicted as:
where
Is
-
- saturation current
b F
-
- preirradiation forward gain
-
v~~ - collector emitter voltage
VB
-
- base voltage
Iss
-
- surface saturation current
-
NSS - ideality factor for surface
recombination.
Radiation-induced degradation of polysilicon
premise that nonideal base currents are primarily
due to increased recombination at the emitter
periphery due to interface state density buildup in
the surface oxide, leading to the observation that
initially the base current is approximately in the
ratio of emitter areas, and as the dose increases
(where interface state density becomes significant)
this ratio approaches that of the emitter permitters.
This is shown in Figure 2-70 for two different
polysilicon emitter transistors. Thus, gain degrada-
tion due to ionizing radiation will not only be a
function of the spacer oxide process but also of the
device geometry. Additionally, recent work
(Nowlin et al., 1991) has indicated that a dose-rate
CRYSTALLINE EMITTER,
emitter transistors is also the result of an increase COLLECTOR CURRENT, lr: (amperes)
-
in interface traps in the oxide over the surface
Figure 2-69. Gain degradation after exposure to an ion-
emitter-base junction. However, the depletion layer
izing radiation dose of 250 krads(bi) (Nowlin ol.,
spreading found in crystalline emitter devices is
1991).
effect may be present wherein a more significant
ionizing radiation gain degradation is experienced
- .......... A ~ I A ~ =2.5 at lower dose rates [see Figure 2-71]. This effect
will impact radiation test strategies to ascertain
worst-case device performance.
2.6.2 Radiation-Induced Leakage Currents
P$P1 = 1.4
Ionizing radiation dose affects leakage current in
bipolar transistors in two ways: (1) increased leak-
age between adjacent devices, and (2) increased
o 2 4 6i Ol 1 02 103 104 collector-to-emitter leakage. The effects of ioniz-
IONIZING RADIATION DOSE (krads[Si])
ing radiation dose on the generation of device and
device-to-device leakage currents are depicted in
Figure 2-70. Ratio of base currents for two PO~Y- S~
Figures 2-72 and 2-73. Figure 2-72 is a
emitter devices, illustrating that at low doses, base cur-
rents are approximately in the ratio of emitter areas (A),
cross section of a bipolar transistor that uses re-
and at higher doses, the ratio approaches that of the pe- cessed (RoX) which was
rimeters (P) (Nowlin et al., 1991).
10-1
I1111111 I 1 1 1 1 1 1 1 1 I 1 1 1 1 1 1 1 1 I I I I
-
1.1 raddsec i
P 10-2
a
10-3
10-2 10" 104 10-5 10-6
TlME (seconds)
10-3 1 04
TlME (seconds)
(a) 2- x 20-pm2 npn Poly-Si Emitter (Process 1) (b) 2- x 20-pm2 npn Poly-Si Emitter (Process 2)
L
-
- - 1 1 1 1 1 1 I 1 1 1 1 1 1 1 1 I 1 1 1 11111 I l l l Elf
-
- y = 70 krads(Si02) i -
1 VENDOR A
-
16 radslsec -
300 raddsec -
I11111111 I11111111 I 11111~~
TlME (seconds)
(c) 1 1 ym-Diameter pnp Crystalline Emitter
Figure 2-71. Change in 1IP as a function of dose rate [all data taken at room temperature; time measured from start of
irradiation] (Enlow et al., 1991).
INCREASED SIDE-WALL COLLECTOR-TO-EMITTER
CURRENTS CHANNELING ON
WALLED EMI T
n+-BURIED LAYER n+-BURIED LAYER
TO-BURIED-LAYER
CHANNELING
Figure 2-72. Regions of possible radiation-induced charge buildup and leakage currents in recessed-oxide, bipolar, walled
emitter device (Pease, Emily, and Boesch, 1985).
introduced in the early 1970s and has become the
most widely used isolation technique for both bi-
polar and MOS transistors, to obtain isolation be-
tween adjacent transistors. Figure 2-73 illustrates
the effects of radiation on leakage current for bipo-
lar transistors employing ROX technology.
The effects of ionizing radiation dose, i.e., hole
trapping in the field oxide and the subsequent gen-
eration of interface states, result in several types
of leakage current degradation in bipolar transis-
tors, as shown in Figure 2-72. These can be
grouped as (1) device-to-device leakage due to the
- .-
I 02 I 03 1 04 4 o5 10"
IONIZING WADBATPBN DOSE (rads[Si])
Figure 2-73. Effects of ionizing gamma dose on leakage
current for a typical bipolar transistor (Johnston, 1980).
inversion of the p+-layer located beneath the ROX,
or (2) leakage caused by the inversion of the base-
region p-surface that contacts the ROX side wall
due to trapped charge on the ROX surface. The
time-dependent response of these effects is some-
what similar to that experienced in MQSFETs
in that initially there is a buildup of charge, fol-
lowed by annealing, and a subsequent interface
state buildup, all of which are bias-, process-, and
temperature-dependent.
2.7 Ionizing Radiation Dose Effects on
Linear BipBar Integrated Circuits
Linear bipolar ICs are briefly addressed here,
separate from bipolar transistors [Section 2.61
because:
1. Currently, most linear IC applications are
achieved with bipolar technology. How-
ever, it should be noted that MOS and
BICMOS technology devices are becom-
ing more widely used for linear applica-
tions.
2, Linear applica.tion ICs have failure modes
distinctly different than digital IGs.
Bipolar linear ICs are sensitive to ionizing radia-
tion dose effects. The primary paa.meters of con-
cern are input bias current (Ib), input offset current
(IOS), input offset voltage (Vos), and open-loop
voltage gain (AVOL). However, for nonhardened
commercial ICs, parameter changes can begin to
occur at levels of around 10 krads(Si), as indicated
by an increase in bias current. In general, bias cur-
rent will increase before any changes in either in-
put offset current or voltage occur. Moreover, it is
usually changes in these two parameters, rather
than the open-loop gain or input bias current, that
actually cause IC failure.
A schematic diagram of an operational ampli-
fier connected as an inverting-mode amplifier
is shown in Figure 2-74. The output voltage equa-
tions as a function ofjnite [as opposed to injnite]
open-loop gain, input offset current, and input
offset voltage are provided. From these relation-
ships, the effect of ionizing radiation dose, which
lowers AWL and increases both Ios and Vos, can
be qualitatively deduced. Moreover, since AVOL
is generally large (>90 dB), the effects of changes
in Ios and Vos are usually more significant.
Figure 2-75 depicts the effects of ionizing radiation
dose on various IC parameters for an unhardened
device.
In conclusion:
At present, linear circuit applications
are predominantly implemented with
bipolar ICs. However, this trend is
changing, with both MOS and BICMOS
ICs accounting for a greater share of
these applications.
Bipolar linear application ICs fail in dif-
ferent ways than digital ICs, e.g.,
changes in Ios and Vos. However, fail-
ure modes common to both classes in-
clude increased input bias current and
open-loop voltage gain degradation.
In lieu of abrupt parametric failure
modes, which occur in digital applica-
tion ICs, analog circuits manifest para-
metric failures that can be application-
specific, making the establishment of
specific failure criteria difficult and thus
impacting the development of a radia-
tion hardness-assurance program.
(a) Effects of Finite Open-Loop Voltage Gain
AVOL =
(b) Effect of Input Offset Voltage
AVOL = 00
(c) Effect of input Offset Current
Figure 2-74. Effect of finite open-loop voltage gain, in-
put offset voltage, and input offset current on the perfor-
mance of an operational amplifier.
103 1 o4 1 o5 1 06 1 o3 1 o4 1 o5 106
IONIZING RADIATION DOSE (rads[Si]) IONIZING RADIATION DOSE (rads[Si])
103 1 o4 105 1 06 1 03 104 1 05 106
IONIZING RADIATION DOSE (rads[Si]) IONIZING RABlATlON DOSE (rads[Si])
Figure 2-75. Linear IC parameter variation with ionizing radiation dose (Rose, 1984).
2.8 Ionizing Radiation Dose Effects on devices is approximately lo7 to lo8 rads(GaAs).
Gallium Arsenide Each of the radiation susceptibility categories is
Gallium arsenide (GaAs) is a semiconducting
discussed here in more detail for GaAs, indicating
crystalline material similar to Si; therefore, it is
some of the primary radiation effects problems of
subject to the same basic ionizing radiation effects
concern (Zuleeg and Lehovec, 1980).
that occur in Si. However, some of the different
consequences of radiation effects on the electrical
characteristics of GaAs devices lead to qualita-
tively different radiation susceptibilities. The ioniz-
ing radiation dose hardness of GaAs devices is
generally very good because GaAs technologies do
P not employ gate oxides. Neutron effects (displace-
ment damage) are considerably smaller because
lifetime degradation is generally unimportant in
GaAs technologies [see Chapter 41. Thus, it can be
generally asserted that the ionizing radiation dose
hardness of GaAs circuits is superior to the Si-
based circuits. The ionizing radiation dose hard-
ness level for present-day, state-of-the-art GaAs
The insensitivity of GaAs to ionizing radiation
dose, at least for permanent effects, is due to:
( I ) the absence of gate insulators in GaAs devices,
and (2) the absence of parasitic current leakage
paths under field or passivation insulators (due to
the difficulty of inverting GaAs surface regions).
This latter factor is a result of very high interface-
state densities present (before irradiation) in all
GaAs insulator interfaces; effectively, the Fermi
level at an interface is pinned at a fixed constant
value by the high Nit density. For precisely this
reason, it has not been possible to fabricate high
quality GaAs metal-insulator-semiconductor (MIS)
devices. [It should also be noted with respect to the
first factor that Si JFET technology, which also
does not use gate oxides, also enjoys a higher
tolerance to total dose than other Si technologies.]
The high insensitivity of GaAs to ionizing radia-
tion dose is clearly illustrated in Figure 2-76,
which shows experimental results of drain source
current IDS versus gate voltage VG for an enhance-
-
0 0.2 0.4 0.6 0.8 1 .O
GATE VOLTAGE, VG (volts)
Figure 2-76. Effect of irradiation on the drain current-
gate voltage characteristic of epitaxial GaAs JFET;
channel region doping density, 10' ~l cm~ (Zuleeg and
Lehovec, 1980).
ment-mode GaAs JFET, before irradiation and
after exposure to an ionizing radiation dose of lo8
rads(GaAs). Before the irradiation, threshold volt-
age VT was 0.40 volt, and it did not change signifi-
cantly after irradiation.
Although GaAs devices are basically immune to
long-term ionizing radiation dose effects, a tran-
sient effect has been observed that is associated
with ionizing-radiation-induced charging of chro-
mium-doped semi-insulating (SI) GaAs substrates,
which are widely used in GaAs FET structures for
isolation purposes. This substrate charging causes
a reduction in the drain current IDS of the transis-
tor, with observed time constants as large as sec-
onds; its effect on IDS is depicted in Figure 2-77,
which shows IDS normalized to its pre-irradiation
0
0 10 20 30 40 50 60 70
TIME (seconds)
Figure 2-77. Pulsed radiation response characteristics at
various levels of drain current for a GaAs JFET (Simons
and King, 1979).
value plotted versus time following 100
rads(GaAs) of pulsed (3-nsec) 600-keV x-ray irra-
diation for a series of initial IDS values. These IDS
transients are characterized by peak reductions in
current amplitude ranging from 90 percent of the
quiescent current at 0.5 rnA to less than 5 percent
at the 10-mA level. The recovery-time constants
associated with these data range from 10 to 14
seconds.
A schematic model indicating the cause of the
transient reduction in IDS is shown in Figure 2-78.
A net negative charging of the semi-insulating (SI)
substrate is depicted, which induces a back-gate
depletion region in the p-GaAs epitaxial layer (n-
channel region) next to the interface with the sub-
strate. This induced depletion region then reduces,
BACK-GATE DEPLETION
SI GaAs
SUBSTRATE
Figure 2-78. Schematic cross section of gate region
GaAs JFET, indicating the effects of transient substrate
charging (Anderson, Simons, and Tseng, 1986).
or pinches, the electron current flow in the n-chan- require a source of power and a means of convert-
nel. The substrate charging was attributed (Ander- ing that power into a form that can be utilized by
son, Simons, and Tseng, 1986; Simons and King, the on-board electronic systems. Most earth-orbit
1979) to electron trapping in deep trap levels asso- satellites utilize large arrays of solar cells to con-
ciated with the chromium impurities. Based on the vert sunlight to electrical power. The power is then
time constants for the discharge of the traps (re- bused at high voltage (270 volts) to a preprocessor
covery of IDS), the energy level of the traps was that lowers the voltage to 28 volts and then on to a
determined to be -0.8 eV. The transient charging power supply that supplies regulated power to the
problem can be avoided by using carefully pre- on-board electronics, usually at f.5 volts or +I0
pared intrinsic SI GaAs substrates having low im- volts.
purity
(Zuleeg, N0t t hof f 9 and
The conversion of power from 28 volts to 5
Troeger, 1982) Or by the use of a conducting p-
volts, or any other voltage, is performed by a dc-dc
GaAs buffer layer Simons9 and Tseng3
converter. The two ways to supply regulated power
1986; Anderson er 1982) between the active
to spacecraft electronics are known as centralized
channel and SI substrate.
and distributed architectures. In a centralized archi-
2.9 Power Selmaiconductor Devices and
tecture [see Figure 2-79], 28-volt power is supplied
Integrated Circuits
to a single dc-dc converter, which then generates
This section addresses the effects of ionizing ra-
multiple outputs and buses the conditioned power
diation dose on power semiconductor devices and
to all the boards on the spacecraft.
integrated circuits." However, before proceeding A distributed architecture [Figure 2-80] buses
with a discussion of radiation effects in power the 28-volt power directly to each board, where an
semiconductor devices and ICs, several back- on-board dc-dc converter converts the power
ground subjects will be discussed to provide a con- according to the needs of that particular board.
text for understanding this class of ICs. Distributed power offers a number of significant
system advantages. Since all busing to the boards
2.9.1 Power Distribution
is at a relatively high voltage, power losses are
A spacecraft system is used as an example here;
very low, using only moderately sized wire. Any
however, this discussion can be generalized by
voltage losses that occur dunng busing are incon-
substituting an al t t ~nat e primary electrical Power
sequential since regulation occurs directly on the
source for the solar-cell array.
board. The delivered power is virtually free from
~ 1 1 spacecraft, and vi*ually any other complex
the noise and cross talk associated with busing
electromechanical system (e.g., tank, aircraft, etc.),
Power long wires. Each board is
BOARD #I
+1OV
OARD #3
+2
I - 0 BOARD #4
+5v
BOARD #5
-5v
Figure 2-79. Centralized power architecture (Desko, 1991).
*Tnis section is largely taken from Desko (1991).
dc-dc 1 0 BOARD # I
+1ov
4 B dc-dc 2
Figure 2-80. Distributed power architecture (Desko, 1991).
isolated from the fluctuating power demands of
other boards. Each local supply has control cir-
cuitry to protect itself and the load it powers.
A failure on one board can be isolated to protect
the rest of the system. For critical circuits, redun-
dancy can be provided. Since all power supplies
dissipate heat, a distributed architecture aids in
heat dissipation, which can be a critical factor in
space where convective cooling is absent.
0
+270V
6
A distributed power system also increases the
amount of monitoring and control possible. The
power conditions on each circuit board can be
monitored and individual circuit boards can be
shut down to conserve power when not in use. Sys-
tem design flexibility is greatly enhanced since
power needs are specified at the circuit-board
level, not the system level. Also, circuit-board per-
formance can be enhanced by selection of the op-
timum power supply for that particular board.
. .
.
dc-dc
dc-dc dc-dc
requires a high-performance dc-dc converter
architecture and high-performance silicon devices
and/or integrated circuits to obtain high power den-
sities.
PREPROCESSOR
-<) BOARD #5 -
-5v
2.9.2 Power Semiconductor Device and IC
Application
The objectives of the following discussion are to
(1) provide an understanding of dc-dc converter
operation, and (2) indicate the requirements placed
on semiconductor devices based on the converter
operation.
.
+28V
-
dc-dc
7 0 BOARD #4
-
The requirement is to convert dc voltage ob-
tained from the solar collectors, nuclear reactor, or
radioactive thermal generator (RTG), which is
preregulated to 28 volts, to regulated dc voltage (or
voltages) to power the on-board electronic equip-
ment. The system that delivers regulated dc voltage
is referred to as a power supply and is composed of
0 BOARD #3
+5V
-
- -
a dc-dc converter plus control circuitry. The dc-dc
It is apparent that the advantages of a distributed
converters used in many commercial applications
power architecture are significant, especially for
and in all space applications utilize an electrical
a 'pace system. These however, are
isolation transformer to fully isolate the load and
subject to some constraints' Each P ~ ~ ~ ~ - ~ ~ P P ~ Y
the source. However, the discussion will begin
module must fit on a circuit board and take up
with a simple dc-dc converter with no isolation.
minimal volume while supplying all the power
+5v
needs of the circuit board. 1; addition, the weight
In dc-dc converters or Power supplies, the dc
must be minimized; the weight of all the local
output voltage must be controlled within some
-
supplies should not be significantly greater than
specified limits, while the input voltage and output
the weight of the centralized dc-dc converter. The
load may fluctuate. This regulation of the output
local supply must indeed contain all the control
voltage is accomplished in a switch-mode Power
circuitry previously described to protect both itself
supply through the use of switches, as seen sche-
and its load as well as the rest of the system.
matically in Figure 2-81. Ideally, these switches
Finally, a distributed power architecture typically
are nondissipating and the efficiency of this
method of conversion is very high - 80 to 90
percent. A switch-mode converter works by open-
ing and closing the switches that supply voltage to
the output. By controlling the ON and OFF dura-
tions, the desired average output voltage can be
achieved, as seen in Figure 2-82. In this simple cir-
cuit, the average output voltage can be set any-
where from zero to VIN since the average output
voltage is given by:
(2.15)
-- ( ~ r n ) ( t O N )
'OUT =
to^ +
By using an L-C (inductor and capacitor) filter
network, this square-wave output can be converted
to a steady dc output of the desired value with the
desired amount of output ripple, as seen in Figure
2-83. Methods other than switch-mode, such as a
linear regulator, are available to obtain a regulated
Figure 2-81. Switch-mode power supply schematic
(Desko, 1991).
dc output. However, all other methods require the
use of dissipative components, which significantly
lower power-supply efficiency (by as much as 35
percent); and are unsuitable for space applications.
The most common method of controlling the
output voltage is switching at a constant frequency
and adjusting the ON duration of the switch (duty
7 . ...a -, .
Figure 2-82. Output voltage of a switch-mode power supply (Desko, 1991).
TIME, t
Figure 2-83. Output voltage of a switch-mode power supply using an L-C filter network (Desko, 1991).
cycle) to control the average dc output voltage, a
method known as pulse-width modulation (PWM)
switching. Other methods of control are possible
for switch-mode controllers that are also referred
to as PWM, such as switching at constant fre-
quency and adjusting the OFF duration. Fre-
quency-modulation (FM) switching is most
common for resonant converters. For zero-voltage-
switch resonant converters (where the voltage
square-wave output with frequency l/t is sent to
the switch. As the output varies from the desired
voltage, the duty cycle varies to bring the output
voltage back to the desired value. For a PWM sup-
ply, the switching frequency is typically a few ki-
lohertz to a few hundred kilohertz. The error
typically varies slowly with respect to the switch-
ing frequency, so excellent control of the output
voltage is maintained.
waveform crosses zero when the switch is turned
Thus, it can be seen that by valying the duty
ON), 'Onstant 'On-
cycle of a switch, any desired dc output voltage
trol is used.
value can be obtained and controlled. In order to
In a PWM converter, a control signal must be
generated to control the duty cycle of the switch in
order to obtain the desired value of output voltage.
This control signal is generated by amplifying the
difference between the actual dc output and the
desired dc output and comparing it with a repeti-
tive waveform such as a sawtooth. The block dia-
gram and control signal waveforms are shown in
Figures 2-84 and 2-85. The constant frequency,
obtain a constant value of output voltage, an L-C
filter network is used. No energy is dissipated in
these passive elements since the voltage and cur-
rent are always out of phase by 90 degrees; hence,
power-supply efficiency remains unchanged. Also,
a diode is added to provide a path for the inductor
when the switch is opened. The resulting circuit is
shown in Figure 2-86.
VERROR SWITCH
AMPLIFIER COMPARATOR CONTROL
SIGNAL
V~~~
(REFERENCE)
Figure 2-84. PWM control circuit block diagram (Desko, 1991).
OFF OFF OFF
v
I t I
ON I ON I ON I
Figure 2-85. Control circuit waveforms (Desko, 1991).
SWITCH
CONTROL
SIGNAL
d i
When the switch is ON, the diode becomes re- ON, the diode is reverse-biased, isolating the out-
verse-biased and the input supplies energy to the put stage. The input supplies energy to the induc-
load as well as the inductor. When the switch is tor. When the switch is OFF, the output stage
OFF, the inductor current flows through the diode, receives energy from the inductor as well as the in-
transferring some of its stored energy to the load. put. Once again, since the average voltage across
Thus, using the fact that in steady state the average the inductor in steady state is zero:
voltage across an inductor is zero:
(vIN ) ( t oN ) + (vIN - vow) (tom) = O
(2.20)
(' IN - VOUT) ( ~ON) = ( ~om) ( ~om) (2.16) or
= duty cycle .
Assuming no power loss in the circuit,
Assuming no power loss, i.e.,
('IN )('IN ) = ( ~ou- r ) ( ~oUT) I
(2. 22)
('IN ) (VIN! = ('OUT) (VOUT) I
(2. 18)
yielding
then
IOUT/IIN = 1 / duty cycle ,
(2.19)
Thus, for this circuit, the output voltage varies
directly with duty cycle while the output current
varies inversely with duty cycle.
The circuit configuration of switch, diode, and
passive elements is referred to as the circuit topol-
ogy. The topology shown in Figure 2-86 is known
as a buck, or step-down, converter. This topology
can only deliver an output voltage that is less than
the input voltage. This is one of the two basic con-
verter topologies used for dc-$6 converters. The
other basic converter topology is the boost, or step-
up, converter. All other topologies, and there are
many, are either combinations of, or variations on,
these two.
As its name implies, the step-up converter can
deliver an output voltage that is higher than the in-
put voltage [see Figure 2-87]. When the switch is
IOU* = I I N (1 - duty cycle) .
(2.23)
This topology boosts the voltage and lowers the
current.
The discussion thus far has focused on direct dc-
dc conversion without isolation. As mentioned ear-
lier, for space and many other applications,
isolation of the input and output is essential and is
carried out using an isolation transformer. In this
type of converter, the high-frequency output from
the switch of the basic PWM is applied as an ac
input to the primary of an isolation transformer.
The ac output from the secondary of the isolation
transformer is then rectified and filtered to produce
the desired value of output voltage. The added
weight of the transformer can be reduced by using
as high a switching frequency as possible. The
turns ratio, N1:N2, of the transformer may also be
used to step up or step down the output voltage.
Implementing isolation in a step-down converter
topology results in the idealized circuit shown in
Figure 2-86. Step-down (buck) converter schematic Figure 22-87. Step-up (boost) converter schematic
(Desko, 1991). (Desko, 1991).
Figure 2-88. Taking into account the transformer
turns ratio for the step-down converter gives
which is similar to the earlier result for a
nonisolated step-down converter. To achieve full
isolation in the power sueply, the PWM control
Figure 2-88. Step-down converter with isolation
(Desko, 1991).
signal from the secondary side to the primary side
must also be isolated. This is accomplished using
one or more isolation transformers.
The isolation transformers and the passive ele-
ments, capacitors and inductor, comprise most of
the volume and weight of the power supply. By
going to a higher switching frequency in a PWM
power supply, smaller transformers and passive el-
ements can be used, which lower the weight and
volume and hence increase the power density of
the power supply. For a space system, using the
highest frequency possible is desirable in order to
achieve high power densities. For a PWM con-
verter, the frequency upper limit is approximately
500 kHz because of the switching losses, which
increase linearly with frequency. Above this fre-
quency, the efficiency of the power supply begins
to decrease significantly, lowering its overall
power density.
frequencies, if it were not for the load inductances
present in the power supply. The load inductances
tend to cause both voltage and current overshoot
during switching and to produce a phase shift be-
tween the current and voltage waveforms. The in-
ductive load increases the power loss and sets
the upper switching limit at approximately 500
kHz. In addition to switching losses, the large
current and voltage overshoots and large power
dissipation in the switch can severely stress the
switch. Additionally, because of the square-wave
nature of the switch waveforms, which generate
high-frequency harmonics, electromagnetic inter-
ference (EMI) can be substantial in a system using
a high-frequency PWM power supply. These prac-
tical limitations are overcome by using more com-
plex converter topologies. However, these other
configurations represent variations of the basic
buck or boost topologies.
The implementation of the dc-dc converter re-
quires two distinctly different types of circuit or
device technology. One is a device type that can
serve as the power switch with two modes of op-
eration: (1) full conduction, passing current with
very low power dissipation; and (2) OFF mode,
blocking current flow with very low leakage. The
second type is a low-signal-level circuit that con-
trols the power switch and provides other required
alarm and/or control signals needed for device pro-
tection, etc. Each of these device types will be dis-
cussed.
2.9.3 Power Semiconductor Devices
In general, it is desirable to use the highest
switching speeds possible because of the large
weight and volume savings and the resulting in-
crease in power density. Moreover, the megahertz
All switches experience some switching losses
or near-megahertz frequency switching used in
since no switch can turn on or turn off instanta-
these converters requires a high level of perfor-
neously. During this switching period, it is possible
mance from the switch in terms of switching
to have voltage across the switch as well as current
speed, in addition to the requirements for high
flowing through the switch, which results in power
OFF-state breakdown voltage and low ON-state
dissipation during each switching cycle. As the
resistance (to reduce conducting losses). The only
switching frequency increases, the switching losses
power semiconductor device that can meet these
increase. However, these switching losses would
requirements today is the power MOSFET. By ap-
be insignificant, allowing operation at very high
plying a control signal to the power MOSFET gate
terminal, it is possible to realize switching speeds MOS IC technology and were developed in re-
up to 20 MHz, block up to 500 volts in the OFF sponse to the deficiencies of the power BJT. A
state, and experience minimal conduction losses in cross-section view of a discrete n-channel power
the ON state. In addition, the extremely high im- MOSFET is shown in Figure 2-89. The device
pedance of the gate allows for very simple control structure is referred to as a double-diffused MOS
circuitry. (DMOS) structure because both the p-body and the
Many types of power semiconductor devices are
used today as switches in power electronics. The
list of devices includes (in addition to the power
MOSFET): the bipolar junction transistor (BJT),
the insulated gate bipolar transistor (IGBT), diodes
(both bipolar and Schottky) and thyristor-type de-
vices (four-layer pnpn structures) such as the SCR
and the gate turn-off (GTO) thyristor. However,
with the exception of the power MOSFET, for one
reason or another these devices are inadequate for
the task at hand.
n+ source diffusions are self-aligned with respect
to the edge of the polysilicon gate. The symbol
for this device is shown in Figure 2-90. It is a
three-terminal device consisting of a gate, source,
and drain electrode. The gate is composed of poly-
crystalline silicon or some other refractory material
and is separated from the underlying, lightly
doped, n-type, single-crystal silicon by an insulat-
ing material such as silicon dioxide. The source
electrode is connected to both the n+- and p-body
diffusions, thereby shorting them together. The
drain is connected to the n+-diffusion on the back
The power BJT, developed in the 1 9 5 0 ~ ~ is a
side of the silicon. The lightly doped, n-type region
very mature technology and for many Years it was
between the p-body diffusion and the back-side n+-
the only power semiconductor device available for
region is known as the drift region. The smallest
high-speed switching. However, the maximum
functioning DMOS structure, shown in Figure
switching speed is only about 50 kHz due to its
2-89(a), is referred to as a unit cell.
long turn-on and turn-off times. As mentioned ear-
lier, power is dissipated during these intervals.
Above 50 kHz, these transition times become a
significant fraction of the switch period and effi-
ciency plummets. Also, the control circuitry is very
complex and expensive compared to an MOS de-
vice, because a BJT is a current-controlled device
and requires large control currents. The IGBT is
simply a combination of a MOSFET and a BJT,
which allows easier control circuitry. However,
switching speeds are even slower than for a BJT.
The SCR and GTO thyristors are inappropriate
for the application addressed here. The SCR,
somewhat like the diode, is not a fully controllable
switch. The SCR can be turned on by a control sig-
nal, but it can only be turned off by the action of
the circuit in which it is connected. The GTO is
fully controllable; however, the currents required
'for turn-off are very high and switching speed is
extremely slow.
The power MOSFET has only been commer-
cially available for power electronics applications
since the early 1980s. These devices evolved from
Conduction between the n-type source and drain
regions is prevented by the intervening p-type
body region when the gate-source electrode volt-
age VGS is less than the threshold voltage VT.
When a positive voltage greater than the threshold
voltage is applied to the gate electrode, an n-type
inversion region forms under the gate electrode,
allowing conduction between the n-type source
and drain regions [see Figure 2-89(a)]. Hence,
switching occurs by applying a control signal to
the gate electrode. Since the gate is insulated from
the underlying silicon, the control signal is basi-
cally a bias voltage with no steady-state current
flow. However, some current must be supplied to
the gate to charge and discharge the input gate ca-
pacitance during switching. In the OFF state, with
zero gate bias (VGS = 0), this device can support a
large positive drain-to-source voltage, VDs, which
is supported by the reverse-biased n-Ip-body diode
[see Figure 2-89(b)]. The maximum blocking volt-
age is determined by the breakdown voltage of this
diode and, to first order, depends on the doping
level of the drift region - the lighter the doping,
TOP VlEW
(a) ON State
- - - - - - y*...,.
VG>VT
, GATE
.
.
.
- -
POLY-Si GATE
1 1 OXIDE
> / f
I
POLY-Si GATE
I I OXIDE
J L
p--BODY
- - - - - - - - - - - -
n+-SOURCE n+-SOURCE
n-DRIFT REGION
DEPLETION
REGION
n--DRIFT REGION
v v n+ 1
DRAIN
v~~ > O
!f 7 1 ! 1r
SlDE VIEW
- - - - - - - - - - - - - - - - - - - - - - - - - - - . - , - - - - _- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
VBD >.VDS >> 0
(b) OFF State
SIDE VIEW
Figure 2-89. Cross section of a double-diffused MOS (DMOS) structure (Desko, 1991).
DRAIN
SOURCE
Figure 2-90. Symbol for a DMOS device (Desko,
1991).
the higher the breakdown voltage. In the ON state,
with VGS > VT and VDS > 0, a current appears a.t
the drain electrode. ON-state conduction losses
occur because of the finite resistance RON between
the drain and source, arising primarily from the
lightly doped drift region. To reduce the drain-
source resistance, the drift region is usually made
as thin as possible, which is usua,lly the n-lp-body
depletion width at the rated breakdown voltage
plus some safety factor. Further reductions in RON
require increased device area. The I-V characteris-
tics for a power MOS E T or DMOS are showr, in
Figures 2-91 and 2-92. The threshold voltage,
above which the device is turned on, is typically 2
to 5 volts.
2.9.4 Power Integrates Circuits
As mentioned, additional circuitry is required to
control the switching cycle or frequency of the
switch in order to maintain the output voltage at
the required level. The circuit blocks required for
this include operational amplifiers (op-a-mps),
comparators, timing logic, drivers, inverters, oscil-
lators, and others; the list is extensive. A block dia-
gram illustrating one particular control circuit
architecture is shown in Figure 2-93. The control
signal is generated on the secondary side, using the
amplified error signal, and sent across an isolation
transformer to the driver circuit, which then turns
the switch on and off.
The control circuit shown in Figure 2-93 was
designed to generate a variable-frequency control
Figure 2-91. DMOS output characteristics (Desko,
1991).
signal for a resonant converter. The dc output volt-
age and reference voltage pass through an error
amplifier. The output is inverted and then con-
verted from a voltage signal to a current signal,
This signal then passes through a monostable
multivibrator where a digital control signal is
generated. The digital signal passes across an iso-
lation transformer to some timing logic and then
on to an additional monostable oscillator vvhere the
final gate control signal is generated. This control
signal is then routed to the power MOSFET gate
through a driver circuit. The driver circuit is neces-
sary to charge and discharge the gate capacitance
during each switching cycle. The monostable oscil-
lator shown in the figure is used to generate feed-
back to the secondary side. This circuit requires
two additional small isolation transformers. This
Figure 2-92. DMOS transfer characteristics (transcon-
ductance) (Desko, 1991).
MOSFET
GATE
t
DRIVER
.
4
MONOSTABLE
4
Figure 2-93. Resonant converter control circuit (Desko, 1991).
I
control circuit is a simplified version of a control an application the DMOS configuration shown in
circuit designed for space applications. The num- Figure 2-89(a) is unsuitable. However, several al-
ber of circuit blocks shown are only a fraction of ternate configurations exist.
the number actually used. Additional circuit blocks
One approach uses a lateral drift region instead
are needed protect the power
from a
of the vertical drift region to electrically isolate this
riety of conditions that could damage it.
high-voltage device from the other devices using
Although the control circuit and power device
(switch) can be implemented using a separate IC
chip for each function, a significant penalty in
added weight, volume, and power consumption, as
well as a reduction in reliability, will be accrued
using this approach. Thus, a class of ICs known as
"smart-power" ICs (or PICs) that integrates all of
the required functions has been developed. Since
PIC technology requires the integration of power
MOS (DMOS) devices with CMOS, BJT, Zener
diodes, and resistors, PICs are considered sepa-
ERROR
AMPLIFIER
INVERTER OSCILLATOR +
+
junction isolation (JI). Cross sections of two pos-
sible lateral DMOS structures are shown in Figure
2-94. The long lateral drift region supports the
voltage in the OFF state. The lightly doped p-type
substrate used for these structures is fully compat-
ible with the current practice of using p-type start-
ing wafers for very-large-scale ICs (VLSICs). The
main drawback of this approach is that for high-
voltage applications, a large amount of area is
taken solely for the purpose of electrically isolating
devices.
+ LOGIC
4J
rately for this discussion. In addition, the integra-
Another approach utilized is dielectric isolation
tion of a DMOS device on a single chip with
(DI), wherein a buried, wrap-around region allows
and BJT devices requires, in
the drain region to be contacted on the silicon top
cases, that the terminals of the power device be
surface [see Figure 2-95]. Devices are thereby
On One side of the for such
electrically isolated from each other by the buried-
"REF + MONOSTABLE
GATE
0
DRAIN SOURCE
0
n+
n-
GATE
0
DRAIN SOURCE
0 C
Figure 2-94. Cross section of two lateral DMOS structures employing junction isolation (Desko, 1991).
"GS ' h
DRAIN GATE SOURCE
Figure 2-95. Cross section of a lateral DMOS employing dielectric isolation (Desko, 1991).
oxide layer. While this approach is more area-effi- processing requirements result due to conflicting
cient at higher voltages, it is very inefficient at fabrication requirements. Moreover, these fabrica-
lower voltages. tion issues are exacerbated when designing for ra-
Additional costs are incurred due to the added
diation hardness.
wafer-processing needed to form the DI substrate.
2-95 Radiation Effe& and Hardening
Dielectric isolation is advantageous in radiation
Strategies
environments because it prevents latchup. Neither
Radiation-hardened semiconductor devices suit-
the J1 Or D1 approach can match the low
able for space-system applications are available
achieved using discrete devices; however, the abil-
from a number of manufacturers. However, at the
it^ to integrate the into a sing1e IC present time, a monolithic radiation-hardened PIC
may more than compensate for this deficiency in
is not yet available.
most a~~l i cat i ons.
L *
The effects of radiation on DMOS devices and
A cross section of a 'IC
the various other semiconductor devices associated
CMOS, BIT, and diode circuits is shown in Figure
with PICs are shown in Table 2-5.
2-96. Although these alternate structures permit the
integration of DMOS and low-power devices, e.g.,
CMOS, BJTs, diodes, etc., stringent design and
Figure 2-96. Smart power IC (PIC) cross section using DMOS, CMOS, BJT, and diode circuits (Desko, 1991).
POWER DMOS
C 4
f---- HIGH-VOLTAGE CMOS ----)
Table 2-5. The effect of critical radiation environments on devices.
- LOW-VOLTAGE CMOS
Device
DMOS CMOS BJT
Environment Major Effect Lesser Effect Major Effect Lesser Effect Major Effect Lesser Effect
Ionizing radiation dose X X X
Neutrons X X X
Singleevent upset X X X
Dose-rate upset X X X
2.9.5.1 CMOS and BJT Devices
The effects of the various radiation environ-
ments on low-voltage CMOS and bipolar devices
and ICs are fairly well documented. Special proce-
dures have been developed both in device and
chip design and in wafer fabrication that can
harden a device or IC chip to these critical radia-
tion environments.
For CMOS devices, the critical radiation envi-
ronment is ionizing radiation dose, which can lead
to large changes in threshold voltage, resulting
in the n-channel device turning on at zero gate
voltage. The mechanism for this is the buildup of
positive charge in the oxide under gate bias. The
procedure used to prevent this is to use as thin a ra-
diation-hardened gate oxide as possible, since the
threshold voltage shift varies with at least the
square of gate thickness, using low-temperature
processing following gate oxidation. In practice,
oxide thicknesses are kept below 250A and subse-
quent process conditions are kept at 850C or less.
The oxidation growth temperature and ambient
have also been shown to play a role in reducing the
threshold voltage shift.
For BJTs, ionizing radiation can cause surface
inversion in the base region, which can lead to
emitter-to-collector leakage and gain degradation
due to surface recombination effects. These prob-
lems can be ameliorated through the use of hard-
ened field oxides.
2.9.5.2 DMOS Devices
For DMOS devices, all environments produce
major effects. Ionizing radiation dose alone results
in four major deleterious effects: threshold voltage
shift, rebound (or super-recovery), breakdown volt-
age shift, and mobility reduction. Each of these
four effects is examined below.
The power MOSFET is susceptible to threshold
voltage shifts due to the buildup of charge in the
gate oxide. However, it is not possible (as it is in
the case of CMOS devices) to use very thin gate
oxides to reduce this effect. Using such thin oxides
can lead to gate rupture in a space SEU environ-
ment due to the presence of energetic heavy ions.
Also, thinning the gate oxide can result in a reduc-
tion of reliability due to gate oxide breakdown.
Consequently, gate oxides are kept between 500A
and 1,000A. Since this relatively thick gate oxide
results in a large threshold voltage shift, the thresh-
old voltage must be set higher initially, which can
lead to a reduction in drive current for the device.
The buildup of interface states during ionizing ra-
diation dose lowers the carrier mobility, which re-
sults in an increase in the resistance of the device
in the ON state, RON. This increase results in addi-
tional power dissipation in the switch, which low-
ers the dc-dc converter efficiency. Because a large
reduction in oxide thickness to reduce this effect is
not possible, the only way to compensate for this
effect is to derate the ON resistance of the device,
which results in a larger device than would other-
wise be necessary in order to meet the ON resis-
tance specifications of the device.
The thick oxides used for the DMOS device can
also result in a serious rebound problem. Rebound,
or super-recovery, refers to the annealing out of
oxide charge while interface states continue to ei-
ther increase or remain constant over time. The net
result is that the threshold voltage for n-channel
transistors rebounds to higher than initial values,
which further lowers the device drive current.
These three effects (threshold voltage reduction,
mobility degradation, and rebound) are illustrated
in Figures 2-97 through 2-99 for a 700& hardened
gate oxide. Figure 2-97 shows the effect of increas-
ing ionizing radiation dose on the device transfer
curve, or transconductance. The curves shift to the
left, in a parallel manner at lower doses, indicating
the buildup of oxide traps. As irradiation continues,
the buildup of interface states lowers device mobil-
ity and the curves are seen to change slope. The
change in threshold voltage as a function of ioniz-
ing radiation dose is plotted in Figure 2-98. The
effect of rebound is shown in Figure 2-99, where
curves are seen to begin shifting to the right.
The fourth potential ionizing radiation dose ef-
fect for DMOS devices is the reduction in break-
down voltage. This effect results from the buildup
10- l 3
- 2 - 1 0 1 2 3 4 5
GATE VOLTAGE (volts)
Figure 2-97. Effect of ionizing radiation dose on DMOS
(80cell) transconductance; dose rate = 1.11 x 105 rads
(Si02)/min, VDs = 10 volts (Desko, 1991).
of positive charge in the thick field oxide used in
the termination region of the device. This terrnina-
tion region is necessary for a smooth transition in
voltage across the silicon surface region at the
edges of the device. The termination region of a
device using field-shield termination is shown in
Figure 2-100 with the accompanying electric field
lines. The oxide charge can change the electric
field distribution in this region and lower the de-
vice breakdown voltage. Preventing this problem
requires using a hardened field oxide or a ring
termination structure.
2.10 Nonvolatile Memory Technology
Nonvolatile memories, i.e., memories that retain
information in the absence of applied power, are
widely used in a variety of military and cornrner-
cia1 systems to retain critical information (such
as codes or passwords, system configurations,
operating systems, look-up tables, baseline data,
etc.) that must be preserved despite the loss of sys-
1.2 0 1 0 volts .............. 0 .... ..........
t t
5 volts ,
i 0
....................... .................... g 0.8 .................... .:. : 1
h
m
C
5 1.6
IONIZING RADIATION DOSE (rads[Si])
>
Y
4?
Figure 2-98. Effect of ionizing radiation dose on DMOS
(80cell) threshold voltage; dose rate = 1.1 1 x 105 rads
(Si02)/min, VDs = 10 volts, IDS = 10 mA (Desko,
1991).
1 1 1 1 1 1 1 I I1111111
IN SlTU BIAS, VG
OI I I I I I r l
m !2
---- 1 Mrad(Si)
-
--- 1 -hour ANNEAL
- VDS = 0 volt -
I I I
10-12
-0.7 0.7 2.1 3.5 4.9
VGS (volts)
Figure 2-99. Rebound effect demonstrated on an 80-cell
DMOS subjected to 1 Mrad(Si) ionizing radiation dose
and the effects of annealing; dose rate = 179 rads(Si)/
sec, VDS = 0.1 volt, anneal temperature = 150C
(Desko, 1991).
tem power (Dressendorfer, 1991). An example of
the widespread use of nonvolatile memories is
shown in Figure 2-101. In addition, many of these
systems must operate in natural space andlor
weapon-produced nuclear environments.
0 volt
n+ + HIGH VOLTAGE
OXIDE
Figure 2-100. High-voltage device termination structure (field shield) @esko, 1991).
The many different nonvolatile memory tech-
nologies, each with its own specific electrical and
radiation performance characteristics, are briefly
described below:
Programmable Read-Only Memory
(PROM). A device that may be pro-
grammed once after the completion of
its fabrication, and then subsequently
read a large number of times. The pro-
gramming is usually performed electri-
cally by "blowing" fuze links to imprint
the appropriate information into the
memory.
Erasable Programmable Read-Only
Memory (EPROM). A device that can
be programmed after manufacture and
then erased and rewritten with new in-
formation, as desired. In ultraviolet
EPROMs (UVEPROMs), erasure is ac-
complished by exposing the device to
ultraviolet light for several minutes; re-
writing the device is then done electri-
cally. This erasure process is generally
cumbersome and time consuming; thus,
this device is not suitable for applica-
tions requiring frequent alterations of
the stored information.
One-Time Programmable, Erasable
Programmable Read-Only Memory
(OTP EPROM). A UVEPROM that is
packaged in plastic (without a transpar-
ent window). Because of this packaging
difference, it is less expensive than an
EPROM, but cannot be erased.
Electrically Erasable Programmable
Read-Only Memory (EEPROM) A
device in which both the erase and pro-
gramming functions can be performed
electrically in a relatively straightfor-
ward manner. This name has been tradi-
tionally associated with floating-gate
and silicon-nitride-oxide-semiconductor
(SNOS) devices, rather than being a
generic description of all memories with
the characteristic of electrical erase and
programming.
EMBEDDED RADAR WARNING COCKPIT REMOVABLE SOLID-STATE FLIGHT
RECEIVERS WITH EEPROM MEMORY DATA CARTRIDGE RECORDER INCIDENT RECORDER
EEPROM TECHNOLOGY EEPROM, BUBBLE EEPROM TECHNOLOGY
Capacity: 48-96 kbits Capacity: 8 Mbits
Capacity: 30 minutes voice and data
Features: Features: Features:
Remotely programmed Easily removable cartridge Ejectable
Nonvolatile Nonvolatile Nonvolatile
Solid-state
Solid-state Solid-state
Availablity: Now Application: Availablity: Under development
Input: Threat libraries
Output: Mission planning
parameterslmaintenance data
EEPROM TECHNOLOGY EEPROM, SRAM EEPROM TECHNOLOGY BUBBLE MEMORY
Capacity: 48-96 kbits Capacity: 36 Mbits Capacity: 16-48 kbits Capacity: 200 Mbits
Features: Features:
Remotely programmed Nonvolatile EEPRO Remotely programmed Nonvolatile
Nonvolatile Nonvolatile Radiation-resistant
Solid-state Solid-state Solid-state
Availablity: Now Availablity: Now Application:
Computer data storage
Availablity: Now
VERIFIER PORT MISSION DATA RECORDER
OPTICAL DlSK
MAGNETIC TAPE CASSETTE OPTICAL DISK ROTARY MAGNETIC TAPE Capacity: lGbit
Capacity: 14.4 Mbits Capacity: 1 Gbit
Capacity: 240 Mbitslsec Features:
Features: Features: for 1 hour
Nonvolatile
U. S. Na y standard Nonvolatile Features:
High density
Ground-based system High density
High data rates Quick access
Application: Quick access Archival mass storage Application:
Maintenance data computer Application: Application: Digital maps
program (loaderlverifier)
Digital maps VideoIFLIR recorder Sensor storage
Availablity: Now Sensor storage Radar recorder Availablity:
Availablity: Sensor storage
Write once; 1-2 years
Write once; 1-2 years Availablity:
Reamri te; 3-5 years
Reamrite; 3-5 years 1-2 years
Figure 2-101. Examples of nonvolatile memory technology usage in a military aircraft (Fedorak, 1989).
Ferroelectric Technology. A device
which utilizes the hysteresis properties
of ferroelectric material to store infor-
mation.
larly stores information as the direction
of magnetization, but in a small toroid
of magnetic material. These technolo-
gies tend to have low density (on the
Plated Wire and Magnetic Core Tech-
scale of integrated circuits) and are not
nology. Plated wire technology utilizes
compatible with IC processing.
magnetic coating on small wires to store Magnetic Bubble Technology. Memo-
information as the direction of magneti- ries use a magnetic material in which
zation. Magnetic core technology simi- "bubbles" (localized regions of reverse
magnetization) are used to store infor-
mation. Although the processing of
these devices uses many of the tech-
niques of IC processing, they cannot be
easily integrated on the same substrate
as standard IC transistors.
Magnetic Tape and Disks. Store infor-
mation as localized regions of reversed
magnetic field. They require mechanical
devices in order to locate and access
information.
Optical Disks. Utilize a change in opti-
cal properties to store information.
Battery-Backed Static Random Ac-
cess Memory (SRAM). This is not
a true nonvolatile memory technology,
since the SRAM does require the unin-
terrupted application of power in order
to retain information. However, in these
devices this uninterrupted power is
supplied by a battery that is made part
of the device subsystem; hence, from
the system perspective, power does not
have to be continuously applied. For
a number of applications, this is a viable
means of achieving nonvolatile opera-
tion with SRAM performance.
Terminology unique to the context of nonvola-
tile memory technology is listed below
(Dressendorfer, 199 1):
Retention. The length of time that the
information can be retained correctly,
particularly under worst-case storage
conditions, e.g., unpowered, high-tem-
perature, etc.
Endurance. The number of times a de-
vice may be written, erased, and rewrit-
ten and still function properly as a
nonvolatile memory.
Program or Write Tfme. The time neces-
sary to write information into the
memory.
Read Time. The time necessary to read
information from the memory.
Erase Time. The time necessary to erase
information from the memory (often the
same as write time, but may be different
for some nonvolatile memory devices or
architectures).
Write/Erase/Read Voltage. The voltage
necessary to perform the write, erase, or
read functions.
This section discusses the ionizing radiation
dose characteristics only for EPROM and
EEPROM (both floating gate and SNOS), ferro-
electric, and one type of thin-film magnetic non-
volatile memories. The technologies omitted from
this discussion obtain their nonvolatility from the
permanent alteration of a structure by the opening
of fuze links (except battery-backed nonvolatile
memory). Thus, the radiation performance of such
a device is wholly based on the performance of
peripheral circuits and is covered in Chapter 5.
Battery-backed nonvolatile memory performance
is governed by the radiation response of the SRAM
being used; thus, this information is covered in
Sections 2.4 and 2.5 (MOS technology devices).
The various technologies and their applications
can be placed in perspective by viewing nonvola-
tile memories as existing in two hierarchies: (I)
reprogramming ease [Figure 2- 1021, and (2) data
recovery speed [Figure 2- 1031. The implication of
Figure 2-103 is that the technologies selected for
primary storage are capable of faster operation
than secondary memory, etc. In addition to these
two factors, other considerations for the selection
of a particular technology include radiation perfor-
mance, integration density, endurance, retention,
power consumption, weight, size and cost.
A summary of the advantages and disadvantages
of several technologies that are being considered
for space strategic application is shown in Table
2-6. From this table, the difficulty in selecting the
optimum technology for a specific application can
be understood. Figures 2-104 through 2-106 are
provided to summarize solid-state nonvolatile
Figure 2-102. Reprogramming ease hierarchy for solid-state memory devices (Fedorak, 1989).
technologies to support Table 2-6. Note that the 2.10.1 Floating-Gate Erasable
ferroelectric technology, which displays excellent Programmable Read-Only Memory
endurance and speed, is also deemed extremely
A typical floating-gate EPROM (FG EPROM)
immature, thus precluding an easy selection for a
cell is shown in Figure 2-107. The dielectric under
specific application. Moreover, this technology se-
the floating gate is silicon dioxide of -200A thick-
lection problem does not reflect the added con-
ness. The dielectric between the floating and con-
straint of radiation hardness.
TERTIARY
MEMORY
COMPUTER
CPU
t - t
MEMORY
-
BUS
I10
Figure 2-103. Computer memory hierarchy: data recovery speed (Fedorak, 1989).
EMERGING
TECHNOLOGIES
SEMICONDUCTOR
EEPROM
EEPROM
SEMICONDUCTOR,
BUBBLE
BUBBLE, OPTICAL
DlSK
OPTICAL DISK
STRUCTURAL
NOMENCLATURE
PRIMARY
SECONDARY
TERTIARY
QUATERNARY
A A A
PRIMARY
MEMORY
SECONDARY
MEMORY
DRUM
DMTU
GPDC
FUNCTIONAL
NOMENCLATURE
MAIN STORE
BACKING STORE
MASS STORE
ARCHIVES
PRIMARY
MEMORY
PRESENT
TECHNOLOGIES
CORE, SEMICON-
DUCTOR, PLATED
WIRE
BULK CORE, DRUM,
DISK, SEMICON-
DUCTOR
DISK, TAPE, DRUM
TAPE (OFFLINE)
S-3lP-3
-
Table 2-6. Summary of potential nonvolatile technologies (Kuehl, 1990).
Technology Advantages Disadvantages
ROM, PROM High speed, high density, excellent Cannot be rewritten
radiation hardness
EEPROM/MNOS~ High density, fast read time
(Westinghouse, Sandia)
Thin-film plated wirea High speed, moderate density,
(Honeywell) excellent radiation hardness
~a~net or es i s t i ve~ Speed trades with density, good
(Honeywell) potential hardness
Ferroelectrica
High speed, high density, good
(Ramtr0n)potential hardness
Plated wireb Moderate speed, excellent
radiation hardness, expensive
Moderate speed and density,
excellent radiation hardness
Wear out, slow write time; susceptible
to burnout
Limited density (2K to 4K)
Immature sensing technology; data
retention at high dose rates is an issue
Long-term wear-out & materials issues
Very low density (high volume, weight)
Inefficient for small memories,
expensive
Magnetic bubbleb Very high density Very slow, vulnerable to transient
radiation-induced data loss during
access
Notes:
a Immature technology.
Not monolithic.
TIME (seconds)
I 1 1 1 1 1 1 1
EPROM
Read
FG EPROM
Read
Figure 2-104. Typical performance characteristics of solid-state electronic nonvolatile memory technologies
(Schwee, 1990).
EPROM
Write
Erase
Write
FERRO-
ELECTRIC
Read
FERRO-
ELECTRIC
WritelErase
SNOS EEPROM
Write
I
SNOS EEPROM
Erase
10-8 2 4 610-7 10-6 10-5 10-4 10-3 10-2 1 03
EPROM
FG EEPROM
FERROELECTRIC
MAGNETIC
THIN FILM
0 2 4 6102 1 o4 1012 l0l4 loi6
ENDURANCE (number of cycles)
Figure 2-105. Typical endurance characteristics of solid-state electronic nonvolatile memory technologies
(Schwee, 1990).
EPROM I
I
1 FG EEPROM I
-
EEPROM
IONIZING RADIATION DOSE (rads[Si])
Figure 2-106. Ionizing radiation dose hardness of nonvolatile memory elements
for solid-state electronic memory technologies (Schwee, 1990).
trol gates can be either silicon dioxide or another This difference can detected by the sense amplifier.
dielectric (such as silicon nitride), usually about Since the voltage configuration is the same during
200W to 400W thick. Programming is performed read and programming, read-disturb problems are
using channel hot-electron injection. A large posi- avoided by having a significant difference in volt-
tive voltage is applied to the control gate (-12 age levels for these two operations.
volts) with a relatively high voltage (-8 to 9 volts)
applied to the drain (bit line). Source and substrate
are held at ground potential. Electrons in the chan-
nel are accelerated by the high field near the drain
where some acquire enough energy to surmount
the Si/Si02 barrier and are attracted to the floating
gate. Erasure is performed by illumination with
UV light (with photon energy >4 eV), which
photoinjects electrons over the Si/Si02 barrier at
the floating gate where they are subsequently col-
lected, either at the top control electrode or the sili-
con substrate. Programming results in a threshold
voltage >5 volts for the control gate.
-
Since floating gate devices can be erased by
ultraviolet illumination, it is expected that they will
also be erased in an ionizing radiation environ-
ment. An example of the threshold voltage shifts
observed with ionizing radiation is shown in
Figure 2- 108 [comparison with model calculations
are also shown]. The memory window is seen to
change appreciably at 1 o4 rads(Si), and almost
completely collapses by lo5 rads(Si). Thus, with
suitably hardened peripheral circuitry, a floating-
gate memory cell could support nonvolatile opera-
tion to this level.
Erasure by UV light results in threshold voltage
2.10.2 Floating-Gate Electrically Erasable
of -1.5 volts. During read, the control gate is held
Pcogrammable
at 5 volts, and the bit line is precharged to 1 to 2 A typical floating-gate EEPROM (FG
volts. A "0" in the cell allows current to flow EEPROM) transistor is shown in Figure 2-109,
through the cell, pulling down the bit line, whereas with a thin tunneling dielectric (silicon oxide or
a "1" (VT > 5 volts) does not allow current to flow.
m\\\\v GATE OXIDE
POLYSlLlCON
CONTROL GATE
I
POLYSlLlCON
FLOATING GATE
Figure 2-107. Cross section of a typical EPROM floating-gate transistor (Dressendorfer, 1991).
l o2 1 03
IONIZING RADIATION DOSE (rads[Sil)
Figure 2-108. Threshold voltage shifts of a floating-gate transistor as a function of ionizing dose for transistors
programmed with different initial threshold voltages (Snyder et al., 1989).
"G "D
POLYSILICON
POLYSlLlCON
FLOATING GATE
7-
GATE OXIDE TUNNEL OX1
FIELD
Figure 2-109. Cross section of a typical EEPROM floating-gate transistor (Dressendorfer, 1991).
silicon oxynitride, typically 80A to 100A thick) bit line of the selected cell are brought to a high
grown over the drain region. voltage, and the program line is held at zero. Dur-
Programming is achieved by applying a high
positive voltage (typically 16 to 20 volts) to the
gate, and grounding the source, drain and sub-
strate; Fowler-Nordheim tunneling occurs between
the drain and the floating gate. Erasure is achieved
by grounding the gate and applying a high positive
voltage to the drain.
A full-featured EEPROM memory cell is more
complicated than that of an EPROM. A representa-
tive example of an array of floating-gate tunnel
oxide (FLOTOX) cells for a byte architecture is
shown in Figure 2-1 10. During programming, the
word line and program line of the selected cell are
brought to a high voltage (-20 volts), and the bit
line is held at zero. During erase, the word line and
ing read, the word line of the selected cell is
brought to 5 volts, the program line is held at a ref-
erence voltage, and the bit line is precharged to -2
volts. The threshold voltage of the selected
memory transistor relative to the reference voltage
determines whether current will flow and dis-
charge the bit line. The drain isolation transistors
prevent disturbing unselected transistors on the
same bit lines as the selected cell (read disturb) and
are used to select the appropriate transistor during
the read operation. The gate isolation transistor al-
lows selection of a particular byte during read of a
given set of bit lines. The ionizing radiation dose
response of an EEPROM is similar to that of an
EPROM since both share a common operating
methodology.
PROGRAM LINE BIT LINE 0 BIT LINE 7
WORD
LlNE N
WORD
LlNE N+
Figure 2-110. EEPROM memory array of FLOTOX cells for a byte architecture (Dressendorfer, 1991).
2.103 Silicon-Nitride-Oxide Semiconductor
Nonvolatile Memory Technology
Metal-nitride-oxide semiconductor (MNOS)
nonvolatile memory devices were first reported in
1967 by Wegener et al. (1967). MNOS nonvolatile
technology is similar to MOS technology except
that the gate oxide is replaced with a stack of di-
electrics. This stack of dielectrics serves as a
charge-trapping region, and in that sense it re-
places the floating gate of floating-gate nonvolatile
memory technology. There are several varieties
of MNOS technology, the modern versions being
silicon-nitride-oxide semiconductor (SNOS) in
which the gate electrode is polysilicon. In this area,
all the variants of this technology will be referred
to as SNOS, since the basic principles of operation
are similar in all cases. The discussion will focus
on n-channel transistors; the operation of p-chan-
nel devices is similar with appropriate changes of
voltage polarities and definition of the logic states.
Figure 2- 1 1 1 is a cross section of an SNOS tran-
sistor, showing the typical thicknesses for the vari-
ous layers of the dielectric stack (memory stack).
The device is written by applying a positive volt-
age to the gate electrode. The magnitude and dura-
tion of this voltage must be sufficient that electrons
can tunnel through the thin bottom oxide into the
trapping dielectric region (which can be either sili-
con nitride or silicon oxynitride) where they are
subsequently trapped. At the same time, holes
trapped in the dielectric can tunnel through the bot-
tom oxide into the substrate. The resultant negative
space charge causes a shift in the threshold voltage
of the device in the positive direction, which, in the
case of an n-channel transistor, can lead to en-
hancement-mode operation and a logical "1" state.
To erase or clear the device, a large negative volt-
age is applied between the gate and substrate, the
magnitude and duration of which must be suffi-
cient to allow the trapped electrons to be tunneled
out of the trapping dielectric and for holes to be
tunneled from the substrate into the dielectric
where they become trapped. This space charge
leads to a negative shift in the threshold voltage of
the transistor, which, for an n-channel transistor,
TUNNEL OXIDE
( I 6A TO 20A)
I \
DRAIN SOURCE
Figure 2-111. Cross section of an SNOS memory transistor showing the typical thicknesses of the various layers of the di-
electric (memory) stack (Dressendorfer, 1991).
can lead to depletion-mode operation and a logical
" 0 state.
The rate at which carriers tunnel into (or out of)
the trapping dielectric from (or into) the silicon
substrate is affected by the following parameters:
(1) the magnitude of the electric field across the
tunnel oxide (which, in turn, is determined by the
applied voltage, the dielectric constants, and thick-
ness of the three layers in the memory stack, the
doping density of the substrate, and trapped charge
in any of the dielectric layers or at their interfaces);
(2) the tunnel oxide thickness; (3) the barrier
heights between the tunnel oxide, the silicon sub-
strate, and the trapping dielectric; (4) the effective
mass for carriers in the tunnel oxide; and (5) the
temperature.
The total number of carriers trapped in the trap-
ping dielectric depends upon the: (1) tunneling
rate; (2) magnitude of the applied voltage; (3)
length of time the voltage is applied; (4) density,
energy, depth, and location of traps in the trapping
dielectric; (5) cross section of these traps (which
can depend upon the electric field); and ( 6)
temperature.
As time elapses, the trapped space charge gradu-
ally leaves the trapping dielectric. The rate-limiting
mechanisms governing charge decay can be differ-
ent from those governing charge injection during
program or erase operations. For example, the rate-
limiting mechanism may be thermal emission from
trap sites rather than back-tunneling through the
oxide for certain geometries and temperatures.
Based upon the above discussion of operation,
several observations can be made regarding the ef-
fects of the various layers in the memory stack.
The thickness of the tunnel oxide influences the
charge injection and decay, thicker oxides leading
to less injection at a given field and a slower rate
of charge back-tunneling (i.e., slower decay rate of
threshold voltage). The trapping dielectric affects
charge trapping and decay. Depending upon the
energy level of the traps, trapped charge can be
thermally emitted and then tunnel out of the dielec-
tric, leading to a net reduction in the space charge.
The top oxide can act as a barrier to reduce charge
injection from the gate electrode. This charge can
become trapped and compensate that injected from
the substrate, leading to less threshold shift than if
such injection did not occur. This effect becomes
more important as the total thickness of the
memory stack is reduced.
In order to achieve low rates of charge loss from
the trapping dielectric and thus low threshold-volt-
age decay rates, the SNOS structure usually must
be annealed at a relatively high temperature (800
to 900C) in a hydrogen ambient. The effect of this
anneal is to reduce the number of interface trap
levels at the Si/Si02 interface. Since this anneal is
performed as the last high-temperature step in the
overall process flow, it typically occurs either just
before or just after contacts are opened in the final
dielectric layer before the first metallization layer
is deposited. The hydrogen anneal degrades the ra-
diation hardness of MOS peripheral devices, and
this represents a trade-off in retention characteris-
tics and radiation hardness.
2.10.3.1 Design Considerations
SNOS memories are typically based upon the
gated access approach, in which an MOS transistor
is in series with the SNOS transistor (Hagiwara et
al., 1980; Knoll, Dellin, and Jones, 1983). A
memory cell can consist of either one or two
SNOS transistors per bit, with each SNOS transis-
tor having an MOS access transistor, as shown in
Figure 2-1 12. In operation, the cell is written by
pulsing the gate voltage positively relative to the
silicon substrate (the p-well) and sourceldrain
(which are usually held at ground potential). The
erase or clear is performed by holding the gate at
ground potential and pulsing the p-well positively.
This requires that the well potential be able to be
controlled during data change operations. The
MOS access transistor and SNOS memory transis-
tor can be separate, as shown in Figure 2-112, or
integrated, as shown in Figure 2-113, to provide a
more compact cell layout.
In order to read the memory cell, the bit line is
precharged, the gate to substrate voltage of the
SNOS transistor held at zero, and the MOS access
transistor turned on. The sense amplifier provides
SOURCE DRAIN
p-WELL
n-SUBSTRATE
Figure 2-112. Cross section of a typical SNOS memory cell having separate MOS access transistors (Dressendorfer, 1991).
MEMORY GATE
I
SOURCE
DIELECTRIC I
DRAIN
Figure 2-113. Cross section of an SNOS memory cell with a merged MOS access transistor (Dressendorfer, 1991).
a trickle charging current to the bit line and moni-
tors the bit-line voltage. When the memory cell
contains a " 0 (i.e., in depletion mode), it sinks this
charging current and pulls the bit-line potential to
a low value. When the memory cell contains a "1"
(i.e., in enhancement mode and thus draws no cur-
rent), the charging current is greater than the bit-
line leakage; thus, the bit-line voltage is at a high
value.
The sensing scheme for the memory cell of Fig-
ures 2- 1 12 or 2- 1 13 requires that one of the logic
states be enhancement mode and the other be
depletion mode, with enough current drive at zero
gate voltage to overcome the sense current applied
to the bit line. This places requirements not only
on the difference between the logic "1" and logic
" 0 threshold voltages (the memory window), but
also upon the center position of the window. For
circuits intended to operate in a radiation environ-
ment, the "1" threshold must typically be greater
than zero, and the " 0 threshold must be less than
approximately -0.5 volt in order to have reliable
sensing. The rate at which the bit line is pulled
down also depends upon amount of current drive
the logic "0" state has above the minimum. This
drive degrades with time as the threshold voltage
decays, so the minimum read access time will in-
crease with time. Thus, there is a trade-off between
read access time and retention SNOS memories.
During the read operation, the gate voltage of
the SNOS transistor is held at the same potential as
the substrate. This minimizes read-disturb prob-
lems since any applied potential could affect the
charge stored in the device. The design of SNOS
memories must minimize unwanted voltages de-
veloped across the memory stack for either the
transistor being read or other transistors in the ar-
ray where the read is inhibited.
An individual memory cell can also be com-
posed of two SNOS and two MOS transistors. The
write operation of the individual transistors is sirni-
lar to that described for the cell of Figure 2-1 12,
except that one SNOS transistor is written into the
positive threshold state and the other into the nega-
tive threshold state. This configuration could repre-
sent a logic "I," with logic " 0 represented by the
transistors written into the opposite states. Reading
this memory cell now depends upon a difference
being generated in the voltages on the bit and bit-
bar lines as the two SNOS transistors are con-
nected to them. In this sensing scheme, the
requirements on the threshold voltages of the indi-
vidual SNOS transistors are less severe than for the
single transistor cell described above. The differ-
ence in threshold voltages between the two transis-
tors need only be approximately 0.05 volt (rather
than the 0.5 volt above), and the center position of
the window is relatively unimportant as long as at
least one of the transistors is depletion mode.
Memories with two transistors per bit will have
longer retention than those with one transistor per
bit when compared under identical conditions. Pro-
cessing constraints and control necessary to obtain
a given level of memory performance are also re-
duced. However, this increased robustness comes
at the price of a reduced density, since for the same
size chip, a memory with two transistors per bit
will have approximately one-half the storage ca-
pacity of a memory with one transistor per bit.
A third design approach is a shadow RAM,
where the SNOS transistors are connected to a
standard SRAM cell via control transistors. All
read and write operations are carried out on the
SRAM cell, with the stored information transferred
to the SNOS nonvolatile element only upon activa-
tion of a control signal (when power loss is de-
tected, for example). This approach provides a
memory with the read and write speed of the
SRAM, and requires much less endurance from the
nonvolatile memory elements. It is a much larger
memory cell, however, and its operating character-
istics may not be suitable for all applications.
2.10.3.2 Radiation Effects
Ionizing radiation will lead to a net loss in
trapped charge in SNOS transistors, thus affecting
the retention of the memory. This effect is shown
in Figure 2-114, where SNOS threshold voltages
for the two logic states are shown as a function of
time. Plotted are the retention curves for identical
transistors written into different initial states by al-
-4
l o0 2 6101 102 103 1 o4 l o5 106 1 o7 1 08 1 09
RETENTION TIME (seconds)
Figure 2-114. Effect of irradiation on SNOS threshold voltage for transistors written into different initial states. [At 5 x lo4
seconds, the transistors were irradiated with 500 krads(Si)] (McWhorter, Miller, and Dellin, 1986).
2-89
tering the programming time. The absolute value
of threshold voltage for both states is reduced by
the radiation, leading to a reduction in the memory
retention of the devices. The shift in threshold volt-
age caused by a given ionizing radiation dose de-
pends upon the threshold voltage at the time the
irradiation occurs and the dose rate of the radia-
tion. Models have been developed that can de-
scribe this radiation-induced threshold voltage
shift and its subsequent effect on the retention
properties of SNOS transistors. Models have also
been developed that can predict the radiation-in-
duced threshold voltage shift for both logic states
as a function of initial threshold voltage, dose rate,
and ionizing radiation dose. An example of the
kind of results obtainable with the predictive
model is shown in Figure 2-1 15 for a relatively
low dose-rate irradiation of 0.09 rad(Si)/sec.
I l l 1 I I I l l I I l l ! I I I l l I I l l ! I I l l 1 I I I l l I
. - UNSET STATE
-
' --
\ i
"1 " STATE
' y = 500 krad (Si)
-?.
. ---- "0" STATE
1 ;
........................... ................................. ................................. - 4; - : i ................. i ................. i ....... A
4
5-, :
- ' --
?--,&-, : -1:
- -4-- -- :
RETENTION TIME (seconds)
1 1 1
-
Figure 2-115. Retention curve for an SNOS transistor in
the "1" state in a low-dose-rate (0.09 radlsec) environ-
ment (McWhorter et al., 1987).
: - 4 1
7
i 10
\I: i YEARS
.............................................................................................................................................. -
\'* -
--
-
-i--
I- - - - '
- .....-,. -,----.-;--.--+---.-.-.--.-4..,i ............... : ......................................
.4 :
:
: - C L :
&"
- @+#--- :
i -e-' .
r n~ I 1 1 1 1 I 1 1 1 1 I 1 1 1 1 I 1 1 1 1 I 1 1 1 1 I 1 1 1 1 I 1 1 1 1 I
-
.....-
-
I I I
SNOS transistors will continue to function prop-
erly after being irradiated to very high ionizing
radiation dose levels; little degradation in opera-
tional properties has been observed at doses as
high as lo9 rads(Si). Devices may be written or
erased after receiving ionizing radiation doses of
this magnitude with minimal changes in their char-
acteristics. However, as described above, the pro-
cessing associated with the fabrication of the
provide the nonvolatile storage element when inte-
grated with a base semiconductor IC technology
(such as CMOS or bipolar). Because the technol-
ogy is still in the development phase, many issues
remain unresolved regarding its capabilities and
practical applications. Since little has been pub-
lished in the open literature on these activities,
only a brief description of the concepts of opera-
tion and characteristics will be provided here.
SNOS transistors can degrade the ionizing radia-
tion dose hardness of the MOS control devices.
A magnetic thin film possesses a hysteresis
loop. Information can be stored as the direction of
Thus, the ionizing radiation dose hardness of an
magnetization, and can be altered or read by the
SNOS memory for writelerase operations will be
application of an external magnetic field. The ex-
determined by the hardness of the peripheral
ternal field can be produced by current flow
circuitry.
through a conductor near the magnetic film. Two
-
2.10.4 Thin-Film Magnetic Nonvolatile
primary physical phenomena can be employed to
Memories
read the direction of the magnetization in the film:
Magnetic memories have existed for many years
magneto-inductance and magneto-resistance.
in a variety of forms, ranging from magnetic tape
Figure 2-1 16 illustrates the basic structure of a
and disk media to core and plated-wire memory.
possible nonvolatile memory element in a mag-
An extension of magnetic technology to the inte-
netic thin-film memory. The thin magnetic film
grated circuit format utilizes magnetic thin films to
can be magnetized in either of the two directions
WORD
CURRENT
>Az; Tl C FILM
APPLIED FIELD
u
APPLIED FIELD
Figure 2-116. Structure of a thin-film magnetic memory current (Dressendorfer, 1991).
along the "easy" axis of magnetization. To read the
direction of this magnetization by the magneto-in-
ductive effect, a current is pulsed along the word
line. This causes a changing magnetic flux in the
magnetic thin-film material, which, in turn, gener-
ates a potential in the sense line, the polarity of
which depends upon the direction of magnetization
in the film. Reading by means of the magneto-re-
sistive effect relies upon the fact that the resistance
of the magnetic field depends upon the direction of
the magnetization relative to that magnetic field.
Thus, to read in this mode, a current is driven
through the word line to establish an external mag-
netic field, and a current is driven through the
sense line. The voltage generated by this current in
the same sense line then gives the resistance and
thus the direction of magnetization.
Fabrication of the magnetic memory elements
can use standard IC processing techniques, al-
though the materials are different from those typi-
cally used. These elements can be fabricated as a
separate processing module from the base technol-
ogy, and thus can be utilized either by CMOS or
bipolar peripheral circuitry. Tight process control is
required of the magnetic memory elements.
Both the magneto-inductive and magneto-resis-
tive modes may be operated as destructive read-out
(DRO) or nondestructive read-out (NDRO). Signal
levels tend to be rather small (- 1 mV), placing se-
vere demands on the sense circuitry. Because of
these small signals, the read access time is some-
what slower than the other memory technologies
discussed, being of the order of 1 pe c . Write
times can be significantly faster. The magneto-in-
ductive readout approach does not scale as well as
the magneto-resistive since the signal is propor-
tional to the cell size.
Based on data from other magnetic technolo-
gies, it is expected that magnetic thin-film memory
elements will have very high endurance (>1015
cycles) and long retention (>20 years).
The radiation response characteristics of mag-
netic memory elements can be expected to be quite
good. Ionizing radiation dose is likely to have little
effect on the stored magnetization, so the hardness
of the memory to this environment will be limited
by the hardness of the peripheral circuitry.
2.10.5 Ferroelectric Nonvolatile Memory
Technology
A ferroelectric material exhibits an electric di-
pole moment, even in the absence of an applied
electric field. As a result, the polarization of the
material depends upon its electrical history, and
this polarization state may be used as the indicator
of stored information. Ferroelectric crystals are
classified into two primary groups: (1) order-disor-
der, in which the ferroelectric effect is associated
with the ordering of ions; (2) and displacive, in
which the polarization change is caused by a dis-
placement of a sublattice of one type of ion relative
to other ions in the crystal.
Ferroelectrics of most interest for nonvolatile
memories are of the displacive type. An example
0
A = DIVALENT OR MONOVALENT
METAL ATOMS (e.g., Pb, Ba)
0 0 = OXYGEN ATOMS
0
6 = TETRAVALENT OR PENTAVALENT
METAL ATOM (e.g., Ti, Zr)
Figure 2-117. Structure of the ferroelectric perovskite
crystal type AB03, showing the two stable positions of
the B ion that lead to the permanent polarization state
(Dressendorfer, 199 1).
of the ionic motion giving rise to the permanent
polarization in perovskite crystals (such as lead
titanate and barium titanate) is shown in Figure
2-117. The titanium atom at the center of the unit
cell has two stable positions as shown, each giving
rise to a different net polarization in the crystal.
The stable position (and thus polarization) can be
altered by the application of an electric field. This
effect is illustrated by the hysteresis loop in Figure
2- 11 8, where the polarization of a ferroelectric is
plotted as a function of the applied electric field.
This hysteresis loop is very similar to that ob-
served for ferromagnetic materials, where magne-
tization is plotted as a function of applied magnetic
field.
Shown in Figure 2-118 are several key param-
eters for ferroelectric materials. The spontaneous
polarization (Ps) is the maximum polarization due
to the ferroelectric susceptibility. The remanent
polarization (P,) is the polarization at zero applied
field. The maximum polarization (Pma,) is the
maximum total polarization (including both the
ferroelectric and linear dielectric contributions); it
ELECTRIC FIELD (kV1cm)
Figure 2-118. Typical hysteresis curve for a ferroelectric
thin film, showing several important parameters
(Dressendorfer, 199 1).
is not a basic material property since it depends
upon the applied electric field. The coercive field
(E,) is the field at zero polarization, and is a mea-
sure of the field required to switch the ferroelectric
from one polarization state to the other. It should
be noted that the values of these parameters are
unique only for a saturated hysteresis loop; paths
interior to the saturated loop can be traced out for
lower drive fields. Another important parameter for
ferroelectrics is the Curie temperature (T,), the
temperature at which the material undergoes a
transition from the ferroelectric state to a
paraelectric state. As the temperature approaches
the Curie temperature, the spontaneous polariza-
(a) Hysteresis Curve
FERROELECTRIC
CAPACITOR
P
SENSE
CAPAC'TOR T
(b) Readout Scheme
Figure 2-119. Conceptual operation of a ferroelectric
memory capacitor (Dressendorfer, 199 1).
tion decreases. Above the Curie temperature, all ety of integrated circuit technologies, although in
memory of the stored polarization state is lost. actual practice a number of difficulties in process
The conceptual operation of a simple ferroelec-
integration must be overcome, as describedbelow.
tric memory device can be understood with the aid
The capacitor can be an element separate from any
of Figure 2-119. Depicted is a hysteresis curve
others in the base technology; it can be inserted as
showing the two stable polarization states and the
a process module into the baseline technology
charge that will result from pulsing the capacitor to
flow. The elements of the capacitor are the top and
Vm. The read-out scheme for the memory is also
bottom electrodes and the ferroelectric film itself.
shown, with a sense capacitor in series with the
It may also be necessary to include barrier layers
ferroelectric capacitor. If a large positive voltage
to prevent interactions between the ferroelectric
pulse is applied to a ferroelectric capacitor and the
capacitor elements and the materials of the base
voltage returned to zero, the polarization will be in
technology. An example of the way in which a fer-
the state labeled "0." Similarly, if a large negative
roelectric capacitor might be inserted into a CMOS
voltage pulse is applied, the resulting polarization
technology is shown in Figure 2-120.
will be in the state labeled "0." If a large negative
voltage pulse is applied to the capacitor structure,
for a device in the "0" state, an amount of charge
Qo will appear on the electrode of the sense ca-
pacitor, whereas for a device in the "1" state, an
amount of charge Q1 will appear on the sense ca-
pacitor. Thus, the output signal for the two logic
states will depend upon the maximum polarization,
the remanent polarization, and the sense
capacitance.
2.10.5.1 Technology Description
The ferroelectric capacitor conceptuaIly can be
integrated in a straightforward manner into a vari-
A number of common issues arise in attempting
to integrate ferroelectrics into a baseline integrated
circuit technology, whether that technology be
bipolar, CMOS, or GaAs. The ferroelectric capaci-
tor itself presents a number of material and device
physics issues. Although there is a great deal of
literature on the characteristics of bulk ferroelec-
trics, it is not easily extrapolated to the thin films
(< 0.5 pm) that must be used in integrated circuits.
Optimization of the film is complicated by the
fact that the film preparation techniques can have a
significant impact on the resultant properties.
A number of avenues are being explored, including
FERROELECTRIC
DIELECTRIC 1
BIT LINE
Figure 2-120. Cross section of a ferroelectric capacitor memory cell (Dressendorfer, 1991).
approaches based upon various solution chemis-
tries followed by spinning the ferroelectric film
onto the substrate, sputtering, metallo-organic
chemical vapor deposition (MOCVD), cluster-ion
beam, gas-jet deposition, laser ablation, and low-
pressure chemical vapor deposition (LPCVD).
Film properties are also affected by any thermal
environments to which they are exposed. In most
cases, in order to obtain the desired perovskite
phase of lead-zirconate-titanium (PZT), a sintering
step in the temperature range of 550C to 700C
is required.
is required to effectively integrate that capacitor
into a baseline technology flow. The integration
must be performed in such a way as to minimize
adverse effects on the baseline devices from the
ferroelectric processing and likewise on the ferro-
electric devices from the baseline processing.
Since both the ferroelectric and baseline technol-
ogy require thermal treatments to achieve the
desired properties, interactions between the two
are likely to occur. Other process development and
integration issues include possible contamination
of the baseline devices from the materials in the
The electrodes used for the ferroelectric capaci-
ferroelectric devices, long-term compatibility of
tor affect its subsequent properties markedly. Much
the ferroelectric device materials, etching of the
of the work to date on PZT thin films has centered
ferroelectric and electrodes, electrode compatibil-
on the use of platinum for the electrode, although
ity and adherence, contact methodology, possible
a number of other materials are being explored.
stress effects, interactions of ambients with the
Some proprietary materials have been reported to
ferroelectric, topography reduction and control,
provide ferroelectric devices markedly improved
and packaging and assembly issues.
over those obtained with platinum. An alternative technology approach is being
In addition to the development underway for
pursued by Westinghouse Corporation. Rather than
the ferroelectric capacitor itself, significant work
using a ferroelectric capacitor as the memory
Ti =
Al
BSQ
MEMORY GATE
Al METAL 1 Al
FIELD OXIDE
FERROELECTRIC TAPERED REFLOWED
"-WELL WINDOW
p-epi
p+ SUBSTRATE
Figure 2-121. Cross section of a ferroelectric transistor in the Westinghouse 1-mm process (Larnpe et al., 1990).
element, the ferroelectric film is used as the gate
dielectric for a FET, forming a ferroelectric mate-
rial FET (FEMFET), as shown in Figure 2-121.
In this case, the silicon surface may be accumu-
lated, depleted, or inverted at zero applied voltage
to the gate electrode. Thus, the polarization state
of the ferroelectric may be sensed by determining
the threshold of the transistor (which could be en-
hancement mode for one polarization state and
depletion mode for the other state). The operation
of the memory element in full memory array
could be very similar to that of an SNOS device,
except that positive pulses applied to the gate elec-
trode lead to the more negative threshold voltage
state, and negative gate voltages result in the more
positive threshold voltage state.
2.10.5.2 Radiation Effects
Several studies of the effects of radiation on
ferroelectric capacitor structures have been re-
ported. Under constant bias, the retained polariza-
tion is reduced with ionizing radiation dose, as
illustrated in Figure 2-122. The dose level at which
this degradation is observed depends upon the pro-
cessing details of the ferroelectric film, and it can
be greater than 10 Mrads(Si) with appropriate pro-
cessing. The degradation does not appear to be af-
fected by cycling the device prior to radiation.
However, if the device is cycled during the radia-
tion, no degradation relative to unirradiated
samples is observed. The primary effect of the
ionizing radiation appears to be the alteration of
the switching characteristics of the ferroelectric,
probably from the buildup of space charge in the
device. An example of post-radiation switching
characteristics for devices irradiated under several
bias conditions is shown in Figure 2-123.
2.10.6 Summary
Currently, floating-gate memories dominate
semiconductor nonvolatile memory technology.
SNOS memories have been preferred for applica-
tions requiring radiation hardness, although there
are several companies manufacturing them for
commercial applications. Ferroelectric devices are
just emerging; it remains to be seen whether they
will make significant inroads into the overall mar-
0
10-1 1 00 101 1 02
IONIZING RADIATION DOSE (Mrads[Si])
Figure 2-122. Effect of 60~o-ionizing radiation dose
(225 rads[Si]/sec) on the switched polarization charge of
thin-film ferroelectric capacitors prepared by different
processing techniques (Schwank et al., 1990).
ket. Thin-film magnetic memories are still in the
development phase.
I 1111111l I I
VG = o
- -
-. ................... -
\ ;
. .
\ !
- 7
\ . .
- : ... .\-. ........... j.. .................. -
SNLl
-- NATIONAL '\
- ----
SNL 2 .\ ; -
-.- KRYSALIS
* \
Floating-gate and SNOS memories have very
similar performance characteristics in reading,
writing, and endurance. SNOS does not have the
same ultimate retention capability as floating gate.
SNOS may be able to scale to lower voltage opera-
tion than floating gate devices. Ferroelectric
memories offer the potential of much faster writing
characteristics than either of these two, and with
higher endurance. Retention is not yet completely
demonstrated, but it could be at least comparable.
Magnetic thin-film memories are slower reading
devices than the others. They should be able to
scale to low-voltage operation, but materials and
process considerations may limit their density.
Magnetic memories should offer very high endur-
I I
ance and retention.
The intrinsic radiation tolerance of floating-gate
memory elements is less than that of SNOS. Ferro-
electric memory elements are much more tolerant,
as are magnetic thin-film memory elements.
An overview comparison of some of the impor-
tant characteristics of these technologies is given in
Table 2-7. Note that the radiation hardness charac-
teristics given in this table represent those of the
1 1 1 1 1 1 1
Table 2-7. Comparison of several characteristics of solid-state electronic nonvolatile memory technologies.
Ionizing
Nominal Radiation Dose
Density Read Access Intrinsic
Available limea Write(W)/Erase(E) ~ndur ance~ ~e t e nt i on~ HardnessC
Technology (Mbits) (nsec) limea (cycles) (years) (rads[Si])
EPROM 16 <I00 10 to 200 p e c (W) 102 >20 10s
220 minutes (E)
FG EEPROM 4 <lo0 0.1 to 10 msec (W) 104 >20 10s
1 to 100 msec (E)
SNOS EEPROM 1 -200 0.1 to 10 msec (w) 104 >20d 106
1 to 100 msec (E)
Ferroelectric 0.016e <I00 <I00 nsec >1012(f) >20( ~ >lo7
Magnetic thin film -1,000 -200 nsec >1015(f) >20(O >lo7
Notes:
aTypical ranges.
bTypical specifications.
CExpected hardness of nonvolatile memory element; support circuitry may limit actual hardness.
d~rade-offs between endurance and retention are possible.
eUnder development.
f~rojected values, additional work necessary to verify.
Table 2-8. Properties of optical fibers (Morrow, 1986).
Frequently
Core Cladding Numerical Nominal Encountered
Type of Diagram Diameter Diameter Aperture, Attenuation Bandwidth CorKladding
Fiber of Fiber ( ~ m ) @In> NA (dBflun) (MHz-km) Sizes (pm)
Multimode, @ 50 to 400 125 to 500 0.15 to 0.4 <50 4 5 100/140,2001250,
step index 400/450
Multimode, n 30 to 75 100 to 250 0.2 to 0.3 <I0 ROO 501125,62.51125,
graded index 851125
Single mode, 3t ol O 50 to 125 -0.10 <3 at 850 nm R,000 91125
step index
Plastic-clad, n 50 to 500 125 to 800 0.2 to 0.4 4 0 <25 -
silica
Plastic n 200 to 600 400 to 1,000 -0.5 <1,000 at 650 nm - -
diation hardening of these optical fibers. A sum-
mary of the properties of optical fiber types is
given in Table 2-8.
A step-index fiber is an optical fiber that
Y
P
consists of an inner core and an outer cladding.
w"
The operation of step-index fibers is based on a
Q
difference in refractive indices between that for the
core of the fiber and that for the cladding surround-
VG = -5 volts
ing the core. The light ray entering the fiber end
will experience total internal reflection at the core-
cladding interface and propagate down the fiber [as
4
shown in Figure 2-1241, so long as the angle of re-
flection is less than the critical angle, 8,. The mag-
nitude of the total acceptance angle for light
-30 entering the fiber is usually expressed by the nu-
-1 50 0 150 -150 0 150
merical aperture NA, which is given by the expres-
ELECTRIC FIELD, E (kVlcm)
sion:
Figure 2-123. Hysteresis curves for ferroelectric thin-
1/2
NA = nlsinO, = (nf-nf) , (2.25)
film capacitors before irradiation and after irradiation
with 0-, -5, and +5-volt biases (Schwank et al., 1990).
where nl is the refractive index of the fiber core,
n2 is the refractive index of the cladding, and 8, is
the maximum angle for total internal reflection. As
nonvolatile memory element itself; a full memory
shown in Table 2-83 typical values for NA range
device may exhibit lower hardness levels (or expe-
from about 0.1 to 0.4. As might be expected, the
rience single event upset) because of the character-
larger the NA, the easier it is to couple a light-
istics of the support circuitry.
emitting diode (LED) to the fiber.
2.11 Radiation Effects on Optical Fibers and
A light pulse of a certain shape and magnitude
will, upon entering and traveling a significant dis-
Electro-Optic Components
tance through a real, nonideal fiber, experience a
2.11.1 Optical Fibers reduction in magnitude and a temporal-spreading
The rapid growth in the development of optical- of the pulse shape. The first effect is due to attenu-
fiber technology during the 1980-1990 time frame ation in the fiber, while the second is due to disper-
has led to the development of many types of opti- sion. The attempt to minimize both of these
cal fibers and significant improvements in the ra- deleterious effects has been the driving force be-
INCIDENT
LIGHT RAY
Figure 2-124. Propagation of light rays in an optical fiber.
1 0-2
10" 1 00 10' 1 o2
SOURCE SPECTRAL WIDTH (nm)
-
-
Figure 2-125. Dispersion effects for a variety of fiber types and light sources (Li, 1978).
hind continued modification and improvement of set up within the fiber with differing group veloci-
optical fibers. The operating wavelength chosen ties for each of the modes. The various group ve-
for a fiber-optic link is also often determined by locities associated with these modes lead to
the need to minimize attenuation and dispersion. dispersion (pulse broadening), which limits the in-
Hence, these effects can dictate the choice of formation bandwidth of multimode step-index fi-
source and detector. bers. The maximum difference in arrival time at
-
-
-
-
4 - LASER ---4 LED iL
STEP INDEX
-
-
--
GRADED -
-
----
SINGLE-MODE
-
- 7
-
-
-
-
-
- FIBER /
LENGTH, prn
/ /-
0.85/ /
-
-
-
- / / 1
-
- / 1.05/
-
- / /
-
I .25- / / =
-------
-
-
0 0
/
0 0
0-
0 0
0
0 0
0 -
-
0 - 0
InGaAsP 0
-
-
0 0
0
-
-
0 0
0
-
-
0 0
0
- -
0. 850 , 0q. 25
-
0 0
'.05 LENGTH, prn ,
-
0 0
0
0 0
0 -
- 0 0
0
0 0
0
0
-
0 0 0
0 I I q I I I I I I
I 1 1 1 1 1 1
Signal dispersion in a fiber, which determines
the bandwidth of the fiber, is due to modal disper-
sion and chromatic (wavelength-dependent) dis-
persion. As shown in Figure 2-125, modal
dispersion will dominate in fibers with a large NA,
which can support several different angles at which
light rays can enter the fiber. As a consequence of
the differing path lengths traveled by these rays,
several modes of electromagnetic propagation are
IT
the end of a fiber of given length increases with
NA and is typically 20 to 50 nseclkm. Since light
source coupling efficiency also increases with NA,
a compromise between efficient coupling of the
LED to the step-index fiber and the maximum
bandwidth of the fiber is required. In spite of this
compromise, multimode step-index fibers are at-
tractive and useful, especially for moderate-length
and bandwidth applications that require transmis-
sion of considerable power.
0
10-I 2 4 6 8100 10'
WAVELENGTH, h (microns)
Figure 2-126. Contributions to attenuation in glass fibers (Wolf, 1979).
Attenuation of the optical signal as it travels
through the fiber core is caused by two mecha-
nisms; scattering and absorption. Scattering
mechanisms will not be discussed in any detail
because they do not influence radiation effects in
fibers and are usually small compared with absorp-
tion phenomena. However, scattering effects do
influence the choice of state-of-the-art fibers. As
shown in Figure 2-126, scattering decreases
strongly with increasing wavelength. In recent
years, the purity and quality of fibers has reached
the point where fiber attenuation has decreased to
the scattering limit, making longer wavelengths
more desirable.
2.11.2 Radiation Effects on Fiber Optics
core. From the point of view of radiation effects,
the most important property of fibers is the absorp-
tion of light in the core of the fiber by various
types of color centers, many of which are present
prior to irradiation. Examples are shown in Figure
2-126 over a wide wavelength range and can
include intrinsic absorption mechanisms, such as
Si-0 bond-induced absorptions, and extrinsic at-
tenuation due to impurities and defects in the glass
core of the fiber. Because of the nature of fibers,
absorption is expressed in decibels per kilometer
(dB/km) of fiber length rather than in inverse
centimeters (cm-l), as is usually the case for
absomtion coefficients. The two units are related
I
as follows: attenuation in dB/km = 4.3 x lo5 x
(absorption coefficient in cm-l). Thus, an attenua-
The rmchanism for propagating the signal light
tion of 10 dB/km, suitable for'a practical fiber of
ray down the core of a long fiber immediately
moderate length, is equal to 2.3 x 10-5 cm-l, an
suggests that the most important radiation effect
exceedingly small absorption coefficient.
is radiation-induced signal attenuation in the fiber
The radiation damage mechanism in optical fi-
bers basically involves the trapping of radiolytic
electrons and holes in either preexisting or radia-
tion-created sites. The incident radiation creates
high-energy electrons, which, in turn, excite elec-
trons from the valence band. Radiolytic electrons
and holes are trapped in defect sites that arise from
preexisting material impurities or from knock-on
atomic displacement. Radiolytic, or photochemi-
cal, displacement also causes electrons and holes
to be trapped in defect sites. Radiation-created
electron-hole pairs can decay nonradiatively to
provide sufficient energy to the glass matrix to dis-
place an oxygen atom. The resulting color centers
have optical absorption in the visible near-infrared
band. These optical absorption centers result in
increased darkening (loss) as a function of wave-
length. Other specific radiation-induced degrada-
tion effects are engendered by transient ionizing
radiation and neutron irradiation. These effects are
discussed in Chapters 3 and 4, respectively.
Inspection of Figure 2- 126 illustrates the origin
of the "window" region in which fiber links are
located in order to minimize attenuation. Elec-
tronic transitions are dominant in the ultraviolet
region, while Si - 0 bond effects dominate in the
infrared region. Fortunately, these two intrinsic
mechanisms do not overlap significantly in the
wavelength range of about 0.7 to 2 pn. Within this
range, it is necessary to minimize the concentration
of impurities such as heavy metals, and
for the lowest attenuation fibers, the OH or water
content of the fiber. The combined effects of dis-
persion and OH absorption have resulted in three
"windows": 0.85, 1.3 and 1.56 pn. These windows
are illustrated in Figure 2-127 for a fiber
of moderate water (OH) content. Note the exist-
ence of the OH bands and the absorption con-
tinuum, which decreases with increasing
wavelength out to about 1.6 pm.
As illustrated in Figure 2-125, for a fiber to be
functional a difference in the core and the cladding
Figure 2-127. Attenuation in a moderate-water-content fiber morrow, 1986).
refraction indices is required. It follows, then, that
the core and cladding must be of different materi-
als. For the case of plastic-clad silica (PCS) core
fibers, or for all-silica fibers, dopants that alter the
refractive index in the appropriate direction must
be added to the glass, but yet not significantly in-
crease the attenuation in the fibers. Because impu-
rity content can dramatically affect radiation
response, the particular method used to achieve the
proper index difference is of critical importance to
hardened-fiber technology. As it turns out, most
glass dopants, such as the most popular one, ger-
manium (Ge), raise the index of silica and thus
must be used to dope the core of the fiber. The im-
plications of this for radiation hardness will be dis-
cussed in more detail later in this section. The
ultimate goal, from both commercial and rad-hard
points of view, has been to produce an all-silica
fiber with an exceedingly pure core and a doped
cladding. Only within the last decade or so has this
goal been closely approached. One of the problems
has been that very few dopants that lower the re-
fractive index of silica, and thus that can be used to
dope the cladding, are available. The emergence of
fibers with pure silica cores and fluorine- and/or
boron-doped cladding has resulted in all-glass fi-
bers with excellent radiation resistance. The intrin-
sic and extrinsic effects on the radiation response
of fiber optics are given in Table 2-9.
A fiber-optic waveguide consists of a core and
its surrounding cladding; it can be constructed
from various combinations of core and cladding.
The core can be either pure silica or doped silica.
Table 2-9. Fiber-optic parameters that affec
Pure silica provides good radiation hardness with a
high intrinsic attenuation. Ge-doped silica has
somewhat increased radiation sensitivity with low
intrinsic attenuation and easier processing. Phos-
phorous (P) doping significantly increases radia-
tion sensitivity and has somewhat higher intrinsic
attenuation, but is much easier to process; it has
decreased transient response and temperature
dependence.
The cladding can also be pure or doped silica.
Pure silica is difficult to process. Fluorine (F) or
Ge/F doping provides adequate radiation hardness.
P-doping also provides adequate radiation hard-
ness, but with optimum ease of processing.
While a detailed discussion of fiber fabrication
techniques is beyond the scope of this chapter, it is
important to note that, as in the case of Si MOS
devices, fabrication techniques can profoundly af-
fect the radiation response of the fiber. Some of the
pertinent aspects of fabrication are briefly ad-
dressed here. Essentially, the fabrication process
involves formation of an appropriate glass pre-
form, from which the fiber is then drawn in a draw
tower. A variety of methods, such as outside vapor
deposition (OVD, used by Corning) and plasma
chemical vapor deposition (PCVD, used by
AT&T), are available to fabricate a preform with
the desired layers and dopants in place. The pre-
form is then placed in a high-temperature furnace
in the draw tower, as shown in the diagram of
Figure 2-128. After the fiber is drawn, a coating is
applied to the fiber and the fiber is wound on a
:t radiation response (Friebele et al., 199 1).
Fiber Parameters System Parameters
Intrinsic
Core and cladding material
Growth method
Wavelength (extrinsic)
Light intensity (bleaching)
Temperature
Unknown impurities Injection conditions (cladding modes)
Dopant type and combinations
Water (OH) content
Stress
Ambient atmosphere (plastic fibers)
Core diameter (fat fibers are more resistant)
DOWNFEED
MECHANISM
w STRENGTH
MONITOR
Figure 2-128. Schematic of a typical draw tower for
optical fiber production (Morrow, 1986).
drum. The material properties of the preform and
many of the parameters associated with the draw-
ing process can affect the intrinsic absorption in
the fiber as well as the response of the fiber to ra-
diation. The furnace temperature profile, drawing
speed, drawing tension, and the coating process are
all influential. For example, the attenuation spec-
trum in Figure 2-129 shows a drawing-induced
band near 0.6 pm in a step-index fiber, which can
affect the radiation response of the fiber. Perhaps
one of the most important points to note here is
that preforms are in many cases manufactured by
different companies than those that draw the fibers.
In general, for data transmission applications,
losses in the range of 0.16 to 0.5 dBkm are insig-
nificant since the link distances are at most 100
km. However, in the fiber gyroscope, coil lengths
>I km are used for accuracy, and the light may
transit the coil a number of times. Thus, for this
application, transmission loss is a much more seri-
ous problem and radiation-induced degradation
must be minimal (e.g., <1 dB/km). For data-link
applications, 5 dB is acceptable for 20- to 100-
meter links (e.g., 50 to 250 dBkm).
For many military applications, the strength
characteristics of the fiber are critical to useful sys-
tem life. In addition, the mechanical properties of
the fiber and the stresses that the fiber is placed
under can affect both the intrinsic attenuation and
the radiation response of the fiber. The actual
strength of a fiber is determined by inherent flaws,
which act as stress concentrators, and by the sus-
ceptibility of the surface to corrosion by moisture
0.2 0.6 1 .O 1.4
WAVELENGTH (microns)
Figure 2-129. Drawing-induced defect absorption in an
unirradiated step-index pure silica core fiber (Pinnow,
1973).
and other ambient elements. With appropriate coat- shown that micrometeorites can severely damage
ing and cabling techniques, fibers can be made that uncabled, exposed fibers in the space environment.
have very good strength for even highly stressful
applications. Evidence for this is exhibited by the
recent successes of various tethered weapon-devel-
opment programs, such as the fiber-optic guided
missile (FOGM) program.
Bending losses are also a serious source of prob-
lems under certain conditions. Macrobending loss,
in which the fiber is wound or bent at a radius less
than approximately 10 times the fiber diameter,
can significantly increase the total intrinsic attenu-
ation; in addition, it can result in more rapid radia-
tion-induced accumulation of attenuation losses.
Microbending losses, due to dimensional fluctua-
tions along the corelcladding interface induced
during drawing, can also affect attenuation and the
susceptibility of the fiber to externally applied
stresses. Finally, it is interesting to note that evi-
dence from the recent recovery of the long-dura-
tion experiment facility (LDEF) space vehicle has
Regarding radiation effects in fibers, the analog
of lattice damage effects in semiconductor devices,
which is important in a neutron environment, is not
particularly significant in fibers for typical neutron
or proton requirements for military and space ap-
plications. The reason for this is that the glass
structure is already a highly disordered structure
and does not exhibit the perfection of the semicon-
ductor lattice, which is so easily perturbed by lat-
tice damage. Thus, the focus for radiation effects in
fibers is transient and permanent attenuation in-
duced by ionizing radiation. These effects are illus-
trated in Figure 2-130, which shows the change in
transmitted optical signal level caused by a 1-krad
dose from a 50-nsec-wide x-ray pulse. It is impor-
tant to note that the time scale along the abscissa in
Figure 2-130 is logarithmic and is not to scale; a
typical radiation pulse width is 20 nsec. During
irradiation, the signal level increases due to lumi-
TIME 4
Figure 2-130. Schematic drawing of time-dependent effects in an optical fiber during and after exposure to ionizing radia-
tion [the time scale is logarithmic] (Sigel and Evans, 1974).
RADIATION BURST --)
LUMINESCENCE
PERMANENT
ABSORPTION
INITIAL
LIGHT LEVEL
RECOVERY
. . . .
............
. . . . . . . . . . . .
. . . . .
.........
. . . :. ....
..... : .;.
:.
........
".':"
MAXIMUM TRANSIENT
. . . ABSORPTION
...............
. . . . . . .
... : . : ......a,...
. . . .
: ...........
. . . . . . . . .
. . . . . . . . .
. . . .
. . . :.;..: .:.
. . . . .
. . . . . . . . . . .
'.: ::: ::.. :'. .:.
.......
.....
....
...:::. .....
. . . . . . . . . . .
. . . : . ....
.:.
............
. . .
... :.: ; ..-:::: .;.:
.....
. . . .
. . . .
..:.. I . . . . .
. . . . . . . . .
. . . :....
nescence generated in the fiber. Immediately after
the peak of the x-ray pulse, the signal level de-
creases and becomes less than the pre-irradiation
level due to radiation-induced color-center absorp-
tion. The signal level continues to decrease for
some time after the radiation pulse. The attenua-
tion then anneals with time to some permanent
value. Typically, the absorption remaining 24 hours
after irradiation is considered "permanent." Conse-
quently, the demarcation between "transient" and
"permanent" attenuation is somewhat arbitrary and
usually highly dependent on the ambient
temperature.
The rate of growth of permanent ionizing-radia-
tion-induced attenuation in fibers varies greatly,
depending on the characteristics of the fiber. Early
fibers fabricated from ordinary glasses like Pb-
silicate exhibit very strong radiation-induced at-
tenuation, as shown in Figure 2- 13 1. Note that for
these early data, results at the second and third
windows are not even shown because at that time
(mid-1970s) only the first window (near 0.85 mm)
was used as an operating wavelength. Also, note
that emission spectra of some LEDs are given, as
well as Si detector responsivity. The fibers near the
top of this figure show very rapid attenuation
PHOTON ENERGY (eV)
6 5 4 3 2 1
1 0 2 % ~ I I , I
-
-
-
- -
-
-
-
-
-
-
-
-
-
-
Na-Ca-SILICATE (NRL)
-
-
-
-
' ' - - - , , SiO2:B2OXSiO2 (BTL) -
-
i02(Ge):SiOp (CGW) =
-
-
-
-
-
-
LEDs:GaAsP G
0.2 0.4 0.6 0.8 1 .O 1.2
WAVELENGTH (microns)
Figure 2-131. comparison of 60~o-induced attenuation in a variety of high- and low-loss fibers and glasses 1 hour after
irradiation (Sigel and Evans, 1974).
buildup; the attenuation is normalized to dose so
that these fibers exhibit more than 1 dB/km for
each rad of exposure.
More recently, a great deal of progress has been
made in developing radiation-hardened fibers, ac-
companied by the accumulation of a large body of
data on radiation behavior of fibers. Several impor-
tant features of the response of fibers to 6 0 ~ o -
irradiation are shown in Figure 2-132 for both
doped and undoped core fibers 1 hour after expo-
sure to 100 krads. Since dopants are usually in-
volved in the formation of various types of
radiation-induced color centers, it is not surprising
that the results in Figure 2-132 indicate a wide
variation in induced loss, depending on the dopants
in the fiber core [Suprasil and Suprasil W are pure
core fibers]. The highest losses were observed in
the multiply-doped fibers, while the lowest in-
WAVELENGTH (microns)
Figure 2-132. Induced attenuation spectra for a variety
of doped and pure silica core fibers at room temperature
1 hour after 100 krads 60~o-irradiation [note that both
boron and phosphate doping increase the infrared at-
tenuation] (Friebele and Gingerich, 1980).
duced attenuation is in the pure core fibers. Note
that with the exception of the boron and phospho-
rus co-doped fibers, the loss is inversely propor-
tional to wavelength. This can generally be
attributed to the fact that the absorption peak for
many color centers, in particular for the E; center
associated with Ge, is located in the ultraviolet
(UV) portion of the spectrum. Thus, the general
shape of the spectra in Figure 2-132 is due to the
strong absorption tail from these centers in the UV.
Comparison of the Ge-doped Bell Telephone
Laboratories (BTL, also AT&T) fiber with the Ge-
doped Corning (CGW) fiber indicates that the
dopant alone does not determine the fiber radiation
response, a result that is not too surprising. Of par-
ticular interest is the fact that the BTL fiber has
very low loss at 1.5 pm after 100 krads exposure.
Present-day AT&T fibers are even better at this
wavelength. One reason this is significant is be-
cause a graded-index fiber cannot be fabricated
without using a core dopant [see Figure 2-1241,
and such fibers are an attractive compromise be-
tween multimode, step-index fibers and single-
mode fibers. While the BTL fiber is comparable to
the undoped core fibers at 1.5 pm, it is clear that
for large radiation doses the undoped core fibers
are definitely superior to Ge-doped fibers. The at-
tenuation growth in the former is linear with dose
to quite high doses, while the growth of attenuation
for the latter fiber type is highly sublinear with
dose. One result of this is that for low dose appli-
cations (less than a few krads), Ge-doped fibers
actually experience less attenuation loss. The satu-
ration of the attenuation with increasing dose in the
undoped core fibers is a general characteristic of
these fibers, and is responsible for their excellent
radiation hardness at high doses.
An important process that takes place in fibers
during and after 60~o-irradiation (as suggested by
the result in Figure 2- 130) is color-center anneal-
ing. At low dose rates in pure core fibers, the re-
covery of attenuation during irradiation strongly
mitigates the loss process and results in a rad-hard
fiber. The competition between annealing and for-
mation of an easily saturable color center, as for
the RayChem fiber in Figure 2-133, can result in
-
-
QSF F1 CLAD-HIGH OH
-
0 1 2 3 4 5 6 7 8
IRRADIATION TIME (minutes)
Figure 2-133. %o-induced attenuation at -55C and 0.82 pn in a variety of pure core fibers clad with polymer (PCS) or
fluorosilicate (Fl), or a germanium-doped core (standard Coming fiber); dose rate = 4.1 kraddmin (Barnes, 1982).
actual decreases in attenuation as irradiation pro-
ceeds. As might be expected, the balance between
annealing and color-center growth depends on the
dose rate so that the observed saturation level var-
ies with dose rate. This general result is shown for
pure-silica core fibers with different coating mate-
rials in Figure 2- 134. Note that the saturation level
for 300 radslmin is lower that for the higher dose
rate of 1,300 radslmin. For the polyirnide-clad fi-
ber, the extrapolated attenuation at 1 Mrad is well
under 20 dB/km, indicating that this fiber has ex-
cellent radiation hardness. The variation in attenu-
ation with coating type was a somewhat
unexpected result. It was concluded that since the
attenuation takes place in the fiber core, the varia-
tion with coating material was not due to the coat-
ing itself, but rather to the effect of the coating
application process on the core characteristics.
index, pure core fiber are shown in Figure 2-135
for operation at 0.85 pm and irradiation at 22 radsl
sec. Note that the induced attenuation is much
larger at -55OC and decreases with increasing tem-
perature. Because of the greater annealing at 65OC,
the saturation in the loss is reached at only a few
krads. In general, as might be expected, the anneal-
ing rate is less at lower temperatures. However, not
surprisingly, there is an important exception to this
rule, as shown in Figure 2-136 for several different
fibers operating at 0.8 pm and irradiated to 2 krads
at a rate of 95 radslsec. Note that while most of the
fibers show the expected behavior, the fibers con-
taining phosphorus show the opposite effect; i.e.,
greater induced loss is experienced at higher tem-
peratures. It was noted in the discussion of Figure
2-132 that P-doping caused fibers to have some
unique properties in their response to irradiation.
Returning to Figure 2-133, an important feature
Generally, P-doped core fibers exhibit greater per-
of these data, related to annealing effects, is that
manent radiation-induced attenuation, other things
they were all taken at -55OC, where the annealing
being equal, compared to similar fibers without
rate is much less than at room temperature. Com-
phosphorus. However, as noted in the summary of
parative results at different temperatures for a step-
30 -
I I l l l l l l l I I l l l l l l I I1111111 I I111111
25
-
0 I I1111111 I I1111111 I I 1 1 1 1 1 1 1 I I l l l l l L
l o ~ 2 4 68102 103 104 1 05
IONIZING RADIATION DOSE (rads[Si])
Figure 2-134. %o-irradiation of pure silica core fibers illustrating the effect of fiber
coating on radiation response (Barnes, Greenwell, and Nelson, 1987).
300
I 1 1 1 1 1 1 1 1 1 1 1 1 1 I 1 1 1 1 1 1
OPERATING WAVELENGTH = 0.85 micron
AVERAGE PULSE POWER = 1 nW
250 - DOSE RATE = 22 radslsec
n
Z
50
-
1 02 103
IONIZING RADIATION DOSE (rads[Si])
Figure 2-135. 60~o-irradiation of step-index fibers at various temperatures (Greenwell, 1989).
2 krads(Si02)
DOSE RATE. 95 radslsec i
TEMPERATURE ("C)
transient radiation effects [Subsection 2.11.41,
phosphorus is not all bad; its presence in the fiber
core kills the strong transient attenuation observed
immediately after a radiation pulse [see Figure 2-
1301.
It was noted earlier that the OH absorption
bands in the 0.8- to 1.6-pn range restrict fiber op-
eration to certain wavelengths, commonly re-
ferred to as "windows." Thus, from the point of
view of intrinsic losses, high OH content is unde-
sirable. However, as shown in Figure 2-133, high-
OH-content fibers exhibit less radiation-induced
attenuation than low-OH-content fibers, and a
compromise between these two effects must be
made. It is noteworthy, however, that recently de-
veloped high-purity core fibers with low OH con-
tent have achieved hardness levels similar to those
observed with high-OH fibers.
All of the radiation-induced attenuation data
examined thus far in Figures 2-133 through 2-136
have been for fibers operating near 0.8 pm. In the
discussion of the spectral loss data in Figure 2-132,
it was noted that, with the exception of fibers
Figure 2-136. Effect of temperature on the ionizing-ra-
diation-induced attenuation in various fibers (Share,
containing boron and phosphorus, the induced
1981).
losses were much less at longer wavelengths. This
101 1 02 I 03
IONIZING RADIATION DOSE (rads[Si])
Figure 2-137. 60~o-irradiation of single-mode fibers at 22 radslsec showing induced attenuation at the first-, second-, and
third-window wavelengths (Greenwell, 1989).
result is generally true, and is shown to be the case
in Figure 2-137 for single-mode fibers 6 0 ~ o -
irradiated at 22 radslsec at room temperature. Note
that a difference by a factor of about 10 exists in
the induced attenuation at 10 krads between 0.85
and 1.55 pm. Thus, from the standpoint of radia-
tion hardness, longer operating wavelengths are
more desirable unless for some reason, the fiber
must contain phosphorus [see Figure 2-1321.
only a minimal effect in Ge-doped fibers. Photo-
bleaching also offers the possibility of compensat-
ing for the lack of annealing that occurs at lower
operating temperatures. An example of this effect
is shown in Figure 2-138 for a pure-silica core fi-
ber operating at -55C and 0.872 pm. Both irradia-
tion and recovery curves are shown as a function
of light power level present in the fiber during ir-
radiation and anneal. [A dBm is defined as 10 log
Thus far, pure-silica core fibers operating at
(PI1 mW), i.e., the log of the LED power normal-
long wavelengths have been observed to offer the
ized to a reference power of 1 mW.] Note that at
greatest radiation hardness for exposure to steady-
very low powers, the induced loss is high, but that
state ionizing radiation. In fact, further radiation
at the maximum power level, the attenuation at 10
resistance can be achieved in these fibers by taking
krads is less by a factor of about 7. Hence, by turn-
advantage of photobleaching. In these fibers, it is
ing on the LED, annealing similar to that at higher
temperature can be achieved during irradiation.
possible to include additional color-center anneal-
*
ing by merely allowing the signal-generating LED A relationship that describes the recovery of the
or laser to remain on during and after the irradia- radiation-induced attenuation of single-mode opti-
tion. The light-induced anneal of absorbing centers cal fibers has been developed by Friebele et al.,
is termed photobleaching. While this is a signifi- (1991). This relationship is made possible due to
cant process in pure core fibers even at the longest the significant correlation between certain optical
wavelength of the third window (1.55 pm), it is fiber fabrication parameters of matched-clad,
second minute hour
l i
100 101 102 103 1 0 4 1 0 ' ~ lo0 lo1 lo2 lo3 lo4 lo5
IONIZING RADIATION DOSE (rads[Si]) TIME (seconds)
Figure 2-138. Radiation-induced loss in a single-mode, low-OH fiber during irradiation at -55OC and after
irradiation to 10 krads(Si) (1,300 rads[Si]/min) at several light output power levels at 0.872 pn (Evans, 1988).
single-mode fibers and the induced attenuation and
recovery kinetics following exposure to ionizing
radiation. The equation depicting this attenuation
and recovery is:
A, = ( A ~ - ~ ~ ) ( l - ~ t ) - ~ + Af , (2.26)
where:
A, = initial attenuation
Af = final attenuation
c = (l/t)[(2)ltx- 11 (where z is the
half-life of incremental loss)
a = time
x = l/(n-1) (where n is the
kinetic order of recovery).
Excellent agreement between the data and the
curve fit has been obtained for a number of optical
fibers, as shown in Figures 2-139 and 2-140. This
relationship has made it possible to predict the ra-
diation-induced response of an optical fiber from a
knowledge of the fiber's fabrication parameters.
2.11.3 Radiation Environments
Two radiation environments - natural space
and a nuclear-weapon-enhanced space environ-
ment - are discussed here and their impact on
optical fibers addressed.
2.11.3.1 Natural Space Environment
The slow accumulation of ionizing radiation
dose to tens of krads(Si) at low dose rates* will not
significantly affect any optoelectronic components
except for the optical fiber. Even in the case of fi-
bers, if a prudent choice of a rad-hard fiber is made
and the optimum operating wavelength of 1.3 pm
is employed [1.55 pm is also good if no phospho-
rus is in the fiber core], the losses will not consti-
tute fiber-optic system failure, even for fiber
lengths approaching 1 km. At low dose rates, a
pure core fiber such as the one shown in Figure
2-134 will exhibit a saturation in induced attenua-
tion at low levels of attenuation. As noted earlier,
the dynamic balance between color-center growth
and anneal is responsible for this saturation effect.
Thus, as the dose rate decreases the net attenuation
will also decrease.
In summary, it can be stated that the natural
space environment for ionizing radiation dose con-
siderations is not particularly difficult to satisfy if
a properly chosen fiber-optic system is employed.
2.11.3.2 Strategic Radiation (Combined Nuclear
Weapons and Natural Space) Environment
Depending on the particular military program,
strategic radiation requirements can vary signifi-
cantly. Due to prompt gamma rays and other
6 8 10 12 14 16
ANALYZED CORE (Ge)
4 6 8 10 12 14 16
CORE OXYGENIREAGENT RATIO
(a) Initial Attenuation, A, (b) Final Attenuation, Af
Figure 2-139. Estimated effects of initial and final attenuation on core (Ge) and oxygen-to-reagent ratio used during core
deposition (Friebele et al., 199 1).
*Solar flare dose rates for protons can reach 1 rad(Si)/sec, but these rates last for a maximum of 1 day, usually less.
4 6 8 10 12 14 16 4 6 8 10 12 14 16
CORE OXYGEWEAGENT RATIO CORE OXYGEWEAGENT RATIO
(a) n Versus Core Oxygen (b) z Versus Core Oxygen
Figure 2-140. Estimated effect of kinetic recovery order and half-life of incremental loss on the two-way interaction of core
oxygen-to-reagent ratio and draw speed (Friebele, et al., 1991).
sources of ionizing radiation released during the
detonation of a nuclear weapon, the ionizing radia-
tion dose requirement of 0.1 to l Mrad(Si) is much
more stringent than that from the natural space en-
vironment. In addition to the Si integrated circuits
in transmitters and receivers, these dose levels can
pose serious problems for optical fibers. If doped
core fiber, such as a Ge-doped core telecornmuni-
cations fiber, is used and the fiber is relatively long
(100 meters to 1 km), then the attenuation will
continue to increase linearly with dose as shown in
Figure 2-133 and can become prohibitively large in
a long fiber. Thus, a pure core fiber must be em-
ployed, if possible, so that the saturation effects
shown in Figures 2- 133 and 2-134 can be taken
advantage of in the application. For large ionizing
radiation dose requirements, an operating wave-
length of 1.3 or 1.55 pm should be chosen and the
fiber core should not contain any phosphorus. In
addition, the fiber should have polyimide as a pri-
mary coating because this improves the ionizing
radiation dose hardness; if the coating is perma-
nent, the polyimide increases reliability. Finally,
the fiber-optic system should be examined for any
epoxies or lenses in the light path that can darken
easily. If the material darkens very easily, as some
epoxies do, and the dose is very large (1 Mrad[Si]),
then such optical elements should be avoided.
Table 2-10. Impact of system requirements on fiber choice.
System Requirements Fiber Behavior Candidatesa
Minimum down time (<I msec) Minimum transient absorption
High ionizing dose (unmanned -
missile, satellite)
Moderate ionizing dose (manned -
aircraft, ground links)
Si02 core (PCS, all glass)
Si02 core, Ge-Pdoped silica
core
Low to moderate dose rate (1 second Good long-term recovery Si02 core (Ge-doped silica core
down time) (manned - fallout,
without P), silicate plus Ge,
reactor environs, space ambient) plastic
Neutron flux (weapons, reactor) Boron-free core and cladding Si02 core (F-doped silica or poly-
mer clad), binary Gedoped
silica core -Si02 clad
Note: Thoice depends upon system architecture, attenuation, and bandwidth requirements.
2.11.4 Summary
A few important conclusions summarize radia-
tion effects on fibers:
1. Considerable progress has been made in
developing radiation-hardened fibers;
these fibers are now available.
2. No single fiber type will optimally satisfy
all performance and environmental re-
quirements. Thus, the system perfor-
mance requirements and the
environmental requirements must be de-
fined before a fiber can be selected. Table
2-10 relates cable selection criteria.
3. An undoped core fiber (which eliminates
graded-index fibers) with a high OH con-
tent and a polyimide buffer coating most
closely satisfies all environmental require-
ments.
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THIS PAGE INTENTIONALLY LEFT BLANK.
CHAPTER 3
IONIZING DOSE RATE EFFECTS ON
SEMICONDUCTOR MICROELECTRONICS
3.1 Diode Transient Radiation Response
Transient ionizing dose effects include "dose-
rate," or "gamma-dot ( j ) ," phenomena as well as
single-event phenomena. Dose-rate phenomena
are usually associated with x-ray and gamma-ray
radiation produced by the detonation of nuclear
weapons, which can subject an entire system (in-
cluding active and passive electronic devices and
the associated packaging and mounting - e.g.,
printed circuit board-material) to ionizing radia-
tion. One specific effect of the transient radiation
is to generate very high hole-electron densities
that result in photocurrents in semi- conductor
devices. These photocurrents can engender a num-
ber of deleterious effects, ranging from temporary
upset to burnout (destruction) of an integrated
circuit (IC).
In general, the threat addressed in this chapter
is the result of relatively short radiation pulses,
40 nsec to 1 psec in duration, with high dose-rate
values (e.g., >lo9 radslsec). The most common
units for expressing the amplitude of the dose-
rate exposure are rads(M)lsec, where M refers to
the material absorbing the radiation. Single-event
phenomena (SEP) are generally expressed in
terms of critical charge (Q,) at a junction in Cou-
lombs, and the linear energy transfer (LET)
expressed in MeV-cm2/g.
The following, more detailed, discussion of
these transient ionizing dose effects will initially
concentrate on the response of discrete devices,
e.g., diodes, silicon bipolar transistors, metal-
oxide semiconductor field-effect transistors
(MOSFETs), and gallium arsenide FETs. The
discussion is then extended to address the re-
sponse of complex integrated circuits, e.g., static
random access memories (SRAMs), micropro-
cessors, etc.
The key to understanding photocurrent pro-
duction is understanding the radiation response
of a reverse-biased pn junction. Simply stated,
the photocurrents in a reverse-biased junction are
the sum of three distinct components (Wirth and
Rogers, 1964), and can be separated into (I)
minority-carrier hole transport across the junc-
tion from the n-type silicon, (2) minority-carrier
electron transport across the junction from the p-
type silicon, and (3) the current resulting from
electron-hole pair generation in the depletion re-
gion. Minority carriers are transported by diffu-
sive transport and electric-field-aided drift.
Physically, the photoresponse is the result of
carrier generation throughout the diode at a rate
G = go j hole-electron pairs/cm3-sec , (3.1)
where go is the generation constant (4.2 x loi3
hole pairs/cm3-rads[Si]), and j is the absorbed
dose rate in the bulk semiconductor of the diode
in rads(Si)/sec.
The two critical concepts in diode photo-
response are the physics of the generation of pri-
mary photocurrent and the concept of a carrier
collection volume around the pn junction, which
determines the magnitude of the photocurrent.
When the diode junction is reverse-biased, a
large electric field is established in the junction,
which sweeps minority carriers across the deple-
tion region and holds the minority-carrier den-
sity at the edges of the junction close to zero [see
Figure 3-l(a)]. Far from the junction (i.e., many
minority-carrier diffusion lengths), the radiation-
induced carrier generation and minority-carrier
recombination are in steady-state equilibrium.
The hole and electron carriers generated in the
depletion region constitute a current that is in
phase with the incident transient radiation pulse.
This prompt photocurrent I, flows from the n- to
the p-region since holes are swept into the
p-region and electrons into the n-region.
On the average, only carriers within one diffu-
sion length, i.e., L, = (Dn~,)lJ2, on each side of
the junction are collected, where D, = carrier dif-
fusion constant and T, = carrier lifetime. Carriers
beyond one diffusion length have a high prob-
ability of recombining before reaching the junc-
tion and contribute little to the photocurrent.
Because of the increase in minority-carrier
density gradients at the junction due to the onset
- BEFORE PULSE
----AFTER PULSE
TRANSITION
(a) Reverse-Biased Diode
TRANSITION
REGION
A
p-REGION 0-0- n-REGION
(b) Forward-Biased Diode
Figure 3-l(a, b). pn junction minority-camer densi-
ties prior to and immediately after an incident pulse of
ionizing radiation (Wirth and Rogers, 1964).
of the radiation pulse, the corresponding diffu-
sion gradients increase, thereby enhancing the
diffusion of carriers toward the junction. Thus, a
portion of the carriers remote from the junction
diffuse toward and reach the junction with a cor-
responding delay time. This current is often
called the delayed component of photocurrent, Id.
Both I, and Id are transient currents superim-
posed on the usual leakage currents.
In the case of the forward-biased junction, the
applied bias does not completely cancel the
depletion-region field potential. Hence, an elec-
tric field is still maintained in the junction neigh-
borhood, so that a prompt photocurrent will flow
from the n- to the p-region. As seen in Figure
3-l(b), the carriers produced in the bulk material
decrease the carrier density gradient at the junc-
tion, resulting in a decrease in the forward con-
duction current. The total current can now be
defined as the normal conduction current plus the
prompt and delayed photocurrents that flow from
the n- to the p-region.
The excess minority-carrier densities in the p-
region are
An = goyt,, (3.2)
and in the n-region are
With an increase in carrier densities far from
the junction and the densities held to zero at the
junction, carrier diffusion will cause an increased
diode current in the reverse direction. To a good
first-order approximation, the low-voltage re-
verse-biased photocurrent can be included in par-
allel with a dc electrical model of the diode, as
shown in Figure 3-2. If the electrical model of
the diode includes conductivity modulation as
well as reverse breakdown, the radiation-inclu-
sive model represents the overall photoresponse
of the diode over a wide range of dc conditions.
An explicit solution of the photocurrent flow-
ing across the junction is difficult to obtain since
it requires solving the continuity equation, with
excess minority-carrier concentration and life-
time and electric field in the quasi-neutral region
dependent on each other. However, a closed solu-
tion can be generated if simplifying assumptions
A
I (mA)
I
-
NORMAL
- - STEADY-STATE RADIATION EXPOSURE
---- HIGH TEMPERATURE
Figure 3-2. pn junction diode radiation-inclusive,
steady-state current-voltage (I-V) characteristic
(Raymond, 1985).
are made such that: (1) the diode has one-dimen-
sional geometry, (2) no conductivity modulation
exists, (3) the diode has negligible electric field
and is uniformly doped except at the junction,
and (4) the voltage across the junction is con-
stant.
Based on these assumptions and for a constant
applied bias Vo to the junction, the resulting
relationship for the total primary photocurrent,
Ipp = Ip + Id, is
For the case of present interest, that of a rectan-
guIar ionizing radiation pulse of amplitude
G = go j. and width tp, Equation 3.4 reduces to
Ipp = ~ A G [ W, + L, erf (K)
and
1, = ~AG(L, {erf [dt/Zn]
where
e = electron charge
A = junction area ( ~ m- ~ )
go = generation constant for the material
j. = dose rate (rads[Si]/sec)
Wt = depletion-region width (cm)
L, = diffusion length (cm) for electrons =
(Dn tn)lI2
t = time
Lp = diffusion length (cm) for holes =
(D, ~ p ) " ~
tp = radiation pulse width
and
The depletion-region width W, represents the
prompt-component collection length; the sum of
the error function (erf) terms represents the
delayed, diffusion-component collection length.
Figure 3-3 depicts the primary photocurrent
PULSE DURATION: 0.1 psec -
TOTAL DOSE: 0.56 rad(Si)
0 0.05 0.10 0.1 5 0.20
TIME (psec)
Figure 3-3. Primary photocunent for the 2N2051 col-
lector-base junction (Wirth and Rogers, 1964).
obtained from Equation 3.5 and compares it with
that obtained from experimental flash x-ray data.
For very short radiation pulse widths, where tp
is very small compared with the minority-carrier
lifetimes 2, and z, , then from Equation 3.5, the
photocurrent is given by
and
- -- eAGtp
J;;r (a"""
The product Gtp is the total photocurrent carrier
density generated during the incident radiation
pulse and, of course, is proportional to the total
incident dose. In many devices, T~ and z, are
small, and corresponding terms in Equation 3.6
can be neglected. For steady-state photocurrent,
such as from nuclear power reactor gamma rays,
it can be seen from the previous discussion that
the steady-state photocurrent I,, is given from
Equation 3.5a (unbounded time) as
Subsequent to the development of the Wirth-
Rogers model [Equations 3.5 through 3.71, an
enhanced model (Enlow and Alexander, 1988)
was developed that provides a more accurate rep-
resentation of some devices because it includes
the effect of the electric field in the quasi-neutral
region and high-injection effects on minority-
canier lifetime. The difference in the prediction
of a diode response between the enhanced and
the Wirth-Rogers models is shown in Figure 3-4.
The cause of the difference is the result of an ef-
fective increase in photocurrent collection vol-
ume, which is engendered by the inclusion of
electric field and high-injection excess minority
carriers. Figure 3-5 compares predicted and mea-
sured response for two diodes using the enhanced
model.
Figure 3-4. Normalized photocurrent as a function of
dose rate, demonstrating the nonlinearity of the en-
hanced photocurrent model (Enlow and Alexander,
1988).
3.2 Diode 'Ihnsient Radiation Response
Further insight concerning the transient radia-
tion response of a diode may be obtained by con-
sidering an equivalent circuit that will provide an
approximate model of this response. The de-
velop-ment of this model is the primary objective
of this section.
Extension of the diode model to the transient
photoresponse is essentially a modification of the
electrical model to include transient effects and
TIME (nsec)
(a) Diode 1
0 50 100 150 200
TIME (nsec)
(b) Diode 2
Figure 3-5 (a, b). Measure and predicted waveforms (100 nsec) normalized to the peak of the measured waveform at
5.0 x lo9 rads (Si)/sec (Enlow and Alexander, 1988).
the definition of a time-dependent primary photo-
current, as shown in Figure 3-6. The accuracy of
the model depends principally on the accuracy of
the electrical model parameters. The time depen-
dence of the reverse-biased diode photocurrent
$&t) is determined by delays associated with car-
rier motion to and through the junction. As with
the diode steady-state photocurrent, the key con-
cepts are the first-order, radiation-inclusive diode
model and the effective carrier-collection vol-
umes that determine the magnitude of the diode
photocurrent. The magnitude and time depen-
dence of the diode photocurrent is the composite
of depletion layer and bulk semiconductor ef-
fects. id = I , [exp(qVD/mkT) - 11
Carriers generated in the depletion region will
essentially be swept out immediately (t < 1 nsec)
and represent the prompt photocurrent compo-
nent that essentially follows the radiation pulse,
Cd = DIFFUSION CAPACITANCE = f (Id)
CT = DEPLETION CAPACITANCE = f (Vn)
-
Ipp(t) = REVERSE-BIASED PHOTOCURRENT = f (y, VD)
rb = DIODE BODY RESISTANCE
(3.8)
I , = REVERSE SATURATION CURRENT
Since the depletion layer width is a function of
a
the reverse-bias voltage, circuit effects on the
voltage may modulate the photocurrent.
Figure 3-6. Radiation-inclusive diode transient model
(Raymond, 1982).
. .
Carriers that diffuse to the junction from a long,
bulk region exhibit an
(where L is the length of the bulk region) in
function time dependence of the form
response to a step function in radiation intensity
I, (t) = q ~ ( t ) ~ L er f ( t / ~) "~ ,
(3.9)
yu(t) (Brown, 1960). The decay of this diffusion
component following the end of a square radia-
tion pulse is
for t > t,.
Typically, the peak photocurrent of an ideal
p+n diode is the sum of a large but slow diffusion
component from the long, lightly doped n-region,
a smaller but fast component from the depletion
layer, and a small and relatively fast diffusion
component from the heavily doped p+-region. A
\ PULSE RESPONSE WITH
\\PROMPT AND DIFFUSION
0.2
PROMPT SATURATION
-9-
---
i'o I
STEP
\PULSE
Y I I I
0 0.5 1 .O 1.5 2.0 2.5
NORMALIZED TIME, V4
diode photocurrent response with prompt and
Figure 3-7. Ideal diode photocurrent response
diffusion components is shown in Figure 3-7. (Raymond, 1985).
The dashed line shows the response if the radia-
tion is cut off at some time - a pulse rather than
a step function. The error function is shown in
Figure 3-8 for convenient reference.
The time-dependent photocurrent is a relatively
complex function for an arbitrarily shaped radia-
tion pulse. Fortunately, it can be approximated
for radiation pulses that are either long or short
compared to the minority lifetime. The longest
photoresponse will be approximately equal to the
NORMALIZED TIME, Vz
steady-state photocurrent. If the radiation pulse is
short compared to the minority-carrier lifetime,
the peak diffusion photocurrent from a long, uni-
formly doped semiconductor region can be
approximated as
The variation in peak diffusion photocurrent with
the radiation pulse width is shown in Figure 3-9.
In terms of an effective collection volume for the
narrow-pulse approximation, the pulse width 5
replaces the lifetime z with an increase of about
Figure 3-8. Error function of ( t / , ) I n versus t,k
(Raymond, 1985).
proximate value inferred fiom the diode electri-
cal recovery time.
For a p+n diode, the lifetime and volume of the
p+-region might be small compared to the radia-
tion pulse width, while comparatively long for
the n-region. In this case, the peak diode photo-
current is expressed as
13 percent in the coefficient for the small-
argument approximation of the error function.
Ipp(peak) z q g o j ~ [ ( ~ n T, ) " ~ + Wt
The approximate lifetime can be based on the ap-
+ ( ] (3.11)
h
where @, ~, )l / ~ is the diffusion carrier collection tocurrent generator still increases with radiation
length for the p+-region, W, is the depletion layer
intensity despite limitation of the diode current
width, and the last term of the equation is the ef-
by the circuit. In this case, the diode saturates
fective carrier collection length in the n-region.
and is internally fomard-biased by the photocur-
rent. The diode recovery time can be determined
The expressions for transient photocurrent
by considering the time-dependent photocurrent
have been based on carrier diffusion from uni-
as the fomard-biased current, and the circuit cur-
forrnly doped regions. The presence of the built-
rents as the reverse current.
in field due to variations in doping level modifies
the carrier collection volume and time depen-
dence of the transient photocurrent.
In some circuit applications, the circuit time
constants are long compared to the total photo-
current pulse width. In this case, the total charge
Qpp in the photocurrent pulse is the critical circuit
parameter. For a narrow-pulse exposure of the
p+n diode, this charge can be expressed as
1
At high pulsed-ionizing-radiation levels it can
be assumed that the magnitude of the diode pho-
It is a misconception to assume that the photo-
currents "short out" a diode during a high-level
radiation exposure. The difference between the
"shorting" concept and the true diode recovery
behavior can be critical in a survivable circuit
design.
The diodelcircuit photoresponse at extremely
high-intensity ionizing radiation exposure can
result in sufficient power dissipation to cause
permanent damage. Damage may be a result of
either metallization or junction burnout in a
single-junction diode. The energy required to
damage a diode has been established by exten-
sive characterizations using electrical overstress.
The energy necessary to cause device damage is
RADIATION PULSE WIDTH/MINORITY-CARRIER LIFETIME RATIO, tp/T
101
Y
I
n
A
n
0.
e.
Figure 3-9. Peak diode photocurrent as a function of radiation pulse width (Espig, 1985).
L
- I 1 1 1 1 1 1 1 I I 1 1 1 1 1 1 1 I I I1 I I l k
- -
- -
- -
- -
- -
- -
....................... -.. .................................. .:.
q ~ g , j ( DT ) ~ J ~ , STEADY-STATE VALUE
-
-
-
W -
a
- -
a
- -
3 -
-
-
-
n
........................ -
-
-
-
-
-
-
-
i NARROW-PULSE
-
STEADY-STATE
2 - i APPROXIMATION APPROXIMATION -
IO-2 I I I I I I I ~ I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
lo-3 4 6 810-2 lom1 1 o0 lo1
much greater than that directly absorbed from the
radiation environment. Diode burnout then de-
pends on energy absorbed from the associated
circuitry and its power supplies.
The most sensitive configuration for diode
burnout is with a reverse-biased diode connected
between the supply voltage and ground [Figure
3-10]. Power dissipation in the diode resulting
from a high-intensity ionizing-radiation pulse
will be:
where r,, is the diode body resistance, vd is the
diode junction voltage, and V is the diode reverse
voltage. The approximate radiation exposure
necessary to damage a diode in this configuration
can be calculated by assuming that the current
pulse is the peak photocurrent for the duration of
the radiation pulse. For a p+n diode, the photo-
current contribution is principally for the n-re-
gion and the depletion layer. For the condition
where the radiation pulse width is short com-
pared to the n-region lifetime, the peak photocur-
rent is
Figure 3-10. Diode bumot equivalent circuit
(Raymond, 1985).
The worst case for the diode would be the maxi-
mum reverse bias, which, in this case, would be
just below the breakdown voltage. Assuming that
the critical burnout energy is the same as that
determined from electrical overstress data, the
critical radiation dose rate for burnout can be
defined as shown in Figure 3- 1 1. Junction area
does not enter into the calculation since the
assumed variations of both photocurrent and
burnout energy increase linearly with junction
area. Results shown in Figure 3- 11 are not
intended to define diode burnout value accurately
for any specific diode, but rather to indicate the
approximate levels of concern.
101"
101 2 4 6 8i 02 1 o3
RADIATION PULSE WIDTH, tp (nsec)
Figure 3-11. Radiation intensity versus radiation
pulse width for burnout threshold (Espig, 1985).
33 Transient Ionizing Radiation Response of the collector currents at times later than about
of Bipolar Transistors one base-layer transit time. In order to simplify
3.3.1 Photocurrent Modeling
A bipolar transistor may be envisioned as be-
ing comprised of two interconnected diodes: one
normally operated in the forward-biased region,
forming the emitter-base junction; and one nor-
mally operated in the reverse-biased region,
forming the base-collector junction. Thus, the
informzition provided in Section 3.2 can be used
to characterize and model the radiation response
of bipolar transistors.
For the purposes of discussion, consider an
npn transistor connected in the grounded emitter
configuration and biased in its active region
(Wirth and Rogers, 1964). If it is irradiated, the
resulting hole-electron pairs will diffuse and drift
across each junction in a manner analogous to
that discussed for a single diode: prompt currents
will be caused by carrier generation in each
depletion region, and delayed currents will be
caused by the diffusion of minority carriers from
one region to another. For an npn transistor, elec-
trons diffuse out of the base layer and holes are
injected into it from the adjoining regions. These
currents are called the primary photocurrents.
The hole current entering the base is amplified
by current gain of the device and results in a col-
lector current transient in addition to the collec-
tor component of the primary photocurrent. The
amplified component of the collector current
transient is called the secondary photocurrent.
An exact expression for the secondary photo-
current would be very complicated if it included
carrier redistribution times, recombination pro-
cesses, and the effects of a three-dimensional ge-
ometry. Fortunately, assumptions can be made to
yield simple expressions that are useful in under-
standing the mechanisms involved and in making
reasonably accurate estimates of actual device re-
sponse. The two most important assumptions are
that the charge-control model (Beaufoy and
Sparkes, 1957) is applicable and that the device
has one-dimensional geometry. Although the
charge-control model used does not adequately
handle events that change very rapidly with time,
it is suitable for a study of the buildup and decay
the mathematics and obtain analytic solutions for
the collector current response, it was also neces-
sary to consider the external base circuit of the
transistor as an open circuit to changes in base
voltage caused by radiation. A simplified version
of the analysis and the final equations follow.
Beaufoy and Sparkes (1957) proposed a
charge-control model of a transistor wherein the
excess minority-carrier charge Q(t) in transit
across the base region is given by
where I(t) is the majority-carrier current entering
the base region and T~ is the base-layer minority-
carrier lifetime. The collector current is given by
where hFE is the transistor common-emitter cur-
rent gain. These relations are good approxima-
tions to the more exact continuity-diffusion equa-
tion models when the following conditions are
assumed to be satisfied:
1. The transistor is operated in the active
region,
2. Time variations of the base and collec-
tor current and, in this case, the radia-
tion intensity are small during one base
transit time,
3. The transistor has a one-dimensional
geometry,
4. The base region is either field free or
has an impurity grading such that the
built-in electric field E(x) has the form
[Dd F(x)/dx]/p[F(x)], where D and p
are the diffusion and mobility con-
stants, respectively, for minority carri-
ers and F(x) is an arbitrary function.
The following analysis also assumes that the col-
lector voltage and the base current are constant,
and therefore the collector depletion-layer ca-
pacitance and external circuit parameters need
not be considered.
The emitter depletion capacitance is also ig-
nored in this analysis in order to obtain a linear
model and closed-form solutions. This is a valid
approximation for many devices that are operated
in the active region because the change in the
charge accumulated on the emitter depletion ca-
pacitance during the radiation pulse is small
compared to changes in Q. While this approxi-
mation is valid for the devices discussed in the
text, it can lead to significant errors when consid-
ering very-high-frequency devices or when a de-
vice is operated at or near cutoff.
In an ionizing radiation environment, the base
majority-carrier current i(t) has six components:
(1) a diffusion component from the collector, (2)
a collector junction depletion-region component,
(3) an emitter junction depletion-region compo-
nent, (4) a component resulting from carrier gen-
eration within the base region, (5) a diffusion
current from the emitter, and (6) the normal base
current. The analytical form of components (1)
through (3) have been presented in Section 3.2,
and the development of components (4) and (5)
are provided in Wirth and Rogers (1964). The re-
sult is:
Ib(t)= -Q/Zb + i l + i2+ i3 + i4 + i5 + i6.(3.18)
If the emitter efficiency is assumed to be unity,
the ratio p,Jnp, is small, and the current corre-
sponding LO several forms of carrier generation
rate are given below.
For a step function of magnitude G at t = 0,
+ C- Dp2, erf (E) - /& e-tlTb
For steady-state conditions of Equation 3.19,
For a rectangular pulse of magnitude G and
duration T, a solution can be obtained directly
from Equation 3.19 by superpositioning two step
functions of opposite sign, one delayed by an
amount T. The response for an arbitrary
generation rate of duration T, where T is very
short compared to device time constants, is
and
T
Ic(t) = q ~ j g(h)dh [ (;:/Yz2 e - t / ~ c +
0 =b
for T < t. The total collector current in Equation
3.21 is the sum of primary and secondary compo-
nents, which can be distinguished by the pres-
ence of the amplification factor hFE. During the
radiation pulse, electrons (for an npn transistor)
generated in the base and collector depletion re-
gions diffuse to the collector region and consti-
tute a primary photocurrent given by the first
term in Equation 3.21. As these electrons are col-
lected, holes are accumulated in the base region
and, according to the charge-control model, pro-
duce the secondary photocurrent given by the last
term in Equation 3.21. After the termination of
the short radiation pulse, holes generated in the
collector and emitter regions, within one diffu-
sion length of the junctions, diffuse into the base.
The collector component of this primary photo-
current is described by the fust term in Equation
3.22. The secondary photocurrent defined by the
last term in Equation 3.22 results from the
buildup and recombination of excess holes,
which are generated directly within the base re-
gion or injected into the base from the collector
and emitter regions. The photocurrent predicted
by Equation 3.21 can be constructed rapidly by
using Figure 3-12, where the product of exp(-ti
z, ) and the error function terms is presented in
normalized form.
The accuracy of the model, described by
Equations 3.19 through 3.21, is depicted in Fig-
ures 3- 13 and 3-14, where the measured and pre-
dicted responses are in good agreement. At
higher doses, the peak collector current becomes
a nonlinear function of dose because of the ef-
fects of the electric field in the collector region.
The difference between measured data and pre-
dicted response in this region is attributed to dif-
ferences between the actual collector resistivity
of the device and the nominal value of resistivity
used in the calculation.
In some devices, the common emitter current
gain decreases significantly with increasing col-
lector current because the base-spreading resis-
tance produces a nonuniform bias condition on
the base-emitter junction (emitter crowding).
Since radiation-induced carriers are generated
uniformly in the base region and are injected
over the entire collector junction area, emitter
crowding is not as severe as that which occurs if
a corresponding number of carriers are injected
from the base lead. Therefore, at high current
levels, errors are introduced in predictions be-
cause the effective current gain of the transistor
may be higher than the measured current gain.
Equations 3.21 and 3.22 were derived on the
basis that the collector region was field-free, and
NORMALIZED TIME, t/zb
Figure 3-12. Plot of f(t) versus normalized rime wrth and Rogers, 1964).
TIME (psec)
Figure 3-13. Predicted and measured collector photocurrent waveforms for a 2N336 transistor; dose = 0.5 rad(Si), pulse
duration I. 0.1 p e c (Wirth and Rogers, 1964).
therefore the delayed photocurrent (holes)
injected from the collector to the base was caused
only by diffusion. The assumption that the col-
lector region is field-free is not always valid, par-
ticularly for devices with high-resistivity collec-
tor regions that are operated at high current lev-
els. The effect of the electric field upon the
delayed component of collector primary photo-
current is demonstrated by the following argu-
ment. After the minority carriers are generated in
the collector region, the diffusion process and the
electric field resulting from the collector bias cur-
rent transport some of these carriers into the base
region. This base current causes an increase in
the collector current and thereby produces a
larger electric field. The increase in the electric
field in turn causes an increase in the rate at
which carriers are injected into the base, etc. For
transistors having high-resistivity collector re-
gions as well as large h,, this positive feedback
mechanism (commonly referred to as collector
multiplication) may cause momentary instability,
with the result that the collector current initially
increases exponentially with time. Stable opera-
tion is resumed when recombination reduces the
carrier concentration in the collector to a level
where the rate at which carriers are injected into
the base cannot be sustained by the electric field.
This instability is illustrated in Figure 3-15 by the
............. I . . . ...............
p
10-11 1 ( 1 1 1 1 1 1 1 I I
i 0-2 2 4 6 i 0 - 1 1 o0 10'
DOSE (rads[Si])
Figure 3-14. Predicted and measured peak collector
photocurrent versus dose for a 2N336 transistor; bias
= 5 mA, x-ray pulse width = 0.1 psec (Wirth and
Rogers).
collector current response of a 2N105 1 transistor.
At a IGW exposure level, the electric field is not
large enough to be a significant factor, and the
usual transient response is observed. At the high
exposure level, the electric field caused by the
larger collector-current transient is sufficient to
start the unstable buildup in the current, which
occurs at about 0.1 psec.
The effect of a non-zero electric field in the
collector region can be modeled by including the
field term in the continuity equation describing
the minority-carrier density in the collector
region. Since it is assumed that the minority-
carrier density is always small compared to the
majority-carrier density, this field is determined
by the product of the collector resistivity and the
current density, as shown in Equation 3.23:
Predictions of primary and secondary photo-
current current can be obtained from Equation
3.23 by making the standard difference approxi-
mations for the partial derivatives and by solving
the resulting set of first-order equations.
A mathematical model that includes the elec-
tric fields in the collector is given by Equation
3.23. In this model, the minority-carrier density
Figure 3-15. Collector photocurrent waveforms for a 2N1051 transistor; x-ray pulse duration = 0.1 pec (Wirth and
Rogers, 1964).
in the collector region is described by a continu-
ity equaticn that contains the electric field term.
Since this field is directly proportional to the col-
lector current, which is, in turn, a function of the
electric field, this model is nonlinear and can
only be solved by numerical methods. Because
the model is nonlinear, predictions of both pri-
mary and secondary photocurrent are functions
of the initial collector current bias. [This has
been confirmed experimentally for 2N105 1 and
2N336 transistors and becomes significant in
these devices at bias levels of about 10 mA.1
Hence, primary photocurrents are not indepen-
dent of the mode of device operation and do not
necessarily scale linearly with dose. Therefore,
primary photocurrents determined experimen-
tally from the reverse-biased collector-base diode
are not necessarily accurate evaluations of the
primary photocurrents obtained under normal
transistor operating conditions. The magnitude of
the errors introduced by neglecting the electric
field or by using experimentally determined val-
ues for the primary photocurrent depends
strongly upon: (1) the design of the transistor
(e.g., in devices that have low collector resistiv-
ity, the electric field may be negligible, whereas
it may be significant at normal operating current
levels in devices with a high-resistivity collector
region); and (2) the type of circuit in which the
transistor is embedded (e.g., if the transistor satu-
rates at low values of collector current, the elec-
tric field may not be large enough to be signifi-
cant).
3.3.2 Alternative Total Photocurrent
Response Model
An alternative method for modeling photocur-
rents in a bipolar transistor considers the photo-
response of the transistor as a combination of the
junction photocurrents and the transistor gain.
The junction photocurrents are defined as the
emitter and collector primary photocurrents.
Enhancement of the primary photocurrents by
the transistor gain causes the secondary photo-
current. As for the diode, a reasonable first-order
model of the transistor is an ideal electrical
model with the addition of photocurrent genera-
tors, as shown in Figure 3-16. Interaction be-
tween the primary photocurrents and transistor
photoresponse is determined by circuit condi-
tions. For example, consider the common-emitter
photoresponse for a circuit, as shown in Figure 3-
17. If the input is shorted (i.e., Rg, VBB = O), the
primary photocurrent will flow to ground through
the external circuit. Therefore, the transient col-
lector photocurrent 61, will be equal to the col-
lector primary photocurrent. On the other hand, if
the source resistance is large compared to the
common-emitter input resistance RiE (as deter-
mined by the quiescent emitter current bias), then
the primary photocurrents will flow into the tran-
C C
Figure 3-16. First-order transistor photo-response
model (Raymond, 1985).
Figure 3-17. Common-emitter transistor photo-
response (Raymond, 1985).
sistor base. These currents will be multiplied by
the tramistor gain in the transient collector pho-
tocurrent. Thus, for R, >> R,
where the second term is the secondary collector
photocurrent.
For the collector primary photocurrent, the
maximum carrier-collection volume is that of the
base and collector region. The collector volume
is determined by the collector base junction area
and the effective carrier diffusion length plus the
collector junction depletion layer width Wc. For
a nonepitaxial transistor, the steady-state carrier
diffusion length is equal to the minority carrier
diffusion length (LpC for an npn transistor). For
an epitaxial transistor, the steady-state carrier dif-
fusion length is approximately equal to the high-
resistivity collector epitaxial width WCE. Expres-
sions for the steady-state collector primary pho-
tocurrents are then
When the total collector current exceeds the satu-
ration limit (-VCc/R,), the collector-base junc-
tion will be forward-biased and the transistor
saturates. The saturation recovery time will then
depend on circuit bias conditions, as it does for
an electrical pulse.
3.3.3 Physical Photocurrent Model
Photocurrent effects are described here as they
relate to the physical geometry of a bipolar tran-
sistor. The photoresponse sensitivity of all junc-
tion semiconductor devices is determined princi-
pally by the junction photocurrents. In a bipolar
transistor, these are the collector and emitter pri-
mary photocurrents. In integrated circuits, photo-
currents from the isolation junction are important
in determining overall circuit response.
The magnitude of the photocurrent is deter-
mined by the effective carrier collection volume
for a given radiation pulse width. For the planar
bipolar transistor shown in Figure 3-18, the car-
rier collection volumes can be the volume be-
tween the surface and emitter-base junction for
thin emitters, the volume between the surface and
IppC - qg0?[vg + AC (WC + LK)] . (3.25)
collector-base junction (excluding the emitter
for a nonepitaxial npn transistor, and
volume) for the base, and the volume defined by
the collector-base junction area and an effective
IppC - q g o ~ [ ~ B A ~ ( W ~ + wCE)]
minority-carrier diffusion length for the collector.
3 (3.26)
Carriers generated in the base region will flow
for an exuitaxial nun transistor. either to the emitter or collector iunction as deter-
mined by the built-in electric field distribution
With a finite collector load resistance RL, the
transient collector photocurrent will be limited.
and junction bias condition.
BASE EMllTER BASE
n-EPITAXIAL REGION
I
COLLECTOR
Figure 3-18. Planar bipolar transistor structure (Raymond, 1982).
The time dependence of the collector primary
photocurrent is essentially that of a "short-base"
pn diode, where the transistor inactive base is the
short-base p-region and the collector is the bulk
n-region. Carriers generated in the junction
depletion layer contribute a photocurrent compo-
nent that essentially follows the radiation with an
effective time constant typically less than 10
nsec, which may be estimated by z - 112 nfT. Ad-
ditional time delay in carrier collection from the
inactive base is experienced for transistors of
large base area and small local base contact. In
this case (principally encountered in photo-tran-
sistors), a lateral diffusion delay is observed in
the base component of the primary photocurrent.
The principal time delay in the collector primary
photocurrent is diffusion of carriers from the bulk
collector region. For a wide-collector,
nonepitaxial transistor, the time dependence is an
error function response, as presented for the junc-
tion diode. For an expitaxial device, the collec-
tion volume and time delays are both reduced.
3.3.4 Other Transient Ionizing Radiation
Effects on Bipolar Transistors
Two separate effects that result in high tran-
sient dose-rate environments are: (1) nonlinear
photocurrents and (2) storage time.
3.3.4.1 Nonlinear Photocurrents
In Section 3.2, the linear relationship relating
primary photocurrent to dose rate for a pn junc-
tion was presented [in Equation 3.6aI as:
Ipp = e AW, goy (amperes) , (3.27)
where e go = 6.7 p~/ cm~-radl sec, and A Wt is
the effective volume for photocurrent production
in and near the junction. However, for high dose
rates, e. g. , 2 lo8 rads(Si)/sec, the photocurrent
response can take on an anomalous nonlinear
characteristic. This effect is depicted in Figure
3-19, where a linear response observed for low
dose rates is followed by a discontinuous (jump)
increase at the higher dose rates. Subsequent to
the step increase in photocurrent, a linear
response again occurs until saturation is reached.
The explanation for this nonlinear response is
that when the incident radiation is sufficiently
penetrating, hole-electron pairs are produced
homogeneously throughout the device. The holes
collected in the active region of the base, as well
as those that diffuse into the region from the col-
lector and emitter, flow laterally outward toward
the base contact, as shown in Figure 3-20. This
current produces a lateral voltage drop outward,
parallel to the base-emitter and base-collector
junctions. The center of the emitter junction is
then more forward-biased than the periphery, and
the emitter potential and that of the central por-
tion of the base remain in phase. If the corre-
sponding lateral currents are large enough, as in
the case of a high-dose-rate incident pulse, this
base-emitter potential drop can exceed the break-
down voltage BVEBo. If this happens, the emitter
and base are essentially shorted through this low-
impedance breakdown path. The device is now in
a common-emitter configuration insofar as the
base photocurrent drive is concerned and the
photocurrent is amplified to produce a very large
collector current, which results in the anomalous
nonlinear photocurrent. Under certain conditions,
the lateral photocurrent distribution is the reverse
of the preceding. The photocurrent density can
become electrically unstable, producing en-
hanced photocurrents near the center of the emit-
ter (Habing and Wirth, 1966).
1 0-1
107 2 4 6alO8 1 o9 lolo
DOSE RATE (reds[Si]lsec)
Figure 3-19. Transistor nonlinear photocurrent be-
havior with dose rate for two values for collector base
voltage (Hibing and Wuth, 1966).
B E B
I I
EMl TER
I I
n
I I
-]=BASE p - -
n
COLLECTOR kz l l -11-
Figure 3-20. Lateral photocurrent flow within a circular transistor (Habing and Wirth, 1966).
Theoretical results can approximately predict photocurrent will essentially be an amplified rep-
the dose-rate level at which the anomalous be- resentation of the dominant primary photocur-
havior occurs in many cases. The junction break- rent.
down in many instances is temporary, with
subsequent partial healing of the emitter-base
breakdown path. This allows the device to revert
to quasi-normal operation, but at the increased
levels of photocurrent shown following the dis-
continuity in Figure 3-19.
3.3.4.2 Radiation Storage Time
If a transistor is operated in the linear region,
the overall photoresponse is the straightforward
combination of the time dependence of the pri-
mary photocurrents and that of the transistor
electrical response. For example, the maximum
common-emitter transistor photocurrent occurs
when the external base impedance is large com-
pared to the transistor input impedance. In terms
of the LaPlace transforms for the currents and
frequency-dependent gain,
Exposure to a high-intensity ionizing radiation
pulse may result in a collector photocurrent large
enough to saturate the transistor in the circuit. To
a first-order approximation, the radiation-induced
storage time is that resulting from the primary
photocurrents as external base drive. Using an
external base drive, the transistor radiation stor-
age time tSR can be expressed as
where 2, is the storage time constant for the tran-
sistor and is a function of the collector minority-
carrier lifetime and doping profile. For a nonep-
Ic (s) = [IppC ( s ) + IppE (s)]
itaxial planar transistor, z, is approximately equal
to the collector minorit y-carrier lifetime. Figure
x [hFE(s) + 11 ,
(3.28)
3-21 shows radiation storage time as the time the
transistor remains saturated after the radiation
and the time-dependent current is given by the
inverse transform,
pulse ends.
Accurate representation of the overall transis-
I&) = f '[I~(S)] .
(3.29)
tor photoresponse requires an accurate electrical
model for the transient level and frequency
If the primary photocurrents are fast compared to
response of interest. If the transistor is operated
the transistor response, the worst-case secondary
in the linear region and the transient photocurrent
photocurrent
be the waveform of input-
is small compared to the quiescent bias current,
current response. if the small-signal models such as the ones shown in
sistor is fast compared to the time constants of
Figure 3-22 provide an accurate representation of
the primary photocurrents, then the secondary
the device.
0
GAMMA
RADIATION
PULSE
Figure 3-21. Collector current and dose-rate pulse
versus time showing radiation storage time (Messen-
ger and Ash, 1992).
3.4 Transient Ionizing Radiation Response of
Metal-Oxide Semiconductor Field-Effect
Transistors (MOSFETs)
3.4.1 MOSFET Photocurrent Model
Development
The model developed for the pn diode [Sec-
tions 3.1 and 3.21 and extended to support the bi-
polar transistor discussion [Section 3.31 is also
applicable to the discussion of the transient ion-
izing dose response of the MOSFET. For com-
ple teness, the Wirth-Rogers model and governing
assumptions are repeated in this section. In addi-
tion, some recent enhancements to the model are
discussed. The following discussion has been
paraphrased from Massengill (1987).
Subject to the assumptions to be discussed
here, the solution of the continuity and minority-
carrier diffusion equations for a rectangular ra-
diation pulse yields a total photocurrent of:
6
E
(a) Hybrld PI Model
(b) EbersMoll Model
Figure 3-22 (a, b). Radiation-inclusive transistor
models (Raymond, 1985).
for t > 5. The depletion region width W, repre-
sents the prompt-component collection length.
The sum of the error function (erf) terms repre-
sents the delayed, diffusion-component collec-
tion length.
The assumptions implied with the use of the
minority-carrier diffusion and continuity equa-
tions can be very important. The assumptions are
(Wirth and Rogers, 1964):
1. A one-dimensional, infinite, single
junction device,
2. No electric fields except in the deple-
tion region,
3. Uniform doping on each side of the
junction,
4. Majority-carrier concentrations that are
not appreciably altered by the radia-
tion, i.e., low-level injection.
Of these conditions, the fourth is most suspect.
Dose rates >10l0 rads(Si)/sec may cause signifi-
cant increases in the concentrations of majority
carriers (Messenger, 1979). This majority con-
centration modulation necessitates the solution of
the ambipolar diffusion equation (McKelvey,
1966), which is difficult because of the nonlinear
nature of the equations. The solution would ulti-
mately change the diffusion lengths, L, and Lp
and the minority-carrier lifetimes, T, and z, .
However, as will be seen in later sections, typical
design-rule dimensions of most modern inte-
grated circuits are much smaller than these diffu-
sion lengths. Thus, the diffusion collection is
usually limited by the geometry of the region
(e.g., boundaries, other junctions, etc.) and not by
the diffusion lengths. Thus, the precise diffusion
lengths are not as critical in determining the pho-
tocurrent magnitudes as is the geometry.
Several extensions of the Wirth-Rogers model
have been developed. Donovan, Hauser, and
Simons (1974) have developed forms of the
model applicable to a pn junction region with
finite length, as shown in Figure 3-23. If the
lengths of the bulk regions are on the order of the
minority-carrier diffusion lengths, then the fol-
lowing replacements must be performed in the
Wirth-Rogers equations:
where Wp and W, are the distances from the edge
of the depletion region to the boundary on the p
and n sides of the junction, respectively, and D,
and Dp are the diffusion coefficients for electrons
and holes, respectively.
Long, Florian, and Casey (1983) have devel-
oped equations describing the effects of a high-
low junction in the proximity of the photocurrent
junction, as shown in Figure 3-24. This case
applies to the epitaxial-substrate (n-n+) interface
found in most modern CMOS structures. For this
case, the following replacements are made in the
Wirth-Rogers equations:
L
Lp 4 L tan h (W/L) +
cos h (w/L)
/ (3.36)
Figure 3-24. Collection region bounded by a high-low
junction (Donovan, Hauser, and Sirnons, 1974).
where
L = minority-carrier diffusion length
in the epitaxial layer (n-region)
L+ = minority-carrier diffusion length
in the substrate (n+-region)
W = distance between the edge of the
depletion region and the substrate
Dm = diffusion coefficient for minority
r
carriers in the epitaxial layer.
Figure 3-23. Bounded collection region (Donovan,
Hauser, and Sirnons, 1974).
Recent work at Sandia National Laboratories
and Rensselaer Polytechnic Institute has ad-
dressed the modification of the Wirth-Rogers
models for application under high injection con-
ditions (Gover, n.d.; Ishaque, Becker, and Block,
1987). In addition, a significant extension to the
Wirth-Rogers model has been developed by
Enlow and Alexander (1988) [see Section 3.11.
3.4.2 MOSFET Photocurrent Equivalent
Circuit
Transient radiation produces several effects on
MOS devices. First, electron-hole pairs are cre-
ated in the bulk, and these carriers are collected
by the pn junction. Carriers created under the
gate region will be collected by the pn junctions,
even if the device is operating in cut off and no
conductive channel exists. For a symmetrical de-
vice, approximately one-half of the total photo-
current will flow across the source-substrate
junction and the other half will flow across the
drain-substrate junction. The source and substrate
of a MOS device are normally connected to-
gether so the net external source photocurrent
will equal the drain photocurrent. Because of the
large areas associated with the diffused source
and drain pn junction, most of the MOS photo-
current comes from these junctions while only a
small percentage of the total arises from under
the gate area.
Illustrated in Figure 3-25 are some of the im-
portant parameters. The current is assumed to re-
sult from the collection of all charge generated in
the volume defined by the width of the depletion
layer W, and within one diffusion length L. The
prompt drain current may be expressed as
The collection area,
A = (Y + 2L) x (width of p-diffusions +2L) ,
(3.39)
where Y is the effective device length.
An estimation of the photocurrent sensitivity
of a MOSFET can be made from the above equa-
tions and the following typical values (Donovan,
Hauser, and Simons, 1974):
L = 2 x cm (t - lo4 second) . (3.40b)
With the assumption that the cell is square, these
values give
Based on this discussion, a schematic repre-
sentation of these photocurrents can be devel-
oped. Such a representation is shown in Figure
3-26, where a CMOS inverter is used as an ex-
ample.
In this example, the local photocurrents caused
by the dose-rate exposure are depicted as ideal
current sources. Photocurrents are present across
each semiconductor junction and are directed
onto the p-regions of the junctions. The figure
does not show the photocurrents across the
source regions of the transistors. Such photocur-
rents will have no net effect on device response,
because they can, at most, turn on only the
source-substrate diodes and cycle current in the
SOURCE GATE DRAIN
n-EPI
Figure 3-25. Typical MOSFET structure.
Figure 3-26. Local photocurrents produced by a
dose-rate event in a CMOS inverter (Ma and
Dressendorfer, 1989).
vicinity of the node. The action of these photo-
currents in an SRAM cell is depicted in Figure 3-
27. Sources P, and P2 model drain photocurrents
of the p-channel devices, P3 and P4 those of the
n-channel devices, and P, the photocurrent across
- -
the p-well, represented in this figure as the re-
verse-biased diode between VD, and Vss.
The magnitudes of junction photocurrents
have been modeled analytically and depend on
the injection level of excess carriers characteris-
tic of the event and the material and processing
parameters of the affected device. A complete
summary of photocurrent expressions, including
their ranges of applicability, is given in
Massengill's Ph.D. dissertation (Massengill,
1987). For the many integrated circuits available
today, the magnitudes of photocurrents directed
onto device nodes are limited by device geom-
etries. For example, the charge deposited in the
p-well of the device represented in Figure 3-26 is
collected both as the n-channel drain photocur-
rent and as the p-well photocurrent. The collec-
-
tion length, comprising combined drift and diffu-
sion currents for both the drain and the well, ex-
ceeds the well depth; i.e., either node would col-
lect all of the charge deposited in the well if the
other were not present. Thus, the collected cur-
rent magnitude is determined by partitioning the
charge onto the two nodes, rather than by the de-
tails of transport processes. A reasonable choice
for partitioning allows each node (required by
VDD
"ss
Figure 3-27. Local photocurrents produced. by a
dose-rate event in SRAM cell (Ma and Dressendorfer,
1989).
design rules to be nonoverlapping) to collect the
charge deposited in its equilibrium depletion re-
gion and to assign charge deposited in the equi-
librium "quasi- neutral" regions to the nearest
junction. Because of such partitioning, the photo-
currents collected by most devices can be com-
puted without resort to detailed collection analy-
ses. In many cases, the photocurrent magnitudes
depend more strongly on layout geometry than
on carrier mobilities, lifetimes, or local fields.
In subsequent sections, the effect of these local
photocurrents will be extended to develop an
overall understanding of transient radiation ef-
fects on complex microelectronics.
3.5 Transient Ionizing Radiation Effects on
Silicon Integrated Circuits on
Insulating Substrates
The use of an insulating substrate technology
(e.g., silicon on sapphire [SOS], silicon on buried
oxide, etc.) provides a method for improving IC
hardness to transient radiation. This improvement
is the result of the reduced transient radiation
charge-collection volume. Thus, this technology
is usually employed for applications where a
high transient-dose-rate threat (e.g., >10 rads[Si]
sec) due to a nuclear weapon exists, which the
system must be capable of surviving and be able
to continue to operate (or rapidly resume opera-
tion) without outside intervention.
The lack of outside intervention implies that
critical information required for the system to
function (e.g., operating system) and data such as
track files, threat evaluations, and prioritization,
etc. must be preserved in this hostile environ-
ment. Such applications include satellite onboard
data-processing (OBDP) system critical vector
memories, circumvention system critical data
memories, intercontinental ballistic missile
(ICBM) guidance systems, etc.
In addition to being more resistant to transient
radiation than bulk technology ICs, silicon-on-
insulator (SOI) ICs will recover from a transient
event more rapidly, which can also be important
in certain applications. As a general rule, very
large-scale integrated circuit (VLSIC) bulk tech-
nology devices (e.g., 2 64k SRAM) upset at dose
rates in the range of 1 to 2 x lo9 rads(Si)/sec,
whereas SO1 technology devices upset at
21 x 10" rads(Si)/sec.
The transient ionizing radiation response in
silicon insulating substrate technologies (e.g.,
SOS or silicon on buried oxide) differs signifi-
cantly from the response of bulk silicon technol-
ogy devices. As stated, the primary reason for
this difference is the reduced collection volume
[see Figure 3-28]. However, for silicon on oxide
[hereafter to be referred to as SOI), the lack of a
natural source-to-body contact in conjunction
with the occurrence of a parasitic bipolar transis-
tor, formed by the source, channel, and drain re-
gions of the MOS transistor [see Figure 3-29],
will also have a dramatic effect on the perfor-
mance of the individual MOSFET and conse-
quently on the IC.
Although gallium arsenide (GaAs) is an insu-
lating technology, the transient ionizing radiation
response of circuits fabricated on this material
differ from the response of SO1 and SOS technol-
ogy circuits. This difference can be attributed to
the radiation response of the GaAs material.
Hence, transient ionizing radiation response of
these GaAs ICs is discussed separately [Section
3.61.
3.5.1 Silicon-on-Insulator Transistors
As previously stated, the active region (body)
is isolated from the substrate in SO1 devices, thus
limiting the photocurrent collection volume.
However, because of the smaller size of the de-
vice, the efficiency of the parasitic bipolar device
[Figure 3-29], which is formed by the source
base and base-drain junctions, is enhanced
(Davis et al., 1985; Mikawa and Ackerman,
1987). The gain of the parasitic bipolar transistor
enhances the photocurrent and, thus, dominates
the transient response.
The following discussion [based on Alles (1990)l
provides a qualitative understanding of the tran-
sient response of an SO1 transistor. In order to
study the effect of transient-radiation-induced
photocurrents on SO1 transistors, it is first neces-
sary to point out particular aspects of the transis-
tor structure to be studied. As shown in Figure 3-
30, the source and drain implants extend to the
underlying oxide. This configuration is referred
to as a fully bottomed junction (FBJ) and is the
method employed for all radiation-hardened SO1
designs. In addition, in both the OFF and ON
transistors, there is a quasi-neutral (nondepleted)
region of the body, and thus, the transistors are
referred to as partially depleted.
In SO1 devices with FBJs, isolation of the active
region (body) from the substrate limits the vol-
ume of the depletion regions (to source and drain
side walls) and eliminates charge collection from
the substrate, which otherwise would be under
the source and drain. This limited collection vol-
ume, along with typical device (gate) dimen-
sions, which are much less than carrier diffusion
lengths, leads to device photoresponses that fol-
low the radiation pulse closely (Kjar and
Kinoshata, 1973); i.e., no significant diffusion
component of the photocurrent follows the radia-
tion pulse. However, isolation of the body re-
gions of SO1 transistors introduce floating-body
effects (Tihanyi and Schlotterer, 1975) associated
with the finite volume of the transistor body re-
gion. During normal device operation, the tran-
sistor body potential may be large enough to
forward-bias the body-source junction. This ef-
fect has been characterized extensively [see, for
example, Davis et al. (1985); Kato, Wada, and
Taniguchi (1985); and Coligne (1986)l. Tran-
sient-radiation-induced photocurrents may also
forward-bias the body-source junction and acti-
vate the parasitic bipolar transistor (Davis et al.,
1985), leading to bipolar enhancement of wan-
sient-radiation-induced photocurrents.
A common way to reduce or eliminate float-
ing-body effects is to electrically connect the de-
vice body to its source, or to a supply, using one
or more body ties. Even when body ties are used,
finite, distributed resistance (R BODY) still ex-
ists between any point within the transistor body
and the body tie(s), as shown in Figure 3-31. Be-
cause of this resistance, using body ties does not
necessarily completely eliminate bipolar effects
CHANNEL STOPPERS CHANNEL STOPPERS
FIELD OXIDE
n-SUBSTRATE
(a) CMOS Bulk (b) CMOS Epi on Bulk
SILICON SILICON
BACK CHANNEL
Si SUBSTRATE
(c) CMOSISOS (d) SO1
Figure 3-28 (a, b, c, d). Cross section of an SAOI transistor with the parasitic bipolar and back-gate devices (Alles, 1990).
POLY GATE
I 1
(EMITTER) (COLLECTOR)
BIPOLAR JUNCTION
TRANSISTOR
SOURCE BACK CHANNEL DRAIN
-
BACK ("BURIED") CHANNEL
Si SUBSTRATE
Figure 3-29. Cross section of an SAOI transistor with the parasitic bipolar and back-gate devices (Alles, 1990).
/ POLY Si GATE
BACK CHANNEL
OXIDE
Si SUBSTRATE
I
Si SUBSTRATE
Y
Figure 3-30. Schematic illustration of possible radiation-induced leakage current paths in an SO1 transistor (Ma and
DressendorKer, 1989).
(current) is removed from the body through a
body tie is determined by the distributed resis-
tance and by the capacitances associated with the
body node. Transient currents within the body
create potential gradients, and localized regions
of the body-source junction can become forward-
BODY DRAIN biased, resulting in bipolar amplification of the
radiation-induced photocurrent. Thus, the gain of
the parasitic bipolar transistor, determined by
OXIDE
base width (gate length) and doping levels, play
an important role in determining the transient-
SUBSTRATE
I/
radiation-induced photocurrent response of SO1
MOS transistors. As feature sizes decrease, bipo-
lar gains correspondingly increase, making bipo-
Figure 3-31. Three-dimensional representation of an
lar effects significant in aggressively scaled tech-
n-channel SO1 device (Alles, 1990).
nologies. When body ties are utilized, the
in the case of single events, but it can signifi-
distributed body resistance becomes important in
cantly reduce the photocurrent response to both
determining the transient response of MOS/SOI
single-event (Kerns et al., 1989) and dose-rate
devices. The resistance determines the portion, if
radiation (Davis et al., 1985).
any, of the body-source junction that becomes
forward-biased at a given dose rate, and thus con-
-
Excess minority carriers induced by ionizing
trols the amount of transient-induced photocur-
radiation must either diffuse to junctions or pass
rent that is subject to bipolar enhancement. The
through the distributed body resistance (if body
body resistance is determined by the device
ties are used) to be removed from the body, or
dimensions, body (well) resistivity, and position-
recombine in the body. The rate at which charge
ing of the body ties.
3.5.2 Silicon-on-Sapphire Technology Devices
The photocurrents resulting from transient ion-
izing radiation in SOS technology devices are
much larger than those in SO1 because the con-
ductivity of sapphire is greater than that of SiO,.
However, the low minority-carrier lifetimes in
SOS films (Kjar and Kinoshata, 1973) result in
negligible parasitic bipolar transistor gain. Thus,
SOS ICs provide high tolerance to transient ion-
izing radiation, being of the same order as SO1
devices (e.g., upset levels for VLSICs 21 x 10"
rads[Si]/sec.)
3.6 Transient Ionizing Dose Rate Response
of Gallium Arsenide Semiconductor
Devices
The transient ionizing dose rate response of
GaAs devices is influenced by four factors:
1. pn junction photocurrent generation
2. Substrate photocurrents
3. Charge trapping in the substrate
4. Shunt currents through the semi-insu-
lating (SI) substrate.
These effects will be discussed in the following
sections.
3.6.1 pn Junction Photocurrents
Dose-rate, or photocurrent, effects are pro-
duced in ICs as the excess carriers generated by
the incident ionizing radiation are collected by pn
junctions. These effects are manifested in a cir-
cuit by large current or voltage perturbations
whose magnitude and duration depend on the
peak dose rate y , pulse duration t, junction area
A, collection volumes, carrier lifetimes z, and
circuitldevice time constants (especially when
greater than the pulse duration). For the simplest
case of a pn junction exposed to a square pulse of
dose rate j and duration t >> z,,zp, the primary
photocurrent is given by:
Here, W, is the depletion-layer width and go
is the pair generation constant, which is about
6.63 x 1013 pairs/cm3-rad for GaAs. Although go
is slightly higher for GaAs than for Si, GaAs is
characterized by much shorter diffusion lengths
(L, and Lp) and minority-carrier lifetimes. Thus,
in principle, GaAs devices should be somewhat
harder to transient upset than silicon devices for
this effect alone. However, in actuality, the upset
levels in GaAs devices are dominated by sub-
strate photocurrents and substrate charge trap-
ping [discussed below] (Buchanan, 1985; Zuleeg,
Notthoff, and Troeger, 1983).
3.6.2 Substrate Photocurrents
Substrate photocurrents can flow between con-
tact pads or metallization placed directly on chip
surfaces. Measurements have shown that such
currents can be larger by several orders of mag-
nitude than device photocurrents and, in fact, can
dominate circuit response (Zuleeg, Notthoff, and
Toeger, 1983); however, it has also been found
that circuit response can be reduced by an order
of magnitude by placing the bonding pads and
metal interconnects on an insulating layer.
3.6.3 Substrate Charge Trapping
A transient ionizing event will result in charge
being trapped in the deep levels that are charac-
teristic of several insulating substrate materials
(Simons et al., 198 1). Conduction in FET struc-
tures can be severely affected (even cut off) by
the trapped charge, which decays with time con-
stants ranging from milliseconds to seconds.
Recent work has shown, however, that this
backgating-like effect can be appreciably reduced
(and perhaps even eliminated) by the use of high-
quality liquid-encapsulated-crystal (LEC) sub-
strates andfor by various FET structural modifi-
cations, such as implanting a p-layer beneath the
n-channel (Anderson et al., 1982). The effect can
also be minimized by operating at high current
levels.
Transient response data reported for GaAs
digital ICs of medium-scale-integration (MSI)
complexity have shown a broad range of upset
thresholds. Schottky-diode-FET-logic (SDFL)
circuits have demonstrated thresholds ranging
from 1 x lo8 to 2 x 101 rads(GaAs)/sec (Walton
et al., 1983), while the enhancement JFET (E-
JFET), 256-bit RAM functioned without soft er-
rors up to dose rates of 6 x lo9 to 1 x 101
rads(GaAs)/sec (Notthoff, Zuleeg, and Troeger,
1983). While these circuit upsets apparently re-
sulted from photocurrent phenomena, disruptions
in buffered-FET-logic (BFL) gate and ring oscil-
lator performance for tens of milliseconds have
been observed following 1-psec LINAC expo-
sures at total doses between about 10, and lo3
rads(GaAs) (lo8 to lo9 rads[GaAs]/sec) and after
3-nsec flash x-ray (FXR) pulses at the 100-rad
level (3 x 101 rads[GaAs]/sec), all as a result of
the backgating problem. Radiation-induced back-
gating has also been reported in power metal-ox-
ide gate FETs (MESFETs) and in a monolithic
amplifier operating at X-band (Anderson and
Binari, 1983), although transient-free operation
of a microwave MESFET was observed up to a
dose rate of 3 x 101 rads(GaAs) sec (Castle,
1983).
3.6.4 Semi-Insulating Substrate Shunt
Currents
Based on extensive experimental work and
analysis, Zuleeg, Notthoff, and Troeger (1 983)
argue that the upset levels in GaAs JFETs with
channel lengths below -1 pm are dominated by
shunt currents between the source and drain
through the semi-insulating (SI) substrate, as in-
dicated by $, in Figure 3-32, which schemati-
cally illustrates the shunt current effect. The cur-
rents $,, and $, , are the usual junction photocur-
rents, and these dominate the upset levels for
devices with longer channel lengths. In effect, the
normally high-resistivity SI substrate becomes
conducting because of the induced carrier densi-
ties from ionization in the substrate, and offers a
low-resistance shunt path for currents between
the source and drain regions (Bowers and
Barnett, 1970). For a 1-pm channel length, the
predicted upset dose-rate threshold due to the
shunt substrate current is -5 x 101 rads(GaAs)l
sec.
As illustrated in Figure 3-33, short-pulse
(<lo0 nsec) upset thresholds reported for GaAs
ICs compare quite favorably with those charac-
technologies (Simons, Donovan, and Hauser,
1977; Long, 1980). Long-pulse (>1 psec) thresh-
olds decrease somewhat for silicon devices (be-
cause of the long lifetimes) but should not
change appreciably for GaAs devices in the ab-
sence of severe backgating problems. Moreover,
GaAs FET circuits are not susceptible to latchup
associated with extraneous four-layer paths as are
many bipolar and CMOSIbulk silicon ICs. Ex-
tremely low upset thresholds can be expected for
both GaAs and Si charge-coupled devices
(CCDs) (I lo6 to lo8 rads[M]/sec).
3.7 Transient Ionizing Dose-Rate Upset
Response of Microelectronics
The transient ionizing dose radiation response
of integrated circuits is addressed here. Dose-rate
upset is investigated using a static random-ac-
cess memory (SRAM) IC as an example. The use
of an SRAM permits four separate upset events,
relevant to system failure modes, to be examined:
(1) memory-cell upset, (2) input/output (YO) cir-
cuit upset, (3) write-mode address upset, and (4)
"pushout," an increase in SRAM access time that
results from transient ionizing radiation. This dis-
cussion basically follows the work of Massengill
(1987) and Massengill and Diehl (1984). Al-
though the discussion refers to MOSFET tech-
nology, the theory is relevant to silicon bipolar
and GaAs technology ICs. A brief explanation of
SRAM cell operation is provided as well as a
definition of bit errors and memory corruption.
3.7.1 CMOS SRAM Operation
Figure 3-34 shows the circuit schematic for the
standard six-transistor CMOS SRAM cell. This
cell stores one bit of information via high- or
low-voltage levels at information nodes (1) and
(2). These voltage levels are always complemen-
tary (in the steady state) due to the inverting
properties of the p-channelln-channel pairs. The
feedback properties of the inverter arrangement
provide stability of the stored information; the
voltage levels at (I) and (2) remain complemen-
tary as long as power is supplied to the cell and
no external effects perturb the states.
teristic of silicon large-scale-integration (LSI)
For steady-state operation, when the voltage at of the cell, voltage (2) is high. Transistor MN2 is
(1) is low, transistor MN1 is ON and MP1 is OFF and MP2 is ON. The feedback arrangement
OFF, thus providing a low-impedance path from of the two inverters provides a self-sustaining
(1) to V,, (or ground). However, since MP1 is state.
OFF, no-direct path exists (excluding leakage
Writing and reading to and from
currents) for current ' DD V ~ ~ ' This 'Iher-
the cell is achieved via the bit lines, B 1 and B2
ent propem is One Of the major advantages Of
through the access @msistors MN3 and MN4.
that is, the circuits have very
When these access @ansistors are ON, the
little current
(and thus low Power consump-
voltages at (1) and (2) are available to other cir-
tion) in the steady-state mode. On the other side
c,i,y for reading or writing processes. It is
SEMI-INSULATING
GaAs 1
Figure 3-32. Cross section of enhancement mode GaAs JFET, indicating source-drain shunt current path through semi-
insulating substrate (Zuleeg, Norrhoff, and Troeger, 1983).
PROJECTED ----
GALLIUM ARSENIDE
FET LOGIC
I
FET MICROWAVE AMPLIFIER
I
SILICON
I
IIL
TTL, STL
ECL
I
LINEAR 4
DOSE RATE (rads[M]lsec)
NMOS
CMOS
CMOSISOS
Figure 3-33. Reported and projected short-pulse dose-rate-upset thresholds (Simons, Donovan, and Hauser, 1977).
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
........................................................................
, , l
...................................................................... .......................................... .................. . .
..........................
.... :...::: ,:. ................................
.......................................
1 07 108 1 09 1010 I
important to note that the only appreciable cur-
rent flow through the cell occurs when the cell is
switching states. During the brief switching tran-
sient, both n-channel and p-channel transistors
turn ON and a direct, low-impedance path exists
between VDD and Vss.
3.7.2 Upset Definitions
Although the discussion here is oriented to
SRAM-type ICs, the information and definitions
can be extended to any type of circuit. Memory-
type circuits are addressed since they are typi-
cally the most widely used component and the
corruption of stored critical data poses a signifi-
cant problem for the ability of a system (strategic
satellite, missile, etc.) to function in a nuclear
weapon environment.
The types of upset that can occur in a transient
ionizing dose environment include:
1. Memory-cell upset: An SRAM cell,
shown in Figure 3-34, holds one bit of
information via a stable complemen-
tary pair of voltages on nodes (1) and
(2). A memory-cell upset occurs when
the state of the cell is changed due to
external stimulus, e.g., a transient volt-
age perturbation causing the state of
the latch to switch.
2. Output voltage upset: This type of up-
set occurs when the signal on the out-
put pins is significantly disturbed by
the transient. A commonly used stan-
dard definition describes upset as oc-
curring when the voltage perturbation
exceeds (VDD - Vss)/2.
3. Write-mode address upset: Radiation-
induced corruption of the SRAM ad-
dress or address decode circuit upset
can result in data being written into
unknown locations. Thus, although the
memory cells themselves have not up-
set, the net result is that "bad" data are
stored at unknown locations.
4. Pushout or SRAM access time delay:
The advent of a radiation event during
certain portions of the read or write
cycle can result in a momentary in-
crease (pushout) in the time required to
complete either theread or write cycle.
3.7.3 Integrated Circuit Upset
An IC upset can be delineated into two sepa-
rate components: (1) local upset, and (2) global
upset. Local upset refers to the operation of an IC
element (e.g., memory cell, inverter, etc.) due to
the photocurrents generated within that element.
-
BIT
0
"ss
Figure 3-34. CMOS SRAM cell (Ma and
Dressendorfer, 1989).
A schematic representation of this effect is
shown in Figures 3-35 and 3-36, where P, and P2
are the p-channel drain photocurrents, Pg and P4
are the n-channel drain photocurrents, and P5 is
the p-well photocurrent. Moreover, the local up-
set results from the direct interaction of PI
through P4, with the signals stored on informa-
tion nodes (1) and (2).
The effect of these local photocurrents is expli-
cated in the following paragraphs, paraphrased
from Ma and Dressendorfer (1989). The p-chan-
nel and n-channel devices within a CMOS RAM
cell each have different equilibrium depletion
region volumes for prompt photocurrent collec-
tion. Diffusion collection volumes are also differ-
ent for n- and p-channel devices in CMOS ICs.
In the case of one transistor type, the volumes are
constrained by the volume of the well; in the
other, by the adjacent epitaxial or substrate vol-
ume. These basic design and operation features
result in different values for each of the local
photocurrents [PI, P2, P3 and P4 of Figure 3-36].
The resulting differential "noise" results in desta-
bilization of the logic state of a RAM cell during
Figure 3-35. Local photocurrents produced by a dose-rate
Figure 3-36. Local photocurrents produced by a dose-
rate event in an SRAM cell (Ma and Dressendorfer,
1989).
dose-rate events. For instance, in p-well CMOS
RAM cells, the OFF p-channel device has the
largest collection volume of the transistors in the
cell. Local photocurrents can drive the low node
high and reverse the logic state. Local photocur-
rents dominate the cell response to dose-rate
events in technologies that use insulating sub-
strates [Section 3.51.
Global upset, the second component of IC
upset, can be the result of radiation-induced
photocurrents reducing the static excitation volt-
age (V,, - V,,) to the entire IC and to the indi-
event in a CMOS inverter (Ma and Dressendorfer, 1989).
vidual IC elements (e.g., memory-cell array, etc.)
as well. This effect has been denoted as railspan
collapse since it is not the absolute value of either
rail (i.e., VDD or VSS) that is important but the
difference, or span (VDD - Vss), that is critical
(Massengill and Diehl, 1984). Railspan collapse
depends upon the robustness of the ON-chip
power distribution system and the external power
distribution system impedance, including the im-
pedance of the IC package and any decoupling
capacitors used (Massengill, Diehl, and Wrobel,
1985; Massengill, Diehl, and Browning, 1986). It
should be noted that these effects only become
important considerations at very high dose rates
(e.g., > 1 x 1Ol1 rads[Si]/sec for SO1 technology
and 2 1 x lo9 rads[Si]/sec for bulk technology).
In order to achieve high-dose-rate upset levels,
special low-inductance packages must be used to
minimize inductive railspan collapse. Further-
more, decoupling capacitors need to be inserted
in the package on the VDD and Vss circuit, large
capacitors (external to the package) placed in
close proximity to the external VDD and Vss
pins, and multiple VDD-to-Vss pin paths used.
An example of such an arrangement is the 256k
CMOSISOI SRAM developed by Texas Instru-
ments, which uses four VDD pins, four VSS pins,
and two (in-package) 24-pF VDD and Vss
decoupling capacitors to achieve a dose-rate tol-
erance of 2 l x 1Ol1 rads(Si)/sec.
Anothe~ aspect of global upset is reduction in
the differential supply voltage (VDD - VSS) to a
memory cell due to the finite resistance of the
internal IC power distribution runs. This sag in
the local VDD voltage and rise of the local Vss
voltage due to photocurrent contributions can
lower the differential voltage to a memory cell to
the point that a stable state cannot be maintained.
The following discussion of dose-rate upset
describes a methodology for its simulation in
VSLICs and provides an example, again follow-
ing the work of Massengill and Diehl(1984) and
Massengill (1987).
An unambiguous, complete simulation of tran-
sient-dose-rate effects in an IC is not possible
since it would require the simultaneous analysis
of thousands to millions of pn junctions. How-
ever, a full chip-level simulation can be accom-
plished through use of a procedure (Massengill
and Diehl, 1984) that incorporates the following
steps:
Circuit-level simulation of the indi-
vidual RAM cell to determine the
subcircuit response to transient-radia-
tion-induced currents. This capability
is not routinely included in circuit-
level simulation codes such as SPICE.
Transient-radiation-induced current
simulation requires incorporation of
dynamically controlled current sources
representing the total diffusion and drift
photocurrents onto each device node
as a function of time and of the termi-
nal characteristics of the modeled de-
vices. The current produced by the
sources is a function of the amplitude
ana time profile of the dose-rate pulse
and also of the characteristics of the
device materials, particularly minor-
ity-carrier lifetime. Figure 3-37 shows
the photocurrent waveforms for a
CMOS RAM cell. The photocurrent is
injected in the locations designated in
Figure 3-36 (PI through P,) in order to
simulate the response of each of these
SRAM cells to dose-rate events. Note
that in the cell, the well-junction pho-
tocurrent is much larger than that of
any (or all) of the photocurrents col-
lected at the transistors composing the
cell.
Extraction of a simple, two-compo-
nentmodel of the I-Vcharacteristics of
one RAM cell, where V is the railspan
(V,, - V,,) and I is the total rail-to-rail
current drawn during an event. This
step requires linearizing the device re-
sponse determined in the previous step.
Figure 3-38 shows such simulatedchar-
acteristics for the RAM cell on the bulk
silicon substrate and the best fits ob-
tained by linear regression.
3. Incorporation of the linear RAM cell
models into a global, linear network
that represents the interconnect net-
work supplying voltage to the cells.
The resulting network, depicted sche-
matically in Figure 3-39 includes the
finite-resistance values of the inter-
connections and provides a chip-level
representation of the power-supply dis-
tribution scheme of the IC modeled
here [depicted in Figure 3-40].
4. Simulation of the network to determine
the minimum voltage span across each
RAM cell in the IC as a function of the
dose-rate amplitude and pulse length.
Figure 3-41 is a representation of the
RAM arrays in normal operation (with-
out transient ionizing radiation). Simu-
lations of the bulk array subject to
dose-rate events above and below the
threshold for transient upset are de-
picted in Figure 3-42.
5. Assessment of the efSect of the simu-
lated railspan on the RAM cell capa-
bility to retain stored information. The
minimum value of railspan required
for information retention is a circuit-
design-dependent parameter, obtain-
able either by simulations or by experi-
mental measurement of the minimum
operating voltage of an unirradiated
entire RAM IC. For the 10-volt chip
used in examples of Figures 3-41 and
3-42, the minimum railspan required
for reliable state storage is approxi-
mately 1.6 volts.
The accuracy of the technique described above
for predicting IC response to dose-rate events
rests on the assumption that subcircuit (local) and
chip-level (global) responses are not strongly in-
terdependent. Certainly, for very short, high-am-
0.7
I I I I I I
TlME(psec)
Figure 3-37. A photocurrent waveform typical of a
CMOS SRAM cell fabricated on a bulk silicon sub-
strate exposed to neutrons in order to reduce minority-
carrier lifetimes (Massengill, 1987).
2.0
I I I I I I I I I
- -
i DOSE RATE i
............. < ........................ ,. ...................-
RAILSPAN VOLTAGE (vob)
plitude pulses, and/or for ICs with very "hard"
rails or small global photocurrents, local effects
influence the upset level of cells. A graphic tech-
nique for including the interactionoflocal and
global effects has been developed (Ackerman et
al., 1986) and indicates that global effects are
strongly dominant in bulk and epi-CMOS cir-
cuits, whereas local effects dominate in CMOS/
SO1 devices (Davis et al., 1985; Mikawa and
Ackerman, 1987). These devices have smaller
total photocurrents than comparable silicon-
substrate devices because SO1 ICs do not contain
the well junctions that collect the majority of
photocurrent in junction-isolated CMOS ICs.
CMOSISOS devices also have small local photo-
currents, due to the absence of large well
junctions,and therefore exhibit dose-rate upset
thresholds that are generally higher than bulk and
epi-CMOS devices of comparable design. Dose-
rate upset in CMOSISOS is attributable to radia-
tion-induced photoconductivity of the sapphire
substrate (Kjar and Kinoshata, 1973), which used
in the renders the substrate ineffective in isolat-
ing information- storage elements. A simulation
code has been developed to predict dose-rate up-
set thresholds and bit-error patterns for devices
that upset by this mechanism, but it is presently
tailored to model devices fabricated on semi-in-
sulating GaAs (Brown et al., 1986).
RAM CELL
Rssu RSSH RSSH
VDD
RDDU
Figure 3-38. Rail-to-rail current drawn by a simu- Figure 3-39. Global linear network supplying voltage
lated RAM cell as a function of railspan voltage for to the cells and including linear models of RAM cells
various dose rate (Ma and Dressendorfer, 1989). (Ma and Dressendorfer, 1989).
For nonregular arrangements of subcircuits,
such as those found in devices incorporating
combinational logic (such as microprocessors)
and/or for devices with interconnect networks
that cannot be reduced to a planar network repre-
sentation, Steps 2 through 4 [above] must be
modified. Such analyses require a special design
code that uses state-of-the-art numerical tech-
niques in order to handle the dynamic interac-
tions of the large numbers of junctions encoun-
tered in modern ICs (Massengill, 1987). With
such a full-scale simulator, linearization of RAM
cell characteristics is not required, nor is con-
struction of the chip-level representation of the
RAM CELL
. .
Figure 3-40. Chip-level representation of the power-
supply distribution typical of a CMOS SRAM.
Figure 3-41. Representation of the voltage span
across RAM cells within an array under normal
unirradiated operating conditions (Ma and
Dressendorfer, 1989).
interconnect network including these models.
The cell characteristics are simulated in situ, lo-
cal and global interactions are automatically si-
multaneously included, and the noise margin or
voltage railspan maps of the IC nodes are pro-
duced as output. The full simulator results con-
firm those of the simpler, modular method for the
examples provided here (Massengill, 1987).
Using any of these techniques, simulation of
voltage railspan as a function of dose-rate excita-
tion allows estimates of the dose-rate upset
threshold (the minimum dose-rate amplitude for
a given pulse width for which at least one logic
state is upset).
RAILSPAN
(a) Dcse-Rate Event Below Inforrnat~on-Loss ThreshoM
(b) Dose-Rate Event Resuhing In Upset
Figure 3-42 (a, b). Representation of the voltage
span across a bulk RAM cell array subjected to dose-
rate events (Ma and Dressendorfer, 1989).
3.7.4 Pushout Upset
As previously stated, pushout is an increase in
SRAM access time that results from transient
ionizing irradiation (Murrill and Self, 1993). This
particular upset mode may limit device hardness
during operation (i.e., dynamic versus static) and
in general occurs at lower dose-rate levels than
static-mode upset Figure 3-43]. Dynamic testing
can be accomplished in two basic ways: (1)
unsynchronized, where a wide radiation pulse
(21 psec) that encompasses the SRAM operating
cycle is applied; or (2) synchronously, where a
narrow radiation pulse (20 to 50 nsec) is incre-
mentally moved through the SRAM cycle such
that every portion of the cycle is exposed to ra-
diation. Synchronous testing permits every sensi-
tive region of the SRAM operation to be sub-
jected to radiation-induced transients.
The actual cause of pushout is attributed to the
interaction of the photocurrents with the opera-
tion of the SRAM timing and decode circuits.
Moreover, as can be seen in Figure 3-44, the ex-
act placement of the radiation pulse in the SRAM
cycle has a dramatic effect on the hardness of the
IC. In Figure 3-44, P indicates a transient upset
failure, defined to be an increase in access time
NO UPSET, 5 volts STATIC
NO UPSET, 5 volts DYNAMIC
UPSET
NO. 1 NO. 2 NO. 3 NO. 4
(address transition to data transition) greater than
the specified access time, which for this SRAM
was 40 nsec. Note that P-type upsets were only
seen when the radiation pulse was placed at the
beginning of each cycle, t(garnrna) being the time
of irradiation and to the start of the read cycle
(defined as the time of the address transition).
3.8 Latchup in Integrated Circuits
Latchup is a major concern in both bulk
CMOS and bipolar ICs. The problem is caused
by parasitic bipolar transistor structures that are
inherent in bulk technology CMOS and bipolar
ICs. These parasitic structures can be activated
(latched) by transient ionizing radiation events
(as well as electrical stimuli). When activated, the
parasitic structure assumes a low-impedance
state that can interrupt the normal operation of
the IC and, in most situations, result in circuit
malfunction. Once activated, power must be re-
moved to eliminate the latched condition.
Latchup can occur in several ways, however,
the dominant method is the activation of a para-
sitic four-layer (pnpn) structure, equivalent to a
silicon-controlled-rectifier (SCR), which is found
in both CMOS and many types of bipolar ICs,
e.g., transistor-transistor logic (TTL), Schottky
TTL (STTL), current-mode logic (CML), emit-
ter-coupled logic (ECL), etc.
Four-layer latchup occurs in a microcircuit
when a parasitic pnpn path is triggered into a low
............. j ...... .......i .... ... ...... j.. .......-
I T TRANSIENT UPSET
t (gamma) - t, (nsec)
Figure 3-43. Range of SRAM upset levels due to
Figure 3-44. Effect of radiation pulse timing on
pushout (Murrill and Self, 1993).
SRAM pushout and upset levels (Murrill and Self,
1993).
conductance state. The basic characteristics of
four-layer latchup are illustrated in Figure 3-45.
The nomenclature used is given in Figure 3-
45(a). The four layers are the anode, anode gate,
cathode gate, and cathode with junctions J1, J2,
and J3. As shown in Figure 3-45(b), the pnpn
structure can be represented by two merged tran-
sistors. The dc current-voltage (I-V) characteris-
tic of the path is shown in Figure 3-45(c) for
positive anode voltage with the gates open. When
the positive voltage is large enough to avalanche
J2, the anode current IA reaches a value where
the product of the common-emitter current gains
ANODE
CATHODE
(a) Nomenclature for pnpn Path
I
(c) Positive Voltage I-V Characteristic
J1
CATHODE-
GATE
of the two parasitic transistors is greater than one.
At this point, regenerative action occurs between
the transistors and both are switched to a satu-
rated condition. As illustrated in Figure 3-45(d),
the minimum current for which this condition oc-
curs is called the holding current IH. The anode-
cathode voltage drop in the low-conductance ON
state is the forward voltage drop on the pnp emit-
ter-base junction plus the VCE(sAT) of the parasitic
npn, plus the voltage drop across the resistance
(IR) through the pnp base region. The minimum
voltage in the ON state is the holding voltage VH.
A pnpn path will not exhibit the low conductance
-
(b) Two-Transistor Analog of pnpn Path
I
P
I
/
/
" /
/
/
/
,
/
/
t
n
t
...........................
LATCHING OCCURS AT IA
FOR WHICH Pp p, > 1
-
ANODE
GATE
J2
J3
(d) Current Gain Product Versus Current for pnpn Path
Figure 3-45 (a, b, c, d). Four-layer latchup (pnpn) characteristics (Pease and Alexander, 1982).
state, i.e., it will not latch, if the current gain
product is less than one at all anode currents.
Also the path will not sustain a latch if the cur-
rent is limited to a value less than I, or the volt-
age to a value less than VH.
In addition to the four-layer latchup phenom-
ena, latchup due to second breakdown and
snapback will also be discussed.
3.8.1 Four-Layer Latchup in Bipolar
Transistors
As previously stated, latchup can occur in a
variety of bipolar technology devices. However,
in each case, its cause can be attributed to the
activation of the parasitic four-layer device. Sev-
eral types of bipolar devices exist that are not
susceptible to latchup (e.g., integrated injection
logic [I2L]) due to their inherent design andlor
operating characteristics. Also, those technolo-
gies that have been fabricated using an insulating
substrate are generally latchup-free.
The following discussion addresses several
types of bipolar transistors, which are investi-
gated to identify the presence of a parasitic four-
layer device and the potential for the parasitic
device to satisfy the basic condition required to
latch (e.g., P, x P2 > 1).
In the first example, a TTL 110 circuit that is
part of a larger device will be examined. This I/
0 circuit is illustrated in Figure 3-46, showing
two adjacent npn transistors in an isoplanar I/O
circuit. The parasitic pnpn path is from the base
region of one transistor through the substrate and
out through the collector of an adjacent transistor.
With no current in the substrate, the potential on
the cathode gate is zero and 53 is reverse-biased.
However, under ionizing radiation, a rather large
photocurrent can occur in the substrate that may
forward-bias J3 and temporarily latch the pnpn
structure if the anode-to-cathode bias is >V, and
& x Pn > 1. Once the path is turned on, 53 can be
maintained in forward bias by the shunt resis-
tance Rs between the cathode gate and the sub-
strate ground contact point. If the ground contact
to the substrate is made on the platform to which
the die is bonded, then Rs will be given by the
spreading resistance through the substrate to the
back surface. If the ground contact is made on
the top surface of the chip, Rs will be the resis-
tance through the substrate to the nearest ground
contact. The substrate resistivity for bipolar LSI
circuits usually ranges from 1 IR-cm to 20 Q-cm.
Although the potential for latchup exists in this
first example, it should be noted that the transis-
CATHODE ANODE
p- BASE p-BASE 7
1
- -
Figure 3-46. Cross section of two closely spaced isoplanar npn transistors showing the substrate latchup path pease
and Alexander, 1982).
tor gains (pl x P2) for the parasitic npn and pnp
transistors [shown in Figure 3-46] for an actual
device, the Fairchild 9408 Microprogram Se-
quencer, proved to be less than one. Thus,
latchup is precluded for this particular IC.
In the second example, integrated Schottky
logic (ISL) and Schottky transistor logic (STL),
two forms of high-density bipolar logic, are ana-
lyzed. Both ISL and STL use single-input, mul-
tiple-output inverters as the basic logic unit. In
ISL, the npn switch is kept out of deep saturation
by a vertical parasitic pnp transistor and in STL
by a collector-base Schottky clamp. The isolated
outputs are Schottky contacts to the npn collector
region. AP ISL two-output inverter is shown in
Figure 3-47.
Within the ISL/S?Z logic array, the only para-
sitic pnpn path is from the Schottky collector
(output) through the epitaxial layer, the p-type
npn base region, and the npn emitter. Such a path
exists since the Schottky contact can function as
a p-type region, injecting minority camers at
high current density.
An analysis of this parasitic pnpn path for the
ISLISTL inverter shows that the pnpn path is an
integral part of the circuit, as illustrated in Figure
3-48 for an STL inverter. Since the inverter input
node is the cathode gate of the parasitic SCR, a
positive voltage pulse on this node will latch the
SCR and the output will remain in the ON state
until power is removed. Thus, if this path could
be latched, the inverter output would always be
low and the circuit would not function properly.
Proper electrical operation of the circuit guaran-
tees that the path does not latch. Since the para-
sitic pnp gain is higher at elevated temperature, a
useful latchup screen for this circuit would be an
elevated-temperature test.
The results of the latchup analysis on this ISL/
STL gate array are: (1) if the circuit is opera-
tional under elevated temperature, the only po-
tential latchup path is one between closely
spaced components involving the substrate; and
(2) a potential for latchup exists. Thus, to prevent
latchup, gold doping (Dawes and Derbenwick,
1976) was used to degrade minority-carrier life-
times and reduce the pv x DL product to <1
(where pv = the gain of the vertical. transistor and
& = the gain of the lateral transistor).
3.8.2 Four-Layer Latchup in CMOS
Integrated Circuits
The formulation of the parasitic structure is
described in the following discussion [para-
phrased from Troutrnan (1986)l. A simple inverter
circuit will be used as an example since this cir-
cuit configuration is frequently incorporated in
the implementation of more complex ICs.
Figure 3-49 shows the cross section of an
inverter circuit, and in Figure 3-50 the equivalent
bipolar parasitic transistor circuit is superim-
posed on this cross section. Note that there are
two vertical pnp and two lateral npn transistors.
Both the n-well and the p-type substrate serve
two functions. The n-well is the base for either
vertical pnp and the collector for either lateral
npn. Likewise, the p-type substrate serves as the
base for either lateral npn and the collector for
either vertical pnp. Each of the collector regions
can develop a voltage drop between the collector/
base junction and the collector contact, which
can be modeled as a collector resistance. In addi-
tion, current flowing through some fraction of the
collector resistance can forward-bias the emitter-
base junction of the opposite bipolar device if the
IR drop exceeds several tenths of a volt.
Resistor Rwl in Figure 3-50 represents resis-
tance from the n-well contact to the intrinsic base
region of the first vertical pnp, while resistor Rw2
represents resistance from the intrinsic base re-
gion of the first to the second. RW3(Rw4) repre-
sents the resistance from the intrinsic base region
of VT2 to the point X1(X2), where the current
from LT1 (LT2) is collected. Electrons injected
from the n+ emitters are not all collected at one
point, but the picture has been somewhat simpli-
fied to illustrate the lumped equivalent model. In
some cases (particularly for epi-CMOS), the
points X1 and X2 can be considered the same;
then, the parallel combination of Rw3 and Rw4
can be replaced by a single resistor. In a similar
manner, R,, represents resistance from the sub-
BURIED LAYER
INPUT
OUTPUTS
Figure 3-47. Cross section and circuit diagrzlm of a two-output ISL inverter (Pease and Alexander, 1982).
BURIED LAYER
w
Figure 3-48. Cross section and circuit diagram of a two-output STL inverter (Pease and Alexander, 1982).
-
Figure 3-50. Parasitic bipolar portion of an n-well CMOS inverter (Pease and Alexander, 1982).
strate contact to the intrinsic base region of the
first lateral npn, and Rs2 represents resistance be-
tween the base regions of LT1 and LT2. The re-
sistor Rs3(Rs4) represents resistance from the
base intrinsic region of LT2 to the point Y1(Y2),
where the current from VTl(VT2) is collected.
Again, the physical behavior has been simplified
for the sake of a lumped equivalent circuit.
The total equivalent circuit for the inverter cir-
cuit has the form shown in Figure 3-51. The
simple CMOS inverter, consisting of an n-chan-
nel driver and a p-channel load, is the desired re-
sult of a given layout. In parallel with it, how-
ever, is the circuit formed by the parasitic
bipolars and associated resistors. Under normal
operations, the circuit performs as an inverter,
and the bipolar portion can be ignored. Under
certain conditions, the bipolar operation can
pedance path to ground. If the current from the
supply is not limited somehow, an irreversible
change can take place, such as the fusing of an
aluminum line somewhere in the chip's power
supply or ground line. Even if the current is lim-
ited so that no damage occurs, however, the pnpn
low-impedance state could cause a circuit to mal-
function. To guarantee accurate circuit behavior,
the pnpn must remain in its high-impedance
state.
The actual circuit used to model the parasitic
bipolar devices in a CMOS inverter structure is
shown in Figure 3-52; the corresponding I-V
characteristic is shown in Figure 3-53. Note that
the description of the operation of this structure
is similar to that provided for bipolar transistor
latchup explanation; it is repeated here for com-
pleteness.
dominate the behavior of the total circuit. In par-
The I-V characteristic shown in Figure 3-53
ticular, if the bipolar circuit switches from its
schematically depicts the high- and low-imped-
norma!ly high-impedance state to a low-imped-
ance states. Any characteristic observed for a
ance state, the power supply then sees a low-im-
u
VSS(OR GROUND)
Figure 3-51. Complete circuit schematic for n-well CMOS inverter (Troutman, 1986).
Figure 3-52. Parasitic bipolar portion of a four-terminal pnpn structure [the most common version of the lurnped-ele-
ment model] (Troutman, 1986).
Figure 3-53. Illustrative pnpn I-V characteristic
(Troutman, 1986).
specific prlpn structure depends on how switch-
ing is initiated. Since a pnpn structure is really a
four-terminal device, the observed characteristic
also depends on the terminal conditions of the n-
well and substrate contacts. In Figure 3-53, these
are shown short-circuited. Two key points identi-
fied on this characteristic are: (1) the intersection
of the switching point current I, with the switch-
ing point voltage V,, and (2) the intersection of
the holding current IH with the holding voltage
VH. I, marks the transition from the high-imped-
ance region (also referred to as the blocking state
or OFF region) to the negative differential
resistance region, and IH marks the transition
from the negative differential resistance region to
the low-impedance region (also referred to as the
latched or ON region) A stable high-impedance
state is defined by I < I,, and a low-impedance
state by I, < I < IZ, where IZ is the radiation cur-
rent of the device. At the turn-off point (ITO),
reverse bias on the center junction is zero. The
blocking and latched regions are also referred to
as states since the parasitic pnpn device can sta-
bly reside in each and can be switched from one
to the other.
During normal CMOS IC operation, the pnpn
maintains its high-impedance blocking state, and
the voltage supplies for the IC pass all their cur-
rent through the MOSFET structures. If, how-
ever, minority carriers are somehow introduced
into a bipolar base region, the pnpn can go into
its low-impedance state and latch the cell. Using
the structure of Figure 3-52 as a reference, note
the vertical npn bipolar structure, which can be
turned on if any n+-diffusion injects enough elec-
trons into its p-well base. In a positive-feedback
configuration with the vertical npn is a lateral
pnp bipolar transistor. Holes from a p+ source1
drain diffusion can be injected into the n-sub-
strate base of the pnp. For such canier injection
to result in latchup, the following conditions
must be satisfied:
1. The loop gain of the relevant pnpn [in
Figure 3-53] must exceed unity for the
circuit to latch, i.e., bpnp x bnp > 1.
Under this condition, the positive feed-
back forces the loop to draw current to
the limit of the power supply's sourc-
ing capability (or the circuit's current
sourcing capability).
2. A triggering condition must allow the
loop to achieve the current level re-
quired to switch itself ON (latched).
3. The IC bias supply and associated cir-
cuitry must be capable of supplying at
least the holding current and voltage
required to sustain the latch once it is
initiated.
Latchup can be initiated electrically by signals
applied to IC terminals, or it can be triggered by
radiation events. Here, the focus is on radiation-
induced latchup. The SCR may be turned ON by
a radiation-induced electrical transient, by ioniz-
ing radiation characteristics of dose-rate events
(Brucker, 1977), or by a single event (Kolasinski
et al., 1979; Soliman and Nichols, 1983). Each
of these triggering mechanisms injects minority
carriers into the base of the parasitic bipolars.
Ionizing radiation from dose-rate events can in-
ject current across the well/substrate junction.
For p-well CMOS, the photocurrents from gener-
niques for latchup investigations include the use
of radioactive 252Cf as a high-LET particle source
(Reier, 1986; Stephen et al., 1984a) and a scan-
ning electron microscopy (SEM) to identify
latchup paths (Dressendorfer and Armendariz,
1980). Theoretical models for heavy-ion-induced
latchup are also available (Shoga and Binder,
1986).
3.8.3 Other Latchup Mechanisms
3.8.3.1 Snapback
Latchup in n-channel devices can also be
caused by an effect called snapback (Ochoa et
al., 1983), which results in a high-current mode
that interferes with normal circuit operation. This
effect does not involve an SCR structure.
Snapback can be initiated by current injected into
a p-well due to avalanching junctions or result
from ionizing radiation. Investigators have mea-
sured snapback-sustaining voltages signscantly
lower than the drain-substrate avalanche voltage.
This effect therefore imposes a maximum operat-
ing voltage constraint on susceptible ICs (Ochoa
et al., 1983). Snapback is a three-layer effect,
where drain avalanche current is sustained by
minority-carrier injection from the source of an
NMOS device. Figure 3-54 shows typical
snapback characteristics and a proposed lumped-
parameter model. Unlike latchup, there is no
positive feedback loop, so snapback can be ter-
minated by normal cycling, for instance, when
the transistor output goes to zero. Because of the
mechanisms involved, latchup prevention tech-
niques that degrade the &, , x P,,, product by
irradiation have little effect on the snapback
threshold drain voltage.
atedmajority carriers, i.e., electrons in the sub-
3.8.3.2 Second Breakdown
strate (holes in the well), act as base currents of
the parasitic bipolar devices and tend to turn on
Another mechanism that can cause latchup in
the SCR. The heavy ions present in galactic cos-
diodes, bipolar and MOS transistors, and espe-
mic rays and solar flares produce long ionization
cially in integrated circuits, is second breakdown
tracks that can also provide carrier injection to
(Schafft, 1967; Sze, 1981; Sze and Gibbons,
initiate latchup. Several researchers have investi-
1966). Second breakdown can sometimes be in-
gated this mechanism using heavy ions acceler-
duced at low current levels without damage to
ated in cyclotrons (Kolasinski et al., 1979;
the junction. The usual result of second break-
Nichols et al., 1986; Shiono et al., 1986; Soliman
down is,of course, permanent junction damage
and Nichols, 1983). Other experimental tech-
(Sunshine and Lampert, 1972). Because ionizing
\ VAVALANCHE I
LOAD LINE
VSUS VDD
(a) I-V Characteristics
(b) Lumped Parameter Model
Figure 3-54 (a, b). The snapback phenomenon: I-V characteristics and a Lumped-parameter representation (Ochoa et
al., 1983).
pulses can trigger this action, latchup can ensue.
Second breakdown is similar to SCR action in
that once it is initiated, i.e., the ON state is
reached, it is sustained until the latchup current is
reduced below the threshold, as shown in Figure
3-55. Dielectric isolation does not guarantee a
latchup-free system in this case, although the
substrate plays no role as it does in the four-layer
pnpn switch. Bipolar collector-base junctions and
reverse-biased diodes are susceptible if they have
a second-breakdown characteristic by virtue of
their construction. Diffused passive components,
such as resistors, are also susceptible if the junc-
tion region isolation for the resistor possesses a
second-breakdown characteristic.
Second breakdown is manifested by a sudden
drop in the bipolar transistor voltage VCE with an
almost simultaneous surge in collector current.
This phenomenon limits high-power transistor
operation to a specific safe operating area (SOA)
of its characteristic curves, as seen in Figure
3-56. Chronologically, this instability occurs at
the breakdown voltage at which the collector cur-
rent equals Ic in Figure 3-57, immediately fol-
lowed by a sudden drop to a low-voltage regions
at the end of the dotted lines in Figure 3-57. The
final stage is imminent when Ic grows to cause
device destruction. Associated with second
breakdown are the final values of collector cur-
rent, which result in the formation of a hot spot
and production of a localized microplasma in the
COLLECTOR-EMITTER VOLTAGE, VCE (volts)
Figure 3-55. Typical second-breakdown characteris-
tic (Messenger and Ash, 1992).
. -
loo 2 4 68101 102 103
COLLECTOR-EMITTER VOLTAGE, VCE (volts)
Figure 3-56. Safe operating area bounds for silicon
transitors for peak junction temperature at 150" C
(Sze, 1981).
device, short-circuiting the junction (Ward,
1976). Reverse-bias second breakdown can be
caused by an inductive load suddenly forcing a
large negative polarity current through the de-
vice, resulting in a high transient breakdown re-
verse bias at the junction. This also causes a
plasma formation and pinhole shorts at the junc-
tion.
3.8.4 Latchup Windows
Even though an IC experiences latchup in
response to an experimental dose-rate level, it
may operate normally at a higher dose-rate level
and then latch up at a third, yet higher level.
A dose-rate region of latchup-free behavior be-
tween two regions of possible latchup is called a
latchup, window (Azarewicz and Hardwick,
1982). Such windows can cause problems in
hardness assurance because they make identifica-
tion of latchup-immune ICs more uncertain.
Several mechanisms have been hypothesized to
explain these windows, but the responsible
mechanism has not yet been unambiguously
determined. A mechanism suggested by Coppage
et al. (1983) proposes that over some range of
dose rates, competing photocurrents from trans-
mission gates elsewhere in the device can cancel
the injection current to the pnpn structure. They
attribute the windowing effect to the complex
COLLECTOR-EMITTER VOLTAGE, VCE (volts)
Figure 3-57. Collector current versus collector-emit-
ter voltage under second breakdown (SchaEt, 1967).
injection-level dependencies of spatial charge
distributions within CMOS ICs. More recently,
researchers have proposed that the window re-
sults from distributed effects such as lateral sub-
strate currents and distributed resistances, which
are not morlotonic functions of dose rate in some
structures (Johnston and Baze, 1987).
3.8.5 Latchup Mitigation
There are two fundamental strategies for
avoiding latchup (Troutman, 1986):
1. Keeping the parasitic pnpn structure in
the blocking state,
2. Preventing the parasitic pnpn structure
from reaching the latched state.
These two strategies initially may appear similar,
but very important distinctions exist. The first
strategy is implemented by making the switching
point inaccessible to any static or dynamic oper-
ating point. Usually, this means designing the
switching current to be larger than the maximum
suppliable current.
The second strategy is implemented by mak-
ing the holding point inaccessible to any static or
dynamic operating point. This means either
designing the holding voltage larger than the
power-supply voltage (plus a safety margin) or
designing the holding current larger than the
maximum suppliable current. However, in the
second case, transient SCR behavior can result if
device current exceeds the switching current.
Behavior of a circuit containing a parasitic pnpn
structure can be unpredictable once the pnpn is
triggered into the negative differential resistance
region. The safest approach is to avoid entering
the negative differential region, even momen-
tarily, which is guaranteed by the first strategy.
Avoiding the negative differential region may be
accomplished by designing a large enough hold-
ing voltage using the second strategy; however, a
sufficiently large holding voltage is difficult to
design dircctly for all parasitic pnpn structures
encountered in CMOS chip designs because
holding voltage is not well modeled. Finally, it
should be noted that any of the guidelines that
are implemented to raise switching current auto-
matically raise holding current for the same
structure. Thus, Strategy 1 prevents any pnpn
switching, even transient. It is also easier to
implement since the switching edge of the block-
ing state is precisely defined, with no fitting pa-
rameters required.
Techniques to implement these strategies di-
vide into two areas: namely, layout guidelines
and process design. The first is germane to any
CMOS technology and is of interest to the device
and circuit designer. The second relates to the
process features incorporated into a CMOS tech-
nology by the process engineer.
For bulk technology devices, guard structures
are the most effective tool available to the circuit
designer. A minority-carrier guard is used to pre-
collect minority carriers injected into the sub-
strate before they reach a well comprising the
base of a vertical bipolar. It consists of a reverse-
biased pn junction formed by a source/drain or
well diffusion. It is more effective on epi-CMOS
because of the reflecting boundary at the high-
low junction and because of increased recombi-
nation in the highly doped substrate.
A majority-canier guard is used to reduce well
or substrate sheet resistance locally, thus mini-
mizing any ohmic drop from parasitic collector
current. It consists of a source/drain diffusion of
the same type as the background. Operation of a
majority guard in the well is also enhanced on
epi-CMOS because the elimination of substrate
minority-carrier collection at the bottom well
junction means that majority carriers in the well
appear only at its periphery, where they are more
easily shunted away from parasitic emitters.
Multiple well contacts augment the low-by-
pass resistance effected by majority guards in the
well. Some combination of the two should also
be used on I/O circuits to ensure the parasitic ver-
tical bipolar is not turned ON by I/O over- and
undershoots. In addition to avoiding latchup, the
goal here is to prevent large current spikes in
these high-gain devices, which otherwise would
waste power.
A substrate contact ring should be mandatory
for all chips. It minimizes lateral bypass resis-
tance by distributing substrate majority camers.
On epi-CMOS, the contact ring can reduce lat-
eral bypass resistance to below 1 ohm.
The second area in which much work has been
done to avoid latchup is process design, for
which there are two approaches: bipolar spoiling
and bipolar decoupling. Early spoiling tech-
niques attempted to reduce base minority-carrier
lifetime with either gold doping or neutron irra-
diation, but this has led to adverse device effects
such as high leakage current. Later, internal
gettering was introduced to lower lifetime in the
substrate below the denuded zone, but this has
little effect on parasitic lateral bipolars with small
base width. A retrograde doping profile in the
well helps prevent latchup by reducing vertical
transport, but care must be taken to remove in-
jected carriers so that lateral transistor action to
the well edge is not enhanced.
Bipolar decoupling has proved more effective
and easier to implement than bipolar spoiling.
Several methods are possible. A highly doped
substrate beneath a lightly doped epitaxial layer
shunts the lateral parasitic bipolar very effec-
tively. As discussed above, this combination also
improves the efficacy of minority guards in the
substrate and majority guards in the well. A ret-
rograde well can also be used to reduce the well's
sheet resistance, although this is usually not as
effective as the inclusion of majority-carrier
guards in the well. Reverse bias on the substrate
(or well) raises the bypass current needed to turn
on the corresponding bipolar, but using ON-chip
generators to provide this bias necessitates care-
ful guard design to eliminate charge injected by
the generator. Trench isolation eliminates lateral
current flow to and from the well and conceiv-
ably could allow a lithographically limited n+/p+
spacing. Present side-wall inversion problems
must be resolved before diffusions can be butted
against trench walls, however.
Bipolar decoupling provides a simple design
procedure for avoiding latchup:
1. Decouple the vertical parasitic bipolar
using epi-CMOS with a substrate con-
tact ring to minimize lateral bypass
resistance,
2. Decouple the lateral parasitic bipolar
using majority-carrier guards in the
well or minority-carrier guards in the
substrate.
Additionally, the use of an insulating substrate
technology (e.g., SOS or SOI) that isolates the
complementary devices provides an effective
method for eliminating latchup.
3.9 Transient Radiation Effects on Electro-
Optical and Passive Components
The effects of transient ionizing radiation on a
variety of electro-optical devices and components
(e.g., fiber optic cables, detectors, etc.) and vari-
ous passive electronic components (e.g., resistors
and capacitors) are discussed below.
3.9.1 Electro-Optical Components
For many fiber-optic systems, one of the most
stringent requirements is the high-dose-rate, tran-
sient dose requirement. While forward-biased
lasers and light-emitting diodes (LEDs) are es-
sentially immune to high-dose-rate effects, pho-
todiodes, fibers, some connectors, and possibly
optoelectronic integrated circuits (OEICs) are all
susceptible to high-dose-rate effects, which can
significantly degrade system performance. In
many doped core fibers, a large transient pulse of
ionizing radiation can cause serious temporary
darkening of the fiber that lasts well beyond the
time when the system should be back on line and
functioning [see Figures 3-58 and 3-59]. For ap-
plications that require a long fiber (>50 meters)
and fiber-optic links that "operate through" a
relatively high-dose-rate pulse (>10l0 rads[Si]/
sec), the fiber must be chosen with great care. If,
as in the case of a missile or tethered weapon ap-
plication where the projected lifetime is short
and, as a consequence, the cumulative ionizing
radiation dose is not particularly large but the
dose rate is high, then the addition of phosphorus
to the fiber core will reduce the transient attenu-
ation. While pure silica core fibers are available
that can withstand considerably higher dose-rate
pulses, additional technology development re-
mains to be done in this area, especially for those
applications that require specialized fibers, such
as the polarization maintaining single-mode fiber dose effects. Figure 3-60 illustrates that the sig-
in a fiber-optic rotation sensor (FORS). nal level increases as a result of luminescence
during the radiation pulse and reaches a mini-
3.9.1.1 Cptical Fibers
mum at the end of the pulse because of induced
The transient attenuation of the light intensity
absorption.
transmitted through an optical fiber caused by a
pulse of ionizing radiation can be larger, and
Unlike transient luminescence, which exhibits
potentially more of a problem, than the perma-
prompt decay and can be filtered out because it is
nent attenuation caused by ionizing radiation
in the ultraviolet (UV) range, transient attenua-
TIME (seconds)
Figure 3-58. Transient attenuation in a variety of fibers (Fribele, Gingerich, and Sigel, 1978).
tion can last much longer than the ionizing pulse.
As in the case of permanent effects, the degree
of transient attenuation depends strongly on the
characteristics of the core of the fiber. Although
there is considerable variation among both pure
and doped core fibers, generally the pure core fi-
bers exhibit significantly less transient attenua-
tion. Representative transient attenuation data are
shown in Figure 3-58 for a variety of fibers oper-
ating at 0.8 pm after a prompt dose of approxi-
mately 3 krads. Note that the Gedoped Corguide
fiber has the largest attenuation. Again, as in the
case of permanent effects, phosphorus and boron
have relatively unique effects on transient attenu-
ation. While these dopants increase permanent
attenuation, as can be seen at long times in
Figure 3-58, they have the opposite effect on
transient attenuation in that they tend to eliminate
or minimize the attenuation observed shortly
TIME
1 nsec 1 psec 1 msec 1 sec 1 min 1 hour 1 day 1 year
I I
Figure 3-59. Radiation sensitivity of fibers (Schneider et al., 1987).
after the pulse. Note also that the pure-core fibers to a dose rate of approximately 1 x 10"
Suprasil fiber has low transient attenuation. radslsec. This exposure also results in an ionizing
Transient attenuation data from more recent
work are shown in Figure 3-59 for a variety of
fibers operating at 830 nm at room temperature.
To obtain the results in Figure 3-59, a dose of 45
krads was delivered with each pulse, which, for a
typical FXR or LINAC pulse, corresponds to a
dose rate of about 1 x 1012 radslsec. With the ex-
ception of the alkali glasses, the Gedoped core fi-
bers exhibit the most intense transient attenua-
tion, and the addition of phosphorus (P) reduces
the transient effect but enhances the permanent
damage. The Diasil and Fluosil fibers are pure
core fibers. It comes as no surprise, given the
complexity of the various color-center growth
and anneal processes that can take place, that the
recovery curves have a variety of shapes.
In order to summarize other important features
of ionizing radiation-induced transient attenua-
tion in fibers, Figures 3-61 and 3-62 display data
for high-OH and low-OH fibers, respectively.
These results are for the exposure of pure core
radiation dose of 3.5 krads. As for the case of
permanent attenuation, the high-OH fibers per-
form better across all the variables shown in the
figures, with an improvement of roughly a factor
of 10 reduction in transient attenuation. The other
important trends revealed by these results are
about the same for both high- and low-OH fibers,
as follows:
1. The recovery of the transient attenua-
tion is slower at lower temperature,
2. The transient attenuation is less at 1,300
nm than at 830 nm, which is in agree-
ment with permanent attenuation re-
sults,
3. Transient attenuation is also suscep-
tible to photobleaching-inducedrecov-
ery [note the varying power levels Po in
Figures 3-61 and 3-62], except that
photobleaching is not very effective at
less than about 1 msec after exposure.
TIME ---+
Figure 3-60. Transient ionization effects in fibers (Sigel and Evans, 1974).
-I.:
LUMINESCENCE
PERMANENT
ABSORPTION
INITIAL
LIGHT LEVEL
. .
. .
. . . . . . . . .;
. .
. . . . . . . . . . .
I.............. . . .
. . . . . . . . .
. . . . . . .
. . . . . . . . . . .
....
. . . . .
:..:..:.:..
t
:. :'.......' :' MAXIMUM TRANSIENT
....
. . . . . . . . . . ABSORPTION
..............
i
. . . . . . .
...............
;. ... .:. . '. ... :.:
. . . . . . . . .
. . . . . . . . .
. . .
' . . . : . : . . I .:.
. . . . .
. . . . . . . . . . .
:...:. ;'. .::
. . . . .
. . . . . . .
. . . . . . . . .
..:.... ;:.'
............
. . . :. ....
....
..........
...... :.. .
:.... : ... ...:.:.;
.::.
;. ...I.- :..-:.:
. . . . . . . . .
. . . . . . . . .
+ RAD IATlON BURST
1 0 3 ~ I I I I
I I I =J
- I I I
- -
-
-
L = 40 meters -
................-
L = 40 meters
-
-
- -
n
- -
W
-
0
-
3
-
n
4- -
- -
---- h= 1,300 nm
2-
-
10'1 - I I I I I
10-6 1 0 - ~ l o0 l o3 1 06
TlME (seconds)
Figure 3-61. Parameter effects on attenuation in a high-OH fiber (Schneider et al., 1987).
1 0 4 ~
I
-
I I I I I I I 3
-
-
- -
-
-
-
-
-
- -
....................
7 -
-
- -
-
-
7
-
h
-
....................... .................... t ............
n
-
W
........................ ..........................
g 101 = ....................
n
- -
z
-
-
7
- -
-
-
-
-
-
- -
10" - ............... ................ & 100.0 ............... =
8 y = 3.5 krads
-
6 =
-
-
-
4-- h = 830 nm
-
-
---- k = 1,300 nm
2-
-
-
10-1 I I I I I I I
lo-g lo-6 10-3 1 oO 103 l o6
TlME (seconds)
Figure 3-62. Parameter effects on attenuation in a low-OH fiber (Schneider et al., 1987).
3.9.1.2 Electro-Optical Devices
The sensitivity of electro-optical devices to
prompt gamma radiation depends on the device
type. Photodiodes and phototransistors are very
sensitive to radiation. Both types of detectors
have long minority-carrier lifetimes and large
volumes for efficient collection of light-gener-
ated carriers, which causes the devices to gener-
ate and collect large prompt gamma-induced
photocurrents. Photocurrent in the phototransis-
tor is amplified by the gain of the device, which
causes the phototransistor to be more sensitive to
radiation than a photodiode. Intense transient
ionizing pulses can also cause significant tran-
sient currents in silicon PIN photodiodes. Dose
rates of about lo9 rads(Si)/sec are typically large
enough to produce saturated transient pulses
from a silicon PIN photodiode detector. How-
ever, 111-V detectors have been shown to dis-
criminate between optical signals and ionization
pulses of 1 x lo9 rads(Si)sec magnitude with
little or no optimization or circuit compensation.
LEDs have shorter minority-carrier lifetimes
and smaller volumes than photodiodes. Their
photocurrents, therefore, are much smaller than
the photocurrents produced by the photodiodes.
LEDs will emit light for the duration of the pho-
tocurrent pulse. Laser diodes are even less sensi-
tive than LEDs since most laser diodes are GaAs
and have higher electron mobility, larger
bandgap, and smaller geometry than silicon
LEDs.
The photocurrent response of an optical cou-
pler depends on the type of components con-
tained in the device; the most sensitive couplers
can upset around 1 x lo6 rads(Si)/sec. Optical
couplers, which have LEDs and photodetectors
such as photodiodes or phototransistors, will
have responses similar to those described above.
Devices with laser diodes and small-geometry
detectors have the highest upset threshold. If an
amplifier or gating logic is incorporated into the
output ofjthe coupler, the response will also
depend on the transients in these components.
The recovery time may be fairly slow if a linear
IC is used in the coupler circuitry.
High-dose-rate effects in simple LiNbO,
OEICs have also been observed, but only at very
high rates, of the order of 1 x 1013 rads(Si)/sec,
using electron pulses. Temporary reduction
in transmitted signal and coupling between
waveguides can last well beyond the radiation
pulse.
3.9.2 Passive Components
3.9.2.1 Resistors
Radiation effects in resistors are generally
small compared to effects in semiconductors and
capacitors. Transient effects are generally caused
by photons interacting with the resistive medium
and its encapsulation to generate electrons and
ions. If there is a net charge produced in a resis-
tor by photon interactions, a current may be
induced in the resistor in order to replace the
charge removed or added by the incident radia-
tion. This current is referred to as the replace-
ment current.
Pulsed ionizing radiation on discrete resistors:
(1) temporarily changes the effective resistance
of the component, and (2) induces a current pulse
in the component as a result of emission and ab-
sorption of secondary electrons. For many resis-
tors, ionization causes increased conductivity in
the bulk resistance, insulating materials, and sur-
rounding medium, so the effective resistance
decreases. In some cases, however, test results
show that for some resistors, the effective resis-
tance increases during the exposure because of
injected replacement currents. These effects can
be described in forms of a current source IR(t),
which is the replacement current, and a shunt
resistance Rs, which represents the leakage cur-
rents in the resistor and its surrounding material.
The magnitudes of both depend on the dose rate,
surrounding medium, resistance material, and
applied voltage.
Table 3-1 shows shunt resistance values and
peak values of injected replacement currents for
various types of resistors at an exposure rate of
4 x lo7 rads(Si)/sec. Equivalent shunt resistance
is higher for solid construction than for air-core
resistors. For wire-wound and solid-carbon resis-
Table 3-1. Transient effects on resistors (Steel et al.,
1964).
Radiation-Induced Peak Injected
Shunt Resistance, Rs Current, IR
Resistor Tvue (MQ) (uA)
Carbon film 10.4 to 0.6 45
(air core)
Metal Film 2 to 4 18
(air core)
Carbon composition 2.6 to 6 29
(air core)
Solid 10 to 110 27
Metal film (solid) 9 to 100 24
Carbon film (solid) a 32
Wire-wound a
Solid a
Air core a
Note: aWire-wound resistor increase 0.1 to 0.5
percent; carbon film increases 0.5 to about
5 percent. Effective resistance showed in-
crease rather than decrease [see related
text].
tors, an effective increase is shown, which is an
exception to the general rule that ionization
effects decrease resistance. All the resistors emit
a net number of electrons, resulting in a net in-
jected current. The magnitude of the injected cur-
rent generally increases with the increased physi-
cal size. In most practical applications, the cur-
rent is small and may be neglected.
Figure 3-63 shows the shunt conductance Gs
as a function of exposure rate for various resistor
types of 1-Mi2 nominal value. These data were
obtained with external air leakage across the
component essentially eliminated (Steele et al.,
1964). Resistors for which this is not done can be
expected to have larger radiation effects.
On the basis of the curves given in Figure 3-
63, the shunt resistance is (S teele et al., 1964)
where A is the slope of the appropriate line, 11
K is a constant determined from the figure, and
j is the exposure rate.
First-order approximations for the shunt resis-
tance and the replacement current as functions of
the exposure rate are
and
where A is a constant having the dimensions
i2-rad(C)/sec, and P is a constant having the
dimensions A/rad(C)/sec. The proportionality
constants vary with the wattage and potting ma-
terial of the resistor.
EXPOSURE RATE, j (rads[M]lsec)
Figure 3-63. Resistor exposure-rate dependence; ex-
ternal air ionization not included perkins and Bailey,
1964).
0 1 I8 1 I4 318 112
POTTING DEPTH (inches)
Figure 3-64. Effects of potting depth on current injec-
tion for carbon compostion resistors with epoxy and
ceramic cases (Perkins and Bailey, 1964).
Potting reduces ionization and improves the
performance of a resistor and is indicated if
stable values >10 klR must be preserved during
irradiation; conformal coating suffices for lower
values. Spraying and dipping of resistors may be
insufficient to significantly reduce leakage. The
effect of the shunting resistance Rs can be appre-
ciable for unpotted M!2 resistors at lo6 to lo7
radslsec.
The potting thickness may be important in
determining the replacement current in some
cases. Replacement currents as a function of pot-
ting thickness are shown in Figure 3-64. There is
little variation in emission current with paraffin
thickness. However, the high-electron-density
Silastic causes net electron injection to occur at
potting-depth thicknesses greater than approxi-
mately 118 inch. This curve indicates there may
be an optimum potting depth in some cases.
The effect of the replacement current can be
reduced by the "virtual ground" technique wher-
ever the circuit permits its application. A variable
resistor is connected in parallel with the exposed
resistor an3 balanced so that a virtual ground lies
at the electrical center of the irradiated specimen.
Figure 3-65 shows current injection for a resis-
tor versus voltage. The curve is linear with a
change in slope at negative voltages sufficient to
prevent the collection (injection) of low-energy
( 4 0 eV) scattered electrons (Perkins and Bailey,
1964).
3.9.2.2 Capacitors
The main effect of pulsed ionizing radiation on
capacitors is a temporary increase in the conduc-
tivity of the capacitor's dielectric material. The
conductivity increases promptly during the initial
part of the radiation pulse, but decays at a slower
rate than the radiation pulse. The radiation-
induced current and changes to the voltage in the
capacitor are illustrated in Figure 3-66. The
prompt conductivity produced in various types of
capacitor dielectric materials over a range of dose
rates is shown in Figure 3-67. If the conductivity
level for a capacitor is sufficient to be of concern
in a circuit, the time waveform of the conductiv-
ity can be estimated analytically. Capacitors are
generally not a problem because semiconductor
photocurrents usually dominate the response of
the circuit.
Figure 3-65. Effects of applied voltage on current in-
jection for a 100-kW 1-watt carbon composition resis-
tor in l/2-inch Silastic (Boeing, 1964).
DOSE RATE
(rads[Mysec)
RADIATION PULSE
I
f I I
I Ib
TIME, t
I I
VOLTAGE I CAPACITOR
LOSSfl'IME, I RECHARGE = DISCHARGE
AVIAt I (AVlAt = 0)
I I
RECHARGING
CAPACITOR VOLTAGE
(HffiH-IMPEDANCE RECHARGE CIRCUIT)
I '
t
I I
TIME, t
I I
RADIATION I I
I I ITLAYED
CAPACITOR CURRENT
(LOW-IMPEDANCE RECHARGE CIRCUIT)
TIME, t
Figure 3-66. Capacitor photoconductivity characteristics [combined recharging and discharging effects result in a
compsite voltage loss/tirne curve that later becomes a decreasing exponential] (Thatcher and Greeen, 1972).
Figure 3-67. Prompt conductivity versus gamma dose rate (Thatcher and Kalinowski, 1969).
A capacitor exposed to a pulse of ionizing
radiation will exhibit a transient discharge due to
an increase in the shunt conductors of the dielec-
tric. It is convenient to represent the capacitor in
terms of the equivalent circuit shown in Figure
3-68 when using capacitor transient radiation
effects data to predict the behavior of irradiated
circuits. In this representation, the total resistance
RT is given by
where
l/Ro = pre-irradiation leakage
conductance = soC/eeo
1/R, = radiation-inducedleakage
conductance = (s - so)C/eeo
so = initial conductivity
C = capacitance
e = dielectric constant
eo
= dielectric constant of free space
s = conductivity.
At high exposure rates, RT = RS for all practical
purposes.
In applications to circuit design, each capacitor
should be represented by its equivalent circuit
[Figure 3-68]. The conductivity during a speci-
fied high-rate radiation pulse is computed using
the appropriate characteristic parameters, and the
effective leakage resistance is determined from
RT = EEJOC. Using this value for the leakage
C = CAPACITANCE
RT =TOTAL LEAKAGE RESISTANCE
Figure 3-68. Capacitor equivalent circuit (Thatcher
and Kalinowski, 1%9).
resistances of the capacitors, the behavior of the
circuit can be determined. Except where the
radiation pulse is a simple function of time, the
equations governing the circuit behavior may be
quite complicated. It is recommended that the
possibility of using approximations to the radia-
tion pulse be investigated before an exact solu-
tion is attempted.
The voltage remaining on a capacitor imrnedi-
ately after a radiation pulse may be calculated
from a rule of thumb to obtain design informa-
tion. Equation 3.47 [below] is applicable for this
purpose when the radiation pulse duration is
short compared to the recharging time constant
of the circuit:
where RT = EEJOC.
If the delayed components can be neglected dur-
ing the pulse,
and the average dose rate j is given by
where y is the dose delivered in a pulse of t . sec-
onds at a dose rate j .
Combining Equations 3.44 through 3.49, the
voltage at the end of the radiation pulse can be
expressed as:
A more detailed approach is given in Cordwell
(1968).
3.10 Single-Event Phenomena
Advances in memory technology have led to
increased packaging densities while power con-
sumption has been reduced. In general, this min-
iaturization trend has been beneficial to satellite
and avionics technology, except that a new mode
of device failure has accompanied device minia-
turization. In the near-earth regions of space,
high-energy particles are always present in the
radiation belts and occur sporadically at high lati-
tudes due to solar flares and the galactic flux. In
such particle environments, microelectronic de-
vices are susceptible to operational disturbances
known as single-event phenomena (SEP), which
pose a serious problem for silicon MOS and bi-
polar circuits and GaAs circuits. SEP distur-
bances can be divided into four basic categories:
single-event upset (SEU), single-event latchup
(SEL), single-event burnout (SEB), and single-
event gate rupture (SEGR).
Basically, an SEU is an upset to the informa-
tion stored in memory devices, memory elements
of integrated circuits, or the inability of a semi-
conductor device to interpret information due to
a disturbance in processing electronics. By defi-
nition, an SEU is said to occur when a single,
highly ionizing particle produces a track of dense
ionization in a semiconductor material, which
affects device operation through charge collec-
tion (Ward, 1986). Due to the transient, nonper-
manent effect of an SEU, this type of disturbance
is termed a "soft error." The other SEP effects
(i.e., SEL, SEB, and SEGR) are termed "hard er-
rors."
The single-event upset of a computational sys-
tem used in a spacecraft can result in a cata-
strophic mission failure. In addition to
data-register errors, which are similar to soft
errors in memory chips, a bit-flip in a micropro-
cessor can lead to a runaway processor. The run-
away processor can overwrite random access
memory (RAM) before ending up in an idle loop
or coming to a complete halt, with the result that
system survival can be jeopardized.
Microcircuit pnpn latchup from transient ion-
ization is a considerable problem for systems that
are required to operate in the nuclear-threat envi-
ronment. Latchup is a low-impedance state re-
sulting in a high-current drive that persists until
the voltage drops below a certain voltage level
(generally accomplished by cycling device
power) or until device damage occurs from over-
heating. SEL, latchup from heavy ions, has been
observed in bulk CMOS devices and in epitaxial
CMOS devices in which the epitaxial thickness
has not been optimized for prevention of latchup.
SEB is catastrophic failure that occurs when
an n-channel power MOSFET suffers a gate,
drain-source, or source-drain short as a result of
a heavy-ion-induced turn-on of a parasitic bipo-
lar junction transistor inherent within the struc-
ture and results in regeneration or avalanche and
thus burnout. Power bipolar junction transistors
can undergo SEB in a similar manner. SEGR is a
permanent destructive event that results when a
penetrating heavy ion deposits sufficient energy
to cause rupture of the gate dielectric and shorts
from the gate through the channel. SEGR and
SEB are termed hard errors due to their perma-
nent nature.
Since high-energy cosmic rays can easily pen-
etrate several inches of aluminum, shielding
against SEP is impractical. Increasing levels of
integration and device miniaturization have re-
sulted in an increasing susceptibility of devices to
soft errors, and this susceptibility has become a
major concern to the military and aerospace com-
munities. Hence, the system designer must be
able to quantify the SEP susceptibility of the
mission-required electronic components and de-
velop safeguards to ensure mission success.
3.10.1 Historical Background
The first discussion of the concepts underlying
SEU was offered in a paper by Wallmark and
Marcus (1962). These authors predicted that
when IC feature sizes became small enough, cos-
mic rays would start upsetting microcircuits due
to the heavily ionized tracks and cosrnic-ray-
induced spallation reactions. They were so far
ahead of their time, however, that the paper was
entirely overlooked. The next important paper to
be published was Binder, Smith, and Holman
(1975), in which upsets in digital flip-flop cir-
cuits were reported to have been observed in cer-
tain space satellites. Partly because the number of
upsets observed was small, their claim that the
upsets were due to cosmic rays in the iron group
was disputed by most radiation-effects specialists
at the time. Their published paper was quite
remarkable in that: (a) it identified cosmic rays in
the iron group as the likely cause of the upsets,
(b) it showed how to calculate the rate at which
cosmic-ray upsets could be expected to occur,
and (c) their calculations were within a factor of
two of the number of upsets that were actually
observed. However, due to the aforementioned
skepticism, this paper was also largely ignored.
In 1978, two research efforts were completed
that awakened the radiation-effects community to
the new phenomenon of "soft errors," as it was
then called. The first was reported in a paper by
Pickel and Blandford (1978). In this paper, a
model was developed to predict the cosmic-ray
bit-error rate in dynamic MOS RAMs. Specifi-
cally, this cosmic-ray interaction model was used
to estimate the bit-error event rate in an operating
satellite memory, which consisted of 24 NMOS
RAMs, each with 4096 memory bits. The upsets
were attributed to energetic cosmic rays in the
iron and aluminum groups. In this paper, the
number of upsets was large enough to be con-
vincing, and it was this paper that particularly
alerted the space and nuclear radiation effects
community to the existence of this new and im-
portant radiation effect. The method used for cal-
culating the number of upsets to be expected in a
cosmic-ray environment was similar to that of
Binder, Smith, and Holman (1975), but used
more detailed models, both for the device geom-
etry and the cosmic-ray environment. At this
time, circuit upsets were typically referred to as
soft errors or single-particle errors (for single
cosmic-ray particles).
The second effort was not published until 1979
(May and Woods, 1979), in which it was deter-
mined that the upsets being observed at sea level
in dynamic RAMs (DRAMs) were due to alpha
particles emitted from trace amounts of uranium
and thorium present in the packaging materials
used in the fabrication of electronic devices;
these upsets were creating a serious problem
from the standpoint of device reliability. The ex-
perimental measurements were performed with
polonium and americium alpha sources on 4k
DRAMs and 16k CCDs. May and Woods intro-
duced the concept of critical charge for upset and
predicted that the soft-error problem would
worsen as device feature sizes became ever
smaller.
After hearing the Pickel and Blandford paper,
and learning of the work of May and Woods,
Guenzer, Wolicki, and Allas hypothesized that if
alpha particles from uranium and thorium could
upset circuits, then alpha particles from nuclear
reactions induced by energetic neutrons and pro-
tons might also be able to produce such upsets
(Guenzer, Wolicki, and Allas, 1979). In late
1978, measurements were made on 4k and 16k
dynamic MOS RAMs, first in a 14-MeV neutron
beam of a 75-MeV cyclotron at the Naval Re-
search Laboratory, and then with 14-MeV neu-
trons from a deuterium-tritium generator. First
upsets were observed at neutron fluences of -108
n/cm2. The discovery that DRAMs were vulner-
able to such low neutron fluences was startling at
the time because DRAMs are majority-carrier
devices and were expected to be hard to neutron
fluences three to four orders of magnitude larger
than lo8 n/cm2. Fluences for first upset, by 32-
MeV protons, were also about lo8 protons/cm2.
These results were presented at the 1979 IEEE
NSREC. This paper correctly identified neutron-
and proton-induced nuclear reactions as the
cause of the upsets; because more than one par-
ticle was involved (unlike the case of single cos-
mic-ray particles), this paper was entitled,
"Single Event Upset of Dynamic RAMS By
Neutrons and Protons." Thus, the term "single-
event upsets" has taken its name from this paper.
Another important paper presented in 1979
reported the discovery of heavy-ion-induced
latchup in SRAMs (Kolasinski et al., 1979).
These were the first upset experiments to be con-
ducted with high-energy heavy ions from an
accelerator and the first to observe cosmic-ray-
induced latchup. Thus, it was demonstrated that
the SEP events expected in space could be simu-
lated in earthbound experiments.
As SEP were exhibited in greater numbers of
employed space systems, the extent of the threat
was realized and efforts to counter its effects
began at ARPA and DNA. The recent evidence of
high-altitude, atmospheric neutron-induced
single-event upsets in avionics (Taber and
Normand, 1993) clearly demonstrates the con-
tinuing need to study these effects and develop
protection techniques. Thus, although radiation- Table 3-2 delineates the percentage of the
hardening techniques and methods i f improving
the SEP tolerance for systems are available, SEP
hardening must be an essential part of the devel-
opment process for all space and high-altitude
avionics projects since the potential results of not
doing so can be disastrous.
3.10.2 SEP Environment.
Based on source of origin and the nature of the
upset mechanism, the particles that cause SEP
can be grouped into: cosmic-ray heavy ions, cos-
mic-ray protons, geomagnetic-field trapped pro-
tons, packaging-material heavy ions, and neutral
particles. No satellite orbits can be considered ra-
diation-free, and the fact that a satellite's radia-
tion ervironment changes as a function of both
location and time must be taken into account.
Far-earth and geosynchronous orbits have envi-
ronments similar to interplanetary space; the cos-
mic-ray heavy-ion flux is the main concern in
this region. The earth's magnetic field shields
near-earth orbits from the less energetic cosmic
rays, and protons trapped along the magnetic
field lines tend to dominate the SEP production
at low-earth orbits. Centered approximately
2,500 krn above the earth, the Van Allen belts
consist mostly of protons, electrons, and other
charged particles. Of particular significance for
space radiation effects in electronics is the South
Atlantic anomaly (SAA), a magnetic field de-
pression over the coast of Brazil resulting in the
dipping of the trapped-charge belts down to the
earth's atmosphere. The SAA is the source of
most of the trapped radiation received in low-
earth orbits.
Theories of the origin of cosmic-ray particles
indicate that they are thought to be inductively
accelerated, comparable to the acceleration of
particles in a betatron. Rotating planetary bodies
have rotational magnetic fields that generate rota-
tional electric fields. The magnitude of a star's
magnetic field allows particles to gradually ac-
celerate to enormous velocities while being held
in closed paths. Once freed from the field, the
lifetime of cosmic rays is 108 to 109 years be-
cause of the low density of interstellar matter.
streams of high-energy nuclei that isotropically
bombard the earth. The earth's magnetic field
tends to alter the trajectory of the bombarding
particles and influences the environment that or-
biting satellites encounter.
The cosmic-ray heavy ions often possess bil-
lions of electron volts (GeV) of kinetic energy.
This large amount of energy allows the easy
penetration of thick shielding by such ions. Fig-
ure 3-69 shows the typical mass distribution for
heavy ions in the cosmic environment. Notice the
peak at 56Fe. Particularly important are the 100-
MeV 56Fe ions, with extremely high-energy
deposition per unit of track length (known as lin-
ear energy transfer [LET]), of 27 MeV-cm2/mg.
These ions represent the most highly ionizing
particles encountered in the cosmic environment.
Additionally, the material used to make the
chip and its package may contain naturally oc-
curring heavy actinide material (uranium, tho-
rium, and their daughters), which provide alpha
particles that can ionize the circuit materials and
cause SEP. Alpha particles emitted in the header
package can be stopped from entering the chip
by a simple passivation layer (a thin coating of
polyimide varnish or silicon rubber) above the
chip. However, alpha particles arising from
actinide decay in the chip material itself cannot
be similarly stopped. Another source of alpha
particles is heavy-ion bombardment collision
with the silicon nuclei of the chip material. A
single alpha particle can produce about 3 x 106
Table 3-2. Composition of cosmic rays (Gover and
Browning, 1987).
Charge Flux Density Total Flux
Nuclei Grou~ (7.) (rn2-srlsec) (~ercent)
Protons 1 1,300 92.90
Alpha particles 2 8 8 6.30
Light 3-5 1.9 0.13
Medium 6-9 5.6 0.40
Heavy 2 10 2.5 0.18
Superheavy 2 20 0.7 0.05
electron-hole pairs in silicon, which is sufficient
charge to upset MOS VLSI memory arrays. In
fact, actinide concentrations of only 1 ppm can
cause SEP degradation (Messenger and Ash,
1992).
Trapped geomagnetic protons in the Van Allen
belts and the SAA can provide enough energy to
penetrate a device and indirectly cause SEP.
About 1 proton in every 100,000 has energy >30
MeV and can thus undergo nuclear reactions
with the device material nuclei, thereby produc-
ing energetic charged particles that cause SEP.
Such reaction particles include alphas, carbon
ions, and actual fission of the silicon nucleus
(Messenger and Ash, 1992). Finally, neutral par-
ticles can induce SEP from neutron-induced
nuclear recoils or as a result of neutral-particle-
beam (NPB) weapons.
The basic mechanisms of ionization and the
resultant circuit charge collection is common to
heavy-ion-, proton-, and neutral-particle-induced
SEP. Heavy ions produce charge through direct
ionization as they transit the semiconductor ma-
terial. Protons and neutral particles produce suf-
ATOMIC NUMBER (Z)
Figure 3-69. Composition of the heavy-ion cosmic-
ray spectrum as a function of atomic number (Ma and
Dressendorfer, 1989).
ficient electron-hole pairs to cause SEP through
indirect ionization. When a particle such as a pro-
ton or neutron undergoes elastic or inelastic col-
lision with a silicon atom, a nuclear recoil (Si, Al,
Mg, etc.) occurs. The primary recoil atom can be
accompanied by charged secondaries such as
alpha particles and secondary protons, resulting
in the passage of a highly ionizing primary recoil
product and charged secondaries, which can
cause a wake of electron-hole pairs that can re-
sult in SEP. The primary recoil nucleus results in
far denser ionization tracks than are possible by
direct proton ionization.
3.10.3 Basic Single-Event Phenomena
Mechanisms
3.10.3.1 Upset Phenomenology
A highly ionizing particle, such as a 75-MeV
heavy ion, that enters a semiconductor produces
a track of very dense ionization. If this track
passes through a critical node of an electronic
device, its operation can be upset if sufficient
charge is collected at the sensitive node. The up-
set process depends on the properties of the ion-
izing track, the density of the electron-hole pairs
formed in its wake, the angle of track entrance,
the proximity of sensitive nodes, and device
structure and material properties. The charge-col-
lection process and its time scales are essential in
determining the extent of the SEP problem and
the subsequent upset rates.
The ionization process results in charge sepa-
ration and its subsequent collection within a de-
vice. To understand how this results in errors,
consider the concept of device critical charge.
The critical charge Q, is the least amount of
charge that a system recognizes as sufficient to
represent a binary 1 or 0 at a particular storage
node in a memory array. This problem is exacer-
bated when devices are scaled down because
smaller feature size circuits generally result in
critical nodes with smaller capacitance values.
Because of scaling, more advanced memories
have smaller critical charges (McLean, 1987).
Figure 3-70 demonstrates that critical charge de-
creases with feature size without regard to device
technology.
FEATURE SIZE (p)
Figure 3-70. Critical charge necessary to cause upset
decreases as feature-size decreases petersen and
Marshall, 1988).
Figure 3-71 demonstrates the response of a
diode junction field to heavy-ion peneration. As
the ionizing particle begins its transit, it causes
the formation of electron-hole pairs in its wake
[Figure 3-7 1 (a)]. The charge carriers diffuse and
drift radially from the primary ionization track
and dissipate energy by also ionizing the semi-
conductor material. If they are created in the
depletion region surrounding a junction, the elec-
tron-hole pairs created by these secondary ion-
izations are rapidly separated and collected by a
large internal electric field [Figure 3-71(b)].
Electrons or holes that are produced outside the
depletion region can diffuse to the edge of the
depletion region and be pulled into the node
where logic information is stored, thus exacerbat-
ing the information-loss process.
The charge collected by drift has two compo-
nents: (1) charge deposited in the depletion
region, and (2) charge collected from beyond the
depletion region by funneling. The funnel is an
extension of the charge-collection region by an
elongation of the electric field lines along the ion
track Figure 3-7 1 (c)]. This particle-induced fun-
nel causes a greater amount of the charge depos-
ited by the ionizing particle to be collected
promptly (-300 psec), thus increasing the likeli-
hood of an SEU (Shanfield et al., 1985). A more
detailed discussion of the funnel concept follows
in Subsection 3.10.3.2.
3.103.2 Funneling
The model most often used to describe the
funneling mechanism is the McLean-Oldham ef-
fective funnel length model (Oldham, McLean,
and Hartrnan, 1986), which assumes that the
track of an ion is an infinitely long, uniform col-
umn of charge with an initial radius of 0.1 pm
that is generated in 1 psec. This cylinder expands
in the radial direction by ambipolar diffusion and
endures until the plasma density drops to about
the substrate doping density.
(a) Ion Penetration
y o / vo
(b) Depletion Layer Collapse (c) Equipotential Lines
Extend Down the Track
Figure 3-71 (a, b, c). Response of a diode junction
field to heavy-ion penetration (McLean, 1987).
The creation of electron-hole pairs in the origi- erage electric field. Such an assumption ignores
nal depletion layer results in the neutralization of many of the details of the transient response of
the depletion-layer electric field, the collapse of the device, but has been shown to be in good
-
the junction, and propagation of the electric field agreement with experimental results for low-
along the ion track into the previously neutral LET-sensitive devices (i.e., L, < 30 MeV-cm2/
substrate. During the charge-collection process, mg) (Oldharn, McLean, and Hartman, 1986).
the depletion-region electric field extends down
the charge column. After the depletion layer is
neutralized, a dense column of charge, in reality
a "plasma wire," is in contact with an electrode,
which tends to screen external electric fields
from the interior of the column. The distortion of
the equipotential lines down the track means that
much more charge is rapidly collected from out-
side the depletion region than would otherwise
be possible. Thus, funneling will cause more
charge to be collected at the struck node, increas-
ing the possibility of upset Figure 3-72.
At characteristic time t,, determined by the
dielectric relaxation time of the substrate, the
electric field lines return to the original deple-
tion-layer configuration. Thus, the electric field
varies both as a function of position and time.
The effective funnel-length model assumes that
3.103.3 Physical Analysis
Kreskovosky and Grubin (1986) have con-
ducted detailed analyses and model simulations
of the charge-collection process using (1) the
drift and diffusion equations for electrons in the
substrate, and (2) the Boltzmann transport equa-
tion for electrons in the active layer of devices.
The transient response following the strike by a
single ionizing particle requires that the transport
of electrons and holes generated in the device
and the equipotential distortions be determined
as functions of time. This is done by the solution
of the continuity equations,
this spatially complicated and time-variant field
6P
can be represented by an effective average elec-
-= V.PppVy
tric field that exists for a duration t,, and it pro-
6t
vides a self-consistent way to determine this av-
+V. DpVP+g- R
CHARGE COLLECTION
Figure 3-72. Charge-collection curves for a circuit array, showing that maximum charge is collected at the struck node
due to funneling (McLean and Oldham, 1987).
and Poisson's equation,
&v2 y = e ( N- P- ND + NA)
(3.53)
where N and P are the number densities of elec-
trons and holes, and
jl. = mobility
w = electrostatic potential
D = carrier diffusivity
E = device material permittivity
y
= calculated carrier generation rate
R = recombination term
e = electron charge
and ND and NA are the doping concentrations
(donors/acceptors), such that:
where NP(r) is the concentration of particles gen-
erated in the track, t(r) is the time elapsed from
when the radiation particle penetrates the device
to a specific point along the track, and zp is the
time constant of thermalization (-3 psec).
Two processes contribute to carrier generation:
impact ionization, and energy absorption from
the incident ionizing particle. Additionally, the
generation terms are highly material- and bom-
barding-particle-dependent.
Recombination is modeled as a combination of
Schockley-Read-Hall and Auger recombination
(Grubin, Kreskovsky, and Weinberg, 1984):
where z, ,d z, are the carrier lifetimes (-1 psec)
and r is the Auger rate constant. Note that the car-
rier lifetimes greatly exceed the lifetime of an
SEU transient (Kreskovsky and Grubin, 1986).
Arbitrary adjustments of the Auger rate constant
have allowed reasonable matches between ex-
perimental work and computer simulations.
This analysis is only preparatory to beginning
the considerations essential to model SEU simu-
lations on a computer. It is to be noted that mod-
em, widely used modeling tools restrict simula-
tions to two-dimensional analysis; therefore, ap-
proximations are required. Recent efforts by
Howard et al., (1993) have advanced this analy-
sis to a physics-based three-dimensional model
using PADRE. The details of the approximations
and the modeling processes themselves are be-
yond the scope of this handbook; suffice it to say
that efforts to find truly predictive simulations of
SEU phenomena continue.
3.10.3.4 SEU in Linear Circuits
The single-event upset of a digital circuit is the
most well known and widely studied SEP. How-
ever, the passage of a heavy ion through a linear
circuit, such as a sense amplifier or comparator
circuit, also produces the ionization and the
potential collection of charge that could be inter-
preted as a real signal. Sense amplifiers designed
to read magnetic-core and semiconductor memo-
ries are capable of reading extremely small sig-
nals and are susceptible to such disturbances.
Thus, the circuit designer must consider circuit
speed and the VO capacitances to help ensure
that the ion strike is not interpreted as a valid sig-
nal. Recent work in this area has begun to shed
light on how the susceptibility of analog devices
to SEU affects the connected digital circuits
(Koga et al., 1993).
3.10.3.5 Upsets in Logic Circuits
The discussion thus far has centered around
upsets in latching circuits. Memories, with their
low capacitive loading, have historically been
more susceptible than logic circuits such as
microprocessors (Petersen and Marshall, 19 88).
However, microprocessors have large numbers of
gates and are becoming increasingly more sus-
ceptible to upset as each new generation
downsizes the individual logic cells.
In combinational logic circuits, the ionizing
event and potential upset are not as tightly wed in
either the spatial or temporal regime as in the
SRAM. The sensitive region and the location of
stored information may be completely separate.
Information stored in a latch is subject to corrup-
tion by erroneous signals induced in a sensitive
node and transmitted to the latch by logic gates
feeding the latch. For a single event to produce
an upset in combinational logic, the following
conditions must be met (Diehl-Nagle, Vinson,
and Petersen, 1984):
1. The occurrence of an ion strike that is
capable of producing a voltage tran-
sient large enough to propagate into
the adjoining circuitry,
2. The existence of a critical path be-
tween the struck sensitive node and the
data latch, thus allowing the struck
node control of the latch,
3. Generation of a transient of sufficient
energy and duration to write the latch,
4. Arrival of the transient at the latch
during a latch write-enable state.
It is possible that the particle strike location and
timing could be such as to directly affect the
latch itself.
It is important to note that not all sensitive
nodes that are upset will result in output errors
because the potential error can be overridden in
the logic scheme. It is even more noteworthy,
however, that not all errors will occur irnrnedi-
ately after the ion strike. Many machine cycles,
perhaps thousands, can pass before the error
reaches an output path. Software can amplify the
error and cause large regions of the circuit to
have erroneous states before error detection. Fig-
ure 3-73 shows the error propagation in an Intel
80186 microprocessor, obtained by using an
electron microscope to compare the voltages
present in a chip without errors to those present
in a chip that has had an error introduced. The
differences show up as a pattern of highlighted
areas (May et al., 1984).
Heavy-ion irradiation of CMOSISOS VLSI
logic devices has been conducted and the experi-
mental results compared with an analytical
assessment (Newberry et al., 1987). It was deter-
mined that three error types occur: bit errors,
lost-data errors, and lost-data-path errors. A bit
error results from the change of a bit within a
logic word. A lost-data error occurs when one of
the control bits is changed due to a particle hit,
resulting in the failure of a single word to reach
the output. In a lost-data-path error, a control bit
Figure 3-73. Error propagaton in the Intel 80106 microprocessor logic circuit (May et al., 1984).
is changed such that the entire data stream does
not reach the designated output pad. Clearly, the
fact that various types of errors can occur, and
the inability to easily determine the origin of the
error once it reaches the output pad, makes SEU
evaluation of logic devices more challenging
(Newberry et al., 1987). Different approaches to
SEU testing of microprocessors are discussed in
Koga et al. (1985), Koga and Kolaskinsky
(1987), and Elder et al. (1988).
3.103.6 Simultaneous Multiple Single-Bit
Event Upset
The charge within an ion track and its subse-
quent spread can encompass more than one sen-
sitive junction and thus upset more than one
memory bit. The simultaneous upset of multiple
single bits can be attributed to sufficient charge
deposition by a single heavy ion that produces a
track size sufficient to disturb more than one sen-
sitive junction, or it may be due to charge diffu-
sion to more than one sensitive node. Addition-
ally, it has been demonstrated that ion tracks that
strike a junction can affect the lateral spread of
the charge, depending on the nature of the pull-
up load on the struck junction (Zoutendyk,
Edmonds, and Smith, 1988). For example, such
multiple events comprise 5 to 10 percent of the
reported SEU for the Harris HM-6508 CMOS
SRAM. For the 93L422 bipolar RAM, multiple
events comprise slightly more than 1 percent of
the reported SEU (Martin et al., 1987). As device
miniaturization continues and critical-charge val-
ues decrease, the incidence of multiple errors can
be expected to increase.
3.10.4 Circuit Response to Single-Event
Phenomena
"Single" in the term SEP means that the error
(or errors) produced can be attributed to a single
ionizing particle producing ionizing charge in the
device under consideration. Because of the na-
ture of radioactive decay and of the cosmic-ray
flux bathing the earth, SEP are random, both in
time of occurrence and position within devices.
However, two basic types of upset can be defined
and examined: finite lifetime ("soft" errors), and
permanent ("hard") errors. In finite-lifetime up-
sets, the stored information is changed but the as-
sociated hardware is not damaged or altered.
When the cell experiencing such logic upset is
reset and tested, no degradation in its character-
istics is exhibited. These finite upsets typically
occur in random access memories and bipolar
circuits, manifested generally as SEU. Permanent
errors, commonly referred to as "hard errors," are
heavy-ion-induced failures in metal-nitride-ox-
ide-semiconductor (MNOS) structures, silicon-
nitride-oxide-semiconductor (SNOS) structures,
and DMOS and BJT power devices. Hard errors
include SEGR and SEB.
3.10.4.1 Single-Event Upset
MOS Circuits. Three failure modes for radia-
tion-induced soft errors in DRAMS have been
experimentally verified: cell failure mode, bit-
line failure mode, and combined cell-/bit-line
failure mode. Figure 3-74 shows a schematic lay-
out of a DRAM. The horizontal lines are word or
select lines, and the vertical lines are bit or data
lines. An access transistor and storage capacitor
at the intersection of a word and a bit line com-
prise a single DRAM cell. The access transistor
permits the support circuitry to locate the indi-
vidual cells for reading or writing. Figure 3-75
shows that the storage capacitor is formed by us-
ing a thin layer of silicon dioxide as the dielec-
tric. Writing occurs when the appropriate word-
line voltage is applied to the gate of the access
transistor while the bit-line voltage is raised and
charges the storage capacitor. At the end of the
write cycle, the access transistor is returned to its
OFF state. To read the DRAM, the access transis-
tor is turned ON and the cell is connected to a
sense-and-write amplifier that informs external
circuitry of the cell state and restores the cell to
its original state (Messenger and Ash, 1992).
Cell-failure results from charge collection by
the storage capacitor in a one-transistor cell.
When the collected charge exceeds a critical
charge Q, a soft error occurs in the cell.
Bit-line failure occurs when charge collection
reduces a sensing signal as a result of the unbal-
anced charge collection on a floating bit line or
floating-bit-line complement during the access complement collect a differential charge less than
cycle. The actual charge collection results from Q, while floating during a read cycle. Although
the connection of the ion-caused-charge diffusion the individual cell and bit-line charge collections
area to an access transistor. are insufficient to produce a soft error, if their
Studies by Rajeevakumar et al. (1988) identi-
combined charge collection 2Q, an error can
fied the combined cell-/bit-line failure mode,
result. At cycle times less than 100 nsec, this
which occurs when the storage capacitor collects
combined cell-bit line effect becomes the dorni-
a charge less than Q, and the bit line and bit-line
nant upset mode (Rajeevakumar et al., 1988).
BIT
LlNE
BIT
LlNE
TRANSISTOR
RETURN RETURN
TRANSISTOR
Figure 3-74. DRAM schematic showing four information-storage cells (Messenger and Ash, 1992).
WORD LlNE
SILICON
DIOXIDE / \
BIT LlNE
&,<&*Ly17
I
p-TYPE SUBSTRATE
STORAGE
CAPACITOR
Figure 3-75. Diagram of a vertical slice of a single MOS DRAM cell (Messenger and Ash, 1992).
DRAM chips are inherently more susceptible to
SEU than SRAM devices because no competing
recovery mechanism attempts to restore the ap-
propriate logic state.
JUNCTION
SRAM devices use a bistable flip-flop formed
by two cross-coupled inverters as the storage cell.
Figure 3-76 is a schematic representation of a
typical SRAM The potential differences at the
sensitive junctions collect the excess charge from
the ion strike, which can be interpreted as a sig-
nal from the external circuitry to switch state. In
such a flip-flop, the ON transistor controls the
47
v
gate voltage of the other transistor and keeps it in
Figure 3-,6. Schematic of a bulk CMOS SRAM
an OFF condition. When the OFF transistor is
showing upset-sensitive junctions petersen and
driven ON by external means, it forces the ON
Marshall, 1992).
transistor to the OFF condition. Basically, the
flip-flop has two stable states and will remain in
one of these states until forced to change, as long
as power is applied to the circuit. These states
can be easily interpreted by external circuitry as
a logical one or zero. The SEU of the SRAM can
be thought of as a particle strike causing suffi-
cient charge deposition at the drain node junction
of the OFF transistor to cause the flip-flop state
to be reversed and the stored information to be-
come corrupted. This occurs when the excess
charge deposited in the drain of the OFF transis-
tor attempts to drive the connected gate to the
opposite bias and thus causes transition to the
cell's other bistable state. Fortunately, in SRAM
devices, the active transistor on the struck node
attempts to maintain the currently stable cell con-
figuration. Basically, the active transistor on the
hit node attempts to dissipate the deposited
charge and restore the proper gate voltage before
the excess charge switches the gate bias of the
struck OFF transistor. The success or failure of
this inherent restoration mechanism is governed
by the circuit resistor-capacitor (R-C) time con-
stants and plays an important role in the circuit-
hardening techniques [see Section 3.10.61.
Bipolar Circuits. When the memory speed is
the most significant design feature, bipolar
memory is the memory of choice for space appli-
cations. The optimization for speed means that
the employed devices will have smaller capaci-
tance values, smaller geometries, smaller noise
immunity, and smaller critical charges; thus, in
general, bipolar memories are quite susceptible
to SEU. Current flowing through the base of the
bipolar transistor is used to indicate the binary
state of that transistor. Bipolar memories are
characterized by large doping density variations
and several closely spaced charge-collection re-
gions (emitter, base, collector and substrate junc-
tion). The close proximity of multiple charge-col-
lection regions that provide bipolar devices their
inherent speed also presents many charge-collec-
tion regions for a penetrating ion to transit
(Pickel, 1988).
Figure 3-77 shows the most commonly used
types of bipolar memory cells, each cell type
having its advantages and disadvantages. The
fastest cell for reading and writing is the
Schottky cell, but this cell has the largest number
of parts and the highest power consumption.
However, since this cell requires the largest
logic-level voltage swing, it has the best SEU re-
sponse. The IIL cell consumes the least power,
operating at a slower speed than the other two.
The emitter-coupled cell has power consumption
and speed intermediate to the other two.
Figure 3-78 is a cross section of a bipolar tran-
sistor, showing three possible paths for high-
energy particle penetration. It is essential to note
that bipolar structures contain many sensitive
areas, each of which can be upset by different vealed that the voltage applied on a junction can
charge depositions. Additionally, particle track affect the SEU-induced charge collection of a
length can be such that a single particle pen- neighboring junction (Hauser et al., 1985;
etrates several sensitive regions, as depicted in Knudson et al., 1984).
Figure 3-78. Experimental analysis has also re-
L
- -
*
-
(a) Schottky Cell
(b) IIL Cell
6
(c) Emitter-Coupled Cell
Figure 3-77 (a, b, c). Basic types of commonly used
bipolar memory cells (Hauser, 1988).
COLLECTOR EMmER BASE
p-SUBSTRATE
(a) (b) (c)
HITS
Figure 3-78 (a, b, c). Cross section of a bipolar tran-
sistor showing three of the many possible paths for
high-energy particle intersection with pn junction: (a)
emitter-basecollector region, (b) basecollector re-
gion, and (c) collector region (Hauser, 1988).
Gallium Arsenide Devices. High-speed GaAs
circuits are acclaimed for their ionizing radiation
dose hardness; however, their inherent SEU sus-
ceptibility exceeds that of silicon devices. The
greater density of GaAs, relative to silicon, re-
sults in more direct ionization per unit of travel
by the transiting heavy ions. Additionally, GaAs
is sensitive to heavy ions impinging upon both
the source-to-drain and the gate-to-drain volumes
in a GaAs FET structure. Silicon CMOS devices,
on the other hand, are only sensitive to strikes in
the source-to-drain regions. Thus, GaAs FETs
are more susceptible to upset that a comparable
silicon device (Petersen and Marshall, 1988).
3.10.4.2 Single-Event Gate Rupture
Irreversible faults in nonvolatile, micro-
electronic devices such as SNOS and MNOS
memory capacitors are attributed to the rupture
of the gate dielectric as a consequence of the
heavy-ion passage. Studies of such hard failures
(Wrobel, 1987) reveal the following:
1. Hard errors result from the combina-
tion of the energy directly deposited by
the bombarding ion with the energy
delivered by the electrical conduction
through the ion track by the charge
stored in the device.
2. The initial ion forms a highly conduc-
tive plasma -5 nm in diameter, and the
channel grows to 100 nm.
3. The ion strike must be of sufficient
total energy to raise the dielectric tem-
perature enough to cause the rapid ther-
mal diffusion of the gate material and
the subsequent penetration of the di-
electric by this gate material. A scan-
ning electron microscope (SEM) pic-
ture [Figure 3-79] of a failed device
shows that the failure mechanisms are
caused by dielectric penetration by ei-
ther the aluminum or silicon. Addi-
tionally, the SEM photomicrograph
shows that the devices were locally
raised to temperatures above the melt-
ing points of the constituent materials.
4. The post-failure I-V characteristics for
such capacitors were similar to diode
responses, and some were simply
ohmic shorts through the dielectric.
5. An inverse relationship exists between
the deposited ion energy and the ap-
plied voltage (several MV/cm) required
to cause device failure.
To examine the possibility of melting the materi-
als that make up these devices, consider the melt-
ing temperatures of the following materials:
Silicon: 1,412OC
Aluminum : 660C
Silicon nitride: 1 ,900C .
The change in temperature can be calculated as:
energy
AT =
C, (volume) (density)
(3.56)
assuming
(density) = 2.5g/cm3
track radius = 2.5 nm
track length = 80 nm
CV (specific heat) = 0.8 Jlg-=C
(LET) = 40 MeV-cm2/mg,
which leads to
Figure 3-79. SEM photograph of heavy-ion induced failure induced by 252~f fisssion fragments (Wrobel, 1987).
MeV - cm2
AT = 40 (1.6xl0-" J / M~ V )
0.001g
Using a track length of 80 nm allows 40 nm for
the dielectric and 40 nm for the underlying sili-
con, consistent with Wrobel's estimates. This
localized temperature rise only accounts for the
energy deposited by the heavy ion, and conduc-
tion of stored charge through this plasma will
increase the temperature rise. Such localized tem-
perature rises support the premise of material
melting.
-
In addition, Browning et al. (1987) observed
hard errors for MNOS nonvolatile RAMS and
SNOS devices when neutrons induced fissioning
of uranium contaminants in alumina ceramic
packaging lids. This problem was not observed
when the same devices were packaged with gold-
covered kovar lids.
3.10.4.3 Single-Event Burnout
Experimental observation of burnout in power
MOSFETs has been reported by Fischer (1987).
Exposure to 330-MeV gold ions (LET = 83
MeV-cm2/mg) resulted in gate-oxide burnout for
n-channel MOSFETs at voltages below the rated
drain and/or gate breakdown voltages. Space
environments, predicated on the assumption of
"worst case = iron ions," are not this harsh.
p-channel devices were found to be basically
immune to burnout for LETS up to 40 MeV-cm2/
mg. n-channel devices burned out between 22
and 90 percent of their rated breakdown voltage
when bombarded with bromine ions.
3.10.4.4 Single-Event Latchup and
Snapback
Latchup occurs in microcircuits due to electri-
cal transients, pulsed ionizing radiation, and
when a transiting heavy ion turns on a parasitic
pnpn structure within the device. Latchup is a
low-impedance state that results in a high-current
drive that persists until the voltage drops below a
certain voltage level (generally accomplished by
cycling the device power) or until device damage
occurs from overheating. Figure 3-80 is sche-
matic representation of the two parasitic bipolar
transistors inherent in a CMOS structure. The
pnp and npn transistors are cross-connected, so
the base-collector junctions are common.
Latchup prevention techniques seek to address
the problem from both the semiconductor pro-
cess and the circuit design process levels. Process
solutions involve reduction of Lifetime in the sub-
strate (by neutron irradiation), gain degradation
(SO that P,,, P, , of the parasitic pnpn smcture is
below unity), buried layers (CMOSISOS and
CMOSISOI), trench isolation, retrograde wells,
guard rings (channel stops), and epitaxial sub-
strates. Circuit-level solutions include current
limiters, spacings between critical diffusions,
substrate contacts, and biasing substrates so that
they can never become forward-biased during
operations.
Snapback, an induced high-current mode of
operation similar to latchup (but does not involve
a parasitic pnpn structure), occurs in n-channel
devices in NMOS and the NMOS regions of
CMOS integrated circuits [see Subsection
3.8.3.11. This induced high-current mode results
from the fact that inherent in n-channel transis-
tors a region of negative resistance exists that al-
lows a device to settle into an improper, but
stable, mode of operation at a lower drain-to-
source voltage, thus perturbing normal device
operations. Since the onset of snapback is ac-
companied by heating because of the increase in
device bias current, it is essential to terminate
this condition before metal fusing or melting oc-
curs. The snapback condition can be terminated
by normal device switching of the logic levels
(Messenger and Ash, 1992).
3.105 SEP Testing and Modeling
The possibility of a potentially devastating
upset, leading to mission failure, and the neces-
sity of fielding economically viable parts and
(a) Cross Section
VDD*
(b) Schematic
R,
Figure 3-80 (a, b). Cross section and schematic representation of the two parastic bipolar transistors inherent in a
CMOS structure (Ma and Dressendorfer, 1989).
systems that must operate in an SEU enviroment
following subsections highlight the key points of
require that testing and prediction procedures for
the environmental models and the accelerator
parts and systems be available. Early investiga- measurements.
tors in this field, to their credit, produced conser-
vative estimates of upset predictions to allow for
unknowns about the environment and the correla-
tion between earthbound testing and the realities
of space operation. Research, experience, and
improved knowledge have resulted in a recent
review and refinement of upset-rate prediction
methodologies (Petersen et al., 1992), the thrust
of which was to investigate the various prediction
techniques used in the SEP community and to
make recommendations regarding standard ap-
proaches that should be taken. Specifically ad-
dressed were device interaction models, environ-
ment models, and accelerator measurements. The
3.105.1 Modeling Upset Rates in Natural
Environments
The predictive modeling of upset rates in the
magnetosphere of the earth's orbit is generally
done using the CREME computer code model
(Adams, 1986). This landmark work is a gener-
ally effective predictive tool for the ordinary so-
lar minimum environment and is currently under
revision to account for the latest understanding of
the earth's radiation environment and to correct
known deficiencies in model estimates. CREME
allows the user to select from among 12 environ-
ments of varying severity. The appropriateness
and known limitations of each environmental
model are discussed in Petersen et al. (1992). An
essential revision to the CREME model will be to
correct the model's overprediction of heavy-ion
events during solar flares. [Satellite experience
has indicated that large solar flares are accompa-
nied by proton-induced SEUs; the current
CREME model overpredicts the heavy-ion upset
cross sections during flares by two orders of
magnitude.]
3.10.5.2 SEU Characterization Methods
SEU testing for complete device characteriza-
tion requires device cross-section measurement,
either as a function of ion linear energy transfer
(LET) or specific energy loss (dE/dx). The device
cross section is expressed in terms of measured
upsets per unit fluence, and the LET is the
amount of energy deposited along the path by an
ion of known energy. Device cross-section mea-
surement as a function of specific energy loss,
dE/dx, is nearly identical to LET but also in-
cludes the energy released to delta rays, whose
energy may travel a considerable distance from
the particle track. Delta rays are electrons that
have sufficient impulse after leaving their ionized
parent atom to cause further ionizations.
Current laboratory efforts obtain heavy ions
from machines such as the Brookhaven tandem
Van de Graaff accelerator and the University of
California (Berkeley) 88-inch cyclotron. These
facilities produce a variety of different heavy ions
at a limited number of different energies. With
energies of -2 MeV per nucleon available, suffi-
ciently penetrating ions can be selected to ensure
transit through the overlayers and into the active
regions of delidded devices, and with sufficient
LET to exceed that expected in the cosmic envi-
ronment. The normal technique employed in
these experiments is to direct a series of ion
beams, each of specified energy, onto a device
with a known pattern of information storage.
Beam fluence and the number of errors are
recorded, and a single point on the upset cross
section versus LET curve is generated based on
the ion LET at the device surface. For accurate
interpretation of the experimental results, it is
essential to properly account for the changes in
actual specific energy loss caused by overlayers,
etc. that the ions must transit before reaching the
active region of the device under test. Ion types
and energies are varied to fully develop the SEU
cross-section curves.
AIR VACUUM AIR
PARTICLE BEAM
-------
DISCRIMINATOR
Figure 3-81. Typical cyclotron layout for SEU testing (Nichols et al., 1988).
The definition of the threshold LET varies
with the experimentalist. Jet Propulsion Labora-
tory reports define it as that value of LET where
SEU first occurs for fluences exceeding 106 ions/
cm2. Others define it as the LET value where the
cross section is 10 percent of the saturation cross
section (Nichols et al., 1988). The SEU cross
section is defined as:
upset rate
(3 =
particle flux (3.58)
A schematic representation of a typical cyclo-
tron test chamber is shown in Figure 3-8 1. Since
the beam fluences used for SEU testing are sev-
eral orders of magnitude lower than those nor-
mally supplied at accelerator facilities, testers
have developed their own dosimetry designed to
count individual ions. The beam flux is measured
by passing it through a thin film detector (TFD)
made up of organic scintillation material. The
light from the scintillator is conducted to a pho-
tomultiplier tube and counted. The ion energy is
determined by the calibrated surface barrier
detector (SBD) when it is positioned in the beam.
A key feature of these chambers is the ability to
vary particle LET by remotely positioning a
selected device at desired angles in the beam
using a motorized, translatable and rotatable
board (Nichols et al., 1988).
Numbers are percent (%)
in each LET range
36 38 40 42 44 46
LINEAR ENERGY TRANSFER IN SILICON
( ~ e ~ t r n ~ l r n g )
Figure 3-82. Calculated LET distribution of 2 5 2 ~ f
fission fragment (Stephen et al., 1984b).
3.10.5.3 Alternative Screening Methods
Van de Graaff accelerator and cyclotron results
comprise the bulk of the SEU test data available.
However, access to these test facilities is limited
and tests must be scheduled months in advance.
Additionally, the cost of characterizing a single
part costs between $10,000 and $100,000,
depending on the complexity of the experiment
(Kolasinski et al., 1979). Because of these draw-
backs, economical alternatives have been sought,
two of which are discussed below.
252Cf Cosmic-Ray Simulator. Since 100-
MeV 56Fe ions (LET = 27 MeV-cm2/mg in sili-
con) effectively represent the most highly ioniz-
ing particles encountered in the cosmic environ-
ment, acceptable testing sources must be able, as
a minimum requirement, to provide these values.
252Cf, which produces fission fragments with a
wide range of energy and LET values, was pro-
posed as a cosmic-ray simulator. Stephen et al.
(1984b) demonstrated that 95 percent of all 252Cf
fission fragments have LET values between 41
and 45 MeV-cm2/mg, while 59.4 percent have
values between 43 and 44 MeV-cm2/mg [see Fig-
ure 3-82]. By changing the angle of incidence or
attenuating the fragment energies, effective LET
from 20 to 75 MeV-cm2/mg can be realized
(Browning, 1990; Kolasinski et al., 1979;
Velazco et al., 1989). The first efforts to use 252Cf
for SEU testing involved placing a 252Cf source
in an evacuated chamber, bombarding the device
under test (DUT), and calculating a single-upset
cross section that, presumably, was the saturation
cross section (Blandford and Pickel, 1985;
Stephen et al., 1984b). Such tests, however, do
not adequately address the uncertainties associ-
ated with the LET dispersion. Furthermore, they
fail to usefully characterize the SEU threshold
and saturation cross section of a device because
no means exist to provide the SEU cross section
versus LET curve.
Recent work by Block et al. (1990), Browning
(1990), Costantine (1 990), Costantine et al.
(1990), Howard et al. (1991), and Sanderson et
al. (1987) has shown that 252~f can be used as a
valuable diagnostic tool by the researcher who
understands and works within its limitations.
Nd:YAG Dye Laser. An alternative SEU test
method, developed and demonstrated by Buchner
et al. (1990), uses a picosecond, tunable Nd:YAG
dye laser to measure SEU and latchup for differ-
ent kinds of integrated circuits. This technique, in
general, is nondestructive and can easily identify,
and repeatedly return to, the exact location on the
device that is responsible for the SEP, an ability
that, of itself, makes this technique a valuable
testing methodology for those interested in locat-
ing and eliminating design deficiencies.
3.10.5.4 Calculation and Models
Due to the high cost of testing and the sched-
uling problems at the high-energy accelerator fa-
cilities, SEP characterization has been supple-
mented by developing computer simulation pro-
grams to model circuit response to the postulated
single-event environment. Such modeling is an
integral part of ongoing developmental programs
for space electronics. Properly designed models
based on device physics can serve as reasonably
reliable predictive tools that allow the designer to
test and evaluate various options before silicon is
manufactured. As a caution, it must be recog-
nized that a model's predictive validity is only as
good the user's ability to identify inherent model
limitations and avoid the temptation to apply the
model outside of its design limits.
SEU computer simulation models for devices
and circuits generally involve two different tech-
niques, each of which has its limitations: (1)
those that analyze charge deposition, collection,
and transport by use of a physics-based simula-
tion (e.g., PADRE); and (2) those that seek to
separate the processes of charge deposition and
collection and analyze the effect of critical
charge on circuit performance (e.g., SPICE). A
detailed discussion of model capabilities and
limitations can be found in Kerns (1989); and a
tutorial on SEU modeling is presented by
Massengill (1993).
layer technique does not stop cosmic rays, other
hardening techniques must be applied. As device
miniaturization increased SEU susceptibility, the
following process evolutions occurred in an ef-
fort to reduce the charge collected from ion born-
bardments: (1) increased doping concentrations,
(2) decreased oxide thickness, and (3) twin and/
or retrograde tubs on very thin epitaxial layers.
The CMOS-on-epi technology placed the active
regions of a device above a heavily doped sub-
strate. The SO1 technology placed an insulator
under the active devices. These modifications
increased capacitances per unit area and reduced
funnel collection of ionization generated charges
(Fu, Koga, and Kolasinski, 1987). Since the
reduction of the charge-collection volume is key
to reducing the SEU error rate, future manufac-
turing will likely move to very thin silicon layers
over insulators to aid SEP tolerance in CMOS
and bipolar technologies. DRAM manufacturing
has focused on maintaining a relatively constant
level of SEU sensitivity by maintaining a nearly
constant storage capacitance of 50 Cf, even as the
technology has scaled down.
3.10.6.1 Metal-Oxide Semiconductors
The basic problem remains, however; heavy
ions, such as oxygen and iron (normal constitu-
ents in the cosmic spectrum) [see Figure 3-69],
can still generate sufficient charge in a circuit
node to cause a logic state change. On a typical
CMOS SRAM memory cell circuit in a reason-
able cosmic-ray environment, approximately 10-
6 errorbit-day will occur. A hit at the appropriate
drain node deposits charge that drives the con-
nected gate to the opposite bias. At this point, it
becomes a race, with the active transistor on the
struck node trying to eliminate the deposited
charge and restore the proper gate voltage before
the charge switches the gate bias of the active
transistor on the affected node. Frequently, as
shown by the space environment error rates, the
race is lost. One way to reduce MOS logic circuit
3.10.6 SEU Hardening and Processing susceptibility to SEU is to increase the R-C time
Alpha particles emitted in the header package
Constant of the coupling lines. The amount of
can be stopped from entering the chip by a
R-C adjustment is a function of circuit param-
simple passivation layer. Since the passivation-
eters, such as nodal capacitance- For a 16k
SRAM, 100 kQ resistance in the feedback path
has successfully prevented SEU for 140-MeV Kr
at room temperature (Kolasinski et al., 1986).
This resistance is usually incorporated into the
memory cell by high-value polysilicon resistors.
Increased resistance does increase the write time;
thus, SEU hardening impacts performance
@awes, 1985). Additionally, the fact that the
resistivity values of polysilicon resistor vary sig-
nificantly over the planned military temperature
ranges must be taken into consideration since this
affects both electrical and SEP properties.
3.10.6.2 Bipolar Memories
In bipolar memories, the need to delay the
struck OFF transistor from turning off the ON
transistor again means that this transition must be
delayed for a time greater than that required for
the ion-induced charge to dissipate. However,
adding feedback resistors to bipolar cells
decreases the critical charge and thus increases
SEU susceptibility because the base current
flows through the feedback path. Assuming the
heavy-ion strike causes a drop in the collector
voltage of the struck transistor, a hardening tech-
nique to simply delay the voltage drop from ap-
pearing at the opposite side of the cell until the
struck transistor recovers will suffice. However,
if the ion-induced charge deposition occurs in the
emitter and the base, or just the base, the feed-
back path does not influence the transition and
the struck transistor can go to the low-impedance
state. To retain the original state of the memory,
such an occurrence would require that informa-
tion about the previous state be stored in the
feedback path and be capable of restoring the
original state (Hauser, 1988). The addition of one
or more collector-follower transistors or emitter-
follower transistors to the memory-cell feedback
path has been demonstrated to change the
memory-cell response time sufficiently to avoid
upset. Charge stored in the followers provide suf-
ficient stored charge to keep the ON transistor on
until the struck transistor recovers. However,
such a technique provides SEU hardness at the
expense of speed and added circuits, which in-
crease overall device size (Messenger et al.,
1988).
3.10.6.3 Gallium Arsenide Devices
Efforts to improve the SEU immunity of GaAs
devices (Zuleeg and Notthoff, 1988) have shown
that GaAs E-JFET SRAMs can be more SEU-
tolerant than bipolar devices. However, studies
by Campbell et al. (1989) continue to show that
(1) problems exist with enhanced charge collec-
tion at structure element edges, (2) more charge
can be collected at the gate than is deposited in
the active layer, and (3) more charge can be col-
lected at the drain than the total produced by the
impinging ion. These issues indicate that further
work can be done to improve the SEU immunity
of GaAs SRAMs, albeit at the expense of circuit
speed, cell size, and power dissipation.
3.10.7 System Approaches to SEP-Induced
Errors
The potential effects of SEP in memories and
logic devices have a major impact on the design
of electronics for operation in space. To ensure
that systems continue to perform in spite of
errors, the accepted design approach involves
employing two disparate, yet truly complemen-
tary, techniques: error prevention, and error tol-
eration and correction.
3.10.7.1 Error Prevention
Ideally, error prevention seeks to develop hard-
ened systems that are completely immune to SEP
and requires that the system designer select indi-
vidual parts that are designated SEP-immune and
test these parts for the expected environmental
conditions. Such an approach fails to recognize
that individual parts may degrade or fail, and that
repair of an orbiting system is generally not a vi-
able option. A more realistic approach is to
choose as many SEP-immune parts as feasible,
recognizing that errors will occur and incorporat-
ing error toleration and correction schemes into
the system design.
3.10.7.2 Error Toleration and Error
Correction
Error toleration and error correction employ
redundancies to allow for error detection and iso-
lation, and the subsequent return of the system to
its correct state. The three basic forms of redun- Each of the redundancy techniques has ben-
dancy used follow below:
1. Hardware redundancy requires the use
of duplicate units, majority voters with
disagreement detectors, switching con-
figurations, self-checking circuits, and
error detection and correction circuitry.
Hardware techniques for error detec-
tion include error coding approaches
such as parity, Hamming codes, and
checksums.
2. Software redundancy employs algo-
rithms to solve fault-induced problems
using concurrent program execution,
breakpoint reasonableness testing,
checkpoint storage, and the capability
to rollback for recovery.
3. Time redundancy incorporates repeated
execution of a certain system-state tran-
sition or code sequence and watchdog
timers (Sievers and Gilley, 1985).
For a 16-bit word, 6 extra bits are required for
single-bit error detection and correction. If two
bits within the same word become erroneous
because of SEU, several additional bits are
needed for detection and correction. The use of
totally redundant memory cells is a simpler alter-
native, albeit hardware intensive, solution to the
problem of double-bit error correction. However,
since neither solution is effective or efficient be-
cause of the demands on circuitry, a more
accepted solution is Hamming-code single-bit
error correction/double-bit error detection. But for
chip organization such as 8 x 8k, where adjacent
bits in a word are in adjacent cells, Hamming-
code single-bit error correction/double-bit error
detection will either not detect the adjacent errors
or it will detect them but be unable to correct
them. Double-bit errors in the same word can be
avoided by spatially dispersing those memory
cells representing a single word on two separate
chips, as is the practice with the 64k x 1 layout.
Such a solution works, but penalties are incurred
when fine geometries or high-speed operations
are required (Martin et al., 1987).
efits and drawbacks. The system designer must
use these techniques within the constraints of
weight, power, speed, and the need for data in-
tegrity, balancing the use of hardened devices
and correction techniques while meeting mission
constraints.
3.10.8 Conclusion
Single-event phenomena encompass a wide
variety of problems encountered by satellite and
avionic systems. Political scenarios mean little to
this field since the villains are the naturally oc-
cumng components of space radiation that will
always be present in the environments in which
these systems must be deployed. The actual po-
tential for failure increases as more computing
capacity per pound of launch vehicle is required.
Such a necessary goal mandates the use of mi-
croelectronic technology, which is undergoing
continuous downscaling and, thus, increasing
SEP susceptibility - unless vigorous hardening
research keeps pace with device miniaturization.
The challenge is to ensure that SEP circuit hard-
ening guarantees that a single particle cannot
deposit sufficient charge to disturb the circuit.
Recognizing that this challenge may not always
be met, adequate error detection/correction tech-
niques that use hardware and software combina-
tions must be employed to ensure that SEP are
detected and corrected to make space systems
error-tolerant and more surviveable.
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CHAPTER 4
DISPLACEMENT DAMAGE EFFECTS
The purpose of this chapter is to discuss dis-
placement damage effects in semiconductor de-
vices and material. Beginning with a brief
discussion of the interaction of radiation with
solid material, the effects of displacement, rather
than ionization, are emphasized, followed by an
introduction to the dynamics of atomic displace-
ment in crystalline solids. The balance of the
chapter discusses displacement damage effects
on the physical properties of semiconductor, mi-
croelectronic, and optical devices.
4.1 Basic Mechanisms of Displacement
Effects
All energetic nuclear radiation, even including
high-energy gamma rays, can produce displace-
ment damage in crystalline semiconductor mate-
rials. The specific radiations of primary interest
in this chapter are neutrons, electrons, protons,
and deuterons. Displacement damage effects re-
sult from atoms that have been displaced from
their usual sites in a semiconductor crystal. In
the simplest form, the displaced atoms become
extra atoms inserted between lattice positions
(interstitials), leaving behind unoccupied lattice
positions (vacancies). The interaction of radia-
tion with solid material depends on a variety of
factors, including the mass, charge state, and ki-
netic energy of the impinging particle, and the
atomic mass, charge (atomic number, Z), and
density of the target material. The interactions
that can occur between primary particles and tar-
get atoms follow (McLean and Oldham, 1987):
Photons ( + high-energy secondary elec-
trons)
- Photoelectric effect
- Compton scattering
- Pair production
Charged particles
- Rutherford scattering
- Nuclear interactions (heavy particles)
- Coulomb interactions
Neutrons
- Elastic scattering
- Inelastic scattering
- Transmutation reactions.
In this chapter, displacement resulting from
charged-particle interactions (Rutherford scatter-
ing) and neutron interactions (elastic and inelas-
tic scattering) will be addressed. [Target material
ionization engendered by these interactions is
discussed in Chapter 2.1 Charged particles inci-
dent on a target interact primarily by Rutherford
scattering and Coulomb interaction. Rutherford
scattering can cause both excitation and libera-
tion of atomic electron ionization. Additionally,
sufficient energy can be transferred through
Rutherford scattering to atoms to displace them
from their normal lattice positions. Heavy
charged particles can also undergo nuclear inter-
actions of the type described below for neutrons.
For example, when a proton is absorbed in a tar-
get nucleus, the nucleus emits an alpha particle.
Neutrons incident on a target can participate in
elastic scattering, inelastic scattering, and trans-
mutation. In an elastic collision, the neutron
gives up a portion of its energy to an atom of the
target material, and can dislodge the atom from
its lattice position. This process continues as
long as the imparted energy is greater than that
required for displacement (25 eV for most mate-
rials). The displaced atom, referred to as the pri-
mary recoil atom (or primary knock-on atom,
PKA), will subsequently lose energy to ioniza-
tion; it can also displace other lattice atoms.
Inelastic neutron scattering involves capture of
the incident neutron by the nucleus of the target
atom with the subsequent emission of the neutron
at a lower energy. Kinetic energy is lost in this
process and the target nucleus is left in an excited
state. The excited nucleus returns to its original
state by the emission of a gamma ray. The ki-
netic energy of the emitted neutron is reduced,
compared to the incident neutron, by the energy
of the gamma ray. Inelastic neutron scattering
can also cause displacement of the target atom.
Transmutation involves capture of the incident
neutron by the target nucleus and subsequent
emission of another particle (e.g., a proton or an
alpha particle), resulting in the transmutation
(conversion) of the initial element into another
element.
Despite the complexity of these interactions,
the two primary effects in semiconductor devices
are displacement damage (atoms dislodged from
their normal lattice sites) and ionization (elec-
trodhole pair generation). In general, particles
passing through electronic materials deposit a
portion of their energy into ionization and the re-
mainder into atomic displacements. However,
for most practical situations, the ionization and
displacement damage effects can be separated.
For charged-particle irradiation, the primary
modes of electronic device degradation result
from ionization, although a certain amount of
atomic displacement can occur - especially for
the heavier ions. For high-energy neutron irra-
diation, the primary cause of device degradation
is atomic displacement damage, even though
considerable ionization (depending on the neu-
tron energy) can occur. Figure 4-1 depicts the
primary and secondary radiation effects in elec-
tronic devices. Only those interactions that can
produce displacement damage are addressed in
this chapter.
CHARGED
PARTICLES
PRIMARY EFFECTS
---- SECONDARY EFFECTS
/ / / - .. .
Figure 4-1. Schematic indicating primary radiation
effects and secondary effects in electronic devices
(McLean and Oldham, 1987).
.. / / Ov
></
. *
..
4.2 Atomic Displacement Processes
Figure 4-2 is a schematic of the atomic dis-
placement process in a crystalline lattice (e.g.,
silicon). An incident high-energy particle (e.g., a
neutron) interacts with a target lattice atom via
one of the mechanisms described in Section 4.1,
imparting sufficient energy to the lattice atom to
dislodge it from its initial site. The primary re-
coil atom (or PKA) may travel some distance in
the lattice before coming to rest, possibly induc-
ing further displacements in the process itself.
The reflected primary particle continues through
the lattice, also inducing further displacements as
long as its kinetic energy is sufficiently large.
IONIZATION
DISPLACEMENT
DAMAGE
NEUTRONS
The important outcome of the atomic displace-
ments is that defects are produced in the crystal
lattice. These may be simple defects such as va-
cancies and interstitials [as shown in Figure
4-2(b)], simple combinations of these (e.g.,
divacancies), complexes of vacancies and
interstitials with impurity atoms, or even more
/ /
.
0 0 0 0
CRYSTAL
LATTICE
RECOIL ATOM (PKA)
. .
REFLECTED
c
PRIMARY
PARTICLE 0 0 0 0 pRIMARy
(a) Atomic Displacement Event
0 0 0 0
0 INTERSTITIAL
0 0 0 0
VACANCY
(b) Radiation-Induced Defects
Figure 4-2. Schematic of atomic displacement dam-
age in a crystalline solid (McLean and Oldham, 1987).
complex clusters of defects [defect clusters are
important in neutron irradiation]. Figure 4-2(b)
shows a simple vacancy defect at the initial lat-
tice site and a simple interstitial where the PKA
has come to rest. From the theory of crystalline
semiconductors, it is known that any defects or
impurities that disturb the lattice periodicity have
the effect of producing localized, discrete energy
levels lying within the forbidden bandgap of the
perfect lattice, i.e., between the conduction-band
minimum and the valence-band maximum.
These electronic energy levels (gap states) asso-
ciated with the radiation-induced defects cause
an alteration of the electrical properties of the
semiconductor crystal, leading to device degra-
dation or failure. For example, additional recom-
bination centers may be introduced, which can
shorten the minority-carrier lifetimes and conse-
quently degrade the gain of a bipolar transistor.
The appropriate measure of displacement dam-
age in a material is its effect on some pertinent
electrical parameter, such as carrier lifetime or
transistor gain. Subsequent sections of this chap-
ter will address each of the effects in more detail.
In addition, recent developments to characterize
displacement damage in terms of non-ionizing
energy loss (NIEL) [contained in Section 4.3.21
provide a more complete understanding of dis-
placement damage phenomena.
4.3 Dynamics of Atomic Displacement
4.3.1 Damage Creation and Models
The basic physical interaction of displacement
was shown in Figure 4-2. The primary reaction
is caused by an incident particle striking a target
atom and results in the target atom recoiling from
the lattice site, as well as producing a scattered
(reflected) particle. If the recoil has enough en-
ergy, the atom is knocked loose from its lattice
site and comes to rest some distance away at an
interstitial site. Moreover, the recoiling atom and
reflected primary particle will undergo other in-
teractions, which will then produce a cascade of
displaced secondary atoms rather than the single
vacancylinterstitial shown in Figure 4-2.
The simplest mathematical description of the
scattering event illustrated in Figure 4-2 is that of
an elastic two-body collision. The equations for
such a collision follow from the fact that both
energy and momentum are conserved (Curtiss,
1959; Evans, 1955; Profio, 1979; Segre, 1965;
van Lint et al., 1980). Several assumptions are
implicit in using an elastic two-body collision
model. The particles are assumed to act like hard
spheres, with no energy dissipated in electronic
excitations or in nuclear reactions. Furthermore,
no energy is assumed to be lost to the lattice (i.e.,
to other nearby atoms) when the recoil atom es-
capes. These assumptions are frequently well
justified, because the energy lost in breaking
bonds in the lattice is very small compared to the
energy of the particles involved. For example,
only about 25 eV is required to be transferred to
a recoil atom in silicon in order to produce a va-
cancylinterstitial pair. On the other hand, the en-
ergy of typical incident particles is measured in
MeV. In fact, many other materials also have
critical displacement energies around 25 eV. If
only a few electron volts out of a million electron
volts are lost to electronic excitations and lattice
distortions, these effects can generally be ne-
glected.
In principle, any energetic particle (e.g., neu-
trons, electrons, protons, alpha particles, heavy
cosmic-ray ions, etc.) can cause displacement
damage. However, since neutrons interact with
the target atoms differently than do charged par-
ticles, the results of such interactions must be
considered separately. Neutrons do not interact
directly with the electrons in the target material,
and they lose energy only through nuclear inter-
actions. For this reason, displacement processes
are much more important for neutrons than for
charged particles. For charged particles, interac-
tions with atomic electrons cause most of the en-
ergy loss, but Coulomb scattering from nuclei
can lead to displacement damage also.
The qualitative differences between the inter-
actions of charged and uncharged particles are il-
lustrated in Figure 4-3, which compares the
energy deposited in tissue through different pro-
cesses for 10-MeV protons and neutrons. [The
results for silicon are qualitatively similar.] For
the 10-MeV neutrons, the primary interaction is
a nuclear scattering event, but the PKAs lose a
large part of their energy through ionization. The
DEPTH (cm)
Figure 4-3. Energy loss in tissue for neutrons md pro-
tons [proton energy loss indicated separately for elec-
tronic and nuclear processes] ( M c h and Oldham,
1987).
total energy loss for neutrons is plotted in the fig-
ure, but only a small part of this energy loss ac-
tually goes into displacement processes. The
remainder is lost by ionization in the slowing
down of the PKAs [see Figure 4-41. For the pro-
ton curves in Figure 4-3, the nuclear energy loss
and the electronic (ionization) energy loss are
plotted separately. Electronic processes account
for roughly three orders of magnitude more en-
ergy loss than nuclear processes.
In Figure 4-4, proton energy loss from nuclear
processes is plotted as a fraction of total energy
loss (nuclear plus electronic). For neutrons, the
nuclear fraction of total energy loss is plotted for
a primary PKA(Si). For example, a silicon atom
with an initial energy of 1 MeV would lose about
20 percent of its energy through nuclear pro-
cesses. If these results were replotted in terms of
the energy of the incident neutrons, the curve
would obviously be shifted to the right. For this
2
1 0-4
100 6101 102 1 o3 ld
PARTICLE ENERGY (keV)
Figure 4-4. Nuclear fraction of total energy loss for
protons and neutrons striking a silicon target
(Lindhard, S c W and Schiott, 1963).
reason, the neutron curve in Figure 4-4 is a lim-
iting case rather than an "exact" result.
The salient points are that the total energy
fraction going into atomic displacements is one
to two orders of magnitude greater for neutrons
than for protons, and that the neutron range is
many orders of magnitude greater than protons
[Figure 4-31. The conclusion is that neutron irra-
diation is much more effective in degrading elec-
trical properties of semiconductor electronics due
to displacement damage.
Defects created by incident particles can be
classified as simple defects (vacancies, divacan-
cies, vacancy/irnpurity complexes, interstitials,
di-interstitials, interstitial/impurity complexes)
and defect clusters. Several models have been
postulated to characterize displacement damage,
three of which are briefly discussed below.
4.3.1.6 Gossick Model
Failures in the attempt to explain experimental
results in terms of isolated point defects led to
the development of the Gossick model (Gossick,
1959), which postulates the existence of a large
disordered region, or defect cluster [Figure 4-51.
The core of the damage region, with radius Rg, is
assumed to be compensated intrinsic material,
i.e., electrically neutral. The outer shell of the
damaged region, between Ro and R1, is assumed
to be charged by trapped majority carriers (elec-
trons in this example), which balances the
trapped minority-carrier charge. In the Gossick
model, the disordered region presents a potential
barrier to majority carriers and a potential well to
minority carriers, with the result that defect clus-
ters serve as very efficient regions for minority-
carrier recombinations (Srour, 1982).
A "typical" distribution of clusters produced
by a 50-keV silicon recoil atom is shown in Fig-
ure 4-6. No one has argued that the clusters are
truly spherical, although a spherical shape is fre-
UNDAMAGED
REGION
\
REGIONS
DAMAGED \
POSITIVE REGION
NEGATIVE REGION
NEUTRAL REGION
Figure 4-5. Gossick model for defect clusters in neu-
tron-irradiated n-type silicon (Gossick, 1959; Smur,
1982).
quently assumed for convenience in modeling.
The size of the clusters and their spatial distribu-
tion have been somewhat controversial topics
over the years. Gossick himself has noted that a
damaged region would typically constrain lo5 to
lo6 atoms, corresponding to R1 = 15 to 20 nm.
The largest cluster observed by electron trans-
mission microscopy in samples of neutron-dam-
aged silicon, however, are nearly at the limits of
detection, having dimensions of 4 to 5 nm; clus-
ters with dimensions of 15 to 20 nm are not ob-
served in such samples. Variations on the
Gossick model have been postulated by Mueller,
Wilsey, and Rosen (1982) and Srour (1982).
4.3.1.2 Mueller-Wilsey-Rosen Model
The conventional picture developed by
Gossick (1959), and elaborated on by others, has
recently come into question, based on detailed
calculations using the binary-collision simulation
code MARLOWE (Mueller, Wilsey, and Rosen,
1982). In the Gossick model, the PKA cascade
produces a localized cluster of high-defect den-
sity whose dimensions are a large fraction of the
PKA range. This high-defect density gives rise
to a space-charge region, which can be much
larger than the defect cluster (depending on dop-
ing density). Alternatively, the MARLOWE
code calculations predict that PKAs produce long
trails of low-defect density [Figure 4-71, some of
which branch out, with very small clusters of ap-
proximately 50A diameter located at the end of
the tracks. These tracks are expected to have
much less effect on material parameters, e.g., re-
sistance, than small clusters, which can be
viewed as nonconducting voids.
4.3.1.3 Srour Model
The Srour model is a distributed cluster model,
in which the conventional neutron cluster model
is assumed; however, the detailed energy and
elastic angular distributions are taken into ac-
count [see Figures 4-8 and 4-91.
For this model, the PKAs interact with other
silicon atoms, causing displacements and produc-
ing more recoiling atoms. The density of dis-
placements is small near the beginning of the
PKA range and large near the end. The low-de-
fect-density regions probably contribute little to
the measured change in resistance except as com-
pensation centers. The high-defect-density re-
gions can be viewed as localized damage clusters
that act as nonconducting voids. Only those
voids overlapping the sensitive volume of, for
example, a diffused resistor will cause an in-
crease in resistance. Since a distribution of PKA
energies and angles exists, limits are imposed on
the location of the neutron interactions that pro-
duce a PKA, which can cause an overlapping
void. The energy and angular distributions also
result in a distribution of void sizes. Combining
these effects results in a distribution of resistance
changes caused by the statistical nature of neu-
tron interaction, PKA path, and void size.
4.3.2 Energy Deposition by Incident
Radiation
Although the models described in the forego-
ing subsections have been useful in providing an
understanding of these effects, more recent stud-
ies emphasize the non-ionizing energy loss
-36 -24 -1 2 0 12 24 36
DISTANCE AWAY FROM INITIAL DIRECTION (nrn)
Figure 4-6. Typical recoil-atom track with primary energy of 50 keV (van Lint, Leadon, and Colwell, 1972).
Figure 4-7. mi ca1 recoil-atom track with primary
energy of 50 keV, calculated using the Firsov interac-
tion radius [tic marks denote 10-nm increments]
(Mueller, Wdsey, and Rosen, 1982).
0 10 20 30 40 50 60 70 80 90
RECOIL ANGLE, Blab (degrees)
Figure 4-9. Angular distributions of elastic and inelas-
tic interactions in 14-MeV neutron-irradiated silicon
(Srour, 1983).
0 200 400 600 800 1,000 1,200
PRIMARY RECOIL ENERGY, LAB FRAME (keV)
Figure 4-8. Distributions of primary recoil energies for elastic and inelastic interactions in 14-MeV neutron-hdiated
silicon (Srour, 1983).
(NIEL) approach. Additional dynamics of
atomic displacement are presented here to pro-