VLSI Design

Special Issue on Networks-on-Chip

Call for Papers
While semiconductor device scaling continues providing greater transistor counts, much of the traditional power benet of scaling has ceased, leading to the current proliferation of parallel computing architectures. To cope with power consumption challenges without sacricing performance in these architectures, Networks-on-Chip (NoC) architectures have replaced bus-based and point-to-point (P2P) interconnect designs. As we approach hundreds and even a thousand cores on the same chip, there are several open problems across all design layers (technology, circuit, microarchitecture, and application) that require revolutionary approaches from a wide range of disciplines. This special issue on Networks-on-Chip, scheduled to appear in March 2013, seeks original and ambitious manuscripts advancing the state of the art in both theory and practice of designing and analyzing NoCs for the many-core era. Potential topics include, but are not limited to:
NoC architectures for CMP/MPSoCs (topology, rout

Verication, debug, and test of NoCs Modeling, simulation, and synthesis of NoCs Metrics and benchmarks for NoCs NoC performance analysis NoC case studies, application-specic NoC design

Before submission authors should carefully read over the journals Author Guidelines, which are located at http://www.hindawi.com/journals/vlsi/guidelines/. Prospective authors should submit an electronic copy of their complete manuscript through the journal Manuscript Tracking System at http://mts.hindawi.com/ according to the following timetable: Manuscript Due First Round of Reviews Publication Date Lead Guest Editor Paul Bogdan, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA; paulbogdan2010@gmail.com Guest Editors Siddharth Garg, Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada; s6garg@ecemail.uwaterloo.ca Paul V. Gratz, Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA; pgratz@gratz1.com Zhonghai Lu, Department of Electronic Systems, KTH Royal Institute of Technology, Stockholm, Sweden; zhonghai@kth.se Friday, 5 October 2012 Friday, 28 December 2012 Friday, 22 February 2013

ing, switching, ow control, etc.) NoC support for memory and cache access Workload characterization and evaluation Novel interconnect link/switch/router designs Timing, synchronous/asynchronous communication Signaling and circuit design for NoC links Physical design of interconnect and NoC Power, energy, and thermal issues Quality of Service NoCs for real-time multicore systems Network interface issues NoCs for FPGAs and structured ASICs OS support for NoCs and programming models Mapping of applications onto NoCs NoC design for 3D stacked logic and memory Optical and RF for on-chip/in-package interconnects NoC reliability issues Impact of process variations on NoC power/- performance Design methodologies and tools

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