ST7735

ST
Sitronix
1 Introduction 2 Features
Built-in Circuits -DC/DC converter -Adjustable VCOM generation Single chip TFT-LCD Controller/Driver with RAM On-chip Display Data RAM (i.e. Frame Memory) -132 (H) x RGB x 162 (V) bits LCD Driver Output Circuits: -Source Outputs: 132 RGB channels -Gate Outputs: 162 channels -Common electrode output Display Resolution -132 (RGB) x 162 (GM[2:0]= 000, DDRAM: 132 x 18-bits x 162) -128 (RGB) x 160 (GM[2:0]= 011, DDRAM: 128 x 18-bits x 160) Display Colors (Color Mode) -Full Color: 262K, RGB=(666) max., Idle Mode OFF -Color Reduce: 8-color, RGB=(111), Idle Mode ON Programmable Pixel Color Format (Color Depth) for Various Display Data input Format -12-bit/pixel: RGB=(444) using the 384k-bit frame memory and LUT -16-bit/pixel: RGB=(565) using the 384k-bit frame memory and LUT -18-bit/pixel: RGB=(666) using the 384k-bit frame memory and LUT Various Interfaces -Parallel 8080-series MCU Interface (8-bit, 9-bit, 16-bit & 18-bit) -3-line serial interface -4-line serial interface Display Features -Programmable partial display duty -Line inversion, frame inversion -Support both normal-black & normal-white LC -Software programmable color depth mode
ST7735
262K Color Single-Chip TFT Controller/Driver
The ST7735 is a single-chip controller/driver for 262K-color, graphic type TFT-LCD. It consists of 396 source line and 162 gate line driving circuits. This chip is capable of connecting directly to an external microprocessor, and accepts Serial Peripheral Interface (SPI), 8-bit/9-bit/16-bit/18-bit parallel interface. Display data can be stored in the on-chip display data RAM of 132 x 162 x 18 bits. It can perform display data RAM read/write operation with no external operation clock to minimize power consumption. In addition, because of the integrated power supply circuits necessary to drive liquid crystal, it is possible to make a display system with fewer components.
-Non-volatile (NV) memory to store initial register setting -Oscillator for display clock generation -Factory default value (module ID, module version, etc) are stored in NV memory -Timing controller Built-in NV Memory for LCD Initial Register Setting -7-bits for ID2 -8-bits for ID3 -7-bits for VCOM adjustment Wide Supply Voltage Range -I/O Voltage (VDDI to DGND): 1.65V~VDD (VDDI VDD) -Analog Voltage (VDD to AGND): 2.6V~3.3V On-Chip Power System -Source Voltage (GVDD to AGND): 3.0V~5.0V -VCOM HIGH level (VCOMH to AGND): 2.5V to 5.0V -VCOM LOW level (VCOML to AGND): -2.4V to 0.0V -Gate driver HIGH level (VGH to AGND): +10.0V to +15V -Gate driver LOW level (VGL to AGND): -12.4V to -7.5V Operating Temperature: -30 C to +85 C
ST7735
Parallel Interface: 8-bit/9-bit/16-bit/18-bit Serial Interface: 3-line/4-line
Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice.
V1.9
2010-01-20
ST7735
3 Pad arrangement
Boundary (Include scribe Lane) L
3.1 Output Bump Dimension
J A
Item Bump pitch Bump width Bump height Bump gap1 (Vertical) Bump gap2 (Horizontal) Bump area Chip Boundary (include scribe Lane)
Symbol A C H J K CxH L
Size 16 um 16 um 98 um 19 um 16 um 1568 um2 59 um
V1.9
2010-01-19
ST7735
3.2 Input Bump Dimension
C2
C2
A1
A2
C1
H K K2 L Boundary (Include scribe Lane)

Item Bump pitch 1 Bump pitch 2 Bump width 1 Bump width 2 Bump height Bump gap Bump gap1 Bump gap2 Bump area 1 Bump area 2 Chip Boundary(include scribe Lane) Symbol A1 A2 C1 C2 H K K1 K2 C1 X H C2 X H L Size 67 um 50 um 35 um 40 um 90 um 20 um 15 um 32 um 3150 um2 3690 um2 59 um
K1
K1
V1.9
2010-01-19
ST7735
3.3 Alignment Mark Dimension
10 5 15 15
5 10 15 15
80
20
20
15 15
80
15 15
15 15
20 80
15 15
15 15
20 80
15 15
V1.9
2010-01-19
ST7735
3.4 Chip Information
Chip size (um x um): 9900 x 670 PAD coordinate: pad center Coordinate origin: chip center Chip thickness (um): 300 (TYP) Bump height (um): 15 (TYP) Bump hardness (HV): 75 (TYP) No.186 No.185
No.759
No.1
V1.9
2010-01-19
ST7735
4
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Pad Center Coordinates

PAD Name DUMMY VDDIO EXTC DGNDO IM0 VDDIO IM1 DGNDO DUMMY VDDIO TPI[1] DGNDO TPI[2] VDDIO SRGB DGNDO SMX VDDIO SMY DGNDO DUMMY VDDIO DUMMY DGNDO DUMMY VDDIO DUMMY DGNDO DUMMY VDDIO LCM DGNDO DUMMY VDDIO GM2 DGNDO GM1 VDDIO GM0 DGNDO DUMMY GS SPI4W VDDIO TPO[8] TPO[7] TPO[6] TPO[5] TPO[4] OSC X -4750 -4700 -4650 -4600 -4550 -4500 -4450 -4400 -4350 -4300 -4250 -4200 -4150 -4100 -4050 -4000 -3950 -3900 -3850 -3800 -3750 -3700 -3650 -3600 -3550 -3500 -3450 -3400 -3350 -3300 -3250 -3200 -3150 -3100 -3050 -3000 -2950 -2900 -2850 -2800 -2750 -2700 -2650 -2600 -2550 -2500 -2450 -2400 -2350 -2300 Y -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 PAD Name VDD VDD VDD VDD VDD VDD AGND AGND AGND AGND AGND AGND RDX D/CX TESEL DGNDO D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D1 D3 D5 D7 TE RESX CSX D6 D4 D2 IM2 D0 WRX DUMMY DUMMY DUMMY DUMMY TPO[3] TPO[2] TPO[1] DGND DGND DGND DGND X -2250 -2200 -2150 -2100 -2050 -2000 -1950 -1900 -1850 -1800 -1750 -1700 -1630 -1570 -1510 -1450 -1390 -1330 -1270 -1210 -1150 -1090 -1030 -970 -910 -850 -790 -730 -670 -610 -550 -490 -430 -370 -310 -250 -190 -130 -70 0 50 100 150 200 250 300 350 400 450 500 Y -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 PAD Name DGND DGND VDDI VDDI VDDI VDDI VDDI VDDI VCC VCC VCCO VCI1 VCI1 VCI1 VREF VREF VREF DUMMY DUMMY AVDD AVDD AVDD AVDDO AVDDO GVDD GVDD GVDD DUMMY DUMMY C11P C11P C11P C11P C11N C11N C11N C11N C12P C12P C12P C12P C12N C12N C12N C12N AGND AGND AGND VCL VCL X 550 600 650 700 750 800 850 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 1500 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 2650 2700 2750 2800 2850 2900 2950 3000 Y -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231
V1.9
2010-01-19
ST7735
No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 PAD Name VCL C41P C41P C41P C41N C41N C41N C22P C22P C22P C22N C22N C22N C23P C23P C23P C23N C23N C23N VGL VGL VGL VGH VGH VGHO VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOM VCOM VCOM DUMMY DUMMY DUMMY G162 G160 G158 G156 G154 G152 G150 G148 G146 G144 G142 G140 G138 X 3050 3100 3150 3200 3250 3300 3350 3400 3450 3500 3550 3600 3650 3700 3750 3800 3850 3900 3950 4000 4050 4100 4150 4200 4250 4300 4350 4400 4450 4500 4550 4600 4650 4700 4750 4772 4756 4740 4724 4708 4692 4676 4660 4644 4628 4612 4596 4580 4564 4548 Y -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 -231 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 PAD Name G136 G134 G132 G130 G128 G126 G124 G122 G120 G118 G116 G114 G112 G110 G108 G106 G104 G102 G100 G98 G96 G94 G92 G90 G88 G86 G84 G82 G80 G78 G76 G74 G72 G70 G68 G66 G64 G62 G60 G58 G56 G54 G52 G50 G48 G46 G44 G42 G40 G38 X 4532 4516 4500 4484 4468 4452 4436 4420 4404 4388 4372 4356 4340 4324 4308 4292 4276 4260 4244 4228 4212 4196 4180 4164 4148 4132 4116 4100 4084 4068 4052 4036 4020 4004 3988 3972 3956 3940 3924 3908 3892 3876 3860 3844 3828 3812 3796 3780 3764 3748 Y 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 No. 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 PAD Name G36 G34 G32 G30 G28 G26 G24 G22 G20 G18 G16 G14 G12 G10 G8 G6 G4 G2 DUMMY DUMMY DUMMY DUMMY S396 S395 S394 S393 S392 S391 S390 S389 S388 S387 S386 S385 S384 S383 S382 S381 S380 S379 S378 S377 S376 S375 S374 S373 S372 S371 S370 S369 X 3732 3716 3700 3684 3668 3652 3636 3620 3604 3588 3572 3556 3540 3524 3508 3492 3476 3460 3444 3428 3412 3396 3380 3364 3348 3332 3316 3300 3284 3268 3252 3236 3220 3204 3188 3172 3156 3140 3124 3108 3092 3076 3060 3044 3028 3012 2996 2980 2964 2948 Y 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110
V1.9
2010-01-19
ST7735
No. 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 PAD Name S368 S367 S366 S365 S364 S363 S362 S361 S360 S359 S358 S357 S356 S355 S354 S353 S352 S351 S350 S349 S348 S347 S346 S345 S344 S343 S342 S341 S340 S339 S338 S337 S336 S335 S334 S333 S332 S331 S330 S329 S328 S327 S326 S325 S324 S323 S322 S321 S320 S319 X 2932 2916 2900 2884 2868 2852 2836 2820 2804 2788 2772 2756 2740 2724 2708 2692 2676 2660 2644 2628 2612 2596 2580 2564 2548 2532 2516 2500 2484 2468 2452 2436 2420 2404 2388 2372 2356 2340 2324 2308 2292 2276 2260 2244 2228 2212 2196 2180 2164 2148 Y 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 No. 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 PAD Name S318 S317 S316 S315 S314 S313 S312 S311 S310 S309 S308 S307 S306 S305 S304 S303 S302 S301 S300 S299 S298 S297 S296 S295 S294 S293 S292 S291 S290 S289 S288 S287 S286 S285 S284 S283 S282 S281 S280 S279 S278 S277 S276 S275 S274 S273 S272 S271 S270 S269 X 2132 2116 2100 2084 2068 2052 2036 2020 2004 1988 1972 1956 1940 1924 1908 1892 1876 1860 1844 1828 1812 1796 1780 1764 1748 1732 1716 1700 1684 1668 1652 1636 1620 1604 1588 1572 1556 1540 1524 1508 1492 1476 1460 1444 1428 1412 1396 1380 1364 1348 Y 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 No. 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 PAD Name S268 S267 S266 S265 S264 S263 S262 S261 S260 S259 S258 S257 S256 S255 S254 S253 S252 S251 S250 S249 S248 S247 S246 S245 S244 S243 S242 S241 S240 S239 S238 S237 S236 S235 S234 S233 S232 S231 S230 S229 S228 S227 S226 S225 S224 S223 S222 S221 S220 S219 X 1332 1316 1300 1284 1268 1252 1236 1220 1204 1188 1172 1156 1140 1124 1108 1092 1076 1060 1044 1028 1012 996 980 964 948 932 916 900 884 868 852 836 820 804 788 772 756 740 724 708 692 676 660 644 628 612 596 580 564 548 Y 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110
V1.9
2010-01-19
ST7735
No. 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 PAD Name S218 S217 S216 S215 S214 S213 S212 S211 S210 S209 S208 S207 S206 S205 S204 S203 S202 S201 S200 S199 DUMMY DUMMY DUMMY DUMMY S198 S197 S196 S195 S194 S193 S192 S191 S190 S189 S188 S187 S186 S185 S184 S183 S182 S181 S180 S179 S178 S177 S176 S175 S174 S173 X 532 516 500 484 468 452 436 420 404 388 372 356 340 324 308 292 276 260 244 228 212 196 -196 -212 -228 -244 -260 -276 -292 -308 -324 -340 -356 -372 -388 -404 -420 -436 -452 -468 -484 -500 -516 -532 -548 -564 -580 -596 -612 -628 Y 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 No. 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 PAD Name S172 S171 S170 S169 S168 S167 S166 S165 S164 S163 S162 S161 S160 S159 S158 S157 S156 S155 S154 S153 S152 S151 S150 S149 S148 S147 S146 S145 S144 S143 S142 S141 S140 S139 S138 S137 S136 S135 S134 S133 S132 S131 S130 S129 S128 S127 S126 S125 S124 S123 X -644 -660 -676 -692 -708 -724 -740 -756 -772 -788 -804 -820 -836 -852 -868 -884 -900 -916 -932 -948 -964 -980 -996 -1012 -1028 -1044 -1060 -1076 -1092 -1108 -1124 -1140 -1156 -1172 -1188 -1204 -1220 -1236 -1252 -1268 -1284 -1300 -1316 -1332 -1348 -1364 -1380 -1396 -1412 -1428 Y 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 No. 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 PAD Name S122 S121 S120 S119 S118 S117 S116 S115 S114 S113 S112 S111 S110 S109 S108 S107 S106 S105 S104 S103 S102 S101 S100 S99 S98 S97 S96 S95 S94 S93 S92 S91 S90 S89 S88 S87 S86 S85 S84 S83 S82 S81 S80 S79 S78 S77 S76 S75 S74 S73 X -1444 -1460 -1476 -1492 -1508 -1524 -1540 -1556 -1572 -1588 -1604 -1620 -1636 -1652 -1668 -1684 -1700 -1716 -1732 -1748 -1764 -1780 -1796 -1812 -1828 -1844 -1860 -1876 -1892 -1908 -1924 -1940 -1956 -1972 -1988 -2004 -2020 -2036 -2052 -2068 -2084 -2100 -2116 -2132 -2148 -2164 -2180 -2196 -2212 -2228 Y 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227
V1.9
2010-01-19
ST7735
No. 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 PAD Name S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 X -2244 -2260 -2276 -2292 -2308 -2324 -2340 -2356 -2372 -2388 -2404 -2420 -2436 -2452 -2468 -2484 -2500 -2516 -2532 -2548 -2564 -2580 -2596 -2612 -2628 -2644 -2660 -2676 -2692 -2708 -2724 -2740 -2756 -2772 -2788 -2804 -2820 -2836 -2852 -2868 -2884 -2900 -2916 -2932 -2948 -2964 -2980 -2996 -3012 -3028 Y 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 No. 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 PAD Name S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 DUMMY DUMMY DUMMY DUMMY G1 G3 G5 G7 G9 G11 G13 G15 G17 G19 G21 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 X -3044 -3060 -3076 -3092 -3108 -3124 -3140 -3156 -3172 -3188 -3204 -3220 -3236 -3252 -3268 -3284 -3300 -3316 -3332 -3348 -3364 -3380 -3396 -3412 -3428 -3444 -3460 -3476 -3492 -3508 -3524 -3540 -3556 -3572 -3588 -3604 -3620 -3636 -3652 -3668 -3684 -3700 -3716 -3732 -3748 -3764 -3780 -3796 -3812 -3828 Y 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 No. 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 PAD Name G49 G51 G53 G55 G57 G59 G61 G63 G65 G67 G69 G71 G73 G75 G77 G79 G81 G83 G85 G87 G89 G91 G93 G95 G97 G99 G101 G103 G105 G107 G109 G111 G113 G115 G117 G119 G121 G123 G125 G127 G129 G131 G133 G135 G137 G139 G141 G143 G145 G147 X -3844 -3860 -3876 -3892 -3908 -3924 -3940 -3956 -3972 -3988 -4004 -4020 -4036 -4052 -4068 -4084 -4100 -4116 -4132 -4148 -4164 -4180 -4196 -4212 -4228 -4244 -4260 -4276 -4292 -4308 -4324 -4340 -4356 -4372 -4388 -4404 -4420 -4436 -4452 -4468 -4484 -4500 -4516 -4532 -4548 -4564 -4580 -4596 -4612 -4628 Y 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227 110 227
V1.9
10
2010-01-19
ST7735
No. 751 752 753 754 755 756 757 758 759 PAD Name G149 G151 G153 G155 G157 G159 G161 DUMMY DUMMY ALK-R ALK-L X -4644 -4660 -4676 -4692 -4708 -4724 -4740 -4756 -4772 4841 -4841 Y 110 227 110 227 110 227 110 227 110 -220 -220
V1.9
11
2010-01-19
ST7735
5 Block diagram
GVDD
162 Gate buffer 396 Source buffer Voltage reference
Level shifter DAC Gamma circuit Gate decoder Level Shifter
Data Latch
VCOMH
Gamma Table
Vcom generator
VCOM VCOML
Display Ram 132 x 162 x 18bits
Display control
OSC
Color conversion LUT table
Instruction register
C11P
EEPROM Booster 1/2/4
C11N C41P C41N C22P C22N C23P
MCU IF
C23N
D[17:0]
LCM
SRGB
WRX (R/WX) GS
CSX RDX (E)
IM [2:0]
EXTC
SMX
SMY
SDA
VDD VDDI AVDD VCL VGH VGL
DC/X (SCL)
V1.9
12
2010-01-19
ST7735
6 Driver IC Pin Description
Name VDD VDDI AGND DGND I/O I I I I Description Power supply for analog, digital system and booster circuit. Power supply for I/O system. System ground for analog system and booster circuit. System ground for I/O system and digital system. Connect pin VDD VDDI GND GND 6.1 Power Supply Pin
6.2 Interface logic pin Name I/O Description MCU Parallel interface bus and Serial interface select IM2 I IM2=1, Parallel interface IM2=0, Serial interface - MCU parallel interface type selection -If not used, please fix this pin at VDDI or DGND level. IM1 IM1,IM0 I 0 0 1 1 IM0 0 1 0 1 Parallel interface MCU 8-bit parallel MCU 16-bit parallel MCU 9-bit parallel MCU 18-bit parallel DGND/VDDI DGND/VDDI Connect pin
- SPI4W=0, 3-line SPI enable. SPI4W I - SPI4W=1, 4-line SPI enable. -If not used, please fix this pin at DGND level. -This signal will reset the device and it must be applied to properly RESX I initialize the chip. -Signal is active low. CSX I -Chip selection pin -Low enable. -Display data/command selection pin in MCU interface. D/CX (SCL) -D/CX=1: display data or parameter. I -D/CX=0: command data. -In serial interface, this is used as SCL. -If not used, please fix this pin at VDDI or DGND level. RDX I -Read enable in 8080 MCU parallel interface. -If not used, please fix this pin at VDDI or DGND level. -Write enable in MCU parallel interface. I -In 4-line SPI, this pin is used as D/CX (data/ command selection). -If not used, please fix this pin at VDDI or DGND level. I/O -D[17:0] are used as MCU parallel interface data bus. MCU MCU MCU MCU MCU MCU DGND/VDDI
WRX (D/CX) D[17:0]
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2010-01-19
ST7735
-D0 is the serial input/output signal in serial interface mode. -In serial interface, D[17:1] are not used and should be fixed at VDDI or DGND level. -Tearing effect output pin to synchronies MCU to frame rate, activated TE O by S/W command. -If not used, please open this pin. -Monitoring pin of internal oscillator clock and is turned ON/OFF by OSC O S/W command. -When this pin is inactive (function OFF), this pin is DGND level. -If not used, please open this pin.
Note1. When in parallel mode, no use data pin must be connected to 1 or 0. Note2. When CSX=1, there is no influence to the parallel and serial interface.
MCU
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ST7735
6.3 Mode selection pin Name I/O Description -During normal operation, please open this pin EXTC
EXTC
Connect pin
Enable/disable modification of extend command System function command list can be used. All command list can be used.
Open
0 1
-Panel resolution selection pins. G

GM2, GM1, GM0
G M 1 0 1
G M 0 0 1
Selection of panel resolution

VDDI/DGND
M I 2 0 0
132RGB x 162 (S1~S396 & G1~G162 output) 128RGB x 160 (S7~S390 & G2~G161 output)
-RGB direction select H/W pin for color filter setting. SRGB
SRGB
RGB arrangement S1, S2, S3 filter order = R, G, B S1, S2, S3 filter order = B, G, R
VDDI/DGND
0 1
-Module source output direction H/W selection pin. SMX SMX I 0 1 Scanning direction of source output GM= 000 S1 -> S396 S396 -> S1 GM= 011 S7 -> S390 S390 -> S7
VDDI/DGND
-Module Gate output direction H/W selection pin. SMY SMY I 0 1 Scanning direction of gate output GM= 000 G1 -> G162 G162 -> G1 GM= 011 G2 -> G161 G161 -> G2
VDDI/DGND
-Liquid crystal (LC) type selection pins. LCM LCM I 0 1 Selection of LC type Normally white LC type Normally black LC type
VDDI/DGND
-Gamma curve selection pin. GS GS I 0 1 Selection of gamma curve GC0=1.0, GC1=2.5, GC2=2.2, GC3=1.8 GC0=2.2, GC1=1.8, GC2=2.5, GC3=1.0
VDDI/DGND
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Input pin to select horizontal line number in TE signal. TESEL I This pin is only for GM[2:0]=000 mode
VDDI/DGND
TESEL=0 , TE output 162 lines TESEL=1 , TE output 160 lines
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6.4 Driver output pins Name S1 to S396 G1 to G162 VCI1 I/O O O I/O - Source driver output pins. - Gate driver output pins. - Hi-Z - Power input pin for analog circuits. AVDD I - In normal usage, connect it to AVDDO. - AVDD = 5.3V. AVDDO O - Output of step-up circuit 1 - Connect a capacitor for stabilization.
- A power supply pin for generating VCOML.
Description
Connect pin -
AVDDO
Capacitor
VCL
- Connect a capacitor for stabilization. - Power input pin for gate driver circuit. - In normal usage, connect it to VGHO. - Positive output pin of the step-up circuit 2. - Connect a capacitor for stabilization. - Power input pin for gate driver circuit.
Capacitor
VGH
VGHO
VGHO
Capacitor
VGL
- Negative output of the step-up circuit 2 is connected inside the driver. - Connect a capacitor for stabilization.
Capacitor
VREF
- A reference voltage for power system. -This test pin for Driver vender test used. - A power output of grayscale voltage generator.
GVDD
- When internal GVDD generator is not used, connect an external power supply (AVDD-0.5V) to this pin. - Positive voltage output of VCOM. - Connect a capacitor for stabilization. - Negative voltage output of VCOM. - Connect a capacitor for stabilization. - A power supply for the TFT-LCD common electrode.
VCOMH
Capacitor
VCOML
Capacitor Common electrode Step-up Capacitor Step-up Capacitor
VCOM
C11P, C11N C22P, C22N C23P, C23N C41P, C41N
- Capacitor connecting pins for step-up circuit 1 (for AVDDO)
- Capacitor connecting pins for step-up circuit 2 and 4 (for VGHO, VGL, VCL)
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VDDIO DGNDO VCC O O I -VDDI voltage output level for monitoring. -DGND voltage output level for monitoring. -Power input pin for internal digital reference voltage. -In normal usage, connect it to VCCO. -Monitoring pin of internal digital reference voltage. -Connect a capacitor for stabilization. VCCO
VCCO
Capacitor
6.5 Test pins Name TPI[2] TPI[1] TPO[8] TPO[7] TPO[6] TPO[5] TPO[4] TPO[3] TPO[2] TPO[1] -These pins are dummy (have no function inside). Dummy -Can allow signal traces pass through these pads on TFT glass. -Please open these pins. Open
-These test pins for Driver vender test used.
I/O I
Description
-These test pins for Driver vender test used.
Connect pin DGND
-Please connect these pins to DGND.
-Please open these pins.
Open
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7 Driver electrical characteristics
Symbol VDD VDDI VCC VGH-VGL VIN VO TOPR TSTG Rating -0.3 ~ +4.6 -0.3 ~ +4.6 -0.3 ~ +1.95 -0.3 ~ +30.0 -0.3 ~ VDDI +0.3 -0.3 ~ VDDI +0.3 -30 ~ +85 -40 ~ +125 Unit V V V V V V 7.1 Absolute operation range Item Supply voltage Supply voltage (Logic) Supply voltage (Digital) Driver supply voltage Logic input voltage range Logic output voltage range Operating temperature range Storage temperature range
Note: If one of the above items is exceeded its maximum limitation momentarily, the quality of the product may be degraded. Absolute maximum limitation, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the recommend range.
7.2 DC characteristic Parameter Symbol Condition Min Power & operation voltage System voltage Interface operation voltage Gate driver high voltage Gate driver low voltage Gate driver supply voltage Input / Output Logic-high input voltage Logic-low input voltage Logic-high output voltage Logic-low output voltage Logic-high input current VIH 0.7VDDI VDDI V Note 1 VDD VDDI Operating voltage I/O supply voltage 2.6 1.65 2.75 1.9 3.3 3.3 V V Specification Typ Max Unit Related Pins
VGH
10
15
VGL
-12.4
-7.5
| VGH-VGL |
17.5
27.5
VIL
VSS
0.3VDDI
Note 1
VOH
IOH = -1.0mA
0.8VDDI
VDDI
Note 1
VOL
IOL = +1.0mA
VSS
0.2VDDI
Note 1
IIH
VIN = VDDI
uA
Note 1
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Logic-low input current Input leakage current VCOM voltage VCOM high voltage VCOM low voltage VCOM amplitude Source driver Source output range Gamma reference voltage Source output settling time Output offset voltage
Notes: 1. VDDI=1.65 to 3.3V, VDD=2.6 to 3.3V, AGND=DGND=0V, TA= -30 to 85 2. Source channel loading= 2K+12pF/channel, Gate channel loading=5K+40pF/channel. 3. The Max. value is between measured point of source output and gamma setting value.
IIL
VIN = VSS
-1
uA
Note 1
IIL
IOH = -1.0mA
-0.1
+0.1
uA
Note 1
VCOMH VCOML VCOMAC
Ccom=12nF Ccom=12nF |VCOMH-VCOML|
2.5 -2.4 4.0
5.0 0.0 6.0
V V V
Vsout GVDD Below with 99% precision
0.1 3.0
AVDD-0.1 5.0
V V
Tr Voffset
20 35
us mV
Note 2 Note 3
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7.3 Power consumption
VDD=2.8V, VDDI=1.8V, Ta=25, Frame rate = 60Hz, the registers setting are IC default setting.
Current consumption Operation mode Inversion mode Image Typical IDDI (mA) Normal mode One Line Note 1 Note 2 Partial + Idle mode (40 lines) Sleep-in mode
Notes: 1. All pixels black. 2. All pixels white. 3. The Current Consumption is DC characteristics of ST7735
Maximum IDD (mA) 0.5 0.5 0.3 0.3 0.015 IDDI (mA) 0.02 0.02 0.02 0.02 0.01 IDD (mA) 0.7 0.7 0.5 0.5 0.03
0.01 0.01 0.01 0.01 0.005
One Line N/A
Note 1 Note 2 N/A
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8 Timing chart
8.1 Parallel interface characteristics: 18, 16, 9 or 8-bit bus (8080 series MCU interface)
Fig. 8.1.1 Parallel interface timing characteristics (8080 series MCU interface)
Signal D/CX
Symbol TAST TAHT TCHW TCS
Parameter Address setup time Address hold time (Write/Read) Chip select H pulse width Chip select setup time (Write) Chip select setup time (Read ID) Chip select setup time (Read FM) Chip select wait time (Write/Read) Chip select hold time Write cycle Control pulse H duration Control pulse L duration Read cycle (ID) Control pulse H duration (ID) Control pulse L duration (ID) Read cycle (FM) Control pulse H duration (FM) Control pulse L duration (FM)
Min 10 10 0 15 45 350 10 10 100 30 30 160 90 45 450 150 150
Max
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Description -
CSX
TRCS TRCSFM TCSF TCSH TWC
WRX
TWRH TWRL TRC
RDX (ID)
TRDH TRDL TRCFM
When read ID data
RDX (FM) TRDHFM TRDLFM ns ns
When read from frame memory
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TDST TDHT D[17:0] TRAT TRATFM TODH Data setup time Data hold time Read access time (ID) Read access time (FM) Output disable time 10 10 40 40 80 ns ns ns ns ns For CL=30pF
Table 8.1.1 Parallel Interface Characteristics
Note: VDDI=1.65 to 3.3V, VDD=2.6 to 3.3V, AGND=DGND=0V, Ta=25
TR VIH=0.7 x VDDI VIL=0.3 x VDDI TR=TF<=15ns
TF
TR VOH=0.8 x VDDI VOL=0.2 x VDDI TR=TF<=15ns
TF
Fig. 8.1.2 Rising and falling timing for input and output signal
Fig. 8.1.3 Chip selection (CSX) timing
Fig. 8.1.4 Write-to-read and read-to-write timing

Note: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals.
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8.2 Serial interface characteristics (3-line serial)
VIH VIL
CSX
TCHW TSCYCW/TSCYCR TCSS TCSH

VIH VIL
SCL
TSLW/TSLR TSHW/TSHR TSDS TSDH
TSCC
SDA
VIH VIL
TACC
TOH
VIH VIL
VIH VIL
SDA (DOUT)
Fig. 8.2.1 3-line serial interface timing
Signal
Symbol TCSS TCSH
Parameter Chip select setup time (write) Chip select hold time (write) Chip select setup time (read) Chip select hold time (read) Chip select H pulse width Serial clock cycle (Write) SCL H pulse width (Write) SCL L pulse width (Write) Serial clock cycle (Read) SCL H pulse width (Read) SCL L pulse width (Read) Data setup time Data hold time Access time Output disable time
Min 15 15 60 65 40 66 30 30 150 60 60 10 10 10
Max
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Description
CSX
TCSS TSCC TCHW TSCYCW TSHW
SCL
TSLW TSCYCR TSHR TSLR TSDS
SDA (DIN) (DOUT)
TSDH TACC TOH
For maximum CL=30pF For minimum CL=8pF
50 50
ns ns
Table 8.2.1 3-line Serial Interface Characteristics

Note 1: VDDI=1.65 to 3.3V, VDD=2.6 to 3.3V, AGND=DGND=0V, Ta=25 Note 2: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals.
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8.3 Serial interface characteristics (4-line serial)
Fig. 8.3.1 4-line serial interface timing
Signal
Symbol TCSS TCSH
Parameter Chip select setup time (write) Chip select hold time (write) Chip select setup time (read) Chip select hold time (read) Chip select H pulse width Serial clock cycle (Write) SCL H pulse width (Write) SCL L pulse width (Write) Serial clock cycle (Read) SCL H pulse width (Read) SCL L pulse width (Read) D/CX setup time D/CX hold time Data setup time Data hold time Access time Output disable time
MIN 15 15 60 65 40 66 30 30 150 60 60
MAX
Unit ns ns ns ns ns ns
Description
CSX
TCSS TSCC TCHW TSCYCW TSHW
-write command & data ns ns ns -read command & data TSHR TSLR D/CX TDCS TDCH TSDS SDA (DIN) (DOUT) TSDH TACC TOH ns ns 0 10 10 10 10 50 50 ns ns ns ns ns ns For maximum CL=30pF For minimum CL=8pF ram ram TSLW TSCYCR
SCL
Table 8.3.1 4-line Serial Interface Characteristics

Note 1: VDDI=1.65 to 3.3V, VDD=2.6 to 3.3V, AGND=DGND=0V, Ta=25 Note 2: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals.
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9 Function description
9.1 Interface type selection
The selection of given interfaces are done by setting IM2, IM1, and IM0 pins as shown in following table.
IM2 0 1 1 1 1
IM1 0 0 1 1
IM0 0 1 0 1
Interface 3-line serial interface 8080 MCU 8-bit parallel 8080 MCU 16-bit parallel 8080 MCU 9-bit parallel 8080 MCU 18-bit parallel
Read back selection Via the read instruction RDX strobe (8-bit read data and 8-bit read parameter) RDX strobe (16-bit read data and 8-bit read parameter) RDX strobe (9-bit read data and 8-bit read parameter) RDX strobe (18-bit read data and 8-bit read parameter)
Table 9.1.1 Selection of MCU interface
IM2 0 1 1 1 1
IM1 0 0 1 1
IM0 0 1 0 1
Interface 3-line serial 8080 8-bit parallel 8080 16-bit parallel 8080 9-bit parallel 8080 18-bit parallel
RDX Note1 RDX RDX RDX RDX
WRX Note1 WRX WRX WRX WRX
D/CX SCL D/CX D/CX D/CX D/CX
Read back selection D[17:1]: unused, D0: SDA D[17:8]: unused, D7-D0: 8-bit data D[17:16]: unused, D15-D0: 16-bit data D[17:9]: unused, D8-D0: 9-bit data D17-D0: 18-bit data
Table 9.1.2 Pin connection according to various MCU interface

Note1: Unused pins can be open, or connected to DGND or VDDI.
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9.2 8080-series MCU parallel interface
The MCU can use one of following interfaces: 11-lines with 8-data parallel interface, 12-lines with 9-data parallel interface, 19-line with 16-data parallel interface or 21-lines with 18-data parallel interface. The chip-select CSX (active low) enables/disables the parallel interface. RESX (active low) is an external reset signal. WRX is the parallel data write enable, RDX is the parallel data read enable and D[17:0] is parallel data bus. The LCD driver reads the data at the rising edge of WRX signal. The D/CX is the data/command flag. When D/CX=1, D[17:0] bits is either display data or command parameter. When D/C=0, D[17:0] bits is command. The interface functions of 8080-series parallel interface are given in following table.
IM2 IM1 IM0 Interface 8-bit parallel D/CX 0 1 0 0 1 1 1 0 1 0 1 16-bit parallel 1 1 1 0 1 1 0 9-bit parallel 1 1 1 0 1 1 1 18-bit parallel 1 1 1 RDX 1 1 1 1 1 1 1 1 WRX 1 1 1 1 1 1 1 1 Read back selection Write 8-bit command (D7 to D0) Write 8-bit display data or 8-bit parameter (D7 to D0) Read 8-bit display data (D7 to D0) Read 8-bit parameter or status (D7 to D0) Write 8-bit command (D7 to D0) Write 16-bit display data or 8-bit parameter (D15 to D0) Read 16-bit display data (D15 to D0) Read 8-bit parameter or status (D7 to D0) Write 8-bit command (D7 to D0) Write 9-bit display data or 8-bit parameter (D8 to D0) Read 9-bit display data (D8 to D0) Read 8-bit parameter or status (D7 to D0) Write 8-bit command (D7 to D0) Write 18-bit display data or 8-bit parameter (D17 to D0) Read 18-bit display data (D17 to D0) Read 8-bit parameter or status (D7 to D0)
Table 9.2.1 The function of 8080-series parallel interface

Note: applied for command code: DAh, DBh, DCh, 04h, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh
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9.2.1 Write cycle sequence
The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write cycle (WRX high-low-high sequence) consists of 3 control signals (D/CX, RDX, WRX) and data signals (D[17:0]). D/CX bit is a control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is low (=0) and vice versa it is data (=1).
WRX
D[17:0]
The host starts to control D[17:0] lines when there is a falling edge of the WRX.
The display writes D[17:0] lines when there is a rising edge of WRX.
The host stops to control D[17:0] lines.
Fig. 9.2.1 8080-series WRX protocol

Note: WRX is an unsynchronized signal (It can be stopped).
1-byte command
2-byte command
N-byte command
D[17:0] RESX 1
CMD
CMD
PA1
CMD
PA1
PAN-2
PAN-1
CSX
D/CX
1
RDX
WRX
D[17:0]
CMD
CMD
PA1
CMD
PA1
PAN-2
PAN-1
Host D[17:0] Host to LCD Driver D[17:0] LCD to Host
CMD Hi-Z
CMD
PA1
CMD
PA1
PAN-2
PAN-1
CMD: write command code PA: parameter or display data
Signals on D[17:0], D/CX, R/WX, E pins during CSX=1 are ignored.
Fig. 9.2.2 8080-series parallel bus protocol, write to register or display RAM
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9.2.2 Read cycle sequence
The read cycle (RDX high-low-high sequence) means that the host reads information from LCD driver via interface. The driver sends data (D[17:0]) to the host when there is a falling edge of RDX and the host reads data when there is a rising edge of RDX.
Fig. 9.2.3 8080-series RDX protocol

Note: RDX is an unsynchronized signal (It can be stopped).
Read parameter
Read display data
D[17:0] RESX 1
CMD
DM
PA
CMD
DM & data
Data
Data
CSX
D/CX
RDX
WRX
D[17:0]
CMD
DM
PA
CMD
DM & data
Data
Data
Host D[17:0] Host to LCD Driver D[17:0] LCD to Host
CMD Hi-Z
Hi-Z
CMD Hi-Z
Hi-Z
DM
PA1
DM & data
PAN-2
PAN-1
CMD: write command code PA: parameter or display data
Signals on D[17:0], D/CX, R/WX, E pins during CSX=1 are ignored.
Fig. 9.2.4 8080-series parallel bus protocol, read data from register or display RAM
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9.3 Serial interface
The selection of this interface is done by IM2. See the Table 9.3.1.
IM2 0 0
SPI4W 0 1
Interface 3-line serial interface 4-line serial interface
Read back selection Via the read instruction (8-bit, 24-bit and 32-bit read parameter) Via the read instruction (8-bit, 24-bit and 32-bit read parameter)
Table 9.3.1 Selection of serial interface The serial interface is either 3-line/9-bit or 4-line/8-bit bi-directional interface for communication between the micro controller and the LCD driver. The 3-line serial interface use: CSX (chip enable), SCL (serial clock) and SDA (serial data input/output), and the 4-line serial interface use: CSX (chip enable), D/CX (data/ command flag), SCL (serial clock) and SDA (serial data input/output). Serial clock (SCL) is used for interface with MCU only, so it can be stopped when no communication is necessary.
9.3.1
Command Write Mode
The write mode of the interface means the micro controller writes commands and data to the LCD driver. 3-line serial data packet contains a control bit D/CX and a transmission byte. In 4-line serial interface, data packet contains just transmission byte and control bit D/CX is transferred by the D/CX pin. If D/CX is low, the transmission byte is interpreted as a command byte. If D/CX is high, the transmission byte is stored in the display data RAM (memory write command), or command register as parameter. Any instruction can be sent in any order to the driver. The MSB is transmitted first. The serial interface is initialized when CSX is high. In this state, SCL clock pulse or SDA data have no effect. A falling edge on CSX enables the serial interface and indicates the start of data transmission.
Fig. 9.3.1 Serial interface data stream format When CSX is high, SCL clock is ignored. During the high period of CSX the serial interface is initialized. At the falling edge of CSX, SCL can be high or low (see Fig 9.3.2). SDA is sampled at the rising edge of SCL. D/CX indicates whether the byte is command (D/CX=0) or parameter/RAM data (D/CX=1). D/CX is sampled when first rising edge of SCL (3-line serial interface) or 8th rising edge of SCL (4-line serial interface). If CSX stays low after the last bit of command/data byte, the serial interface expects the D/CX bit (3-line serial interface) or D7 (4-line serial interface) of the next byte at the next rising edge of SCL.
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Fig. 9.3.2 3-line serial interface write protocol (write to register with control bit in transmission)
Fig. 9.3.3 4-line serial interface write protocol (write to register with control bit in transmission)
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9.3.2 Read Functions
The read mode of the interface means that the micro controller reads register value from the driver. To achieve read function, the micro controller first has to send a command (read ID or register command) and then the following byte is transmitted in the opposite direction. After that CSX is required to go to high before a new command is send (see the below figure). The driver samples the SDA (input data) at rising edge of SCL, but shifts SDA (output data) at the falling edge of SCL. Thus the micro controller is supported to read at the rising edge of SCL. After the read status command has been sent, the SDA line must be set to tri-state no later than at the falling edge of SCL of the last bit.
9.3.3
3-line serial protocol
3-line serial protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read):
3-line serial protocol (for RDDID command: 24-bit read)
3-line Serial Protocol (for RDDST command: 32-bit read)
Fig. 9.3.4 3-line serial interface read protocol
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9.3.4 4-line serial protocol
4-line serial protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read):
4-line serial protocol (for RDDID command: 24-bit read)
4-line Serial Protocol (for RDDST command: 32-bit read)
Host Driver
Fig. 9.3.5 4-line serial interface read protocol
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9.4 Data Transfer Break and Recovery
If there is a break in data transmission by RESX pulse, while transferring a command or frame memory data or multiple parameter command data, before Bit D0 of the byte has been completed, then driver will reject the previous bits and have reset the interface such that it will be ready to receive command data again when the chip select line (CSX) is next activated after RESX have been HIGH state. See the following example
If there is a break in data transmission by CSX pulse, while transferring a command or frame memory data or multiple parameter command data, before Bit D0 of the byte has been completed, then driver will reject the previous bits and have reset the interface such that it will be ready to receive the same byte re-transmitted when the chip select line (CSX) is next activated. See the following example
If 1, 2 or more parameter commands are being sent and a break occurs while sending any parameter before the last one and if the host then sends a new command rather than re-transmitting the parameter that was interrupted, then the parameters that were successfully sent are stored and the parameter where the break occurred is rejected. The interface is ready to receive next byte as shown below.
Host (MCU to driver)
Fig. 9.4.1 Serial bus protocol, write mode interrupted by RESX
Fig. 9.4.2 Serial bus protocol, write mode interrupted by CSX
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Fig. 9.4.3 Write interrupts recovery (serial interface) If a 2 or more parameter commands are being sent and a break occurs by the other command before the last one is sent, then the parameters that were successfully sent are stored and the other parameter of that command remains previous value.
Fig. 9.4.4 Write interrupts recovery (both serial and parallel Interface)
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9.5 Data transfer pause
It will be possible when transferring a command, frame memory data or multiple parameter data to invoke a pause in the data transmission. If the chip select line is released after a whole byte of a frame memory data or multiple parameter data has been completed, then driver will wait and continue the frame memory data or parameter data transmission from the point where it was paused. If the chip select Line is released after a whole byte of a command has been completed, then the display module will receive either the commands parameters (if appropriate) or a new command when the chip select line is next enabled as shown below. This applies to the following 4 conditions: 1) Command-Pause-Command 2) Command-Pause-Parameter 3) Parameter-Pause-Command 4) Parameter-Pause-Parameter
9.5.1
Serial interface pause
Fig. 9.5.1 Serial interface pause protocol (pause by CSX)
9.5.2
Parallel interface pause
Fig. 9.5.2 Parallel bus pause protocol (paused by CSX)
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9.6 Data Transfer Modes
The module has three kinds color modes for transferring data to the display RAM. These are 12-bit color per pixel, 16-bit color per pixel and 18-bit color per pixel. The data format is described for each interface. Data can be downloaded to the frame memory by 2 methods.
9.6.1
Method 1
The image data is sent to the frame memory in successive frame writes, each time the frame memory is filled, the frame memory pointer is reset to the start point and the next frame is written.
9.6.2
Method 2
The image data is sent and at the end of each frame memory download, a command is sent to stop frame memory write. Then start memory write command is sent, and a new frame is downloaded.
Note 1: These apply to all data transfer Color modes on both serial and parallel interfaces. Note 2: The frame memory can contain both odd and even number of pixels for both methods. Only complete pixel data will be stored in the frame memory.
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9.7 Data Color Coding 9.7.1 8-bit Parallel Interface (IM2, IM1, IM0= 100)
Different display data formats are available for three Colors depth supported by listed below. - 4k colors, RGB 4,4,4-bit input. - 65k colors, RGB 5,6,5-bit input. - 262k colors, RGB 6,6,6-bit input.
9.7.2
8-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH= 03h
RESX IM[2:0] CSX 1 100
D/CX
WRX 1 8080-series control pins 0 0 1 0 1 1 0 0 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 Pixel n 12 bits B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 Pixel n+1 12 bits G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0
RDX D7 D6 D5 D4 D3 D2 D1 D0
Look-up table for 4096 color data mapping (12 bits to 18 bits)
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data. Note 2: 3-time transfer is used to transmit 1 pixel data with the 12-bit color depth information. Note 3: - = Don't care - Can be set to '0' or '1'
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9.7.3 8-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH= 05h
There is 1 pixel (3 sub-pixels) per 2-byte
RESX
1 100
IM[2:0] CSX D/CX
WRX RDX D7 D6 D5 D4 D3 D2 D1 D0
1 8080-series control pins 0 0 1 0 1 1 0 0 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 Pixel n 16 bits 16 bits G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 Pixel n+1 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0
Look-up table for 65k color data mapping (16 bits to 18 bits)
18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green and MSB=Bit 4, LSB=Bit 0 for Red and Blue data. Note 2: 2-times transfer is used to transmit 1 pixel data with the 16-bit color depth information. Note 3: - = Don't care - Can be set to '0' or '1'
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RESX IM[2:0] CSX D/CX
1 100
There is 1 pixel (3 sub-pixels) per 3-bytes.
WRX RDX D7 D6 D5 D4 D3 D2 D1 D0
1 8080-series control pins 0 0 1 0 1 1 0 0 R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 Pixel n 18 bits B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 Pixel n+1 18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: - = Don't care - Can be set to '0' or '1'
V1.9
40
2010-01-19
ST7735
9.7.5 16-Bit Parallel Interface (IM2,IM1, IM0= 101)
Different display data formats are available for three colors depth supported by listed below. - 4k colors, RGB 4,4,4-bit input - 65k colors, RGB 5,6,5-bit input - 262k colors, RGB 6,6,6-bit input
9.7.6
16-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH= 03h
RESX
1 101
There is 1 pixel (3 sub-pixels) per 1 byte
IM[2:0] CSX D/CX WRX RDX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 8080-series control pins 0 0 1 0 1 1 0 0 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 Pixel n 12 bits R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 Pixel n+1 12 bits R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 B3, Bit 3 B3, Bit 2 B3, Bit 1 B3, Bit 0 Pixel n+2 R4, Bit 3 R4, Bit 2 R4, Bit 1 R4, Bit 0 G4, Bit 3 G4, Bit 2 G4, Bit 1 G4, Bit 0 B4, Bit 3 B4, Bit 2 B4, Bit 1 B4, Bit 0 Pixel n+3
Look-up table for 4096 color data mapping (12 bits to 18 bits)
18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data. Note 2: 1-times transfer (D11 to D0) is used to transmit 1 pixel data with the 12-bit color depth information.
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1 101
RESX
1 8080-series control pins R1, Bit 4 0 0 1 0 1 1 0 0 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 Pixel n 16 bits R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 Pixel n+1 16 bits R3, Bit 4 R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 5 G3, Bit 4 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 B3, Bit 4 B3, Bit 3 B3, Bit 2 B3, Bit 1 B3, Bit 0 Pixel n+2 R4, Bit 4 R4, Bit 3 R4, Bit 2 R4, Bit 1 R4, Bit 0 G4, Bit 5 G4, Bit 4 G4, Bit 3 G4, Bit 2 G4, Bit 1 G4, Bit 0 B4, Bit 4 B4, Bit 3 B4, Bit 2 B4, Bit 1 B4, Bit 0 Pixel n+3
18 bits
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for Red and Blue data. Note 2: 1-times transfer (D15 to D0) is used to transmit 1 pixel data with the 16-bit color depth information. Note 3: - = Don't care - Can be set to '0' or '1'
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2010-01-19
ST7735
There are 2 pixels (6 sub-pixels) per 3 bytes
RESX
1 101
1 8080-series control pins 0 0 1 0 1 1 0 0 R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 Pixel n 18 bits B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 Pixel n+1 18 bits G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 5 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 R3, Bit 5 R3, Bit 4 R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 5 G3, Bit 4 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 -
Frame memory
R1
G1
B1
R2
G2
B2
R3
G3
B3
Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: - = Don't care - Can be set to '0' or '1'
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43
2010-01-19
ST7735
9.7.9 9-Bit Parallel Interface (IM2, IM1, IM0=110)
Different display data formats are available for three colors depth supported by listed below. -262k colors, RGB 6,6,6-bit input
9.7.10 Write 9-bit data for RGB 6-6-6-bit input (262k-color)

There is 1 pixel (6 sub-pixels) per 3 bytes
RESX
1 110
IM[2:0] CSX D/CX WRX RDX D8 D7 D6 D5 D4 D3 D2 D1 D0
8080-series control pins 0 0 1 0 1 1 0 0 R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 Pixel n 18 bits G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 Pixel n+1 18 bits G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 5 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D8, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: - = Don't care - Can be set to '0' or '1'
V1.9
44
2010-01-19
ST7735
9.7.11 18-Bit Parallel Interface (IM2, IM1, IM0=111)
Different display data formats are available for three colors depth supported by listed below. - 4k colors, RGB 4,4,4-bit input - 65k colors, RGB 5,6,5-bit input - 262k colors, RGB 6,6,6-bit input.
9.7.12 18-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=03h
RESX IM [2:0] C SX 1 111
D /CX
W RX 1 8080-series control pins 0 0 1 0 1 1 0 0 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 Pixel n 12 bits R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 Pixel n+1 12 bits R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 B3, Bit 3 B3, Bit 2 B3, Bit 1 B3, Bit 0 Pixel n+2 R4, Bit 3 R4, Bit 2 R4, Bit 1 R4, Bit 0 G4, Bit 3 G4, Bit 2 G4, Bit 1 G4, Bit 0 B4, Bit 3 B4, Bit 2 B4, Bit 1 B4, Bit 0 Pixel n+3
R DX
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Look-Up Table for 4096 Color data m apping (12 bits to 18 bits)
18 bits
Fram e m em ory R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data. Note 2: 1-times transfer is used to transmit 1 pixel data with the 12-bit color depth information.
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RESX
1 111
IM[2:0] CSX D/CX WRX RDX D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 8080-series control pins 0 0 1 0 1 1 0 0 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 Pixel n 16 bits R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 Pixel n+1 16 bits R3, Bit 4 R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 5 G3, Bit 4 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 B3, Bit 4 B3, Bit 3 B3, Bit 2 B3, Bit 1 B3, Bit 0 Pixel n+2 R4, Bit 4 R4, Bit 3 R4, Bit 2 R4, Bit 1 R4, Bit 0 G4, Bit 5 G4, Bit 4 G4, Bit 3 G4, Bit 2 G4, Bit 1 G4, Bit 0 B4, Bit 4 B4, Bit 3 B4, Bit 2 B4, Bit 1 B4, Bit 0 Pixel n+3
18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for Red and Blue data. Note 2: 1-time transfer is used to transmit 1 pixel data with the 16-bit color depth information.
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46
2010-01-19
ST7735
RESX
1 111
IM[2:0] CSX D/CX WRX RDX D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 8080-series control pins 0 0 1 0 1 1 0 0 R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 Pixel n 18 bits R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 5 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 Pixel n+1 18 bits R3, Bit 5 R3, Bit 4 R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 5 G3, Bit 4 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 B3, Bit 5 B3, Bit 4 B3, Bit 3 B3, Bit 2 B3, Bit 1 B3, Bit 0 Pixel n+2 R4, Bit 5 R4, Bit 4 R4, Bit 3 R4, Bit 2 R4, Bit 1 R4, Bit 0 G4, Bit 5 G4, Bit 4 G4, Bit 3 G4, Bit 2 G4, Bit 1 G4, Bit 0 B4, Bit 5 B4, Bit 4 B4, Bit 3 B4, Bit 2 B4, Bit 1 B4, Bit 0 Pixel n+3
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Read, Green and Blue data. Note 2: 1-times transfer (D17o D0) is used to transmit 1 pixel data with the 18-bit color depth information.
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47
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9.7.15 3-line serial Interface
Different display data formats are available for three colors depth supported by the LCM listed below. 4k colors, RGB 4-4-4-bit input 65k colors, RGB 5-6-5-bit input 262k colors, RGB 6-6-6-bit input
9.7.16 Write data for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=03h
Note 1: Pixel data with the 12-bit color depth information Note 2: The most significant bits are: Rx3, Gx3 and Bx3 Note 3: The least significant bits are: Rx0, Gx0 and Bx0
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48
2010-01-19
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49
2010-01-19
ST7735
V1.9
50
2010-01-19
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9.7.19 4-line serial Interface
Different display data formats are available for three colors depth supported by the LCM listed below. 4k colors, RGB 4-4-4-bit input 65k colors, RGB 5-6-5-bit input 262k colors, RGB 6-6-6-bit input
V1.9
51
2010-01-19
ST7735
V1.9
52
2010-01-19
ST7735
V1.9
53
2010-01-19
ST7735
9.8 Display Data RAM 9.8.1 Configuration (GM[2:0] = 000)
The display module has an integrated 132x162x18-bit graphic type static RAM. This 384,912-bit memory allows storing on-chip a 132xRGBx162 image with an 18-bpp resolution (262K-color). There will be no abnormal visible effect on the display when there is a simultaneous Panel Read and Interface Read or Write to the same location of the Frame Memory.
Fig. 9.8.1 Display data RAM organization
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9.8.2 Memory to Display Address Mapping 9.8.2.1 When using 128RGB x 160 resolution (GM[2:0] = 011, SMX=SMY=SRGB= 0)
Pixel 1
Pixel 2
--------
Pixel 127
Pixel 128
Gate Out
Source Out
S7 RGB=0
S8
S9 RGB=1
S10 RGB=0
S11
S12 -------- S385 S386 S387 S388 S389 S390 RGB=1 RGB=0 RGB=1 RGB=0 SA ML=' 0 ' ML=' 1 ' -------- R126 G126 B126 R127 G127 B127 0 159 -------1 158 -------2 157 -------3 156 -------4 155 -------5 154 -------6 153 -------7 152 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -------152 7 -------153 6 -------154 5 -------155 4 -------156 3 -------157 2 -------158 1 -------159 0 126 127 -------1 0 -------RGB Order RGB=1
2 3 4 5 6 7 8 9 | | | | | 154 155 156 157 158 159 160 161
RA MY=' 0 ' MY=' 1 ' 0 159 R0 1 158 2 157 3 156 4 155 5 154 6 153 7 152 | | | | | | | | | | | | | | | 152 7 153 6 154 5 155 4 156 3 157 2 158 1 159 0 MX=' 0 ' CA MX=' 1 '
G0
B0
R1
G1
B1
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
0 127
1 126
Note RA = Row Address, CA = Column Address SA = Scan Address MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command ML = Scan direction parameter, D4 parameter of MADCTL command RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command
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9.8.2.2 When using 132RGB x 162 resolution (GM[2:0] = 000, SMX=SMY=SRGB= 0)
Pixel 1 Pixel 2 -------Pixel 131 Pixel 132
Gate Out
Source Out
S1 RGB=0
S2
S3 RGB=1
S4 RGB=0
S5
S6 RGB=1
-------- S391 S392 S393 S394 S395 S396 RGB=0 RGB=1 RGB=0 SA ML=' 0 ' ML=' 1 ' -------- R131 G131 B131 R132 G132 B132 0 161 -------1 160 -------2 159 -------3 158 -------4 157 -------5 156 -------6 155 -------7 154 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -------154 7 -------155 6 -------156 5 -------157 4 -------158 3 -------159 2 -------160 1 -------161 0 130 131 -------1 0 -------RGB Order RGB=1
1 2 3 4 5 6 7 8 | | | | | 155 156 157 158 159 160 161 162
RA MY=' 0 ' MY=' 1 ' 0 161 R0 1 160 2 159 3 158 4 157 5 156 6 155 7 154 | | | | | | | | | | | | | | | 154 7 155 6 156 5 157 4 158 3 159 2 160 1 161 0 MX=' 0 ' CA MX=' 1 '
G0
B0
R1
G1
B1
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
0 131
1 130
Note RA = Row Address, CA = Column Address SA = Scan Address MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command ML = Scan direction parameter, D4 parameter of MADCTL command RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command
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2010-01-19
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9.8.3 Normal Display On or Partial Mode On 9.8.3.1 When using 128RGB x 160 resolution (GM[2:0] = 011)
In this mode, the content of the frame memory within an area where column pointer is 00h to 7Fh and page pointer is 00h to 9Fh is displayed. To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0). 1). Example for Normal Display On (MX=MY=ML=0, SMX=SMY=0) 128 Columns
00h 00 10 20 30 40 50 60 01h ---- ---- 76h 77h ---- 7Fh 83h 01 0Y 0Z 11 1Y 1Z 21 2Y 2Z 31 3Y 3Z 41 4Y 4Z 51 5Y 5Z 6Z 128 x 160 x18bit Fram e RAM
Scan Order
1 2 3 | | | | | | | | | | 158 159 160
128 Columns
00h 01h 02h | | | | | | | | | | | 9Eh 9Fh A0h A1h
00 10 20 30 40 50 60
01 11 21 31 41 51
02 12 22 32 42
03 13
0W 0X 0Y 1W 1X 1Y 2X 2Y 3X 3Y 4X 4Y 5Y
0Z 1Z 2Z 3Z 4Z 5Z 6Z
128RGB x 160 LCD Panel S0 U0 V0 W0 X0 Y0 Z0 SZ UZ VZ WZ XZ YZ ZZ
X0 X1 X2 XX XY XZ Y0 Y1 Y2 Y3 YW YX YY YZ Z0 Z1 Z2 Z3 ZW ZX ZY ZZ
U1 V1 W1 X1 Y1 Z1
V2 W2 X2 Y2 Y3 Z2 Z3
VX WX XX YW YX ZW ZX
UY VY WY XY YY ZY
G2 G3 G4 | | | | | | | | | | | | G159 G160 G161
Display area =160 lines
2). Example for Partial Display On (PSL[7:0]=04h,PEL[7:0]=9Bh, MX=MV=ML=0 ,SMX=SMY=0)
V1.9
160 Lines 160 Lines
128 Columns
00h 00 10 20 30 40 50 60 01h ---- ---- 76h 77h ---- 7Fh 83h 01 0Y 0Z 11 1Y 1Z 21 2Y 2Z 31 3Y 3Z 41 4Y 4Z 51 5Y 5Z 6Z 128 x 160 x18bit Fram e RAM U1 V1 VX W1 W2 WX X1 X2 XX Y1 Y2 Y3 YW YX Z1 Z2 Z3 ZW ZX
Scan Order
1 2 3 | | | | | | | | | | 158 159 160
128 Columns
00h 01h 02h | | | | | | | | | | | 9Eh 9Fh A0h A1h
00 10 20 30 40 50 60
01 11 21 31 41 51
02 12 22 32 42
03 13
0W 0X 0Y 1W 1X 1Y 2X 2Y 3X 3Y 4X 4Y 5Y
0Z 1Z 2Z 3Z 4Z 5Z 6Z
U0 V0 W0 X0 Y0 Z0
UY VY WY XY YY ZY
UZ VZ WZ XZ YZ ZZ
U1 V1 W1 X1 Y1 Z1
V2 W2 X2 Y2 Y3 Z2 Z3
UY VY WY XY YY ZY
G2 G3 G4 | | | | | | | | | | | | G159 G160 G161
Non-Display area =4 lines
Non-Display area =4 lines
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9.8.3.2 When using 132RGB x 162 resolution (GM[2:0] = 000)
In this mode, contents of the frame memory within an area where column pointer is 00h to 83h and page pointer is 00h to A1h is displayed. To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0) 1). Example for Normal Display On (MX=MY=ML=0, SMX=SMY=0) 132 Columns Scan Order
83h 0Z 1Z 2Z 3Z 4Z 5Z 6Z
132 Columns
00h 01h 02h | | | | | | | | | | 9Dh 9Eh 9Fh A0h A1h
00h 00 10 20 30 40 50 60
01h 01 11 21 31 41 51
---- ---- ---- ---- ---- 81h 02 03 0W 0X 0Y 12 13 1W 1X 1Y 22 2X 2Y 32 3X 3Y 42 4X 4Y 5Y
132 x 162 x18 bit Fram e RAM S0 U0 V0 W0 X0 Y0 Z0 SZ UZ VZ WZ XZ YZ ZZ
U1 V1 W1 X1 Y1 Z1
V2 W2 X2 Y2 Y3 Z2 Z3
UY VY WY XY YY ZY
1 2 3 | | | | | | | | | | | | 160 161 162
00 10 20 30 40 50 60
01 11 21 31 41 51
02 12 22 32 42
03 13
0W 0X 0Y 1W 1X 1Y 2X 2Y 3X 3Y 4X 4Y 5Y
0Z 1Z 2Z 3Z 4Z 5Z 6Z
U1 V1 W1 X1 Y1 Z1
V2 W2 X2 Y2 Y3 Z2 Z3
UY VY WY XY YY ZY
G1 G2 G3 | | | | | | | | | | | | G160 G161 G162
Non-Displa y area =4 lines
2). Example for Partial Display On (PSL[7:0]=04h,PEL[7:0]=9Dh, MX=MV=ML=0 ,SMX=SMY=0) 132 Columns Scan Order
83h 0Z 1Z 2Z 3Z 4Z 5Z 6Z
162 Lines
Non-Displa y area =4lines
132 Columns
00h 01h 02h | | | | | | | | | | | | 9Fh A0h A1h
00h 00 10 20 30 40 50 60
01h 01 11 21 31 41 51
---- ---- ---- ---- ---- 81h 02 03 0W 0X 0Y 12 13 1W 1X 1Y 22 2X 2Y 32 3X 3Y 42 4X 4Y 5Y
132 x 162 x18 bit Fram e RAM S0 U0 V0 W0 X0 Y0 Z0 SZ UZ VZ WZ XZ YZ ZZ
U1 V1 W1 X1 Y1 Z1
V2 W2 X2 Y2 Y3 Z2 Z3
UY VY WY XY YY ZY
1 2 3 | | | | | | | | | | | | 160 161 162
00 10 20 30 40 50 60
01 11 21 31 41 51
02 03 12 13 22 32 42
0W 0X 0Y 1W 1X 1Y 2X 2Y 3X 3Y 4X 4Y 5Y
0Z 1Z 2Z 3Z 4Z 5Z 6Z
132R G B x 162
LCD Panel
S0 U0 V0 W0 X0 Y0 Z0 SZ UZ VZ WZ XZ YZ ZZ
U1 V1 W1 X1 Y1 Z1
V2 W2 X2 Y2 Y3 Z2 Z3
UY VY WY XY YY ZY
G1 G2 G3 | | | | | | | | | | | | G160 G161 G162
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162 Lines
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9.9 Address Counter
The address counter sets the addresses of the display data RAM for writing and reading. Data is written pixel-wise into the RAM matrix of DRIVER. The data for one pixel or two pixels is collected (RGB 6-6-6-bit), according to the data formats. As soon as this pixel-data information is complete the Write access is activated on the RAM. The locations of RAM are addressed by the address pointers. The address ranges are X=0 to X=131 (83h) and Y=0 to Y=161 (A1h). Addresses outside these ranges are not allowed. Before writing to the RAM, a window must be defined that will be written. The window is programmable via the command registers XS, YS designating the start address and XE, YE designating the end address. For example the whole display contents will be written, the window is defined by the following values: XS=0 (0h) YS=0 (0h) and XE=127 (83h), YE=161 (A1h). In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps around to YS and X increments to address the next column. In horizontal addressing mode (V=0), the X-address increments after each byte, after the last X-address (X=XE), X wraps around to XS and Y increments to address the next row. After the every last address (X=XE and Y=YE) the address pointers wrap around to address (X=XS and Y=YS). For flexibility in handling a wide variety of display architectures, the commands CASET, RASET and MADCTL (see section 10 command list), define flags MX and MY, which allows mirroring of the X-address and Y-address. All combinations of flags are allowed. Section 9.10 show the available combinations of writing to the display RAM. When MX, MY and MV will be changed the data bust be rewritten to the display RAM. For each image condition, the controls for the column and row counters apply as section 9.10 below
Condition When RAMWR/RAMRD command is accepted Complete Pixel Read / Write action The Column counter value is larger than End Column (XE) The Column counter value is larger than End Column (XE) and the Row counter value is larger than End Row (YE) Column Counter Return to Start Column (XS) Increment by 1 Return to Start Column (XS) Return to Start Column (XS) Row Counter Return to Start Row (YS) No change Increment by 1 Return to Start Row (YS)
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9.10 Memory Data Write/ Read Direction
The data is written in the order illustrated above. The Counter which dictates where in the physical memory the data is to be written is controlled by Memory Data Access Control Command, bits B5 (MV), B6 (MX), B7 (MY) as described below.
Panel
Fig. 9.10.1 Data streaming order
9.10.1 When 128RGBx160 (GM= 011)

MV 0 0 0 0 1 1 1 1 MX 0 0 1 1 0 0 1 1 MY 0 1 0 1 0 1 0 1 CASET Direct to Physical Column Pointer Direct to Physical Column Pointer Direct to (127-Physical Column Pointer) Direct to (127-Physical Column Pointer) Direct to Physical Row Pointer Direct to (159-Physical Row Pointer) Direct to Physical Row Pointer Direct to (159-Physical Row Pointer) RASET Direct to Physical Row Pointer Direct to (159-Physical Row Pointer) Direct to Physical Row Pointer Direct to (159-Physical Row Pointer) Direct to Physical Column Pointer Direct to Physical Column Pointer Direct to (127-Physical Column Pointer) Direct to (127-Physical Column Pointer)
9.10.2 When 132RGBx162 (GM= 000)

MV 0 0 0 0 1 1 1 1 MX 0 0 1 1 0 0 1 1 MY 0 1 0 1 0 1 0 1 CASET Direct to Physical Column Pointer Direct to Physical Column Pointer Direct to (131-Physical Column Pointer) Direct to (131-Physical Column Pointer) Direct to Physical Row Pointer Direct to (161-Physical Row Pointer) Direct to Physical Row Pointer Direct to (161-Physical Row Pointer) RASET Direct to Physical Row Pointer Direct to (161-Physical Row Pointer) Direct to Physical Row Pointer Direct to (161-Physical Row Pointer) Direct to Physical Column Pointer Direct to Physical Column Pointer Direct to (131-Physical Column Pointer) Direct to (131-Physical Column Pointer)
Note: Data is always written to the Frame Memory in the same order, regardless of the Memory Write Direction set by MADCTL bits B7 (MY), B6 (MX), B5 (MV). The write order for each pixel unit is
One pixel unit represents 1 column and 1page counter value on the Frame Memory.
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9.10.3 Frame Data Write Direction According to the MADCTL parameters (MV, MX and MY)
Display Data Direction Normal MADCTL Parameter MV MX 0 0 Image in the Host (MPU) Image in the Driver (DDRAM) MY 0
Y-Mirror
X-Mirror
X-Mirror Y-Mirror
X-Y Exchange
X-Y Exchange Y-Mirror
X-Y Exchange X-Mirror
X-Y Exchange X-Mirror Y-Mirror
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9.11 Tearing Effect Output Line
The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal can be enabled or disabled by the Tearing Effect Line Off & On commands. The mode of the Tearing Effect signal is defined by the parameter of the Tearing Effect Line On command. The signal can be used by the MPU to synchronize Frame Memory Writing when displaying video images.
9.11.1 Tearing Effect Line Modes

Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only:
tvdh= The LCD display is not updated from the Frame Memory tvdl= The LCD display is updated from the Frame Memory (except Invisible Line see above)
Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking Information, there is one V-sync and 162 H-sync pulses per field.
thdh= The LCD display is not updated from the Frame Memory thdl= The LCD display is updated from the Frame Memory (except Invisible Line see above)
Note: During Sleep In Mode, the Tearing Output Pin is active Low.
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9.11.2 Tearing Effect Line Timings
The Tearing Effect signal is described below:
Table 9.11.1 AC characteristics of Tearing Effect Signal Idle Mode Off (Frame Rate = 60 Hz, Ta=25 C)
Symbol tvdl tvdh thdl thdh Parameter Vertical Timing Low Duration Vertical Timing High Duration Horizontal Timing Low Duration Horizontal Timing Low Duration min 13 1000 33 25 max 500 unit ms s s s description
Note: The timings in Table 9.10.1 apply when MADCTL ML=0 and ML=1
The signals rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.
The Tearing Effect Output Line is fed back to the MPU and should be used as shown below to avoid Tearing Effect:
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9.11.3 Example 1: MPU Write is faster than panel read
Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the vertical sync pulse of the Tearing Effect Output Line. This ensures that data is always written ahead of the panel scan and each Panel Frame refresh has a complete new image:
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9.11.4 Example 2: MPU write is slower than panel read
The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync pulse of the Tearing Effect Output Line. This allows time for the image to download behind the Panel Read pointer and finishing download during the subsequent Frame before the Read Pointer catches the MPU to Frame memory write position.
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9.12 Power ON/OFF Sequence
VDD must be powered on before the VDDI. VDDI must be powered off before the VDD. During power off, if LCD is in the Sleep Out mode, VDD and VDDI must be powered down minimum 120msec after RESX has been released. During power off, if LCD is in the Sleep In mode, VDDI or VDD can be powered down minimum 0msec after RESX has been released. CSX can be applied at any timing or can be permanently grounded. RESX has priority over CSX.
Note 1: There will be no damage to the display module if the power sequences are not met. Note 2: There will be no abnormal visible effects on the display panel during the Power On/Off Sequences. Note 3: There will be no abnormal visible effects on the display between end of Power On Sequence and before receiving Sleep Out command. Also between receiving Sleep In command and Power Off Sequence. Note 4: If RESX line is not held stable by host during Power On Sequence as defined in the sequence below, then it will be necessary to apply a Hardware Reset (RESX) after Host Power On Sequence is complete to ensure correct operation. Otherwise function is not guaranteed.
The power on/off sequence is illustrated below
TrPW 0ns VDD VDDI
TfPW 0ns
Timing when the latter signal rises up to 90% of its typical value. e.g. When VDD comes later, this timing is defined at the cross point of 90% of 2.75V, not 90% of 2.6V. Timing when the latter signal falls up to 90% of its typical value. e.g. When VDD comes later, this timing is defined at the cross point of 90% of 2.75V, not 90% of 2.6V.
TrPW-CSX = +/- no limit CSX H or L TrPW-RESX = + no limit RESX (Power down in sleep-out mode) RESX (Power down in sleep-in mode)
TfPW-CSX = +/- no limit
30%
TfPW-RESX1 = min 120ms TrPW-RESX = + no limit TfPW-RESX2 = min 0ms
30%
TfPW-RESx1 is applied to RESX falling in the Sleep Out Mode. TfPW-RESx2 is applied to RESX falling in the Sleep In Mode.
9.12.1 Uncontrolled Power Off

The uncontrolled power-off means a situation which removed a battery without the controlled power off sequence. It will neither damage the module or the host interface. If uncontrolled power-off happened, the display will go blank and there will not any visible effect on the display (blank display) and remains blank until Power On Sequence powers it up.
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9.13 Power Level Definition 9.13.1 Power Level
6 level modes are defined they are in order of Maximum Power consumption to Minimum Power Consumption 1. Normal Mode On (full display), Idle Mode Off, Sleep Out. In this mode, the display is able to show maximum 262,144 colors. 2. Partial Mode On, Idle Mode Off, Sleep Out. In this mode part of the display is used with maximum 262,144 colors. 3. Normal Mode On (full display), Idle Mode On, Sleep Out. In this mode, the full display area is used but with 8 colors. 4. Partial Mode On, Idle Mode On, Sleep Out. In this mode, part of the display is used but with 8 colors. 5. Sleep In Mode In this mode, the DC: DC converter, internal oscillator and panel driver circuit are stopped. Only the MCU interface and memory works with VDDI power supply. Contents of the memory are safe. 6. Power Off Mode In this mode, both VDD and VDDI are removed.
Note: Transition between modes 1-5 is controllable by MCU commands. Mode 6 is entered only when both Power supplies are removed.
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9.13.2 Power Flow Chart
Normal display mode on = NOR ON Partial display mode on = PTL ON Idle mode off = IDM OFF Idle mode on = IDM ON Sleep out = SLP OUT Sleep in = SLP IN NOR ON PTL ON Sleep out Normal display mode on Idle mode off IDM OFF IDM ON SLP IN SLP OUT IDM OFF SLP IN SLP OUT Power on sequence HW reset SW reset
Sleep in Normal display mode on Idle mode off
NOR ON PTL ON
IDM ON
Sleep out Normal display mode on Idle mode on
Sleep in Normal display mode on Idle mode on
Sleep out Partial display mode on Idle mode off IDM ON IDM OFF
SLP IN SLP OUT
Sleep in Partial display mode on Idle mode off IDM ON IDM OFF
PTL ON NOR ON
Sleep out Partial display mode on Idle mode on
SLP IN SLP OUT
Sleep in Partial display mode on Idle mode on
PTL ON NOR ON
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9.14 Reset Table 9.14.1 Reset Table (Default Value, GM[2:0]=011, 128RGB x 160)
Item Frame memory Sleep In/Out Display On/Off Display mode (normal/partial) Display Inversion On/Off Display Idle Mode On/Off Column: Start Address (XS) Column: End Address (XE) Row: Start Address (YS) Row: End Address (YE) Gamma setting RGB for 4k and 65k Color Mode Partial: Start Address (PSL) Partial: End Address (PEL) Tearing: On/Off Tearing Effect Mode (*1) Memory Data Access Control (MY/MX/MV/ML/RGB) Interface Pixel Color Format RDDPM RDDMADCTL RDDCOLMOD RDDIM RDDSM RDDSDR ID2 ID3 After Power On Random In Off Normal Off Off 0000h 007Fh 0000h 009Fh GC0 See Section 9.17 0000h 009Fh Off 0 (Mode1) 0/0/0/0/0 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h NV value NV value After H/W Reset No Change In Off Normal Off Off 0000h 007Fh 0000h 009Fh GC0 See Section 9.17 0000h 009Fh Off 0 (Mode1) 0/0/0/0/0 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h NV value NV value After S/W Reset No Change In Off Normal Off Off 0000h 007Fh (127d) (when MV=0) 009Fh (159d) (when MV=1) 0000h 009Fh (159d) (when MV=0) 007Fh (127d) (when MV=1) GC0 No Change 0000h 009Fh Off 0 (Mode1) No Change No Change 08h No Change No Change 00h 00h 00h NV value NV value
Note: TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only
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9.14.2 Reset Table (GM[2:0]= 000, 132RGB x 162)
Item Frame memory Sleep In/Out Display On/Off Display mode (normal/partial) Display Inversion On/Off Display Idle Mode On/Off Column: Start Address (XS) Column: End Address (XE) Row: Start Address (YS) Row: End Address (YE) Gamma setting RGB for 4k and 65k Color Mode Partial: Start Address (PSL) Partial: End Address (PEL) Tearing: On/Off Tearing Effect Mode (*1) Memory Data Access Control (MY/MX/MV/ML/RGB) Interface Pixel Color Format RDDPM RDDMADCTL RDDCOLMOD RDDIM RDDSM RDDSDR ID2 ID3 After Power On Random In Off Normal Off Off 0000h 0083h 0000h 00A1h GC0 See Section 9.17 0000h 00A1h Off 0 (Mode1) 0/0/0/0/0 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h NV value NV value After H/W Reset No Change In Off Normal Off Off 0000h 0083h 0000h 00A1h GC0 See Section 9.17 0000h 00A1h Off 0 (Mode1) 0/0/0/0/0 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h NV value NV value After S/W Reset No Change In Off Normal Off Off 0000h 0083h (131d) (when MV=0) 00A1h (161d) (when MV=1) 0000h 00A1h (161d) (when MV=0) 0083h (131d) (when MV=1) GC0 No Change 0000h 00A1h Off 0 (Mode1) No Change No Change 08h No Change No Change 00h 00h 00h NV value NV value
Note: TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only
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9.15 Module Input/Output Pins 9.15.1 Output or Bi-directional (I/O) Pins
Output or Bi-directional pins TE D7 to D0 (Output driver) After Power On Low High-Z (Inactive) After Hardware Reset Low High-Z (Inactive) After Software Reset Low High-Z (Inactive)
Input pins RESX CSX D/CX WRX RDX D7 to D0
During Power On Process See 9.14 Input invalid Input invalid Input invalid Input invalid Input invalid
After Power On Input valid Input valid Input valid Input valid Input valid Input valid
After Hardware Reset Input valid Input valid Input valid Input valid Input valid Input valid
After Software Reset Input valid Input valid Input valid Input valid Input valid Input valid
During Power Off Process See 9.14 Input invalid Input invalid Input invalid Input invalid Input invalid
Note: There will be no output from D7-D0 during Power On/Off sequence, Hardware Reset and Software Reset.
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9.16 Reset Timing
Table 9.16.1 Reset timing

Related Pins RESX Symbol tRESW tREST Parameter Reset pulse duration Reset cancel MIN 10 MAX 5 120 Unit us ms ms
Notes: 1. The reset cancel includes also required time for loading ID bytes, VCOM setting and other settings from EEPROM (or similar device) to registers. This loading is done every time when there is HW reset cancel time (tRT) within 5 ms after a rising edge of RESX. 2. Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below: RESX Pulse Shorter than 5us Longer than 9us Between 5us and 9us Action Reset Rejected Reset Reset starts
3. During the Resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time is 120 ms, when Reset Starts in Sleep Out mode. The display remains the blank state in Sleep In -mode.) and then return to Default condition for Hardware Reset. 4. Spike Rejection also applies during a valid reset pulse as shown below:
5. When Reset applied during Sleep In Mode. 6. When Reset applied during Sleep Out Mode. 7. It is necessary to wait 5msec after releasing RESX before sending commands. Also Sleep Out command cannot be sent for 120msec.
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9.17 Color Depth Conversion Look Up Tables 9.17.1 65536 Color to 262,144 Color
Color Look Up Table Output Frame Memory Data (6-bits) R005 R004 R003 R002 R001 R000 R015 R014 R013 R012 R011 R010 R025 R024 R023 R022 R021 R020 R035 R034 R033 R032 R031 R030 R045 R044 R043 R042 R041 R040 R055 R054 R053 R052 R051 R050 R065 R064 R063 R062 R061 R060 R075 R074 R073 R072 R071 R070 R085 R084 R083 R082 R081 R080 R095 R094 R093 R092 R091 R090 R105 R104 R103 R102 R101 R100 R115 R114 R113 R112 R111 R110 R125 R124 R123 R122 R121 R120 R135 R134 R133 R132 R131 R130 R145 R144 R143 R142 R141 R140 R155 R154 R153 R152 R151 R150 R165 R164 R163 R162 R161 R160 R175 R174 R173 R172 R171 R170 R185 R184 R183 R182 R181 R180 R195 R194 R193 R192 R191 R190 R205 R204 R203 R202 R201 R200 R215 R214 R213 R212 R211 R210 R225 R224 R223 R222 R221 R220 R235 R234 R233 R232 R231 R230 R245 R244 R243 R242 R241 R240 R255 R254 R253 R252 R251 R250 R265 R264 R263 R262 R261 R260 R275 R274 R273 R272 R271 R270 R285 R284 R283 R282 R281 R280 R295 R294 R293 R292 R291 R290 R305 R304 R303 R302 R301 R300 R315 R314 R313 R312 R311 R310 Look Up Table Output Frame Memory Data (6-bits) G005 G004 G003 G002 G001 G000 G015 G014 G013 G012 G011 G010 G025 G024 G023 G022 G021 G020 G035 G034 G033 G032 G031 G030 G045 G044 G043 G042 G041 G040 G055 G054 G053 G052 G051 G050 G065 G064 G063 G062 G061 G060 G075 G074 G073 G072 G071 G070 G085 G084 G083 G082 G081 G080 G095 G094 G093 G092 G091 G090 G105 G104 G103 G102 G101 G100 G115 G114 G113 G112 G111 G110 G125 G124 G123 G122 G121 G120 G135 G134 G133 G132 G131 G130 G145 G144 G143 G142 G141 G140 G155 G154 G153 G152 G151 G150 G165 G164 G163 G162 G161 G160 G175 G174 G173 G172 G171 G170 G185 G184 G183 G182 G181 G180 G195 G194 G193 G192 G191 G190 G205 G204 G203 G202 G201 G200 Default value after H/W Reset 000000 000010 000100 000110 001000 001010 001100 001110 010000 010010 010100 010110 011000 011010 011100 011110 100001 100011 100101 100111 101001 101011 101101 101111 110001 110011 110101 110111 111001 111011 111101 111111 Default value after H/W Reset 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 RGBSET Parameter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RGBSET Parameter 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Look Up Table Input Data 65k Color (5-bits) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Look Up Table Input Data 65k Color (5-bits) 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100
RED
Color GREEN
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G215 G214 G213 G212 G211 G210 G225 G224 G223 G222 G221 G220 G235 G234 G233 G232 G231 G230 G245 G244 G243 G242 G241 G240 G255 G254 G253 G252 G251 G250 G265 G264 G263 G262 G261 G260 G275 G 274 G273 G272 G271 G270 G285 G 284 G283 G282 G281 G280 G295 G 294 G293 G292 G291 G290 G305 G 304 G303 G302 G301 G300 G315 G 314 G313 G312 G311 G310 G325 G324 G323 G322 G321 G320 G335 G334 G333 G332 G331 G330 G345 G344 G343 G342 G341 G340 G355 G354 G353 G352 G351 G350 G365 G364 G363 G362 G361 G360 G375 G374 G373 G372 G371 G370 G385 G384 G383 G382 G381 G380 G395 G394 G393 G392 G391 G390 G405 G404 G403 G402 G401 G400 G415 G414 G413 G412 G411 G410 G425 G424 G423 G422 G421 G420 G435 G434 G433 G432 G431 G430 G445 G444 G443 G442 G441 G440 G455 G454 G453 G452 G451 G450 G465 G464 G463 G462 G461 G460 G475 G474 G473 G472 G471 G470 G485 G484 G483 G482 G481 G480 G495 G494 G493 G492 G491 G490 G505 G504 G503 G502 G501 G500 G515 G514 G513 G512 G511 G510 G525 G524 G523 G522 G521 G520 G535 G534 G533 G532 G531 G530 G545 G544 G543 G542 G541 G540 G555 G554 G553 G552 G551 G550 G565 G564 G563 G562 G561 G560 G575 G574 G573 G572 G571 G570 G585 G584 G583 G582 G581 G580 G595 G594 G593 G592 G591 G590 G605 G604 G603 G602 G601 G600 G615 G614 G613 G612 G611 G610 G625 G624 G623 G622 G621 G620 G635 G634 G633 G632 G631 G630 Color BLUE Look Up Table Output Frame Memory Data (6-bits) B005 B004 B003 B002 B001 B000 B015 B014 B013 B012 B011 B010 B025 B024 B023 B022 B021 B020 B035 B034 B033 B032 B031 B030 B045 B044 B043 B042 B041 B040 B055 B054 B053 B052 B051 B050 B065 B064 B063 B062 B061 B060 B075 B074 B073 B072 B071 B070 B085 B084 B083 B082 B081 B080 B095 B094 B093 B092 B091 B090 B105 B104 B103 B102 B101 B100 B115 B114 B113 B112 B111 B110 B125 B124 B123 B122 B121 B120 B135 B134 B133 B132 B131 B130 B145 B144 B143 B142 B141 B140 B155 B154 B153 B152 B151 B150 B165 B164 B163 B162 B161 B160 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 Default value after H/W Reset 000000 000010 000100 000110 001000 001010 001100 001110 010000 010010 010100 010110 011000 011010 011100 011110 100001 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 RGBSET Parameter 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 Look Up Table Input Data 65k Color (5-bits) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000
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B175 B174 B173 B172 B171 B170 B185 B184 B183 B182 B181 B180 B195 B194 B193 B192 B191 B190 B205 B204 B203 B202 B201 B200 B215 B214 B213 B212 B211 B210 B225 B224 B223 B222 B221 B220 B235 B234 B233 B232 B231 B230 B245 B244 B243 B242 B241 B240 B255 B254 B253 B252 B251 B250 B265 B264 B263 B262 B261 B260 B275 B274 B273 B272 B271 B270 B285 B284 B283 B282 B281 B280 B295 B294 B293 B292 B291 B290 B305 B304 B303 B302 B301 B300 B315 B314 B313 B312 B311 B310 100011 100101 100111 101001 101011 101101 101111 110001 110011 110101 110111 111001 111011 111101 111111 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
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9.17.2 4096 Color to 262,144 Color
Color Look Up Table Output Frame Memory Data (6-bits) R005 R004 R003 R002 R001 R000 R015 R014 R013 R012 R011 R010 R025 R024 R023 R022 R021 R020 R035 R034 R033 R032 R031 R030 R045 R044 R043 R042 R041 R040 R055 R054 R053 R052 R051 R050 R065 R064 R063 R062 R061 R060 R075 R074 R073 R072 R071 R070 R085 R084 R083 R082 R081 R080 R095 R094 R093 R092 R091 R090 R105 R104 R103 R102 R101 R100 R115 R114 R113 R112 R111 R110 R125 R124 R123 R122 R121 R120 R135 R134 R133 R132 R131 R130 R145 R144 R143 R142 R141 R140 R155 R154 R153 R152 R151 R150 R165 R164 R163 R162 R161 R160 | R315 R314 R313 R312 R311 R310 G005 G004 G003 G002 G001 G000 G015 G014 G013 G012 G011 G010 G025 G024 G023 G022 G021 G020 G035 G034 G033 G032 G031 G030 G045 G044 G043 G042 G041 G040 G055 G054 G053 G052 G051 G050 G065 G064 G063 G062 G061 G060 G075 G074 G073 G072 G071 G070 G085 G084 G083 G082 G081 G080 G095 G094 G093 G092 G091 G090 G105 G104 G103 G102 G101 G100 G115 G114 G113 G112 G111 G110 G125 G124 G123 G122 G121 G120 G135 G134 G133 G132 G131 G130 G145 G144 G143 G142 G141 G140 G155 G154 G153 G152 G151 G150 G165 G164 G163 G162 G161 G160 | G635 G634 G633 G632 G631 G630 B005 B004 B003 B002 B001 B000 B015 B014 B013 B012 B011 B010 B025 B024 B023 B022 B021 B020 B035 B034 B033 B032 B031 B030 B045 B044 B043 B042 B041 B040 B055 B054 B053 B052 B051 B050 B065 B064 B063 B062 B061 B060 B075 B074 B073 B072 B071 B070 B085 B084 B083 B082 B081 B080 B095 B094 B093 B092 B091 B090 B105 B104 B103 B102 B101 B100 B115 B114 B113 B112 B111 B110 B125 B124 B123 B122 B121 B120 B135 B134 B133 B132 B131 B130 B145 B144 B143 B142 B141 B140 B155 B154 B153 B152 B151 B150 B165 B164 B163 B162 B161 B160 | B315 B314 B313 B312 B311 B310 Default value after H/W Reset 000000 000100 001000 001100 010001 010101 011001 011101 100010 100110 101010 101110 110011 110111 111011 111111 -----| -----000000 000100 001000 001100 010001 010101 011001 011101 100010 100110 101010 101110 110011 110111 111011 111111 -----| -----000000 000100 001000 001100 010001 010101 011001 011101 100010 100110 101010 101110 110011 110111 111011 111111 -----| -----RGBSET Parameter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 | 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 | 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 | 128 Look Up Table Input Data 4k Color (4-bits) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Not used 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Not used 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Not used
RED
GREEN
BLUE
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10 Command
10.1 System function Command List and Description
Table 10.1.1 System Function command List (1)
Instruction Refer D/CX WRX RDX D17-8 D7 NOP 10.1.1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 ID17 1 ID37 0 D6 0 0 0 ID16 ID26 ID36 0 D5 0 0 0 ID15 ID25 ID35 0 MX D4 0 0 0 ID14 ID24 ID34 0 MV D3 0 0 0 ID13 ID23 ID33 1 ML D2 0 0 1 ID12 ID22 ID32 0 RGB D1 0 0 0 ID11 ID21 ID31 0 MH D0 0 1 0 ID10 ID20 ID30 1 ST24 Hex Function
(00h) No Operation (01h) Software reset (04h) Read Display ID Dummy read ID1 read ID2 read ID3 read (09h) Read Display Status Dummy read (0Ah) Read Display Power Dummy read (0Bh) Read Display Dummy read (0Ch) Read Display Pixel Dummy read (0Dh) Read Display Image Dummy read (0Eh) Read Display Signal Dummy read -
SWRESET10.1.2 0 0 1 RDDID 10.1.3 1 1 1 0 1 RDDST 10.1.4 1 1 1 1 0 RDDPM 10.1.5 1 1 0 RDD 10.1.6 1 MADCTL 1 0 RDD 10.1.7 1 COLMOD 1 0 RDDIM 10.1.8 1 1 0 RDDSM 10.1.9 1 1
BSTON MY ST23
IFPF2 IFPF1 IFPF0 INVON ST12
IDMON PTLON SLOUT NORON ST11 ST3 1 DISON TEON GCS2 ST2 0 ST1 1 ST0 0 1 0 -
VSSON ST14
GCS1 GCS0 TELOM ST4 0 0 0 0 -
BSTON IDMON PTLON SLPOUT NORON DISON 0 MY 0 0 0 0 MX 0 0 0 0 MV 0 0 0 0 ML 0 0 0 1 RGB 1 1 1 0 MH 1 1 0 -
IFPF2 IFPF1 IFPF0 1 0 1 -
VSSON D6 0 0 -
INVON 0 0 -
GCS2 GCS1 GCS0 1 1 0 -
TEON TELOM -
-: Dont care
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Instruction Refer SLPIN SLPOUT PTLON NORON INVOFF INVON GAMSET DISPOFF DISPON D/C WR 1 1 RDX D171 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D7 0 0 0 0 0 0 0 0 0 0 D6 0 0 0 0 0 0 0 0 0 0 D5 0 0 0 0 1 1 1 1 1 1 D4 1 1 1 1 0 0 0 0 0 0 D3 0 0 0 0 0 0 0 D2 0 0 0 0 0 0 1 D1 0 0 1 1 0 0 1 D0 0 1 0 1 0 1 0 Hex Function
10.1.10 0 10.1.11 0 10.1.12 0 10.1.13 0 10.1.14 0 10.1.15 0 10.1.16 0 1 10.1.17 0 10.1.18 0 0 1
(10h) Sleep in & booster off (11h) Sleep out & booster on (12h) Partial mode on (13h) Partial off (Normal) (20h) Display inversion off (21h) Display inversion on (26h) Gamma curve select (28h) Display off (29h) Display on (2Ah) Column address set X address start: 0XSX
GC3 GC2 GC1 GC0 1 1 1 0 0 0 0 0 1 0 1 0 XS8 XS0 XE8 XE0 1 YS8 YS0 YE8 YE0 0 D0 0 D0
XS15 XS14 XS13 XS12 XS11 XS10 XS9 XS7 XS6 XS5 XS4 XS3 XS2 XS1
CASET
10.1.19 1 1 1 0 1
XE15 XE14 XE13 XE12 XE11 XE10 XE9 XE7 0 XE6 0 XE5 1 XE4 0 XE3 1 XE2 0 XE1 1
X address end: SXEX (2Bh) Row address set Y address start: 0YSY
YS15 YS14 YS13 YS12 YS11 YS10 YS9 YS7 YS6 YS5 YS4 YS3 YS2 YS1
RASET
10.1.20 1 1 1
YE15 YE14 YE13 YE12 YE11 YE10 YE9 YE7 0 D7 0 D7 YE6 0 D6 0 D6 YE5 1 D5 1 D5 YE4 0 D4 0 D4 YE3 1 D3 1 D3 YE2 1 D2 1 D2 YE1 0 D1 1 D1
Y address end:SYEY (2Ch) Memory write Write data (2Eh) Memory read Dummy read Read data
RAMWR
10.1.21
0 1 0
RAMRD
10.1.22 1 1
-: Dont care
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InstructionRefer D/CX WRXRDX D17-8 D7 0 1 PTLAR 10.1.23 1 1 1 TEOFF 10.1.24 0 0 TEON 10.1.25 1 0 1 IDMOFF 10.1.27 0 IDMON 10.1.28 0 0 1 0 RDID1 10.1.30 1 1 0 RDID2 10.1.31 1 1 0 RDID3 10.1.32 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 D6 0 D5 1 D4 1 D3 0 D2 0 D1 0 D0 0 Hex Function (30h) Partial start/end address set Partial start address (0,1,2, ..P)
PSL15PSL14 PSL13 PSL12PSL11 PSL10 PSL9 PSL8 PSL7 PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0 PEL15PEL14 PEL13 PEL12PEL11 PEL10 PEL9 PEL8 PEL7 PEL6 PEL5 PEL4 PEL3 PEL2 PEL1 PEL0 0 0 0 MY 0 0 0 1 0 0 0 MX 0 0 0 1 1 1 1 MV 1 1 1 0 1 1 1 ML 1 1 1 1 0 0 0 1 1 1 0 0 1 0 0 1 0 1 TELOM
Partial end address (0,1,2, .., P) (34h) Tearing effect line off (35h) Tearing effect mode set & on Mode1: TELOM=0 Mode2: TELOM=1
MADCTL 10.1.26
0 0 1 0
(36h) Memory data access control (38h) Idle mode off (39h) Idle mode on (3Ah) Interface pixel format Interface format (DAh) Read ID1 Dummy read Read parameter (DBh) Read ID2 Dummy read Read parameter (DCh) Read ID3 Dummy read Read parameter
RGB MH 1 1 1 1 0 0 0
COLMOD 10.1.29
IFPF2 IFPF1IFPF0 0 1 0 -
ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 1 1 1 1 0 1 1 0 1 1 -
ID26 ID25 ID24 ID23 ID22 ID21 ID20 1 0 1 1 1 0 0 -
ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30
-: Dont care
Note 1: After the H/W reset by RESX pin or S/W reset by SWRESET command, each internal register becomes default state (Refer RESET TABLE section) Note 2: Undefined commands are treated as NOP (00 h) command. Note 3: B0 to D9 and DA to F are for factory use of driver supplier. Note 4: Commands 10h, 12h, 13h, 20h, 21h, 26h, 28h, 29h, 30h, 36h (ML parameter only), 38h and 39h are updated during V-sync when Module is in Sleep Out Mode to avoid abnormal visual effects. During Sleep In mode, these commands are updated immediately. Read status (09h), Read Display Power Mode (0Ah), Read Display MADCTL (0Bh), Read Display Pixel Format (0Ch), Read Display Image Mode (0Dh), Read Display Signal Mode (0Eh).
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10.1.1 NOP (00h)
00H Inst / Para NOP Parameter Description D/CX 0 WRX RDX 1 D17-8 D7 0 D6 0 NOP (No Operation) D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 HEX (00h) -
No Parameter This command is empty command.
- Dont care
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10.1.2 SWRESET (01h): Software Reset
01H Inst / Para SWRESET Parameter D/CX 0 WRX RDX 1 D17-8 D7 0 SWRESET (Software Reset) D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1 HEX (01h) -
No Parameter - Dont care
-If Software Reset is applied during Sleep In mode, it will be necessary to wait 120msec before sending next command. Description -The display module loads all default values to the registers during 120msec. -If Software Reset is applied during Sleep Out or Display On Mode, it will be necessary to wait 120msec before sending next command.
Legend
SWRESET Command
Parameter Display whole blank screen Display
Flow Chart
Set Commands to S/W Default Value
Action
Sleep In Mode Mode
Sequential transter
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10.1.3 RDDID (04h): Read Display ID
04H Inst / Para RDDID 1st parameter 3rd parameter 4th parameter D/CX 0 1 1 1 WRX 1 1 1 1 RDX 1 D17-8 D7 0 ID17 1 ID37 RDDID (Read Display ID) D6 0 ID16 ID26 ID36 D5 0 ID15 ID25 ID35 D4 0 ID14 ID24 ID34 D3 0 ID13 ID23 ID33 D2 1 ID12 ID22 ID32 D1 0 ID11 ID21 ID31 D0 0 ID10 ID20 ID30 HEX (04h) -
2nd parameter 1
-This read byte returns 24-bit display identification information. -The 1st parameter is dummy data -The 2nd parameter (ID17 to ID10): LCD modules manufacturer ID. -The 3rd parameter (ID26 to ID20): LCD module/driver version ID Description -The 4th parameter (ID37 to UD30): LCD module/driver ID. -Commands RDID1/2/3(DAh, DBh, DCh) read data correspond to the parameters 2,3,4 of the command 04h, respectively. - Dont care Default Value ID1 ID2 NV Value NV Value NV Value ID3 NV Value NV Value NV Value
Status Default Power On Sequence S/W Reset H/W Reset
Flow Chart
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10.1.4 RDDST (09h): Read Display Status
09H Inst / Para RDDST D/CX 0 WRX 1 1 1 1 1 RDX 1 D17-8 D7 0 ST23 ST15 GCS1 RDDST (Read Display Status) D6 0 IFPF2 ST14 GCS0 D5 0 MX IFPF1 D4 0 MV IFPF0 D3 1 ML ST11 ST3 D2 0 RGB D1 0 MH D0 1 ST24 GCS2 ST0 HEX (09h) -
1st parameter 1 2nd parameter 1 3rd parameter 1 4th parameter 1 5 parameter 1

th
BSTON MY
IDMON PTLON SLOUT NORON DISON TEON ST2 ST1
INVON ST12 TELOM ST4
This command indicates the current status of the display as described in the table below: Bit BSTON Description Booster Voltage Status Value 1 =Booster on, 0 =Booster off MY Row Address Order (MY) 1 =Decrement, (Bottom to Top, when MADCTL (36h) D7=1) 0 =Increment, (Top to Bottom, when MADCTL (36h) D7=0) MX Column Address Order (MX) 1 =Decrement, (Right to Left, when MADCTL (36h) D6=1) 0 =Increment, (Left to Right, when MADCTL (36h) D6=1) MV Row/Column Exchange (MV) 1 = Row/column exchange, (when MADCTL (36h) D5=1) 0 = Normal, (when MADCTL (36h) D5=0 ML Scan Address Order (ML) 0 =Decrement, (LCD refresh Top to Bottom, when MADCTL (36h) D4=0) 1=Increment, (LCD refresh Bottom to Top, when MADCTL (36h) D4=1) RGB RGB/ BGR Order (RGB) 1 =BGR, (When MADCTL (36h) D3=1) 0 =RGB, (When MADCTL (36h) D3=0) Description MH Horizontal Order 0 =Decrement, (LCD refresh Left to Right, when MADCTL (36h) D2=0) 1 =Increment, (LCD refresh Right to Left, when MADCTL (36h) D2=1) ST24 ST23 IFPF2 Interface Color Pixel Format IFPF1 Definition IFPF0 IDMON PTLON SLPOUT NORON Display Normal Mode On/Off 0 = Partial Display ST15 ST14 INVON ST12 Vertical Scrolling Status (Not Used) Horizontal Scroll Status (Not Used) Inversion Status All Pixels On (Not Used) 1 = Scroll on,0 = Scroll off 0 1 = On, 0 = Off 0 Idle Mode On/Off Partial Mode On/Off Sleep In/Out 110 = 18-bit / pixel, others are no define 1 = On, 0 = Off 1 = On, 0 = Off 1 = Out, 0 = In 1 = Normal Display, 101 = 16-bit / pixel, For Future Use For Future Use 0 0 011 = 12-bit / pixel,
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DISON TEON GCSEL2 GCSEL1 Gamma Curve Selection GCSEL0 Display On/Off Tearing effect line on/off 1 = On, 0 = Off 1 = On, 0 = Off 000 = GC0 001 = GC1 010 = GC2 011 = GC3 100 to 111 = Not defined TELOM ST4 ST3 ST2 ST1 ST0 - Dont care Status Default Value (ST31 to ST0) ST[31-24] ST[23-16] 0110-0001 0xxx-0001 0110-0001 ST[15-8] 0000-0000 0000-0000 0000-0000 ST[7-0] 0000-0000 0000-0000 0000-0000 Tearing effect line mode For Future Use For Future Use For Future Use For Future Use For Future Use 0 = mode1, 1 = mode2 0 0 0 0 0
Default
Power On Sequence S/W Reset H/W Reset
0000-0000 0xxx0xx00 0000-0000
Serial I/F Mode

RDDST 09h
Parallel I/F Mode

RDDST 09h
Legend
Command
Dummy Clock
Dummy Read
Parameter
Display Send 2nd parameter Send 2nd parameter
Flow Chart
Action Send 3rd parameter Send 3rd parameter Mode
Send 4th parameter
Send 4th parameter
Sequential transter
Send 5th parameter
Sendth parameter
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10.1.5 RDDPM (0Ah): Read Display Power Mode
0AH Inst / Para RDDPM D/CX 0 WRX 1 1 RDX 1 D17-8 D7 0 RDDPM (Read Display Power Mode) D6 0 D5 0 D4 0 D3 1 D2 0 D1 1 D0 0 D0 HEX (0Ah) -
1st parameter 1 2nd parameter 1
BSTON IDMON PTLON SLPOUT NORON DISON D1
This command indicates the current status of the display as described in the table below: - Dont care Bit Description Value 1 =Booster on, BSTON Booster Voltage Status 0 =Booster off 1 = Idle Mode On, IDMON Idle Mode On/Off 0 = Idle Mode Off 1 = Partial Mode On, PTLON Description SLPON Sleep In/Out 0 = Sleep In 1 = Normal Display, NORON Display Normal ModemOn/Off 0 = Partial Display 1 = Display On, DISON Display On/Off 0 = Display Off D1 D0 Not Used Not Used 0 0 Partial Mode On/Off 0 = Partial Mode Off 1 = Sleep Out,
Status Power On Sequence Default S/W Reset H/W Reset
Default Value (D7 to D0) 0000_1000(08h) 0000_1000(08h) 0000_1000(08h)
Flow Chart
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10.1.6 RDDMADCTL (0Bh): Read Display MADCTL
0BH Inst / Para RDDMADCTL 1st parameter 2nd parameter D/CX 0 1 1 WRX 1 1 RDX 1 D17-8 0 MY RDDMADCTL (Read Display MADCTL) D7 D6 0 MX D5 0 MV D4 0 ML D3 1 RGB D2 0 MH D1 1 D1 D0 1 D0 HEX (0Bh) -
This command indicates the current status of the display as described in the table below: - Dont care Bit Description Value 1 = Right to Left (When MADCTL B6=1) MX Column Address Order 0 = Left to Right (When MADCTL B6=0) 1 = Bottom to Top (When MADCTL B7=1) MY Row Address Order 0 = Top to Bottom (When MADCTL B7=0) 1 = Row/column exchange (MV=1) MV Row/Column Order (MV) 0 = Normal (MV=0) 1 =LCD Refresh Bottom to Top ML Vertical Refresh Order 0 =LCD Refresh Top to Bottom RGB RGB/BGR Order 1 =BGR, 0=RGB LCD horizontal refresh direction control MH Horizontal Refresh Order 0 = LCD horizontal refresh Left to right 1 = LCD horizontal refresh right to left D1 D0 Status Power On Sequence Not Used Not Used 0 0 Default Value (D7 to D0) 0000_0000 (00h) No change 0000_0000 (00h)
Description
Default
S/W Reset H/W Reset
Flow Chart
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10.1.7 RDDCOLMOD (0Ch): Read Display Pixel Format
0CH Inst / Para RDDCOLMOD 1st parameter 2nd parameter D/CX 0 1 1 WRX 1 1 RDX 1 D17-8 RDDCOLMOD (Read Display Pixel Format) D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 1 D2 1 IFPF2 D1 0 IFPF1 D0 0 IFPF0 HEX (0Ch) -
This command indicates the current status of the display as described in the table below: IFPF[2:0] 011 101 Description 110 111 18-bit/pixel No used MCU Interface Color Format 12-bit/pixel 16-bit/pixel
Others are no define and invalid - Dont care Status Default Value IFPF[2:0] Default Power On Sequence S/W Reset H/W Reset 0110 (18 bits/pixel) No Change 0110 (18 bits/pixel)
Flow Chart
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10.1.8 RDDIM (0Dh): Read Display Image Mode
0DH Inst / Para RDDIM 1st parameter 2nd parameter D/CX 0 1 1 WRX 1 1 RDX 1 D17-8 0 RDDIM (0Dh): Read Display Image Mode D7 D6 0 D5 0 D4 0 D3 1 D3 D2 1 GCS2 D1 0 GCS1 D0 1 GCS0 HEX (0Dh) -
VSSON D6
INVON D4
This command indicates the current status of the display as described in the table below: - Dont care Bit VSSON D6 Description Reversed Reversed Value 0 0 1 = Inversion is On, INVON Description D4 D3 All Pixels On All Pixels Off Inversion On/Off 0 = Inversion is Off 0 (Not used) 0 (Not used) 000 = GC0, GCS2 001 = GC1, GCS1 GCS0 011 = GC3, 100 to 111 = Not defined Gamma Curve Selection 010 = GC2,
Default Value(D7 to D0) 0000_0000 (00h) 0000_0000 (00h) 0000_0000 (00h)
Flow Chart
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10.1.9 RDDSM (0Eh): Read Display Signal Mode
0EH Inst / Para RDDSM 1st parameter 2nd parameter D/CX 0 1 1 WRX 1 1 RDX 1 D17-8 0 TEON RDDSM (0Eh): Read Display Signal Mode D7 D6 0 D5 0 D4 0 D4 D3 1 D3 D2 1 D2 D1 1 D1 D0 0 D0 HEX (0Eh) -
TELOM D5
This command indicates the current status of the display as described in the table below: - Dont care Bit TEON Description Tearing Effect Line On/Off Value 1 = On, 0 = Off TELOM Tearing effect line mode 1 = mode2, 0 = mode1 D5 Not Used 1 = On, 0 = Off Description D4 Not Used 1 = On, 0 = Off D3 Not Used 1 = On, 0 = Off D2 Not Used 1 = On, 0 = Off D1 Not Used 1 = On, 0 = Off D0 Not Used 1 = On, 0 = Off
Default Value(D7~D0) 0000_0000 (00h) 0000_0000 (00h) 0000_0000 (00h)
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Serial I/F Mode
Read RDDSM
Parallel I/F Mode

Read RDDSM
Legend
Command
Host Display
Send 2nd parameter Dummy Read
Parameter
Display
Flow Chart
Send 2nd parameter Action
Mode
Sequential transter
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10.1.10 SLPIN (10h): Sleep In
10H Inst / Para SLPIN Parameter Description -In this mode the DC/DC converter is stopped, Internal display oscillator is stopped, and panel scanning is stopped. -This command has no effect when module is already in Sleep In mode. Sleep In Mode can only be exit by the Sleep Out Command (11h). Restriction -When IC is in Sleep Out or Display On mode, it is necessary to wait 120msec before sending next command because of the stabilization timing for the supply voltages and clock circuits. Status Power On Sequence Default S/W Reset H/W Reset Sleep in mode Sleep in mode Default Value Sleep in mode D/CX 0 WRX RDX 1 D17-8 D7 0 D6 0 SLPIN (Sleep In) D5 0 D4 1 D3 0 D2 0 D1 0 D0 0 HEX (10h) -
No Parameter -This command causes the LCD module to enter the minimum power consumption mode.
Legend
SLPIN Stop DC-DC Converte r Command
Display whole blank screen (Automatic No effect to DISP ON/OFF Commands)
Parameter Stop Internal Oscillator
Display
Flow Chart
Drain Charge From LCD Panel
Sleep In Mode Action
Mode
Sequential transter
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10.1.11 SLPOUT (11h): Sleep Out
11H Inst / Para SLPOUT Parameter Description -In this mode the DC/DC converter is enabled, Internal display oscillator is started, and panel scanning is started. -This command has no effect when module is already in sleep out mode. Sleep Out Mode can only be exit by the Sleep In Command (10h). -When IC is in Sleep In mode, it is necessary to wait 120msec before sending next command because of the stabilization Restriction timing for the supply voltages and clock circuits. -When IC is in Sleep Out or Display On mode, it is necessary to wait 120msec before sending next command due to the download of default value of registers and the execution of self-diagnostic function. Status Power On Sequence Default S/W Reset H/W Reset Sleep in mode Sleep in mode Default Value Sleep in mode D/CX 0 WRX RDX 1 D17-8 D7 0 0 SLPOUT (Sleep Out) D6 D5 0 D4 1 D3 0 D2 0 D1 0 D0 1 HEX (11h) -
No Parameter -This command turns off sleep mode.
Legend
SLPOUT Display whole blank screen for 2 firames (Automatic No effect to DISP ON/OFF Commands)
Command
Parameter
Start Internal Oscillator
Display
Flow Chart
Start up DC:DC Converter
Display Memory contents In accordance with the current command table settings
Action
Charge Offset voltage for LCD Panel
Mode
Sleep Out mode
Sequential transter
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10.1.12 PTLON (12h): Partial Display Mode On
12H Inst / Para PTLON Parameter D/CX 0 WRX RDX 1 D17-8 PTLON (12h): Partial Display Mode On D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 1 D0 0 HEX (12h) -
No Parameter
-This command turns on Partial mode. The partial mode window is described by the Partial Area command (30h) Description -To leave Partial mode, the Normal Display Mode On command (13h) should be written. - Dont care Status Default Power On Sequence S/W Reset H/W Reset Default Value Normal Mode On Normal Mode On Normal Mode On
Flow Chart
See Partial Area (30h)
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10.1.13 NORON (13h): Normal Display Mode On
13H Inst / Para NORON Parameter D/CX 0 WRX RDX 1 D17-8 NORON (Normal Display Mode On) D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 1 D0 1 HEX (13h) -
No Parameter -This command returns the display to normal mode. -Normal display mode on means Partial mode off.
Description -Exit from NORON by the Partial mode On command (12h) - Dont care Status Default Power On Sequence S/W Reset H/W Reset Default Value Normal Mode On Normal Mode On Normal Mode On
Flow Chart
See Partial Area Definition Descriptions for details of when to use this command
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10.1.14 INVOFF (20h): Display Inversion Off
20H Inst / Para INVOFF Parameter D/CX 0 WRX RDX 1 D17-8 IVNOFF (Normal Display Mode Off) D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0 HEX (20h) -
No Parameter -This command is used to recover from display inversion mode. - Dont care (Example) Memory
Display
Description
T op-Left (0,0)
Default Value Display Inversion off Display Inversion off Display Inversion off
Legend
Command
Display Inversion On Mode
Parameter
Display
Flow Chart
INVOFF (20h) Action Display Inversion OFF Mode
Mode
Sequential transter
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10.1.15 INVON (21h): Display Inversion On
21H Inst / Para INVON Parameter D/CX 0 WRX RDX 1 D17-8 IVNOFF (Display Inversion On) D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 1 HEX (21h) -
No Parameter -This command is used to enter into display inversion mode -To exit from Display Inversion On, the Display Inversion Off command (20h) should be written. - Dont care
(Example) Memory
Display
Description
T op-Left (0,0)
Default Value Display Inversion off Display Inversion off Display Inversion off
Legend
Command
Display Inversion OFF Mode
Parameter
Display
Flow Chart
INVON (21h) Action Display Inversion ON Mode
Mode
Sequential transter
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10.1.16 GAMSET (26h): Gamma Set
26H Inst / Para GAMSET Parameter D/CX 0 1 WRX RDX 1 1 D17-8 D7 0 GAMSET (Gamma Set) D6 0 D5 1 D4 0 D3 0 GC3 D2 1 GC2 D1 1 GC1 D0 0 GC0 HEX (26h)
-This command is used to select the desired Gamma curve for the current display. A maximum of 4 curves can be selected. The curve is selected by setting the appropriate bit in the parameter as described in the Table. GC [7:0] Description Parameter Curve Selected GS=1 01h 02h 04h 08h GC0 GC1 GC2 GC3 Gamma Curve 1 (G2.2) Gamma Curve 2 (G1.8) Gamma Curve 3 (G2.5) Gamma Curve 4 (G1.0) GS=0 Gamma Curve 1 (G1.0) Gamma Curve 2 (G2.5) Gamma Curve 3 (G2.2) Gamma Curve 4 (G1.8)
Note: All other values are undefined. Status Default Power On Sequence S/W Reset H/W Reset Default Value 01h 01h 01h
Flow Chart
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10.1.17 DISPOFF (28h): Display Off
28H Inst / Para DISPOFF Parameter D/CX 0 No Parameter WRX RDX 1 D17-8 DISPOFF (Display Off) D7 0 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 0 HEX (28h) -
- This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory is disabled and blank page inserted. - This command makes no change of contents of frame memory. - This command does not change any other status. - There will be no abnormal visible effect on the display. - Exit from this command by Display On (29h) - The delay time between DISPON and DISPOFF needs 120ms at least.
Description
(Example) Memory Display
Note1: Complete 1 frame display (ex: continue 2-falling edges of VS) Note2: Please use command 28h (display off) combined with command 10h (sleep in) to make module into display off status. Please check the application note of ST7735 when using display off function. Status Default Power On Sequence S/W Reset H/W Reset Default Value Display off Display off Display off
Flow Chart
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10.1.18 DISPON (29h): Display On
29H DISPON Parameter 0 1 0 0 No Parameter - This command is used to recover from DISPLAY OFF mode. Output from the Frame Memory is enabled. - This command makes no change of contents of frame memory. - This command does not change any other status. - The delay time between DISPON and DISPOFF needs 120ms at least DISPON (Display On) 1 0 1 0 0 1 (29h) -
Description
(Example) Memory Display
Default Value Display off Display off Display off
Legend
Command
Display Off Mode
Parameter
Display
Flow Chart
DISPON Action
Display On Mode
Mode
Sequential transter
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10.1.19 CASET (2Ah): Column Address Set
2AH Inst / Para CASET(2Ah) 1st parameter 2nd parameter 3rd parameter 4th parameter D/CX 0 1 1 1 1 WRX RDX 1 1 1 1 1 D17-8 D7 0 XS15 XS7 XE15 XE7 CASET(Colume Address Set)_ D6 0 XS14 XS6 XE14 XE6 D5 1 XS13 XS5 XE13 XE5 D4 0 XS12 XS4 XE12 XE4 D3 1 XS11 XS3 XE11 XE3 D2 0 XS10 XS2 XE10 XE2 D1 1 XS9 XS1 XE9 XE1 D0 0 XS8 XS0 XE8 XE0 HEX (2Ah)
-The value of XS [7:0] and XE [7:0] are referred when RAMWR command comes.
-Each value represents one column line in the Frame Memory.

XS[7:0] XE[7:0]
Description
XS [15:0] always must be equal to or less than XE [15:0] When XS [15:0] or XE [15:0] is greater than maximum address like below, data of out of range will be ignored. 1. 128X160 memory base (GM = 011) (Parameter range: 0 < XS [15:0] < XE [15:0] < 127 (007Fh)): MV=0) Restriction (Parameter range: 0 < XS [15:0] < XE [15:0] < 159 (009Fh)): MV=1) 2. 132X162 memory base (GM = 000) (Parameter range: 0 < XS [15:0] < XE [15:0] < 131 (0083h)): MV=0) (Parameter range: 0 < XS [15:0] < XE [15:0] < 161 (00A1h)): MV=1)
GM Status GM=011 (128x160 memory base) GM=000 (132x162 memory base)
Status Power On Sequence S/W Reset H/W Reset Power On Sequence S/W Reset H/W Reset
Default Value XS [7:0] 0000h 0000h 0000h 0000h 0000h 0000h XE [7:0] (MV=0 ) 007Fh (127) 007Fh (127) 007Fh (127) 0083h (131) 0083h (131) 0083h (131) 00A1h (161) 009Fh (159) XE [7:0] (MV=1)
Default
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10.1.20 RASET (2Bh): Row Address Set
2BH Inst / Para RASET (2Bh) 1st parameter 2nd parameter 3rd parameter 4th parameter D/CX 0 1 1 1 1 WRX RDX 1 1 1 1 1 D17-8 D7 0 YS15 YS7 YE15 YE7 RASET (Row Address Set) D6 0 YS14 YS6 YE14 YE6 D5 1 YS13 YS5 YE13 YE5 D4 0 YS12 YS4 YE12 YE4 D3 1 YS11 YS3 YE11 YE3 D2 0 YS10 YS2 YE10 YE2 D1 1 YS9 YS1 YE9 YE1 D0 1 YS8 YS0 YE8 YE0 HEX (2Bh)
The value of YS [7:0] and YE [7:0] are referred when RAMWR command comes. Each value represents one column line in the Frame Memory.
YS[7:0]
Description
YE[7:0]
YS [15:0] always must be equal to or less than YE [15:0] When YS [15:0] or YE [15:0] are greater than maximum row address like below, data of out of range will be ignored. 1. 128X160 memory base (GM = 011) (Parameter range: 0 < YS [15:0] < YE [15:0] < 159 (009Fh)): MV=0 Restriction (Parameter range: 0 < YS [15:0] < YE [15:0] < 127 (007Fh)): MV=1 2. 132X162 memory base (GM = 000) (Parameter range: 0 < YS [15:0] < YE [15:0] < 161 (00A1h)): MV=0 (Parameter range: 0 < YS [15:0] < YE [15:0] < 131 (0083h)): MV=1
GM status GM=011 (128x160 memory base) GM=000 (132x162 memory base)
Status Power On Sequence S/W Reset H/W Reset Power On Sequence S/W Reset H/W Reset
Default Value YS [15:0] 0000h 0000h 0000h 0000h 0000h 0000h YE [15:0] (MV=0 ) 009Fh (159) 009Fh (159) 009Fh (159) 00A1h (161) 00A1h (161) 00A1h (161) 0083h (131) 007Fh (127) YE [15:0] (MV=1)
Default
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CASET
Legend
1st parameter XS[15:0] 2nd parameter XE[15:0] Command
Parameter
PASET
Display
Flow Chart
1st parameter YS[15:0] 2nd parameter YE[15:0]
Action
Mode RAMWR Sequential transter Image Data D1[7:0],D2[7:0] .Dn[7:0]
Any Command
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10.1.21 RAMWR (2Ch): Memory Write
2CH Inst / Para RAMWR 1st parameter Nth parameter D/CX 0 1 1 1 WRX RDX 1 1 1 1 D17-8 D17-8 D17-8 D7 0 D7 D7 RAMWR (Memory Write) D6 0 D6 D6 D5 1 D5 D5 D4 0 D4 D4 D3 1 D3 D3 D2 1 D2 D2 D1 0 D1 D1 D0 0 D0 D0 HEX (2Ch)
In all color modes, there is no restriction on length of parameters. 1. 128X160 memory base (GM = 011) 128x160x18-bit memory can be written by this command Description Memory range: (0000h, 0000h) -> (007Fh, 09Fh) 2. 132x162 memory base (GM = 000) 132x162x18-bit memory can be written on this command. Memory range: (0000h, 0000h) -> (0083h, 00A1h)
Default Value Contents of memory is set randomly Contents of memory is not cleared Contents of memory is not cleared
Legend
Command
RAMWR Parameter
Display
Flow Chart
Image Data D1[7:0],D2[7:0] .Dn[7:0]
Action
Mode
Any Command
Sequential transter
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10.1.22 RAMRD (2Eh): Memory Read
2EH Inst / Para RAMHD 1st parameter 2nd parameter (N+1)th parameter D/CX 0 1 1 1 1 WRX 1 1 1 1 RDX 1 D17-8 D17-8 D17-8 RAMHD (Memory Read) D7 0 D7 D7 D6 0 D6 D6 D5 1 D5 D5 D4 0 D4 D4 D3 1 D3 D3 D2 1 D2 D2 D1 1 D1 D1 D0 0 D0 D0 HEX (2Eh)
-This command is used to transfer data from frame memory to MCU. -When this command is accepted, the column register and the row register are reset to the Start Column/Start Row positions. -The Start Column/Start Row positions are different in accordance with MADCTL setting. -Then D[17:0] is read back from the frame memory and the column register and the row register incremented as section 9.10 Description -Frame Read can be cancelled by sending any other command. -The data color coding is fixed to 18-bit in reading function. Please see section 9.8 Data color coding for color coding (18-bit cases), when there is used 8, 9, 16 and 18-bit data lines for image data.
Note1: The Command 3Ah should be set to 66h when reading pixel data from frame memory.Please check the LUT in chapter 9.17 when using memory read function.
Default Value Contents of memory is set randomly Contents of memory is not cleared Contents of memory is not cleared
Flow Chart
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10.1.23 PTLAR (30h): Partial Area
30H Inst / Para PTLAR 1st parameter 2nd parameter 3rd parameter 4th parameter D/CX 0 1 1 1 1 WRX RDX 1 1 1 1 1 D17-8 D7 0 PSL15 PSL7 PEL15 PEL7 D6 0 PSL14 PSL6 PEL14 PEL6 PTLAR (Partial Area) D5 1 PSL13 PSL5 PEL13 PEL5 D4 1 PSL12 PSL4 PEL12 PEL4 D3 0 PSL11 PSL3 PEL11 PEL3 D2 0 PSL10 PSL2 PEL10 PEL2 D1 0 PSL9 PSL1 PEL9 PEL1 D0 0 PSL8 PSL0 PEL8 PEL0 HEX (30h)
-This command defines the partial modes display area. -There are 4 parameters associated with this command, the first defines the Start Row (PSL) and the second the End Row (PEL), as illustrated in the figures below. PSL and PEL refer to the Frame Memory row address counter. -If End Row > Start Row, when MADCTL ML=0
End row PEL [7:0] Non-display area
Partial display area
PSL [7:0] Start row Non-display area
-If End Row > Start Row, when MADCTL ML=1

Start row Non-display area
Description
PSL [7:0]
PEL [7:0] End row Non-display area
-If End Row < Start Row, when MADCTL ML=0

End row PEL [7:0] Non-display area PSL [7:0] Start row
-If End Row = Start Row then the Partial Area will be one row deep.
Status GM[2:0] Default Power On Sequence S/W Reset H/W Reset
Default Value PSL [15:0] xxx 0000h 0000h 0000h PEL [15:0] GM[2:0]=011 009Fh 009Fh 009Fh GM[2:0]=000 00A1h 00A1h 00A1h
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10.1.24 TEOFF (34h): Tearing Effect Line OFF
34H Inst / Para TEOFF Parameter Description D/CX 0 WRX RDX 1 D17-8 D7 0 TEOFF (Tearing Effect Line OFF) D6 0 D5 1 D4 1 D3 0 D2 1 D1 0 D0 0 HEX (34h) -
No Parameter -This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line. Status Power On Sequence Default Value OFF OFF OFF
Default
S/W Reset H/W Reset
Legend
Command TE Line Output ON Parameter
TEOFF
Display
Flow Chart
Action
TE Line Output OFF
Mode
Sequential transter
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10.1.25 TEON (35h): Tearing Effect Line ON
35H Inst / Para TEON Parameter D/CX 0 1 WRX RDX 1 1 D17-8 D7 0 0 TEON (Tearing Effect Line ON) D6 0 0 D5 1 0 D4 1 0 D3 0 0 D2 1 0 D1 0 0 D0 1 TELOM HEX (35h)
-This command is used to turn ON the Tearing Effect output signal from the TE signal line. -This output is not affected by changing MADCTL bit ML. -The Tearing Effect Line On has one parameter, which describes the mode of the Tearing Effect Output Line: -When TELOM =0: The Tearing Effect output line consists of V-Blanking information only Tvdl
Tvdh
Vertical time scale

Description
-When TELOM =1: The Tearing Effect output Line consists of both V-Blanking and H-Blanking information
Tvdl Vertical time scale
Tvdh
Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low. Status Power On Sequence Default S/W Reset H/W Reset Default Value Tearing effect off & TELOM=0 Tearing effect off & TELOM=0 Tearing effect off & TELOM=0
Legend
TE Line Output OFF Command
Parameter
TEON Display
Flow Chart
TELOM Action
TE Line Output ON
Mode
Sequential transter
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10.1.26 MADCTL (36h): Memory Data Access Control
36H Inst / Para MADCTL Parameter D/CX 0 1 WRX RDX 1 1 D17-8 0 MY MADCTL (Memory Data Access Control) D7 D6 0 MX D5 1 MV D4 1 ML D3 0 RGB D2 1 MH D1 1 D0 0 HEX (36h)
-This command defines read/ write scanning direction of frame memory.
Bit MY MX MV ML
NAME Row Address Order Column Address Order Row/Column Exchange Vertical Refresh Order
DESCRIPTION These 3bits controls MCU to memory write/read direction. LCD vertical refresh direction control 0 = LCD vertical refresh Top to Bottom 1 = LCD vertical refresh Bottom to Top Color selector switch control 0 =RGB color filter panel, 1 =BGR color filter panel) LCD horizontal refresh direction control 0 = LCD horizontal refresh Left to right 1 = LCD horizontal refresh right to left
RGB
RGB-BGR ORDER
MH
Horizontal Refresh Order
-Bit Assignment
Top-left (0, 0) Memory
Send first Send 2nd Send 3rd
Top-left (0, 0) Display
ML="0"
Description
Send last
Top-left (0, 0) Memory

Send last
ML="1"
Send 3rd Send 2nd Send first
RGB="0" Driver IC R G SIG1 B R G SIG2 B R G SIG132 B R G SIG1 B R
RGB="1" Driver IC G SIG2 B R G SIG132 B
SIG1 R G B R
SIG2 G B R
SIG132 G B B
SIG1 G R B
SIG2 G R B
SIG132 G R
LCD panel
LCD panel
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Top-left (0, 0) Memory Top-left (0, 0) Memory
ML="0"
ML="1"
Send first
Send first
Send 2nd
Send 2nd
Send last
Send last
Send 3rd
Send 3rd
Default Value MY=0,MX=0,MV=0,ML=0,RGB=0,MH=0 No Change MY=0,MX=0,MV=0,ML=0,RGB=0,MH=0
Legend
Command MADCTL Parameter
Display
Flow Chart
Action
1st parameter B[7:0]
Mode
Sequential transter
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10.1.27 IDMOFF (38h): Idle Mode Off
38H Inst / Para IDMOFF Parameter D/CX 0 WRX RDX 1 D17-8 D7 0 IDMOFF (Idle Mode Off) D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 0 HEX (38h) -
No Parameter -This command is used to recover from Idle mode on. -In the idle off mode,
Description 1. LCD can display 4096, 65k or 262k colors. 2. Normal frame frequency is applied. Status Power On Sequence Default S/W Reset H/W Reset Default Value Idle Mode Off Idle Mode Off Idle Mode Off
Flow Chart
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10.1.28 IDMON (39h): Idle Mode On
39H Inst / Para IDMOFF Parameter D/CX 0 WRX RDX 1 D17-8 D7 0 IDMON (Idle Mode On) D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 1 HEX (39h) -
No Parameter -This command is used to enter into Idle mode on. -There will be no abnormal visible effect on the display mode change transition. -In the idle on mode,
1. Color expression is reduced. The primary and the secondary colors using MSB of each R,G and B in the Frame Memory, 8 color depth data is displayed. 2. 8-Color mode frame frequency is applied. 3. Exit from IDMON by Idle Mode Off (38h) command
Top-Left (0,0)
Description
(Example) Memory
Display
Color Black Blue Red Magenta Green Cyan Yellow White Status
R5 R4 R3 R2 R1 R0 0xxxxx 0xxxxx 1xxxxx 1xxxxx 0xxxxx 0xxxxx 1xxxxx 1xxxxx
G5 G4 G3 G2 G1 G0 0xxxxx 0xxxxx 0xxxxx 0xxxxx 1xxxxx 1xxxxx 1xxxxx 1xxxxx
B5 B4 B3 B4 B1 B0 0xxxxx 1xxxxx 0xxxxx 1xxxxx 0xxxxx 1xxxxx 0xxxxx 1xxxxx
Availability Yes Yes No No Yes Default Value Idle Mode Off Idle Mode Off Idle Mode Off
Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence Default S/W Reset H/W Reset
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Legend
Command Idle off mode Parameter
IDMON
Display
Flow Chart
Idle on mode Action
Mode
Sequential transter
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10.1.29 COLMOD (3Ah): Interface Pixel Format
3AH Inst / Para COLMOD Parameter D/CX 0 1 WRX RDX 1 1 D17-8 D7 0 COLMOD (3Ah): Interface Pixel Format D6 0 D5 1 D4 1 D3 1 D2 0 IFPF2 D1 1 IFPF1 D0 0 IFPF0 HEX (3Ah)
This command is used to define the format of RGB picture data, which is to be transferred via the MCU interface. The formats are shown in the table: IFPF[2:0] 011 101 Description 110 111 3 5 6 7 MCU Interface Color Format 12-bit/pixel 16-bit/pixel 18-bit/pixel No used
Note1: In 12-bit/Pixel, 16-bit/Pixel or 18-bit/Pixel mode, the LUT is applied to transfer data into the Frame Memory. Note2: The Command 3Ah should be set at 55h when writing 16-bit/pixel data into frame memory, but 3Ah should be re-set to 66h when reading pixel data from frame memory. Please check the LUT in chapter 9.17 when using memory read function. Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Default Value IFPF[2:0] Default 0110(18-bit/Pixel) No Change 0110(18-bit/Pixel) VIPF[3:0] 0110(18-bit/Pixel) No Change 0110(18-bit/Pixel) Availability Yes Yes No No Yes
Flow Chart
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10.1.30 RDID1 (DAh): Read ID1 Value
DAH Inst / Para RDID1 1st parameter 2nd parameter D/CX 0 1 1 WRX 1 1 RDX 1 D17-8 D7 1 ID17 RDID1 (Read ID1 Value) D6 1 ID16 D5 0 ID15 D4 1 ID14 D3 1 ID13 D2 0 ID12 D1 1 ID11 D0 0 ID10 HEX (DAh) -
-This read byte returns 8-bit LCD modules manufacturer ID -The 1st parameter is dummy data Description -The 2nd parameter (ID17 to ID10): LCD modules manufacturer ID. NOTE: See command RDDID (04h), 2nd parameter. Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Default Power On Sequence S/W Reset H/W Reset Default Value Availability Yes Yes No No Yes
Legend Serial I/F Mode

Read ID1
Parallel I/F Mode

Read ID1
Command
Parameter
Send 2nd parameter
Dummy Read
Display
Flow Chart
Action Send 2nd parameter Mode
Sequential transter
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10.1.31 RDID2 (DBh): Read ID2 Value
DBH Inst / Para RDID2 1st parameter 2nd parameter D/CX 0 1 1 WRX 1 1 RDX 1 D17-8 D7 1 1 RDID2 (Read ID2 Value) D6 1 ID26 D5 0 ID25 D4 1 ID24 D3 1 ID23 D2 0 ID22 D1 1 ID21 D0 1 ID20 HEX (DBh) -
-This read byte returns 8-bit LCD module/driver version ID -The 1st parameter is dummy data -The 2nd parameter (ID26 to ID20): LCD module/driver version ID -Parameter Range: ID=80h to FFh Description ID26 to ID20 80h 81h 82h 83h NOTE: See command RDDID (04h), 3rd parameter. Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence Default S/W Reset H/W Reset Default Value NV Value NV Value NV Value Availability Yes Yes No No Yes Version Changes

Read ID2
Parallel I/F Mode

Read ID2
Command
Parameter
Host Display
Display Send 2nd parameter Dummy Read
Flow Chart
Sequential transter
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10.1.32 RDID3 (DCh): Read ID3 Value
DCH Inst / Para RDID3 1st parameter 2nd parameter D/CX 0 1 1 WRX 1 1 RDX 1 D17-8 D7 1 ID37 RDID3 (Read ID2 Value) D6 1 ID36 D5 0 ID35 D4 1 ID34 D3 1 ID33 D2 1 ID32 D1 0 ID31 D0 0 ID30 HEX (DCh) -
-This read byte returns 8-bit LCD module/driver ID. -The 1st parameter is dummy data Description -The 2nd parameter (ID37 to ID30): LCD module/driver ID. NOTE: See command RDDID (04h), 4th parameter. Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence Default S/W Reset H/W Reset Default Value NV Value NV Value NV Value Availability Yes Yes No No Yes

Read ID3
Parallel I/F Mode

Read ID3
Command
Parameter
Host Display
Display Send 2nd parameter Dummy Read
Flow Chart
Sequential transter
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10.2 Panel Function Command List and Description
Table 10.2.1 Panel Function Command List (1)
Instruction Refer D/CX WRX RDX D23-8 D7 D6 D5 D4 D3 D2 D1 D0 Hex Function In normal mode (Full colors)
(B1h)
FRMCTR1
10.2.1
1 1 1
1 1 1
FPA5 BPA5
RTNA3 RTNA2 RTNA1 RTNA0 FPA4 FPA3 BPA4 BPA3 FPA2 BPA2 FPA1 BPA1 FPA0 BPA0
RTNA set 1-line period FPA: front porch BPA: back porch
(B2h)
In Idle mode (8-colors)
FRMCTR2
10.2.2
1 1 1
1 1 1
FPB5 BPB5
RTNB3 RTNB2 RTNB1 RTNB0 FPB4 FPB3 BPB4 BPB3 FPB2 BPB2 FPB1 BPB1 FPB0 BPB0
RTNB: set 1-line period FPB: front porch BPB: back porch
0 1 1 FRMCTR3 10.2.3 1 1 1 1
1 1 1 1 1 1 1
(B3h)
In partial mode + Full colors
RTNC3 RTNC2 RTNC1 RTNC0 FPC5 BPC5 FPC4 FPC3 BPC4 BPC3 FPC2 BPC2 FPC1 BPC1 FPC0 BPC0 RTNC,RTND: set 1-line period FPC,FPD: front porch BPC,BPD: back porch
RTND3 RTND2 RTND1 RTND0 FPD5 BPD5 FPD4 FPD3 BPD4 BPD3 FPD2 BPD2 FPD1 BPD1 FPD0 BPD0
0 INVCTR 10.2.4 1
(B4h)
Display inversion control NLA,NLB,NLC set inversion Display function setting SDT: set amount of source delay EQ: set EQ period PT: No display area source/VCOM/Gate output control
NLA
NLB
NLC
(B6h)
DISSET5
10.2.5
NO1
NO0
SDT1
SDT0
EQ1
EQ0
PTG1
PTG0
PT1
PT0
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Instruction Refer D/CX WRX RDX D17-8 D7 0 1 PWCTR1 10.2.6 1 1 0 1 SEL1 SEL0 0 PWCTR2 10.2.7 1 1 0 0 0 0 0 BT2 BT1 BT0 1 1 1 0 0 0 0 0 1 (C1h) Power control setting 1 1 1 0 D6 1 0 D5 0 0 IBD4 0 D3 0 D2 0 D1 0 D0 0 Hex Function (C0h) Power control setting
VRH4 VRH3 VRH2 VRH1 VRH0 IB0 0 0 0 VRH: Set the GVDD voltage
BT: set VGH/ VGL voltage
1 0 0 0 0 1 0 0 0 0 1 0 0 1 -
1 0 0 0 0 1 0 0 0 0 1 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
(C2h)
In normal mode (Full colors) APA: adjust the operational amplifier DCA: adjust the booster Voltage
APA2 APA1 APA0 0 0 0
PWCTR3 10.2.8 1
1 DCA2 DCA1 DCA0 0 0 0 1 0 1
1 0 1 PWCTR4 10.2.9 1 0 1 PWCTR5 10.2.10 1 0 1 VMCTR1 10.2.11 1 0 VMOFCTR 10.2.12 1 0 WRID2 10.2.13 1
1 1 1 0 0 0 DCB2 DCB1 DCB0 0 1 0 0 0 0 -
(C3h) In Idle mode (8-colors) APB: adjust the operational amplifier DCB: adjust the booster Voltage
APB2 APB1 APB0
1 1 1 1 1 1 -
(C4h) In partial mode + Full colors APC: adjust the APC2 APC1 APC0 operational amplifier DCC2 DCC1 DCC0 1 0 1 DCC: adjust the booster circuit for Idle mode (C5h) VCOM control 1 VMH: VCOMH voltage control VML: VCOML voltage control (C7h) Set VCOM offset control
VMH6 VMH5 VMH4 VMH3 VMH2 VMH1 VMH0
1 1 1 1 1
1 1 -
VML6 VML5 VML4 VML3 VML2 VML1 VML0 1 1 0 0 0 0 1 1 1
VMF4 VMF3 VMF2 VMF1 VMF0 1 0 0 0 1 (D1h) Set LCM version code
ID2[6] ID2[5] ID2[4] ID2[3] ID2[2] ID2[1] ID2[0]
-: Dont care
Note 1: C0h to C7h are fixed for about power controller
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Instruction Refer D/CX WRX RDX D17-8 D7 0 WRID3 10.2.14 Set the project code 1 1 ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 at ID3 0 1 1 1 1 1 1 1 0 0 (FC) In partial mode + Idle 1 1 D6 1 D5 0 D4 1 D3 0 D2 0 D1 1 D0 0 Hex (D2h) code Function Customer Project
PWCTR6
10.2.15
Sapa Sapa Sapa --[2] [1] [0] Sapc Sapc Sapc --[2] [1] [0] 1 0 0 VMF _EN 1 ID2 _EN 1 0
Sapb Sapb Sapb [2] [1] [0] DCD [2] 0 0 DCD [1] 0 0 DCD [0] 1 0 (D9) EEPROM control status EEPROM Read
1 0 NVCTR1 10.2.16 1
1 1 1
1 0
0 NVCTR2 10.2.17 1 0
1 1 1
1 1 1
1 0 1
0 1 0
1 0 1
1 0 1
1 1 1
1 0 1
0 1 1
(DEh) Command A5 (DFh) Command Action code EEPROM Write
NVCTR3
10.2.18
EE_ IB7
EE_ IB6
EE_ IB5
EE_ IB4
EE_ IB3
EE_ IB2
EE_ IB1
EE_ IB0
1 1
1 1
EE_ EE_ EE_ EE_ EE_ EE_ EE_ EE_ CMD7 CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 1 0 1 0 0 1 0 1 A5
-: Dont care
Note 1: The D1h to D3h registers are fixed for about ID code setting. Note 2: The D9h, DEh and DFh registers are used for NV Memory function controller. (Ex: write, clear, etc.)
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Instruction Refer D/CX WRXRDX D17-8 D7 0 1 1 1 1 1 1 1 GAMCTRP1 10.2.19 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 GAMCTRN1 10.2.20 1 1 1 1 1 1 1 1 1 0 EXTCTRL 10.2.21 1 0 1 VCOM4L 10.2.22 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 TC2[0] 1 0 1 TC1[3] TC3[3] 1 0 1 TC1[2] TC3[2] 0 0 1 TC1[1] TC3[1] 1 1 1 TC1[0] TC3[0] 0 01 (FFh) Vcom 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 --------------------------------1 --------------------------------1 D6 1 --------------------------------1 --------------------------------1 D5 1
VRFP[5] VOS0P[5] PKP0[5] PKP1[5] PKP2[5] PKP3[5] PKP4[5] PKP5[5] PKP6[5] PKP7[5] PKP8[5] PKP9[5]
D4 0
VRFP[4] VOS0P[4] PKP0[4] PKP1[4] PKP2[4] PKP3[4] PKP4[4] PKP5[4] PKP6[4] PKP7[4] PKP8[4] PKP9[4]
D3 0
VRFP[3] VOS0P[3] PKP0[3] PKP1[3] PKP2[3] PKP3[3] PKP4[3] PKP5[3] PKP6[3] PKP7[3] PKP8[3] PKP9[3] SELV0P[3] SELV1P[3] SELV62P[3] SELV63P[3] 0 VRF0N[3] VOS0N[3] PKN0[3] PKN1[3] PKN2[3] PKN3[3] PKN4[3] PKN5[3] PKN6[3] PKN7[3] PKN8[3] PKN9[3] SELV0N[3] SELV1N[3] SELV62N[3] SELV63N[3]
D2 0
D1 0
D0 0
VRF0P[0] VOS0P[0] PKP0[0] PKP1[0] PKP2[0] PKP3[0] PKP4[0] PKP5[0] PKP6[0] PKP7[0] PKP8[0] PKP9[0] SELV0P[0] SELV1P[0] SELV62P[0] SELV63P[0] 1 VRF0N[0] VOS0N[0] PKN0[0] PKN1[0] PKN2[0] PKN3[0] PKN4[0] PKN5[0] PKN6[0] PKN7[0] PKN8[0] PKN9[0] SELV0N[0] SELV1N[0] SELV62N[0] SELV63N[0]
Hex Function (E0h) Set Gamma adjustment (+ polarity)
SELV0P[5] SELV0P[4] SELV1P[5] SELV1P[4] SELV62P[5] SELV62P[4] SELV63P[5] SELV63P[4] 1 VRF0N[5] VOS0N[5] PKN0[5] PKN1[5] PKN2[5] PKN3[5] PKN4[5] PKN5[5] PKN6[5] PKN7[5] PKN8[5] PKN9[5] 0 VRF0N[4] VOS0N[4] PKN0[4] PKN1[4] PKN2[4] PKN3[4] PKN4[4] PKN5[4] PKN6[4] PKN7[4] PKN8[4] PKN9[4]
(E1h) Set Gamma adjustment (- polarity)
SELV0N[5] SELV0N[4] SELV1N[5] SELV1N[4] SELV62N[5] SELV62N[4] SELV63N[5] SELV63N[4]
(F0h) Extension
Command Control
TC2[3] TC2[2] TC2[1] 0 0 0
Level control
-: Dont care
Note 1: E0-E1 registers are fixed for adjusting Gamma
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10.2.1 FRMCTR1 (B1h): Frame Rate Control (In normal mode/ Full colors)
B1H Inst / Para FRMCTR1 1 parameter 2 parameter 3rd parameter
nd st
FRMCTR1 (Frame Rate Control) D/CX 0 1 1 1 WRX RDX 1 1 1 1 D17-8 D7 1 D6 0 D5 1

FPA5 BPA5
D4 1
FPA4 BPA4
D3 0
RTNA3 FPA3 BPA3
D2 0
RTNA2 FPA2 BPA2
D1 0
RTNA1 FPA1 BPA1
D0 1
RTNA0 FPA0 BPA0
HEX (B1h)
-Set the frame frequency of the full colors normal mode. - Frame rate=fosc/((RTNA + 20) x (LINE + FPA + BPA)) Description - 1 < FPA(front porch) + BPA(back porch) ; Back porch 0 Note: fosc = 333kHz Status Default Value GM[2:0] = 000 Default Power On Sequence S/W Reset H/W Reset 02h/2Ch/2Dh 02h/2Ch/2Dh 02h/2Ch/2Dh GM[2:0] = 011 02h/2Dh/2Eh 02h/2Dh/2Eh 02h/2Dh/2Eh
Flow Chart
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10.2.2 FRMCTR2 (B2h): Frame Rate Control (In Idle mode/ 8-colors)
B2H Inst / Para FRMCTR2 1 parameter 2nd parameter 3 parameter
rd st
FRMCTR2 (Frame Rate Control) D/CX 0 1 1 1 WRX RDX 1 1 1 1 D17-8 D7 1 D6 0 D5 1

FPB5 BPB5
D4 1
FPB4 BPB4
D3 0
RTNB3 FPB3 BPB3
D2 0
RTNB2 FPB2 BPB2
D1 1
RTNB1 FPB1 BPB1
D0 0
RTNB0 FPB0 BPB0
HEX (B2h)
-Set the frame frequency of the Idle mode. - Frame rate=fosc/((RTNB + 20) x (LINE + FPB + BPB)) Description - 1 < FPB(front porch) + BPB(back porch) ; Back porch 0 Note: fosc = 333kHz Status Default Value GM[2:0] = 000 Default Power On Sequence S/W Reset H/W Reset 02h/2Ch/2Dh 02h/2Ch/2Dh 02h/2Ch/2Dh GM[2:0] = 011 02h/2Dh/2Eh 02h/2Dh/2Eh 02h/2Dh/2Eh
Flow Chart
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10.2.3 FRMCTR3 (B3h): Frame Rate Control (In Partial mode/ full colors)
B3H Inst / Para FRMCTR3 1 parameter 2 parameter 3rd parameter 4 parameter 5th parameter 6 parameter
th th nd st
FRMCTR3 (Frame Rate Control) D/CX 0 1 1 1 1 1 1 WRX RDX 1 1 1 1 1 1 1 D17-8 D7 1 D6 0 D5 1

FPC5 BPC5 FPD5 BPD5
D4 1
FPC4 BPC4 FPD4 BPD4
D3 0
RTNC3 FPC3 BPC3 RTND3 FPD3 BPD3
D2 0
D1 1
D0 1
HEX (B3h)
-Set the frame frequency of the Partial mode/ full colors. - 1st parameter to 3rd parameter are used in line inversion mode. - 4th parameter to 6th parameter are used in frame inversion mode. Description - Frame rate=fosc/((RTNC + 20) x (LINE + FPC + BPC)) - 1 < FPC(front porch) + BPC(back porch) ; Back porch 0 Note: fosc = 333kHz Status Default Value GM[2:0] = 000 Default Power On Sequence S/W Reset H/W Reset 02h/2Ch/2Dh/02h/2Ch/2Dh 02h/2Ch/2Dh/02h/2Ch/2Dh 02h/2Ch/2Dh/02h/2Ch/2Dh GM[2:0] = 011 02h/2Dh/2Eh/02h/2Dh/2Eh 02h/2Dh/2Eh/02h/2Dh/2Eh 02h/2Dh/2Eh/02h/2Dh/2Eh
Flow Chart
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10.2.4 INVCTR (B4h): Display Inversion Control
B4H Inst / Para INVCTR Parameter D/CX 0 1 WRX RDX 1 1 D17-8 D7 1 0 INVCTR (Display Inversion Control) D6 0 0 D5 1 0 D4 1 0 D3 0 0 D2 1 NLA D1 0 NLB D0 0 NLC HEX (B4h)
-Display Inversion mode control -NLA: Inversion setting in full colors normal mode (Normal mode on) NLA 0 1 Inversion setting in full Colors normal mode Line Inversion Frame Inversion
-NLB: Inversion setting in Idle mode (Idle mode on) Description NLB 0 1 Inversion setting in Idle mode Line Inversion Frame Inversion
-NLC: Inversion setting in full colors partial mode (Partial mode on / Idle mode off) NLC 0 1 Status Power On Sequence S/W Reset H/W Reset Inversion setting in full Colors partial mode Line Inversion Frame Inversion Default Value NLA Default 1d 1d 1d NLB 1d 1d 1d NLC 1d 1d 1d B4h 03h 03h 03h
Flow Chart
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10.2.5 DISSET5 (B6h): Display Function set 5
B6H Inst / Para DISSET5 1 parameter 2 parameter
nd st
DISSET (Display Function set 5) D/CX 0 1 WRX RDX 1 1 D17-8 D7 1 0 D6 0 0 D5 1 NO1 D4 1 NO0 0 D3 0 SDT1 PTG1 D2 1 SDT0 PTG0 D1 1 EQ1 PT1 D0 0 EQ0 PT0 HEX (B6h)
1 1 0 0 0 1st parameter: Set output waveform relation. -NO[1:0]: Set the amount of non-overlap of the gate output
NO[1:0] 00 01 10 11 SDT[1:0] 00 01 10 11 EQ[1:0] 00 01 10 11 00h 01h 02h 03h 00h 01h 02h 03h 00h 01h 02h 03h
Amount of non-overlap of the gate output Refer the Internal oscillator 1 clock cycle 2 clock cycle 4 clock cycle 6 clock cycle Delay amount form gate signal rising edge of the source output Refer the Internal oscillator 0 clock cycle 1 clock cycle 2 clock cycle 3 clock cycle Equalizing period Refer the Internal oscillator No EQ 3 clock cycle 5 clock cycle 7 clock cycle
-SDT[1:0]: Set delay amount from gate signal rising edge of the source output.
-EQ[1:0]: Set the Equalizing period
-2nd parameter: Set the output waveform in non-display area. -PTG[1:0]: Determine gate output in a non-display area in the partial mode Description
PTG[1:0] 00 01 10 11
00h 01h 02h 03h
Gate output in a non-display area Normal scan Fix on VGL Fix on VGL Fix on VGL
-PT[1:0]: Determine Source /VCOM output in a non-display area in the partial mode
PT[1:0] 00 01 10 11 00h 01h 02h 03h
Source output on non-display area Positive Negative V63 V0 V0 V63 AGND AGND Hi-z Hi-z
VCOM output on non-display area Positive Negative VCOML VCOMH VCOML VCOMH AGND AGND AGND AGND
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Status Default Value B6h Default Power On Sequence S/W Reset H/W Reset 15h/00h 15h/00h 15h/00h
Flow Chart
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10.2.6 PWCTR1 (C0h): Power Control 1
C0H Inst / Para PWCTR1 1st paramete
nd
PWCTR1 (Power Control 1) D/CX 0 1 WRX RDX 1 1 D17-8 D7 1 0 0 D6 1 0 1 D5 0 0 D4 0 VRH4 D3 0 VRH3 D2 0 VRH2 0 D1 0 VRH1 0 D0 0 VRH0 0 HEX (C0h)
2 parameter 1 1 -Set the GVDD voltage
IB_SEL1IB_SEL0-
Note: AVDD=5.3V VRH[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 GVDD 5.00 4.75 4.70 4.65 4.60 4.55 4.50 4.45 4.40 4.35 4.30 4.25 4.20 4.15 4.10 4.05 4.00 3.95 3.90 3.85 3.80 3.75 3.70 3.65 3.60 3.55 3.50 3.45 3.40 3.35 3.25 3.00 IB_SEL[1:0] 00 01 10 11 00h 01h 02h 03h AVDD 2.5uA 2.0uA 1.5uA 1.0uA
Description
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh
Restriction
-If this register not using the register need be reserved. -The deviation value of GVDD between with Measurement and Specification : Max <= 50mV
Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Availability Yes Yes Yes Yes Yes
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Status Default Power On Sequence S/W Reset H/W Reset Default Value C0h 02h/70h 02h/70h 02h/70h
Flow Chart
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10.2.7 PWCTR2 (C1h): Power Control 2
C1H Inst / Para PWCTR2
st
PWCTR2 (Power Control 2) D/CX 0 WRX RDX 1 1 D17-8 D7 1 0 D6 1 0 D5 0 0 D4 0 0 D3 0 0 D2 0 BT2 D1 0 BT1 D0 1 BT0 HEX (C1h)
1 parameter 1
-Set the VGH and VGL supply power level
BT[2:0] 000 001

Description
VGH 4X 4X 5X 5X 5X 6X 6X 6X 9.8 9.8 12.25 12.25 12.25 14.7 14.7 14.7
VGL -3X -4X -3X -4X -5X -3X -4X -5X -7.35 -9.8 -7.35 -9.8 -12.25 -7.35 -9.8 -12.25
010 011 100 101 110 111
Restriction
-If this register not using the register need be reserved. -The deviation value of VGH/ VGL between with Measurement and Specification: Max <= 1V -VGH-VGL <= 32V
Default Value C1h 05h 05h 05h
Flow Chart
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10.2.8 PWCTR3 (C2h): Power Control 3 (in Normal mode/ Full colors)
st nd
PWCTR3 (Power Control 3) D/CX 0 WRX RDX 1 1 D17-8 D7 1 0 D6 1 0 D5 0 0 D4 0 0 D3 0 0 D2 0 APA2 D1 1 APA1 D0 0 APA0 HEX (C2h)
1 parameter 1
2 parameter 1 1 0 0 0 0 0 DCA2 DCA1 DCA0 -Set the amount of current in Operational amplifier in normal mode/full colors. -Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver.
AP[2:0] 000 001 010 011 100 101 110 111

Description
Amount of Current in Operational Amplifier 00h 01h 02h 03h 04h 05h 06h 07h Operation of the operational amplifier stops Small Medium Low Medium Medium High Large Reserved Reserved
-Set the Booster circuit Step-up cycle in Normal mode/ full colors.
DC[2:0] 000 001 010 011 100 101 110 111 00h 01h 02h 03h 04h 05h 06h 07h
Step-up cycle in Booster circuit 1 BCLK / 1 BCLK / 1 BCLK / 1 BCLK / 2 BCLK / 2 BCLK / 4 BCLK / 4 BCLK / 4
Step-up cycle in Booster circuit 2,4 BCLK / 1 BCLK / 2 BCLK / 4 BCLK / 2 BCLK / 4 BCLK / 4 BCLK / 8 BCLK / 16
Note: BCLK is Clock frequency for Booster circuit
Restriction
-If this register not using the register need be reserved.
Default Value C2h 01h/01h 01h/01h 01h/01h
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Flow Chart
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10.2.9 PWCTR4 (C3h): Power Control 4 (in Idle mode/ 8-colors)
st nd
PWCTR4 (Power Control 4) D/CX 0 WRX RDX 1 1 D17-8 D7 1 0 D6 1 0 D5 0 0 D4 0 0 D3 0 0 D2 0 APB2 D1 1 APB1 D0 1 APB0 HEX (C3h)
1 parameter 1
2 parameter 1 1 0 0 0 0 0 DCB2 DCB1 DCB0 -Set the amount of current in Operational amplifier in Idle mode/8 colors. -Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver.
AP[2:0] 000 001 010 011 100 101 110 111

Description
-Set the Booster circuit Step-up cycle in Idle mode/8 colors.
DC[2:0] 000 001 010 011 100 101 110 111 00h 01h 02h 03h 04h 05h 06h 07h
Restriction
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Flow Chart
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10.2.10 PWCTR5 (C4h): Power Control 5 (in Partial mode/ full-colors)
st nd
PWCTR5 (Power Control 5) D/CX 0 WRX RDX 1 1 D17-8 D7 1 0 D6 1 0 D5 0 0 D4 0 0 D3 0 0 D2 1 APC2 D1 0 APC1 D0 0 APC0 HEX (C4h)
1 parameter 1
2 parameter 1 1 0 0 0 0 0 DCC2 DCC1 DCC0 -Set the amount of current in Operational amplifier in Partial mode/ full-colors. -Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver.
AP[2:0] 000 001 010 011 100 101 110 111

Description
-Set the Booster circuit Step-up cycle in Partial mode/ full-colors.
DC[2:0] 000 001 010 011 100 101 110 111 00h 01h 02h 03h 04h 05h 06h 07h
Restriction
-If this register not using the register need be reserved. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes
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Flow Chart
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10.2.11 VMCTR1 (C5h): VCOM Control 1
C5H Inst / Para VMCTR1 1st parameter 2nd parameter D/CX 0 1 1 WRX RDX 1 1 1 D17-8 D7 1 VMCTR1 (VCOM Control 1) D6 1 VMH6 VML6 D5 0 VMH5 VML5 D4 0 VMH 4 VML4 D3 0 VMH 3 VML3 D2 1 VMH 2 VML2 D1 0 VMH 1 VML1 D0 1 VMH 0 VML0 HEX (C5h)
-Set VCOMH Voltage VMH[6:0] 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 Description 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah VCOMH 2.500 2.525 2.550 2.575 2.600 2.625 2.650 2.675 2.700 2.725 2.750 2.775 2.800 2.825 2.850 2.875 2.900 2.925 2.950 2.975 3.000 3.025 3.050 3.075 3.100 3.125 3.150 VMH[6:0] 0011011 0011100 0011101 0011110 0011111 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h VCOMH 3.175 3.200 3.225 3.250 3.275 3.300 3.325 3.350 3.375 3.400 3.425 3.450 3.475 3.500 3.525 3.550 3.575 3.600 3.625 3.650 3.675 3.700 3.725 3.750 3.775 3.800 3.825 VMH[6:0] 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 36h 37h 38h 39h 3Ah 2Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h VCOMH 3.850 3.875 3.900 3.925 3.950 3.975 4.000 4.025 4.050 4.075 4.100 4.125 4.150 4.175 4.200 4.225 4.250 4.275 4.300 4.325 4.350 4.375 4.400 4.425 4.450 4.475 4.500 1111111 VMH[6:0] 1010001 1010010 1010011 1010100 1010101 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 1100000 1100001 1100010 1100011 1100100 1100101 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h | 7Fh Not Permitted VCOMH 4.525 4.550 4.575 4.600 4.625 4.650 4.675 4.700 4.725 4.750 4.775 4.800 4.825 4.850 4.875 4.900 4.925 4.950 4.975 5.000
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-Set VCOML Voltage VML[6:0] 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Eh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah -2.400 -2.375 -2.350 -2.325 -2.300 -2.275 -2.250 -2.225 -2.200 -2.175 -2.150 -2.125 -2.100 -2.075 -2.050 -2.025 -2.000 -1.975 -1.950 -1.925 -1.900 -1.875 -1.850 Not Permitted VCOML VML[6:0] 0011011 0011100 0011101 0011110 0011111 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h VCOML -1.825 -1.800 -1.775 -1.750 -1.725 -1.700 -1.675 -1.650 -1.625 -1.600 -1.575 -1.550 -1.525 -1.500 -1.475 -1.450 -1.425 -1.400 -1.375 -1.350 -1.325 -1.300 -1.275 -1.250 -1.225 -1.200 -1.175 VML[6:0] 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h VCOML -1.150 -1.125 -1.100 -1.075 -1.050 -1.025 -1.000 -0.975 -0.950 -0.925 -0.900 -0.875 -0.850 -0.825 -0.800 -0.775 -0.750 -0.725 -0.700 -0.675 -0.650 -0.625 -0.600 -0.575 -0.550 -0.525 -0.500 1111111 VML[6:0] 1010001 1010010 1010011 1010100 1010101 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 1100000 1100001 1100010 1100011 1100100 1100101 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h | 7Fh Not Permitted VCOML -0.475 -0.450 -0.425 -0.400 -0.375 -0.350 -0.325 -0.300 -0.275 -0.250 -0.225 -0.200 -0.175 -0.150 -0.125 -0.100 -0.075 -0.050 -0.025 0.000
Restriction -The VCOMAC = VCOMH VCOML
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Register Availability Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Default Power On Sequence S/W Reset H/W Reset Default Value C5h 51h/4Dh 51h/4Dh 51h/4Dh
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Flow Chart
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10.2.12 VMOFCTR (C7h): VCOM Offset Control
C7H Inst / Para VMOFCTR Parameter D/CX 0 1 WRX RDX 1 1 D17-8 D7 1 VMOFCTR (VCOM Offset Control) D6 1 D5 0 D4 0 VMF4 D3 0 VMF3 D2 1 VMF2 D1 1 VMF1 D0 1 VMF0 HEX (C7h)
-Set VCOM Voltage level for reduce the flicker issue VMF (hex) 00h 01h 02h | 0Eh 0Fh Description 10h 11h 12h | 1Eh 1Fh VMF[4:0] 00000 00001 00010 | 01110 01111 10000 10001 10010 | 11110 11111 VCOMH,VCOML Output Level VMH -16d,VML-16d VMH-15d, VML-15d VMH-14d, VML-14d | VMH-2d, VML-2d VMH-1d, VML-1d VMH, VML VMH+1d, VML+1d VMH+2d, VML+2d | VMH+14d, VML+14d VMH+15d, VML+15d
- 1d=25mV, 2d=50mV 3d=75mv.... - 2.5V <= VMH nd <= 5.0V; -2. 5V <= VML nd<= 0V (n=0~15,16)
Restriction
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Default Value C7h F0h F0h F0h
Default
Power On Sequence S/W Reset H/W Reset
Flow Chart
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10.2.13 WRID2 (D1h): Write ID2 Value
D1H Inst / Para WRID2 Parameter D/CX 0 1 WRX RDX 1 1 D17 D7 1 WRID2 (Write ID2 Value) D6 1 ID26 D5 0 ID25 D4 1 ID24 D3 0 ID23 D2 0 ID22 D1 0 ID21 D0 1 ID20 HEX (D1h) -
-Write 7-bit data of LCD module version to save it to EEPROM. Description -The parameter ID2[6:0] is LCD Module version ID.
Flow Chart
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10.2.14 WRID3 (D2h): Write ID3 Value
D2H Inst / Para WRID3 Parameter Description D/CX 0 1 WRX RDX 1 1 D17-8 D7 1 ID37 WRID3 (Write ID3 Value) D6 1 ID36 D5 0 ID35 D4 1 ID34 D3 0 ID33 D2 0 ID32 D1 1 ID31 D0 0 ID30 HEX (D2h) -
-Write 8-bit data of project code module to save it to EEPROM. -The parameter ID3[7:0] is product project ID.
Flow Chart
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10.2.15 PWCTR6 (FCh): Power Control 5 (in Partial mode + Idle mode)
FCH Inst / Para PWCTR6 1 parameter 2nd parameter Description
st
PWCTR6 (Gamma control adjust) D/CX 0 1 1 WRX RDX 1 1 1 D17-8 D7 1 D6 1 Sapa2 Sapc2 D5 1 Sapa1 Sapc1 D4 1 Sapa0 Sapc0 D3 1 D2 1 Sapb2 DCD2 D1 0 Sapb1 DCD1 D0 0 Sapb0 DCD0 HEX (FCh)
-Set the amount of current in Operational amplifier in Partial mode + Idle mode.
Status Power On Sequence S/W Reset H/W Reset
Default Value FCh 11h/15h 11h/15h 11h/15h
Default
Flow Chart
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10.2.16 NVFCTR1 (D9h): EEPROM Control Status
D9H Inst / Para NVFCTR1 parameter D/CX 0 1 WRX 1 RDX 1 D17-8 NVFCTR1 (NV Memory Function Controller 1) D7 1 0 D6 1 0 D5 0 D4 0 D3 1 D2 0 0 D1 0 0 D0 1 0 HEX (D9h)
VMF_EN ID2_EN 0
-EEPROM control status Description Bit VMF_EN ID2_EN Value 1 = Command C7h enable ; 0 = Command C7h disable 1 = Command D1h enable ; 0 = Command D1h disable
Status Power On Sequence S/W Reset H/W Reset
Default Value D9h 00h 00h 00h
Default
Flow Chart
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10.2.17 NVFCTR2 (DEh): EEPROM Read Command
DEH Inst / Para NVFCTR2 parameter Description NOTE: - Dont care D/CX 0 1 WRX RDX 1 1 NVFCTR1 (NV Memory Function Controller 2) D17-8 D7 1 1 D6 1 0 D5 0 1 D4 1 0 D3 1 0 D2 1 1 D1 1 0 D0 0 1 HEX (DEh) A5
EEPROM Read Command
Flow Chart
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10.2.18 NVFCTR3 (DFh): EEPROM Write Command
DFH Inst / Para NVFCTR1
st nd
NVFCTR1 (NV Memory Function Controller 3 D/CX 0 WRX RDX 1 1 1 1 D17-8 D7 1 D6 1 D5 0 D4 1 D3 1 D2 1 D1 1 D0 1 HEX (DFh)
1 parameter 1 2 parameter 1 3rd parameter 1
EE_IB7 EE_IB6 EE_IB5 EE_IB4 EE_IB3 EE_IB2 EE_IB1 EE_IB0

EE_CMD7 EE_CMD6 EE_CMD5 EE_CMD4 EE_CMD3 EE_CMD2 EE_CMD1 EE_CMD0
A5
-EEPROM Write Command -EE_IB[7:0] : Select Command. ; ADDR: C7h, D1h, D2h Description -EE_CMD[7:0] : Select to Program/Erase ; Program command : 3Ah ; Erase command : C5h NOTE: - Dont care
Flow Chart
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10.2.19 GMCTRP1 (E0h): Gamma (+polarity) Correction Characteristics Setting
E0H Inst / Para GMCTRP1
nd
GMCTRP0 (Gamma +polarity Correction Characteristics Setting) D/CX WRX RDX D17-8 D7 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D6 1 D5 1 VRF0P[5] VOS0P[5] PK0P[5] PK1P[5] PK2P[5] PK3P[5] PK4P[5] PK5P[5] PK6P[5] PK7P[5] PK8P[5] PK9P[5] D4 0 VRF0P[4] VOS0P[4] PK0P[4] PK1P[4] PK2P[4] PK3P[4] PK4P[4] PK5P[4] PK6P[4] PK7P[4] PK8P[4] PK9P[4] D3 0 VF0P[3] VOS0P[3] PK0P[3] PK1P[3] PK2P[3] PK3P[3] PK4P[3] PK5P[3] PK6P[3] PK7P[3] PK8P[3] PK9P[3] D2 0 VRF0P[2] VOS0P[2] PK0P[2] PK1P[2] PK2P[2] PK3P[2] PK4P[2] PK5P[2] PK6P[2] PK7P[2] PK8P[2] PK9P[2] D1 0 VRF0P[1] VOS0P[1] PK0P[1] PK1P[1] PK2P[1] PK3P[1] PK4P[1] PK5P[1] PK6P[1] PK7P[1] PK8P[1] PK9P[1] D0 0 VRF0P[0] VOS0P[0] PK0P[0] PK1P[0] PK2P[0] PK3P[0] PK4P[0] PK5P[0] PK6P[0] PK7P[0] PK8P[0] PK9P[0] HEX (E0h)
1st parameter 1 2 parameter 1 3rd parameter 1 4th parameter 1 5th parameter 1 6 parameter 1 7th parameter 1 8th parameter 1 9th parameter 1 10 parameter 1 11 parameter 1 12th parameter 1 13 parameter 1 14th parameter 1 15 parameter 1 16th parameter 1
th th th th th
SELV0P[5] SELV0P[4] SELV0P[3] SELV0P[2] SELV0P[1] SELV0P[0] SELV1P[5] SELV1P[4] SELV1P[3] SELV1P[2] SELV1P[1] SELV1P[0] SELV62P[5] SELV62P[4] SELV62P[3] SELV62P[2] SELV62P[1] SELV62P[0] SELV63P[5] SELV63P[4] SELV63P[3] SELV63P[2] SELV63P[1] SELV63P[0]
Register Group High level adjustment
Positive Polarity VRF0P[5:0] SELV0P[5:0] SELV1P[5:0] PK0P[5:0] PK1P[5:0] PK2P[5:0] PK3P[5:0]
Set-up Contents Variable resistor VRHP The voltage of V0 grayscale is selected by the 64 to 1 selector The voltage of V1 grayscale is selected by the 64 to 1 selector The voltage of V3 grayscale is selected by the 64 to 1 selector The voltage of V6 grayscale is selected by the 64 to 1 selector The voltage of V11 grayscale is selected by the 64 to 1 selector The voltage of V19 grayscale is selected by the 64 to 1 selector The voltage of V27 grayscale is selected by the 64 to 1 selector The voltage of V36 grayscale is selected by the 64 to 1 selector The voltage of V44 grayscale is selected by the 64 to 1 selector The voltage of V52 grayscale is selected by the 64 to 1 selector The voltage of V57 grayscale is selected by the 64 to 1 selector The voltage of V60 grayscale is selected by the 64 to 1 selector The voltage of V62 grayscale is selected by the 64 to 1 selector The voltage of V63 grayscale is selected by the 64 to 1 selector Variable resistor VRLP
Description
Mid level adjustment
PK4P[5:0] PK5P[5:0] PK6P[5:0] PK7P[5:0] PK8P[5:0] PK9P[5:0] SELV62P[5:0] SELV63P[5:0]
Low level adjustment
VOS0P[5:0]
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Flow Chart
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10.2.20 GMCTRN1 (E1h): Gamma -polarity Correction Characteristics Setting
E1H Inst / Para GMCTRP1
nd
GMCTRP0 (Gamma +polarity Correction Characteristics Setting) D/CX WRX RDX D17-8 D7 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D6 1 D5 1 VRF0N[5] VOS0N[5] PK0N[5] PK1N[5] PK2N[5] PK3N[5] PK4N[5] PK5N[5] PK6N[5] PK7N[5] PK8N[5] PK9[5] D4 0 VRF0N[4] VOS0N[4] PK0N[4] PK1N[4] PK2N[4] PK3N[4] PK4N[4] PK5N[4] PK6N[4] PK7N[4] PK8N[4] PK9N[4] D3 0 VF0N[3] VOS0N[3] PK0N[3] PK1N[3] PK2N[3] PK3N[3] PK4N[3] PK5N[3] PK6N[3] PK7N[3] PK8N[3] PK9N[3] D2 0 VRF0N[2] VOS0N[2] PK0N[2] PK1N[2] PK2N[2] PK3N[2] PK4N[2] PK5N[2] PK6N[2] PK7N[2] PK8N[2] PK9N[2] D1 0 VRF0N[1] VOS0N[1] PK0N[1] PK1N[1] PK2N[1] PK3N[1] PK4N[1] PK5N[1] PK6N[1] PK7N[1] PK8N[1] PK9N[1] D0 1 VRF0N[0] VOS0N[0] PK0N[0] PK1N[0] PK2N[0] PK3N[0] PK4N[0] PK5N[0] PK6N[0] PK7N[0] PK8N[0] PK9N[0] HEX (E1h)
1st parameter 1 2 parameter 1 3rd parameter 1 4th parameter 1 5th parameter 1 6 parameter 1 7th parameter 1 8 parameter 1 9th parameter 1 10 parameter 1 11 parameter 1 12th parameter 1 13 parameter 1 14th parameter 1 15 parameter 1 16th parameter 1
th th th th th th
SELV0N[5] SELV0N[4] SELV0N[3] SELV0N[2] SELV0N[1] SELV0N[0] SELV1N[5] SELV1N[4] SELV1N[3] SELV1N[2] SELV1N[1] SELV1N[0] SELV62N[5] SELV62N[4] SELV62N[3] SELV62N[2] SELV62N[1] SELV62N[0] SELV63N[5] SELV63N[4] SELV63N[3] SELV63N[2] SELV63N[1] SELV63N[0]
Register Group High level adjustment
Negative Polarity VRF0N[5:0] SELV0N[5:0] SELV1N[5:0] PK0N[5:0] PK1N[5:0] PK2N[5:0] PK3N[5:0]
Set-up Contents Variable resistor VRHN The voltage of V0 grayscale is selected by the 64 to 1 selector The voltage of V1 grayscale is selected by the 64 to 1 selector The voltage of V3 grayscale is selected by the 64 to 1 selector The voltage of V6 grayscale is selected by the 64 to 1 selector The voltage of V11 grayscale is selected by the 64 to 1 selector The voltage of V19 grayscale is selected by the 64 to 1 selector The voltage of V27 grayscale is selected by the 64 to 1 selector The voltage of V36 grayscale is selected by the 64 to 1 selector The voltage of V44 grayscale is selected by the 64 to 1 selector The voltage of V52 grayscale is selected by the 64 to 1 selector The voltage of V57 grayscale is selected by the 64 to 1 selector The voltage of V60 grayscale is selected by the 64 to 1 selector The voltage of V62 grayscale is selected by the 64 to 1 selector The voltage of V63 grayscale is selected by the 64 to 1 selector Variable resistor VRLN
Description
Mid level adjustment
PK4N[5:0] PK5N[5:0] PK6N[5:0] PK7N[5:0] PK8N[5:0] PK9N[5:0] SELV62N[5:0] SELV63N[5:0]
Low level adjustment
VOS0N[5:0]
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Flow Chart
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10.2.21 EXTCTRL (F0h): Extension Command Control
F0H Inst / Para EXTCTRL parameter Description NOTE: - Dont care D/CX 0 1 WRX RDX 1 1 EXTCTRL (Extension command control) D17-8 D7 1 0 D6 1 0 D5 1 0 D4 1 0 D3 0 0 D2 0 0 D1 0 0 D0 0 1 HEX (F0h) (01h)
When EXTC PIN =L, this command will enable extension command.
Flow Chart
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10.2.22 VCOM4L (FFh): Vcom 4 Level Control
FFH Inst / Para VCOM4L Parameter1 Parameter2 Parameter3 D/CX 0 1 1 1 WRX RDX 1 1 1 1 D17-8 D7 1 VCOM4L (Vcom 4 level control) D6 1 D5 1 D4 1 D3 1 D2 1 D1 1 D0 1 HEX (FFh)
TC2[3] TC2[2] TC2[1] TC2[0] TC1[3] TC1[2] TC1[1] TC1[0] 0 0 0 1 TC3[3] TC3[2] TC3[1] TC3[0] 1 0 1 0 (1Ah)
TC1[3:0] 0000 0001 0010 0011 0100 0101 0110 Description 0111 1000 1001 1010 1011 1100 1101 1110 1111
Delay time 0 clock 1 clock 2 clock 3 clock 4 clock 5 clock 6 clock 7 clock 8 clock 9 clock 10 clock 11 clock 12 clock 13 clock 14 clock 15 clock
TC2[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
TC3[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
NOTE: - Dont care
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Flow Chart
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11 Power structure
11.1 Driver IC Operating Voltage Specification
Fig 11.1.1 Power Booster Level
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11.2 Power Booster Circuit
VDD CVDD AVDD_I Reference Voltage generator REGP Gray reference Circuit Block (Gamma) Source Output Circuit Block S1 | S396
REGP
Vci1
AVDD_I
REGP AGND
GVDD
AGND VDD C11 AVDD_I
Charge Pump 1
REGP
VCOMH CVCOMH
AVDD CAVDD AGND VGH CVGH Vci1 Vci1 C22 Charge Pump 2 VCOML CVCOML C23 VGL CVGL VCL_I REGP VCOM
VGH_I VDD C41 Charge Pump 4 VCL CVCL Reference Voltage generator VGL_I
Gate Driver
G1 | G162
VDDI CVDDI
VGL_I
VGH_I
VCL_I
AVDD_I CVCC
VCC
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11.2.1 EXTERNAL COMPONENTS CONNECTION
Rated (Min) Pad Name Connection Voltage VDDI VDD VCC C41P, C41N C22P, C22N C23P, C23N C11P, C11N AVDD VGH VGL VCL VCOMH VCOML VDDI (Logic Power) VDD (Analog Power) Connect to Capacitor: VCC -------||-------- GND Connect to Capacitor: C41P -------||--- -----C41N Connect to Capacitor: C22P -------||--------C22N Connect to Capacitor: C23P -------||--- -----C23N Connect to Capacitor: C11P -------||--------C11N Connect to Capacitor: AVDD -------||-------- GND Connect to Capacitor: VGH -------||-------- GND Connect to Capacitor: VGL -------||-------- GND Connect to Capacitor: VCL -------||-------- GND Connect to Capacitor: VCOMH-------||--------- GND Connect to Capacitor: VCOML -------||-------- GND 6.3V 6.3V 6.3V 6.3V 25.0V; 16.0V* 25.0V; 16.0V* 6.3V 6.3V 25.0V; 16.0V* 25.0V; 16.0V* 6.3V 6.3V 6.3V capacitance value 1.0 uF 1.0 uF 1.0 uF 1.0 uF 0.1 uF 0.1 uF 1.0 uF 1.0 uF 0.1 uF 0.1 uF 1.0 uF 1.0 uF 1.0 uF Typical
Note: For the typical specification of capacitor, the surge voltage is 125% of rated voltage. The capacitor of rated voltage of 16V can be only used for the case of VGH < 12.8V and VGL > -12.8V to prevent from stability issue. For normal usage, please use the capacitor of 25V rating.
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12 Gamma structure
12.1 TRUCTURE OF GRAYSCALE AMPLIFIER
The structure of grayscale amplifier is shown as below. 16 voltage levels (VIN0-VIN15) between GVDD and VGS are determined by the high/ mid/ low level adjustment registers. Each mid-adjustment level is split into 64 levels again by the internal ladder resistor network. As a result, grayscale amplifier generates 64 voltage levels ranging from V0 to V63 and outputs one of 64 levels.
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12.2 Gamma Voltage Formula (Positive/ Negative Polarity)
Gray Level 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Voltage Formula (Positive) VINP0 VINP1 VINP2 VINP3 V3-(V3-V6)*(11/30) V3-(V3-V6)*(21/30) VINP4 V6-(V6-V11)*(7/30) V6-(V6-V11)*(14/30) V6-(V6-V11)*(20/30) V6-(V6-V11)*(25/30) VINP5 V11-(V11-V19)*(4/32) V11-(V11-V19)*(8/32) V11-(V11-V19)*(12/32) V11-(V11-V19)*(16/32) V11-(V11-V19)*(20/32) V11-(V11-V19)*(24/32) V11-(V11-V19)*(28/32) VINP6 V19-(V19-V27)*(4/32) V19-(V19-V27)*(8/32) V19-(V19-V27)* (12/32) V19-(V19-V27)* (1632/) V19-(V19-V27)* (20/32) V19-(V19-V27)* (24/32) V19-(V19-V27)* (28/32) VINP7 V27-(V27-V36)* (4/36) V27-(V27-V36)* (8/36) V27-(V27-V36)* (12/36) V27-(V27-V36)* (16/36) V27-(V27-V36)* (20/36) V27-(V27-V36)* (24/36) V27-(V27-V36)* (28/36) V27-(V27-V36)* (32/36) VINP8 V36-(V36-V44)*(4/32) V36-(V36-V44)*(8/32) V36-(V36-V44)*(12/32) Voltage Formula (Negative) VINN0 VINN1 VINN2 VINN3 V3-(V3-V6)*(11/30) V3-(V3-V6)*(21/30) VINN4 V6-(V6-V11)*(7/30) V6-(V6-V11)*(14/30) V6-(V6-V11)*(20/30) V6-(V6-V11)*(25/30) VINN5 V11-(V11-V19)*(4/32) V11-(V11-V19)*(8/32) V11-(V11-V19)*(12/32) V11-(V11-V19)*(16/32) V11-(V11-V19)*(20/32) V11-(V11-V19)*(24/32) V11-(V11-V19)*(28/32) VINN6 V19-(V19-V27)*(4/32) V19-(V19-V27)*(8/32) V19-(V19-V27)* (12/32) V19-(V19-V27)* (1632/) V19-(V19-V27)* (20/32) V19-(V19-V27)* (24/32) V19-(V19-V27)* (28/32) VINN7 V27-(V27-V36)* (4/36) V27-(V27-V36)* (8/36) V27-(V27-V36)* (12/36) V27-(V27-V36)* (16/36) V27-(V27-V36)* (20/36) V27-(V27-V36)* (24/36) V27-(V27-V36)* (28/36) V27-(V27-V36)* (32/36) VINN8 V36-(V36-V44)*(4/32) V36-(V36-V44)*(8/32) V36-(V36-V44)*(12/32)
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40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 V36-(V36-V44)*(16/32) V36-(V36-V44)*(20/32) V36-(V36-V44)*(24/32) V36-(V36-V44)*(28/32) VINP9 V44-(V44-V52)*(4/32) V44-(V44-V52)*(8/32) V44-(V44-V52)*(12/32) V44-(V44-V52)*(16/32) V44-(V44-V52)*(20/32) V44-(V44-V52)*(24/32) V44-(V44-V52)*(28/32) VINP10 V52-(V52-V57)*(5/30) V52-(V52-V57)*(11/30) V52-(V52-V57)*(17/30) V52-(V52-V57)*(23/30) VINP11 V57-(V57-V60)*(8/30) V57-(V57-V60)*(18/30) VINP12 VINP13 VINP14 VINP15 V36-(V36-V44)*(16/32) V36-(V36-V44)*(20/32) V36-(V36-V44)*(24/32) V36-(V36-V44)*(28/32) VINN9 V44-(V44-V52)*(4/32) V44-(V44-V52)*(8/32) V44-(V44-V52)*(12/32) V44-(V44-V52)*(16/32) V44-(V44-V52)*(20/32) V44-(V44-V52)*(24/32) V44-(V44-V52)*(28/32) VINN10 V52-(V52-V57)*(5/30) V52-(V52-V57)*(11/30) V52-(V52-V57)*(17/30) V52-(V52-V57)*(23/30) VINN11 V57-(V57-V60)*(8/30) V57-(V57-V60)*(18/30) VINN12 VINN13 VINN14 VINN15
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13 Example Connection with Panel direction and Different Resolution
13.1 Application of connection with panel direction
Case 1: (This is default case) st - 1 Pixel is at Left Top of the panel - RGB filter order = RGB
1st pixel
IC (Bump down) LCD Front side
CF Glass
TFT Glass
Case 2: st - 1 Pixel is at Left Top of the panel - RGB filter order = BGR
1st pixel
CF Glass
TFT Glass
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Case 3: st - 1 Pixel is at Righ Bottom of the panel - RGB filter order = RGB

1st pixel
CF Glass
TFT Glass
Case 4: st - 1 Pixel is at Righ Bottom of the panel - RGB filter order = BGR

1st pixel
CF Glass
TFT Glass
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13.2 Application of connection with Different resolution
Case1 of Resolution (128RGB x 160) (GM[2:0] = 011) RAM size=128 x 160 x 18-bit (Used) Display size = 128RGB x 160 1). Example for SMX=SMY=0
2). Example for SMX=SMY=1
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Case2 of Resolution (132RGB x 162) (GM[2:0] = 000) RAM size=132 x 162 x 18-bit (Used) Display size = 132RGB x 162 1). Example for SMX=SMY=0
Driver IC (bump down)
G161 G3 S7 S390 G2 G160
GRAM size = 132 x 162 x 18-bits

(0, 0) 00h 01h 02h 00h 01h 02h G4 G2 1st pixel G3 82h 83h
P1 P2 P3 P130 P131 P132
G1
G159 (131, 161) A0h A1h G162 G160 G161
- Display direction control (S/W) - X-Mirror control by MX - Y-Mirror control by MY - XY-Exchange control by MV
- Direction default setting (H/W) SMX = '0' SMY = '0' SRGB = '0'
2). Example for SMX=SMY=1
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13.3 MicroProcessor Interface applications
8080-Seriers MCU + SPI Interface ( IM2=1)
13.3.1 8080-Series MCU Interface for 8-bit data bus (IM1, IM0=00)
Driver IC RESX TE RESX TE SCL SDA
Host
D/CX (SCL) WRX RDX D7 to D1 D0 0 0
D/CX WRX RDX D7 to D1 D0 D15 to D8 D17 to D16
Note: IM2=0, SPI I/F IM2=1, MCU I/F
00 IM2
IM1,IM0 IM2
Fig. 13.3.1 8080 Series MCU Interface for 8-bit data bus
Host RESX TE Driver IC RESX TE SCL SDA
D/CX (SCL) WRX RDX D7 to D1 D0 D15 to D8 0
01 IM2
IM1,IM0 IM2
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D/CX (SCL) WRX RDX D8 to D1 D0 0 0 Note: IM2=0, SPI I/F IM2=1, MCU I/F
10 IM2
IM1,IM0 IM2
D/CX (SCL) WRX RDX D7 to D1 D0 D17 to D8
D/CX WRX RDX D7 to D1 D0 D17 to D8
11 IM2
IM1,IM0 IM2
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14 Revision History
ST7735 Specification Revision History Version 1.0 Date 2008/11/27 Description First issue. Modify address counter description (P58) Modify DISPOFF(28h) and DISPON(29h) command description (P97~98) Modify frame rate control command (B1~B3h) description (P122~124) Modify ROM code default value (P122~140) Modify external components table, AVDD capacitance value change and schottky diode remove. (P154~155) Modify VCC maximum absolute operating voltage (P18) Modify power consumption condition (P20) Modify VMCTR1(C5h) command restriction (P138) Modify the parameter of command 0xDF(P145) Add AVDD, VCI1 voltage.(P16,P128, P154) Add fOSC value (P122, P123, P124) Modify the setting values of VCOM table with HEX. Modify AVDD voltage.( P154) Modify the descriptions in command table with HEX. Modify EXTC description.(P14) Modify VCI1 description to Hi-Z.(P16)
1.1
2009/01/05
1.2
2009/03/09
1.3
2009/08/05
1.4
2009/08/28
1.5
2009/09/01
1.6
2009/09/23
1.7 1.8 1.9
2009/12/04 2009/12/24 2010/01/19
Modify DISSET5 (B6h) command (P126) Modify command 0xDF description (P146) Add Chip information drawing (P5)
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Parallel Interface: 8-bit/9-bit/16-bit/18-bit Serial Interface: 3-line/4-line

Size 16 um 16 um 98 um 19 um 16 um 1568 um2 59 um

H K K2 L Boundary (Include scribe Lane)

Pad Center Coordinates

162 Gate buffer 396 Source buffer Voltage reference

Level shifter DAC Gamma circuit Gate decoder Level Shifter

Display Ram 132 x 162 x 18bits

Color conversion LUT table

EEPROM Booster 1/2/4

C11N C41P C41N C22P C22N C23P

CSX RDX (E)

VDD VDDI AVDD VCL VGH VGL

WRX (D/CX) D[17:0]

-Panel resolution selection pins. G

Selection of panel resolution

TESEL=0 , TE output 162 lines TESEL=1 , TE output 160 lines

Capacitor Common electrode Step-up Capacitor Step-up Capacitor

C11P, C11N C22P, C22N C23P, C23N C41P, C41N

- Capacitor connecting pins for step-up circuit 1 (for AVDDO)

Connect pin DGND

-Please connect these pins to DGND.

-Please open these pins.

VCOMH VCOML VCOMAC

Ccom=12nF Ccom=12nF |VCOMH-VCOML|

2.5 -2.4 4.0

5.0 0.0 6.0

Vsout GVDD Below with 99% precision

0.01 0.01 0.01 0.01 0.005

One Line N/A

Note 1 Note 2 N/A

Symbol TAST TAHT TCHW TCS

Min 10 10 0 15 45 350 10 10 100 30 30 160 90 45 450 150 150

TRCS TRCSFM TCSF TCSH TWC

TWRH TWRL TRC

TRDH TRDL TRCFM

When read ID data

RDX (FM) TRDHFM TRDLFM ns ns

When read from frame memory

Table 8.1.1 Parallel Interface Characteristics

Note: VDDI=1.65 to 3.3V, VDD=2.6 to 3.3V, AGND=DGND=0V, Ta=25

TR VIH=0.7 x VDDI VIL=0.3 x VDDI TR=TF<=15ns

TR VOH=0.8 x VDDI VOL=0.2 x VDDI TR=TF<=15ns

Fig. 8.1.3 Chip selection (CSX) timing

Fig. 8.1.4 Write-to-read and read-to-write timing

TCHW TSCYCW/TSCYCR TCSS TCSH

TSLW/TSLR TSHW/TSHR TSDS TSDH

Fig. 8.2.1 3-line serial interface timing

Symbol TCSS TCSH

TCSS TSCC TCHW TSCYCW TSHW

TSLW TSCYCR TSHR TSLR TSDS

SDA (DIN) (DOUT)

TSDH TACC TOH

For maximum CL=30pF For minimum CL=8pF

Table 8.2.1 3-line Serial Interface Characteristics

Fig. 8.3.1 4-line serial interface timing

Symbol TCSS TCSH

TCSS TSCC TCHW TSCYCW TSHW

Table 8.3.1 4-line Serial Interface Characteristics

Table 9.1.1 Selection of MCU interface

RDX Note1 RDX RDX RDX RDX

WRX Note1 WRX WRX WRX WRX

D/CX SCL D/CX D/CX D/CX D/CX

Table 9.1.2 Pin connection according to various MCU interface