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Minimization of Switching Activities of Partial Products for Designing Low Power Digital Multipliers Using 3 Different Adder Cell

J.Vivek Kumar, PG Scholar, jvivekkumarme@gmail.com Angel College of Engineering and Technology, Tirupur B.M.Prabhu, Assitant Professor, bmprabhu16@gmail.com Angel College of Engineering and Technology, Tirupur Dr.S. Padma Professor, swanisha@gmail.com Sona College of Technology, Salem

Abstract: This article presents the design of multiplier. It means to perform a repeated addition while processing the addition we can get a multiplier and the performance of any processor or controller will depend upon its power, size and delay. So the power, size and delay should be less in order to get an effective processor or controller. Each and every processor has ALU (Arithmetic logic units). That ar ithmetic operation includes Addition, Subtraction, Multiplication, Division, shifter and many units. Multiplication is an important function in arithmetic operations, and it is more complex to develop the next level of bits. To illustrate the proposed multipliers exhibiting low power dissipation, the theoretical analyzing switching activates of partial products are derived and it is also used in DSP, multiplication process is used in many application like measurements and instrumentation applications such as filters, communication, Image processing, Robotics, Intelligence of embedded systems, special effects and graphics etc., The multiplier circuits are schematized and their layouts are design and generated by using VLSI CAD tools.

I. INTRODUCTION

BY increasing the demand on having, microprocessor and microcontroller with high speed and low power, designers should meet lot of problems In fact half adder is the most frequently used in processor for need of doing operation like adder, subtract, multiply and divide. To getting a various operation in ALU in such a wise of list multiplier unit is one of major units, with the highest level of power consumption and lowest speed. The multiplier is a basic building block in processor and controller. Multipliers having wide application in recent trends of embedded world. Multiplier is the processing of adding a number of partial products. It can be perform incisively mentioned that if speed, size and power of this multiplier unit is optimized, when the whole system can optimized in speed, size and power. For optimizing the partial product in those parameters, in the design of digital calculation systems, many units are applied. Now the embedded world everywhere needs this technique for its size, speed and power are consumed. Multiplier is performed an operation like a repeated addition so such additions are in digital electronic technique by full adder and half adder. The difference between full adder and half adder is that in half adder there is no input carry. For designing multiplier unit, which frequently is used in processing DSP, adder unit is used. But in some part of portion in partial product of multiplier unit half adder can also be used instead of full adder, because in comparison to full adder, half adder has low power consumption power and it perform a high speed, Because of by the reason the fewer number of transistor only used. In the operation of planner MOSFET scaling down of CMOS technology leads severe short channel effects will lead to degrade the performance. In designing digital integrated systems, occupied

RES Publication 2012 http://www.resindia.org

space, that is the number of transistor, are of high importance for designer. The lowest space is occupied by units, the best integration process can be done and make as a good result systems with higher speed and lower power can be designed.

CMOS based multiplier is existing method by based on Boolean method. Here the Shannon based logic adder is used to get reduce the number of transistor in CMOS and the power, size also be reduced. While if we can reduce the number of transistor in adder means we can also implement in multiplier, regarding to design an 8x8 multiplier using by a Shannon full adder based, Unless taking the power consumption is dramatically reduced, the result will get a best processor package and performance of VLSI circuits and systems.

The proposed 10T full adder uses the concept of pass transistor logic based multiplexer. The pass transistor design reduces the parasitic capacitances and results in fast circuits. The multiplexer is implemented using pass transistors for carry generation. This design is simple and efficient in terms of area and timing. The proposed 10T full adder circuit can be visualized by modifying the equations (1) as accordingly The modified equations for 10T full adder design sum=a b c =>(a b) c carry=ab+bc+ca (1) =>ab+(a b)c

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International Journal of Modern Electronics and Communication Engineering (IJMECE) Volume No.-1, Issue No.-5, November, 2013

The multiplexer using pass transistor logic can be visualised in 2T model, the select signal for the multiplexer here is (a b). The equations have modified such that select signal is in the form of (a b). The (ab) signal is generated by using the tri-state inverter for (a' b)=>(a' b)^' b=(a+b' )b=>ab+bb'=>ab (2) The sum is generated by implementing 3T XOR module twice. Carry is generated by using pass transistor logic based multiplexer whose select line is (a b) as shown in Figure. 1.

In this design instead of using two NMOS pass transistor devices we have used one NMOS and one PMOS pass transistor device, because of ease of the design and as according to the equation as shown in Figure 7.6.It must be noted that PMOS transistor passes ' l' very good, but cannot pass '0' completely thus, the carry output has weak '0'. NMOS transistor passes '0' very good, but cannot pass '1' completely therefore, the carry output has weak ' 1 ', Having weak '0' and '1' at carry outputs is one of the disadvantages of proposed 8T full adder circuit. In practical situations, this problem can be solved by using an inverter at carry output, but this solution leads to increased power and area.

V. 6 TRANSISTOR ADDER

In the proposed 6T full adder sum is generated using 2T XOR module twice, and carry is generated using NMOS and PMOS pass transistor logic devices as shown in Figure. 3. The equations (Eq 4) are modified so as to visualise the 6T full adder design. And operation of 6 transistor adders shown the performance by Table 2 and Table 3 shown below The modified equations for 6T full adder design are: sum=(a b) c =>(a b) c'+(a b)'c carry=ab+bc+ca =>(a b)^' a+(a b)c (4) In this design (a xor b) signal is passed to the pass transistor multiplexer made of two transistors to choose one among two. To generate carry (a xor b) is sent to multiplexer to choose between a, c. and to generate sum (a xor a) is sent to choose between c`, c.

In the proposed 8T full adder sum is generated using 3T XOR module twice, and carry is generated using NMOS and PMOS pass transistor logic devices as shown in Figure. 2. The equations (4) are modified so as to visualize the 8T full adder design. And operation of 8 Transistor adders shown the performance by Table 2 and Table 3 shown below. The modified equations for 8T full adder design are: sum=a b c =>(a b) c carry=ab+bc+ca (3) =>ab+bc(a+a' )+ac(b+b') =>ab+(a b)c =>(a' b)' b+(a b)c

Figure.3 6 Transistor Adder As per the normal full adders table shown in Table.1 Table.1 Truth table of full adder

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

SUM 0 1 1 0 1 0 0 1

CARRY 0 0 0 1 0 1 1 1

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International Journal of Modern Electronics and Communication Engineering (IJMECE) Volume No.-1, Issue No.-5, November, 2013

In this paper, we have going to propose a 10 Transistor, 8 Transistor, and 6 Transistor adder based multiplier here completely using by this multiplier when we have designed and analyzed carry save adder (CSA) multiplier circuit using based on these three adder cell. The designed feature size is 20m and corresponding supply voltage is 5v. And then various voltages based shown in table of content. The carry save multiplier is a linear array multiplier as shown in Figure.4. The linear multiplier propagates data down through the array cell. Each row of CSAs adds one additional partial product to the partial sum. As the operand size increases, linear array grow at a rate equal to the square of the operand size because the number of rows in the array is equal to the length of the multiplier, and the width of each row is equal to the width of the multiplicand.

VII.

In the multiplier array, a full adder with balanced carry and sum delays is desirable because the sum and carry signals are in the critical path. The speed and power of the full adder are very important for large arrays. The 8x8 bit multiplier circuits were simulated with a BSIM4 layout model. We compared the simulated results of our proposed 1-bit adder cell with existing authors results which shows better performance in terms of power dissipation and area. Our proposed 1-bit adder cell consumes less power, and less area than the various proposed 1-bit adder cells, due to regular arrangement of transistor tree structure, less critical path and multiplexing method of designs. The area is reduced by 48% for proposed 12T design, the area is reduced by 66% for proposed 8T design and area is reduced by 53% when compared to 28T conventional full adder design. The only drawback of our proposed adder cell is that it occupies larger area. From the simulated results it is clear that the multiplier circuits designed based on the proposed adder cell gives better performance in terms of power, area than the CPL-based adder cell. The main reason for the lower propagation delay of 10 Transistor, 8 Transistor, and 6 Transistor adder based multipliers is that they are balanced in the carry circuits.

VIII.

RESULT

By here we have shown in the Fig.3. 4*4 multiplier by using 10 Transistor, 8 Transistor, and 6 Transistor adderbased multipliers as it similar same to 16*16, 32*32, 64*64 etc. Here we shown tabulation as 8 bit multiplier and it has executed by low power consumption compared with normal gates based adder cell. And to implement all three adders in this Array multiplier and Baugh wooley Multipliers

Performance analysis of 10 Transistor, 8 Transistor, and 6 Transistor adder is obtained using simulated output. Hence here worked with Array multiplier and Baugh wooley multiplier by using a 10 Transistor, 8 Transistor, and 6 Transistor adder.

TABLE.2. 10 TRANSISTOR, 8 TRANSISTOR, AND 6 TRANSISTOR ADDER BASED ARRAY MULTIPLIER OPERATING WITH 1.5 VOLT MULTIPLIER

S.no 1 2 3

Input bits 8*8 Array Multiplier 8*8 Array Multiplier 8*8 Array Multiplier

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International Journal of Modern Electronics and Communication Engineering (IJMECE) Volume No.-1, Issue No.-5, November, 2013

TABLE.4. 10 TRANSISTOR, 8 TRANSISTOR, AND 6 TRANSISTOR ADDER ADDER BASED OPERATING WITH 1.5 VOLT MULTIPLIER

S.no 1

Input bits

Area m2 0.040568

159.43

818

0.035992

122.69

8.15

1.29

660.32

698

0.030712

128.70

7.77

5.13

Here the various volt based we have shown the Table.2 and Table.3 as operating with 1.5 volt performed an operation in multiplier by using 10 Transistor, 8 Transistor, and 6 Transistor adder cell and then when we going to increase a power the switching activities are increased at similarly when we operate with 1.5v that means low power consumed operating multiplier is getting a better result so that is major role of operation in this multiplier It take an operation getting a low power and get perfect result is possible in 10 Transistor, 8 Transistor, and 6 Transistor adder cell.

IX. CONCLUSION

The Shannon adder based Carry save adder multipliers circuits are simulated by using Tanners s-edit VLSI CAD tools and Parameters values are analyzed by using same tool. The circuits were compared with existing circuits. 10 Transistor, 8 Transistor, and 6 Transistor adder adder based multiplier gives better performance than existing circuits in term of power dissipation and Area. The proposed multiplier circuits can be used in the low power application of VLSI circuits.

[2] C.Senthilpari, K.Diwakar and Ajay Kumar Singh Low Power and High Speed 8x8 Bit Multiplier Using Non-clocked Pass Transistor Logics November 2009 [3] Nabiallah Shiri Asmangerdi, Javad Forounchi and Kuresh Ghanbari, A new 8- Transistor Floating Full-Adder Circuit, IEEE Trans. 20th Iranian Conference on Electrical Engineering, (ICEE2012), pp.1405-1409, May, 2012. [4] Yi WEI, Ji-zhong SHEN, Design of a novel low power 8transistor 1-bit full adder cell, Journal of Zhejiang UniversitySCIENCE C (Computers & Electronics), vol. 7,pp 504-507, Dec 2011. [5] AK. Singh, C.M.R. Prabhu, K.M.Almadhagi, S.F. Farea, K. Shaban,"A Proposed 10T Full Adder Cell for Low Power Consumption", International Conference on Electrical Engineering/Electronics Computer Telecommunications and Information Technology (ECTICON), pp. 389 -391, 2010. [6] IIham Hassoune, Denis Flandre, .IeanDidier Legat," ULPF A: A New Efficient Design of a Power Aware Full Adder", IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 57, pp. 2066 - 2074, August 2010. [7] J.-F. Lin, Y.-T. Hwang, M.-H. Sheu and C.-C. Ho, A novel high speed and energy efficient 10-transistor full adder design, IEEE Trans. Circuits Syst. I, vol. 54, no. 5, pp. 1050 1059, May 2007. [8] Amir Ali Khatibzadeh, Kaamran Raahemifar, "A 14TRANSISTOR LOW POWER HIGHSPEED FULL ADDER CELL", Canadian Conference on Electrical and Computer Engineering, vol. I, pp. 163-166, 2003. [9] Padmanabhan Balasubramanian and Nikos E. Mastorakis High Speed Gate Level Synchronous Full Adder Designs WSEAS Transactions on circuits and systems February 2009. [10] Z. Abid, H. El-Razouk, D.A. El-Dib Low power multipliers based on new hybrid full adders Microelectronics. J (2008), doi: 10.1016/ j.mejo.2008.04.002. [11] Reto Zimmermann and Wolfgang Fichtner Low-Power Logic Styles: CMOS versus Pass- Transistor Logic IEEE Journal of Solid-State Circuits, Vol.32, No.7, April 1997, pp.10791090. [12] Kiamal Z.pekmestzi speed comparison of 1616 Vedic Multiplier,internation journal of computer applications May 2011.

X. FUTURE WORK

In this paper, power dissipation and area of the multiplier using the proposed adder cell is compared with other multipliers designed using existing adders and used in DSP, multiplication process is used in many application like measurements and instrumentation applications such as filters, communication, Image processing, Robotics, Intelligence of embedded systems, special effects and graphics etc., Further it can be used in applications such as FIR filter, FFT, Rank order filters where adders and multipliers plays a major role.

REFERENCE

[1] Karthik Reddy. G Low Power -Area Designs Of 1bit Full Adder In Cadence Virtuoso Platform International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.4, August 2013.

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[13] Hajira Fathima, Jahangeer Md & Kaleem Fatima Design of Low Power Shannon Based Adder cell using Multipliexing control Input Technique. [14] Harshvardhan Upadhyay Comparsion and Abhishek Choubey Comparison for leakage reduction in CMOS inverter with Stack keeper in VLSI design [15] J. Lin and Y. Hwang:A Novel High -Speed and Energy Efficient 10-Transistor Full Adder Design, IEEE Transactions on Circuits and Systems, Vol. 54, No. 5, May 2007. [16] Y. Jiang, A. Al-Sheraidah, Y. Wang, E. Sha, J. Chung, A novel multiplexer-based low-power fullAdder.IEEE Transactions on Circuits and Systems-II: Express Briefs. v51 i7.

AUTHORS BIOGRAPHY

J.VivekKumar. B.E,( M.E) received his B.E., degree in Electronics and communication Engineering from Maharaja Prithvi Engineering college (2012) Avinashi, Tirupur. He is pursuing M.E Embedded Systems PG scholar in Angel College of Engineering and Technology, Tirupur and his area of Interest are Embedded Systems, Microcontroller and Processors, VLSI. Prof.B.M.Prabhu, M.E., (Ph.D)., received his B.E., Electrical and Electronic Engineering from Anna University Chennai and M.E., VLSI Design from Anna University Coimbatore. He is currently Ph.D in the field of Low Power VLSI. He has published 12 paper national conferences, 2 in international conferences and 2 international journals. Dr. S. Padma, M.E., Ph.D., Professor, Department of Electrical and Electronics Engineering Sona College of Technology, Salem she received her B.E., Electrical and Electronics Engineering from Govt. College of Engineering, Salem-11 and M.E., Power Systems Engineering from Annamalai University and Ph.D Flexible AC Transmission Systems from Anna University, Chennai, and 19 years of teaching experience then she has 5 Memberships in Professional bodies, she have published 11 International Journals, 11 National conferences and 3 International conference and she has published 6 books.

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