EE5349/Spring 2003

Quadrature Phase Shifter Implemented by Polyphase Filter

Instructor: Dr. Khoja

By

Jasper Tong Chen Liao Mingsheng Peng

Abstract
As an extension to the second phase of the RFIC project we designed a phase shifter that takes a single ended source as its input and provides four output signals of same frequency as the input in four different quadrature phases. The designed circuit was simulated in ADS and the tests were conducted on the phases and the amplitudes of the output signals. The integrity of the phase shifter with the previously designed even harmonic mixer was also tested. This was done by integrating the design of the phase shifter as a block into the mixer design.

1. Introduction
In our project, we designed a direct conversion receiver that would require low power and small form factor. In order to eliminate the DC-offset, an even harmonic mixer[1] was designed to perform the task. This mixer needs four input sources in quadrature with two sets of amplitudes for it to function. Therefore there arise a need to obtain four quadrature output signals from a low power single ended input. The phase shifter is shown in Figure 1.

Figure 1 Double-balanced CMOS even-harmonic mixer[1].

A number of options for the design of the implementation of the phase shifter have been considered. The first solution is to design the phase shifter in the digital domain and then converting it to analog domain. The bottleneck in digital implementation has been the speed of the digital components. Using a mixer to upconvert the phase shifted signals to the required LO frequency would require four mixers, which would be hard to integrate and would also introduce more noise and non-linearities to the system. The second option was to use transmission lines, which is not feasible in integrated circuits. The best option is to use RC -1-

polyphase networks[2][3][4] to introduce the phase changes. In this project, we designed a quadrature phase shifter implemented by polyphase filter.

2. Theory of polyphase filter

The polyphase filter is an intriguing filtering circuit that has a frequency transfer function that is not symmetrical about the zero frequency. This characteristic of the filter has been used in many transceiver circuits to implement positive frequency mixing so as to solve the problem of image signal. Due to the symmetric layout of the circuit, the polyphase filter has been able to produce equally balanced quadrature signals at its output. This attribute will be put to use in our design of the polyphase phase shifter. Figure 2 is a simple RC lay out of the polyphase phase shifter[3].

Figure 2 Polyphase filter used to generate differential a quadrature phases from differential input.

The polyphase phase shifter utilizes the simple concept of RC circuits. The relationship among the value of R, C, and in the polyphase filter is[3] RC = 1 (1)

For a frequency of 1.07 GHz, assuming a realistic value of R in integrated circuit to be 100 , we get the value of C to be 1.4874 pf using the equation (1). Now that we have the values of R and C, we can design the phase shifter circuit as shown in Figure 3.

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Figure 3 Polyphase phase shifter circuit with ideal differential signal input.

As can be seen from Figure 3, the differential source required by the phase shifter is provided by passing the signal from a single ended source through a balun to provide the ideal differential signals. The output of the phase shifter with this ideal source is shown in Figure 4.

Figure 4 Plot of output voltage of phase shifter with ideal differential source vs. time.

We can see from Figure 4, that the output of each of the branches of the phase shifter is in quadrature with the neighboring branch. The amplitudes of the -3-

sinusoids are also equal, which is the same as mentioned before. Figure 5 shows the phase for each output of the ideal polyphase phase shifter.

Figure 5 Phase for each output of the ideal polyphase phase shifter.

With the completion of the phase shifter, we will begin the design of the complete circuit including differential signal converter and output matching circuit.

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3. Complete circuit design of polyphase phase shifter

The ADS schematic of the entire polyphase phase shifter system is shown in the Figure 6. Figure 6 shows that the circuit includes the differential signal converter, buffer, polyphase shifter and output matching.

Figure 6 Complete circuit design of polyphase phase shifter.

In the complete circuit, the differential amplifier converts the single ended source to a differential source with 180 degrees of phase difference. The layout of the differential amplifier is shown in Figure 7. Figure 8 shows the outputs of the differential amplifier. The first two plots are the two single-end outputs of the differential amplifier; the third one shows the differential output. From the first two plots, we can see that they are indeed 180 apart.

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Figure 7 The differential amplifier to produce differential signals.

Figure 8 The outputs of the differential amplifier.

Figure 9 is the buffer circuit used to isolate the differential amplifier and the polyphase filter. The buffer is used to isolate the phase shifter from the output of the differential amplifier. The reason for adding the buffer is to ensure that resistances and capacitances of the latter stages will not affect the load impedance of the differential amplifier, and thus the differential amplifier output will be more stable. -6-

Figure 9 Buffer used to isola te the differential amplifier and the polyphase filter.

Figure 10 is the output of the buffer. The first two plots are the two single-end outputs from the buffer; the third one shows the differential output. From the first two plots, we can see that they are indeed 180 apart.

Figure 10 The outputs of the signals from the buffer.

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The output of the buffer is fed to the input of the polyphase phase shifter, the output of the polyphase phase shifter is shown in Figure 11.

Figure 11 The outputs of the polyphase filter.

With the completion of the phase shifting, we need to come up with a solution to satisfy the output requirements. As required by the even harmonic mixer, we will need two inputs at a DC bias of 2.1V with phases of 0 and 180 and amplitude of 0.5V. The other two inputs with 90 and 270 will require DC bias of 2.8V and amplitude of 0.5V. Due to this requirement and the unequal amplitude and bias output of the phase shifter, a matching stage that is a CS amplifier stage, is needed for each of the branch outputs of the phase shifter. This will provide us with the required phase, amplitude and DC bias at the output of the phase shifter system. All four amplifiers are designed according to a common-source amplifier layout as shown in Figure 12.

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Figure 12 Circuits of the output amplifier stages. The left circuit is for 2.1V signal, the right circuit is for 2.8 signal.

Figure 13 shows the final outputs from the matching circuit. The plots show that the bias and the amplitude requirements are satisfied.

Figure 14 The outputs of the amplifier stage.

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Table 1 gives the phases of each of the individual output shown in the Figure 13. It can seen that the maximum phase error is less than 0.4 .
Table 1 The phases of the outputs from the amplifier stage.

4. Simulation of the phase shifter with the even-harmonic mixer

Two system simulations, IP3 and noise figure, were conducted. In the system simulation, the designed phase shifter was embedded into the even-harmonic mixer system. Figure 14 shows ADS diagram for IP3 simulation of the phase shifter with the even-harmonic mixer.

Figure 15 IP3 simulation of the phase shifter with the even-harmonic mixer.

Figure 16 shows the results of the IP3 system simulation. The value of the IIP3 is 1.694 dBm.

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Figure 16 The simulation results of IIP3.

Figure 17 shows the noise figure simulation of the phase shifter with the evenharmonic mixer.

Figure 17 Noise figure simulation of the phase shifter with the even-harmonic mixer.

Table 2 shows the results of the noise figure system simulation. The value of the noise figure is 65.426 dB. The noise figure is quite high. The reason is we did perform the optimal design for noise figure.

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Table 2 The results of noise figure simulation.

5. Conclusions
The main objectives of this project have been achieved. The designed phase shifter has successfully produced four quadrature outputs from one single ended input. The two different sets of voltages required by the input of the even-harmonic mixer have also been satisfied. Much consideration has been placed in the design process to achieve realistic implementation and integration. However, system simulation of noise figure presents quantities that leave much to be desired. The noise figure of the complete mixer system including the phase shifter showed a very high noise figure level. With more time, the system can be tuned to produce a noise figure of an acceptable level.

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Reference
[1] S. J. Fang, S. T. Lee, D. J. Allstot, A. Bellaouar, A 2 GHz CMOS even harmonic mixer for direct conversion receivers, IEEE International Symposium on Circuits and Systems , vol. 4, pp. IV807-IV810, 2002. [2] Tetsuo Yoshida, Polyphase Network Calculation using a Vector Analysis Method, QEX, pp. 9-15, June, 1995. [3] F. Behbahani, Y. Kishigai,J. Leete, and A. A. Abidi, COS mixer and polyphase filters for large image rejection, IEEE Journal of solid-state circuits, vol. 36, no. 6, pp. 873-887. [4] J. A. Weldon, R. S. Narayanaswami, J. C. Rudell, L. Lin, M. Otsuka, S. Dedieu, L. Tee, K.C. Tsai, C. W. Lee, and P. R. Gray, A 1.75-GHz highly integrated narrow-band CMOS transmitter with harmonic-rejection mixers, IEEE Journal of Solid-State Circuits, vol. 36, no. 12, pp. 2003-2015, Dec. 2001.

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