1

Lecture 23, Slide 1 EECS40, Fall 2003 Prof. King

Lecture #23
Warning for HW Assignments and Exams:
Make sure your writing is legible !!
OUTLINE
MOSFET I
D
vs. V
GS
characteristic
Circuit models for the MOSFET
resistive switch model
small-signal model
Reference Reading
Rabaey et al.: Chapter 3.3.2
Howe & Sodini: Chapter 4.5
Lecture 23, Slide 2 EECS40, Fall 2003 Prof. King
MOSFET I
D
vs. V
GS
Characteristic
Long-channel MOSFET
V
DS
= 2.5 V > V
DSAT
Short-channel MOSFET
V
DS
= 2.5 V > V
DSAT
Typically, V
DS
is fixed when I
D
is plotted as a function of V
GS
2
Lecture 23, Slide 3 EECS40, Fall 2003 Prof. King
MOSFET V
T
Measurement
V
T
can be determined by plotting I
D
vs. V
GS
,
using a low value of V
DS
:
DS
DS
T GS n D
V
V
V V
L
W
k I
(

=
2
I
D
(A)
V
GS
(V)
V
T
0
Lecture 23, Slide 4 EECS40, Fall 2003 Prof. King
Subthreshold Conduction (Leakage Current)
The transition from the ON state to the OFF state
is gradual. This can be seen more clearly when
I
D
is plotted on a logarithmic scale:
In the subthreshold
(V
GS
< V
T
) region,
This is essentially the channel-
source pn junction current.
(Some electrons diffuse from the
source into the channel, if this
pn junction is forward biased.)
|
.
|

\
|

nkT
qV
I
GS
D
exp
V
DS
> 0
3
Lecture 23, Slide 5 EECS40, Fall 2003 Prof. King
Qualitative Explanation for Subthreshold Leakage
The channel V
c
(at the Si surface) is capacitively
coupled to the gate voltage V
G
:
ox
dep
ox
dep ox
C
C
C
C C
n + =
+
= 1
C
ox
C
dep
+
V
c

V
G
Using the capacitive
voltage divider formula
(Lecture 12, Slide 7):
p-type Si
n+ poly-Si
n+ n+
depletion
region
V
G
CIRCUIT MODEL DEVICE
The forward bias on
the channel-source pn
junction increases with
V
G
scaled by the factor
C
ox
/ (C
ox
+C
dep
)
V
D
G
dep ox
ox
c
V
C C
C
V
+
=
A dep
Si
dep
N W
C
1
=

W
dep
Lecture 23, Slide 6 EECS40, Fall 2003 Prof. King
Slope Factor (or Subthreshold Swing) S
S is defined to be the inverse slope of the log (I
D
)
vs. V
GS
characteristic in the subthreshold region:
V
DS
> 0
1/S is the slope
) 10 ln(
|
|
.
|

\
|

q
kT
n S
Units: Volts per decade
Note that S 60 mV/dec
at room temperature:
mV 60 ) 10 ln( =
|
|
.
|

\
|
q
kT
4
Lecture 23, Slide 7 EECS40, Fall 2003 Prof. King
V
T
Design Trade-Off
(Important consideration for digital-circuit applications)
Low V
T
is desirable for high ON current
I
DSAT
(V
DD
- V
T
)

1 < < 2
where V
DD
is the power-supply voltage
but high V
T
is needed for low OFF current
Low V
T
High V
T
I
OFF,high VT
I
OFF,low VT
V
GS
log I
DS
0
Lecture 23, Slide 8 EECS40, Fall 2003 Prof. King
The MOSFET as a Resistive Switch
For digital circuit applications, the MOSFET is
either OFF (V
GS
< V
T
) or ON (V
GS
= V
DD
). Thus,
we only need to consider two I
D
vs. V
DS
curves:
1. the curve for V
GS
< V
T
2. the curve for V
GS
= V
DD
I
D
V
DS
V
GS
= V
DD
(closed switch)
V
GS
< V
T
(open switch)
R
eq
5
Lecture 23, Slide 9 EECS40, Fall 2003 Prof. King
Equivalent Resistance R
eq
In a digital circuit, an n-channel MOSFET in the
ON state is typically used to discharge a
capacitor connected to its drain terminal:
gate voltage V
G
= V
DD
source voltage V
S
= 0 V
drain voltage V
D
initially at V
DD
, discharging toward 0 V
The value of R
eq
should be
set to the value which gives
the correct propagation
delay (time required for
output to fall to V
DD
):
C
load
|
.
|

\
|

DD n
DSATn
DD
eq
V
I
V
R
6
5
1
4
3
( )
2
2
Tn DD
n
DSATn
V V
L
W k
I

=
Lecture 23, Slide 10 EECS40, Fall 2003 Prof. King
Typical MOSFET Parameter Values
For a given MOSFET fabrication process
technology, the following parameters are known:
V
T
(~0.5 V)
C
ox
and k (<0.001 A/V
2
)
V
DSAT
( 1 V)
( 0.1 V
-1
)
Example R
eq
values for 0.25 m technology (W= L):
How can R
eq
be decreased?
6
Lecture 23, Slide 11 EECS40, Fall 2003 Prof. King
MOSFET Model for Analog Circuits
For analog circuit applications, the MOSFET is
biased in the saturation region, and the circuit is
designed to process incremental signals.
A DC operating point is established by the bias
voltages V
BIAS
and V
DD
, such that V
DS
> V
GS
V
T
Incremental voltages v
s
and v
ds
that are much smaller
in magnitude perturb the operating point
The MOSFET small-signal model is a circuit which
models the change in the drain current (i
d
) in
response to these perturbations
MOSFET
+

R
D
V
DD
V
BIAS
v
s
G
S S
D
I
D
+ i
d
+
V
DS
+ v
ds

+
Lecture 23, Slide 12 EECS40, Fall 2003 Prof. King
NMOSFET Small-Signal Model
g
m
v
gs
r
o
+
v
gs

i
d
( )
D
DS
D
o
T GS
GS
D
m
ds o gs m ds
DS
D
gs
GS
D
d
I
v
i
g
V V k
L
W
v
i
g
v g v g v
v
i
v
v
i
i

+ =

=
S
D
S
G
transconductance
output conductance
+
v
ds