DIRECT DIGITAL SYNTHESIZER

Design of ROM

Cyrus Miller

Department of Electrical and Computer Engineering University of Maine Orono, Maine

Table of Contents
1 ! # % Project Overvie "pecification Overvie $OM Overvie #&1 $OM "tructure "c(ematics %&1 *% +it Memory Units %&! Tree Decoder ,nput %&# Tree Decoder %&% T(e Memory "tructure %&' Pull/Up 0et or1 %&* "ense 2mplifiers %&) Multiple3ers %&4atc( 4ayouts '&1 *% +it Memory Units '&! Tree Decoder ,nput '&# Tree Decoder '&% T(e Memory "tructure '&' Pull/Up 0et or1 '&* "ense 2mplifiers '&) Multiple3ers '&4atc( "i5ing Programming Testing Complete C(ip 1 # % ' ) ) 1. 1% 1* 1) 1!. !! !! !% !' #1 ## #% #' #) #%1 %! %'

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* ) 6

2ppendi3

"tored Memory

%)

Table of 7igures
7ig& 1&1 DD" +loc1 Diagram 7ig& 1&! 8uadrant Diagram 7ig& %&1 *% +it $OM "c(ematic 7ig& %&!&1 Tree Decoder ,nput "c(ematic 7ig& %&!&! Tree Decoder ,nput "c(ematic Overvie 7ig& %&#&1 Tree Decoder "c(ematic Overvie 7ig& %&#&! Tree Decoder "c(ematic 7ig& %&#&# Tree Decoder #rd "tage "c(ematic 7ig& %&#&% Tree 4ine "c(ematic 7ig& %&%&1 Memory Cell One "c(ematic 7ig& %&%&! Memory Cell 9ero "c(ematic 7ig& %&' Pull Up 0et or1 "c(ematic 7ig& %&* "ense 2mp "c(ematic 7ig& %&)&1 Multiple3er "c(ematic 7ig& %&)&! Multiple3er !:1 "c(ematic 7ig& %&-&1 Cloc1ed D 7lip 7lop "c(ematic 7ig& %&-&! Cloc1ed D 7lip 7lop "c(ematic Overvie 7ig& '&1 *% +it $OM 4ayout 7ig& '&!&1 Tree Decoder ,nput 4ayout 7ig& '&!&! Tree Decoder ,nput 4ayout Overvie 7ig& '&#&1 Tree Decoder 4ayout Overvie 7ig& '&#&! Tree Decoder "tage * 4ayout 7ig& '&#&# Tree Decoder "tage ' 4ayout 7ig& '&#&% Tree Decoder "tage % 4ayout 7ig& '&#&' Tree Decoder "tage % 4ayout 7ig& '&#&) Tree 4ine 4ayoutOvervie 1 ! ) 6 1. 11 1! 1# 1% 1' 1* 1) 116 !. !1 !! !# !% !% !' !* !) !!6

Table of 7igures ;continued<

7ig& '&#&) Tree 4ine 4ayout 7ig& '&%&! Memory "tructure 4ayout 7ig& '&%&! Memory "tructure 4ayout Overvie 7ig& '&%&# Memory One 4ayout 7ig& '&%&% Memory One 4ayout Overvie 7ig& '&'&1 Pull/Up 0et or1 4ayout 7ig& '&'&! Pull/Up 0et or1 4ayout Overvie 7ig& '&* "ense 2mplifier 4ayout 7ig& '&)&1 T o to One MU= 4ayout 7ig& '&)&! T o to One MU= 4ayout Overvie 7ig& '&- 4atc( 4ayout 7ig& *&1 Minimum "i5ed Memory Cell 7ig& *&! >eig(t $estricted Tree 4ine 7ig& *&# Minimum "i5ed *% bit $OM 7ig& *&% Minimum "i5ed !'* bit $OM 7ig& )&1 $OM . 7ig& )&! $OM % 7ig& -&1 Testing t(e Tree Decoder 7ig& -&! Testing t(e Tree 4ine 7ig& -&# Testing t(e "ense 2mplifier 7ig& 6 Complete DD" C(ip !6 #. #. #1 #1 #! ## ## #% #' #* #) #) ##6 %. %. %! %# %% %'

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&eece&maine&edu?researc(?vlsi?!..*?Miller?

Project Overview

@e ere tas1ed it( building a Direct Digital "ynt(esi5er ;DD"<, (ic( play an important role in modern digital communications for sine ave generation& T(ere ere t(ree different groups, eac( or1ing on a separate building bloc1 in t(e development of t(is DD"& T(e t(ree building bloc1s are t(e 2ccumulator, t(e $OM and t(e Digital to 2nalog converter& ,n t(is project, my group as to design a !'* bit $OM to store t(e sinusoidal values for DD"& @e ere to accept - inputs from t(e 2ccumulator and output 6 bits to t(e D2C to effectively model t(e output of a sine ave& T(e pieces involved ere four *% bit $OMs, t o !:1 multiple3ers and a latc(& T(e multiple3ers are used to select t(e rig(t $OM and t(eir outputs are latc(ed using D flip/flops& T(is $OM receives its - bit input from a 1! bit, '. M>5 accumulator designed by 2ravind $eg(u& T(e latc(ed outputs are t(en fed to t o 1. bit Digital to 2nalog convertersA one designed by "teve 7ortune and t(e ot(er designed by $ag(u Tumati&

7ig& 1&1 DD" +loc1 Diagram

2s you can see in t(e diagram, t(e accumulator is just a repeating ramping input& ,t goes t(roug( all of t(e memory cells stored in t(e $OM and t(en repeats, not giving a sine ave at all& T(e sine ave comes from t o t(ingsA t(e $OM itself and (ic( Buadrant t(e signal is in&

7ig& 1&! 8uadrant Diagram T(e $OM stores all of t(e values of Buadrant .., but not(ing more& ,t is possible to only (ave 6. degrees of sine information because of t(e repetitive nature of a sine aveA you only need to c(ange certain t(ings to account for eac( Buadrant& T(e $OM Pointer is used to decide (ic( Buadrant, and t(erefore (ic( ord line, s(ould be accessed&

Specificatio Overview

2 DD" system generates one or more freBuency from a single reference freBuency using digital logic& ,n t(is project, my objective as to design a !'* bit $OM (ic( stores t(e amplitude values for eac( p(ase of DD" output aveform& 2 !'* bit $OM could be designed by using four *% bit $OMs to bot( minimi5e t(e capacitance and also occupy less space on t(e c(ip&

De!i" Specificatio !
T(e different specifications t(at ere given for t(e design of a $OM are as follo s:

0ame
0umber of ro s 0umber of columns 7reBuency Coltage

"pecification
!'* 6 '. M>5 . to ' C

Table !&1 Design "pecifications

RO$ Overview

To implement our design specification, e (ad to loo1 realistically at (at can fit into a c(ip& T(e c(ip is about 6.. microns by 6.. microns sBuare, so t(at directly impacted t(e design of our $OM& @e needed to brea1 t(e !'* ro s of memory up into four *% bit $OM bloc1s in order to fitA t(is also (elps lo er t(e capacitance on t(e lines as ell& To ma1e a *% bit $OM, e ould need t(e * 4east "ignificant +its coming from t(e 2ccumulator& +y using t(ese * bits, e could ma1e a tree decoder capable of accessing one of *% different ro s& Eac( time a signal is used, t(e output is split to eit(er a (ig( or lo signal& 2fter using * of t(ese signals, t(e total output can encompass any one of *% ro s, or !*& To lin1 t(ese four bloc1s of $OM toget(er, a t o stage Multiple3er as needed& T(e $OMDs t(emselves ould output 1. bits eac(, on every cloc1 cycle, and t(ese outputs ould go into t(e first stage& $OM 2 and $OM + ould go into one, $OM C and $OM D t(e ot(er& T(e )t( least significant bit is used to determine (ic( of t(ese is passed alongA t(e output is sent to t(e !nd stage& >ere eit(er ;2 or +< or ;C or D< is c(osen, using t(e Most "ignificant +it to ma1e t(is c(oice& +y using t(is met(od, one can accurately c(oose (ic( of t(e four $OMDs to access and (ic( ro in t(at $OM to access&

#%1 RO$ Str&ct&re

T(e basic $OM structure consists of grid/li1e building bloc1s, enabling $OMDs of any logical si5e to be created it(out any e3tra design or1 involved after t(e initial setup& T(ese building bloc1s are bro1en into four categoriesA Tree Decoder, Memory 2rray, "ense 2mplifiers and Multiple3ers& T(e best ay to begin e3plaining t(e $OM is by describing t(e Memory 2rray& 2s our goal as a !'* $OM it( a 6 bit output, e ill start it( t(e identical *% bit $OM array& T(e Memory stored in t(ese $OMDs consists of *% ro s it( 6 columnsA eac( ro is called a E@ordF and eac( column a E+itF& @(atever is stored in t(ese different memory cells can be accessed at any time and also need to be programmed to be accurate& To access t(ese cells a tree decoder is necessary& T(e tree decoder ta1es t(e * least significant bits from t(e accumulator and uses it to control * stages& Using t(ese stages, e split t(e output #! times to create a possibility of *% different ro s& T(is is (o e can select an individual ro , or alternatively, ord line&

Once t(ese ord lines are activated, t(e data stored on t(e bit lines is accessible by t(e sense amplifier at t(e bottom of t(e $OM& T(ese sense ampDs are used just to increase t(e signal, purifying any distortion and re/centering it according to t(e voltage rails t(at are in use& ,n our case, t(is means t(e sense amp decides (et(er t(e signal bit is (ig( or lo and t(en outputs eit(er .C or 'C accordingly& T(e output coming from t(ese sense amps go directly into t(e multiple3ers& 2s mentioned before, $OM 2 and + s(are a MU= (ile $OM C and D s(are t(e ot(er& 2fter t(e first stage, t(e t o multiple3ers bot( output to t(e t(ird, (ic( is controlled by t(e Most "ignificant +it& T(is output is determined bot( by (ic( $OM is selected and (ic( ord line in t(e $OM is selectedA it is t(e final output of t(e $OM& 7rom (ere, it goes to t(e latc( and is latc(ed before being sent to t(e D2C&

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Sc(e)atic!
'%1 *' +it $e)or, - it!

Eac( *% bit memory unit is made up of ' different partsA ,nputs, Tree Decoders, t(e Pull/Up 0et or1, Memory Cells and t(e "ense 2mplifiers& T(e ,nputs ta1e t(e signal from t(e accumulator and invert it and bot( signals are propagated t(roug( t(e tree decoder& T(is in turn controls t(e decoder and selects (ic( ro of memory to access& @(en accessed, t(e Pull/Up 0et or1 gives a (ig( voltage to eac( bit line unless t(ere is an 0MO" circuit stored in one of t(e memory cells& ,f an 0MO" e3ists, it pulls t(e bit line lo & T(ese bit lines are connected to t(e sense amplifiersA t(e sense amps reset t(e signal to eit(er a pure lo or a pure (ig(, outputting to a later stage in t(e $OM&

7ig& %&1 *% +it $OM "c(ematic

'%2 Tree Deco.er I p&t

T(ere are ) inputs to t(e tree decoderA * signal lines and Cdd& Cdd is t(e input to t(e very first stage, giving it a steady ' volt signal to propagate& T(e ot(er * signal lines are t(e * least significant bits coming from t(e accumulator& T(ese same signal lines go to all four *% bit $OMDsA all select t(e same ro in memory& T(e t o most significant bits are used to c(oose (ic( $OM is selectedA t(at is (o e ere able to fit a !'* bit $OM in a rat(er tig(t space&

7ig& %&!&1 Tree Decoder ,nput "c(ematic T(e si3 signal lines are inverted and bot( t(e signal and its inversion are reBuired for t(e tree decoder& T(ey are bot( used in selecting (ic( output is (ig(A e originally (ad one signal, but t(is reBuired us to use a complementary CMO" design& Using bot( signal lines allo s us to ditc( t(e PMO" and (ave an easier implementation&

7ig& %&!&! Tree Decoder ,nput "c(ematic Overvie

'%# Tree Deco.er

T(e Tree Decoder is t(e means by (ic( a particular ro in memory is selected& T(ere are si3 stages to itA all are identical e3cept for t(e t(ird stage, (ic( is designed to 1eep t(e output from floating& Eac( instance of t(e tree decoder (as an input t(at is eit(er (ig( or lo A if it is lo , not(ing ill output but it or1s in t(e same ay& @(en t(e input is (ig(, t(e decoder loo1s to t(e signal bit to find out (et(er to ma1e output a (ig( or a lo & T(is (ig( signal is sent in a direct pat( t(roug( si3 levels of t(e tree decoder to its final destinationA a ro in memory&

7ig& %&#&1 Tree Decoder "c(ematic Overvie

10

To propagate t(is (ig( signal, t o 0MO" transistors are used in t(e circuit& T(ey bot( are connected to t(e input, it( t(eir output connected to eit(er Output or Output bar& To create t(e output, t(e signal line is connected to t(e gate of t(e 0MO" transistorA (en t(e signal is (ig( it turns on, ma1ing t(e output (ig( as ell& ,f t(e signal is lo , t(e 0MO" turns off and t(e output is lo & >o ever, (en t(e signal line is lo , its inverse is (ig(, and t(at is (at is connected to t(e gate of t(e ot(er 0MO"& T(is is (o Output bar is createdA (enever t(e signal s itc(es from (ig( to lo , one transistor turns on (ile t(e ot(er turns off, it( a negligible overlap bet een t(e t o&

7ig& %&#&! Tree Decoder "c(ematic

11

7or t(e t(ird stage of t(e tree decoder, t o e3tra 0MO" transistors are addedA one to t(e Output and one to t(e Output bar& T(ey are bot( used to ground t(e outputsA t(eir gates are connected to t(e signal t(at is opposite of t(e output, so (enever t(e output is lo t(e transistors turn on& T(is guarantees t(at t(e output is not floatingA it pulls it to ground and in doing (elps lessen t(e dampening to t(e signal&

7ig& %&#&# Tree Decoder #rd "tage "c(ematic

12

2t t(e end of t(e Tree Decoder, a very important combination of devices is connected& To compensate for t(e possibility of a floating output, anot(er 0MO" transistor is attac(ed to t(e output& T(e output line is attac(ed to bot( its source and its gate, it( t(e drain attac(ed to ground& T(is reBuires t(at a voltage source remain (ig(& 2ny errant signals ould trigger t(e 0MO" to turn on and give a pat( to ground, draining any voltage from t(e line& ,f it is a true positive, (o ever, t(e signal ill continue to t(e offset inverter&

7ig& %&#&% Tree 4ine "c(ematic

T(e offset inverter as si5ed it( its 0MO" transistor si3 times larger t(an minimum si5ed, (ile t(e PMO" remained minimum si5ed& T(is gives it a lo er t(res(old voltage, allo ing it to turn on at a lo er voltage level& T(is is important because t(e signal is dampened by t(e time it gets to t(is pointA t(e voltage (ig( level decreases from t(e ' volts at Cdd to about #&- volts& " itc(ing at a lo er level correctly reflects t(e midpoint of t(e signalA t(e second inverter inverts t(e signal and resets t(e midpoint to !&' volts& T(e combination of t(ese t o allo t(e signal to go from . volts to ' volts again, (ic( is important for t(e sense amplifier&

13

'%' T(e $e)or, Str&ct&re

T(e Memory "tructure is (at ta1es t(e information provided by t(e tree decoder and outputs t(e selected stored memory bits& Eac( ro is called a ord line and a properly or1ing tree decoder only selects one ord at a time& T(e number of output bits is eBual to t(e number of columnsA eac( output is connected to every memory cell in its column by t(e bit line& T(e ay e implemented t(is is if no ord is selected, t(e bit lines ill all be (ig(& T(ere is a difference in trying to send a lo or a (ig( signal to t(e sense amplifiers// e c(ose a (ig( to be our norm, meaning t(at our memory (as a structure of lines and bits it(out anyt(ing connecting bet een t(em& @(et(er t(e ord line is c(osen or not, t(e bit line doesnDt connect to it and so doesnDt care& To (ave a lo output, (o ever, reBuires an 0MO" transistor in eac( memory cell& T(is transistor is connected to bot( t(e bit line and t(e ord line, giving t(e bit line a pat( to ground& T(e ord line is attac(ed to t(e gate of t(e transistorA (enever t(e ord line goes (ig(, t(e gate is (ig( and t(e 0MO" turns on& T(is in turn pulls t(e +it 4ine lo , so t(e output seen at t(e sense amplifier is 5ero&

7ig& %&%&1 Memory Cell One

14

7ig& %&%&! Memory Cell 9ero

15

'%/ P&001-p Networ2

T(e Pull/Up 0et or1 is a simple PMO" transistor& ,ts source is Cdd, its drain is t(e bit line and its gate is connected to ground& T(is means t(at it is al ays on, but it is a necessary safeguard due to current considerations&

7ig& %&' Pull Up 0et or1 "c(ematic

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'%* Se !e A)p
T(e sense amp or1s in t(e same ay t(at t(e offset inverter in t(e tree line does& ,t consists of t o minimum si5ed inverters in series, resetting t(e output to eit(er a pure (ig( or a pure lo & T(e sense amp does (ave an offset inverter, but it asnDt necessary to c(ange si5esA t(e s itc(ing midpoint is t(e same as it s(ould be& T(e only reason for t(e sense amp, in our situation, as t(at t(e (ig( signal as not a pure (ig(& ,t dropped do n by at least a volt, so to pull it bac1 up and give a clean output, t(e inverters are t(ere&

7ig& %&* "ense 2mp "c(ematic

17

'%3 $&0tip0e4er!
T(e Multiple3ers are in t o stages, it( eac( stage being identical& T(e t o multiple3ers in t(e first stage accept t o sets of 6 inputs and output 6 bits to t(e second stage& T(e second stage c(ooses (ic( of t(e first multiple3ers to pass on to t(e output&

7ig& %&)&1 Multiple3er "c(ematic

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7ig& %&)&! Multiple3er !:1 "c(ematic

19

'%5 Latc(
T(e outputs from t(e multiple3er are latc(ed using cloc1ed D flip/flops& T(e edge triggered D flip/flop can be easily constructed from t(e $" flip/flop& One essential point about t(e D flip/flop is t(at (en t(e cloc1 input falls to logic . and t(e outputs can c(ange state, t(e 8 output al ays ta1es on t(e state of t(e D input at t(e moment of t(e cloc1 edge& T(is circuit (as t o D latc(es in a master/ slave configuration driven by a cloc1& T(e different logic circuits used in t(is design are ! inverters, % 20D gates and % 0O$ gates& T(e si5ing of t(e transistors as done for eac( of t(is digital logic& 7ig !&'&1 s(o s t(e sc(ematic vie of t(e D flip/flop used for latc(ing&

7ig& %&-&1 Cloc1ed D 7lip 7lop "c(ematic

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7ig& %&-&! Cloc1ed D 7lip 7lop "c(ematic Overvie

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La,o&t!
/%1 *' +it $e)or, - it!

T(e completed *% bit Memory Units are tall and s1innyA t(e limiting factor in si5ing as t(e (eig(t of t(e memory cells& T(e (eig(t and idt( ere t(e same, but t(ey only needed to be 6 units ide (ereas t(ey ere *% units tall&

7ig& '&1 *% +it $OM 4ayout 22

/%2 Tree Deco.er I p&t

T(e Tree Decoder ,nput ould typically be a very simple layout, but in our application e anted to fit several in a very tig(t space& ,t ended up fitting very nicely and is a very simple design&

7ig& '&!&1 Tree Decoder ,nput 4ayout

0otice t(at t(e input bit from t(e top attac(es to t(e gate and t(en continues t(roug( as its o n outputA t(is is t(e signal, t(e output of t(e inverter is t(e signal bar& +y using Metal ! as e did, it allo s eac( piece to be put in a grid (ile (aving all of t(e vertical metal ! strips overlap& T(is comes into play (en e lay out t(e tree decoder itselfA by 1eeping t(e units very basic, arrays of tree decoders are very easily implemented&

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7ig& '&!&! Tree Decoder ,nput 4ayout Overvie

/%# Tree Deco.er

T(e layout of t(e tree decoder becomes increasingly cluttered t(e more stages t(ere are& T(e minimum/si5ed stage * are crammed ne3t to eac( ot(er as tig(t as t(ey can fitA it slo ly e3pands as you go to t(e left, it( "tage 1 being t(e entire lengt( of t(e $OM&

7ig& '&#&1 Tree Decoder 4ayout Overvie

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T(e individual layouts for eac( stage are t(e same, it( t(e only difference being t(e (eig(t involved& "tage ' (as to be t ice as tall as stage *, so t(e lengt(s of t(e connecting ires is longer& 7rom stage * to ' t(ere is also a slig(t c(ange as ellA it( more space to e3pand vertically, t(e units become less ide& 7ollo ing ill be e3amples of t(e stages it( t(e e3ception of "tage 1 and !& +ot( of t(ese stages are identical to "tage % but t(eir (eig(t ma1es t(em very (ard to see&

7ig& '&#&! Tree Decoder "tage * 4ayout

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7ig& '&#&# Tree Decoder "tage ' 4ayout

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7ig& '&#&% Tree Decoder "tage % 4ayout

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7ig& '&#&' Tree Decoder "tage % 4ayout 28

T(e Tree Decoder outputs eac( ro

into t(e Tree 4ine, as s(o n (ere:

7ig& '&#&* Tree 4ine 4ayout Overvie

7ig& '&#&) Tree 4ine 4ayout

T(e (ardest part in designing t(is as t(e (eig(t restrictions& +ecause t(e (eig(t as meant to be t(e minimum (eig(t of eac( memory cell, it forced t(e idt( to increase tremendously& T(e various components almost donDt fit correctly, but t(ey just manage to do so& 0otice also t(e strips of metal ! going verticallyA t(ese connect all of t(e grounds and CddDs toget(er it(out reBuiring any special iring (en you use t(e Tree 4ine in your layout& T(e same t(ing (appened it( t(e rest of t(e Tree DecoderA eac( signal bit, and its inversion, are automatically connected to t(e follo ing decoder&

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/%' T(e $e)or, Str&ct&re

T(e Memory "tructure as t(e basic building bloc1 around (ic( t(e rest of t(e $OM functioned& @it( a net or1 of bit lines and ord lines, t(e Memory "tructure loo1ed li1e a grid&

7ig& '&%&1 Memory "tructure 4ayout

7ig& '&%&! Memory "tructure 4ayout Overvie 30

T(e stored 5eros used t(e same p(ysical structure but added an 0MO" in t(e middle& T(is 0MO" and itDs properties are (at controlled t(e overall si5e of t(e $OM// t(ere as no ay to ma1e it any smaller t(an e did&

7ig& '&%&# Memory One 4ayout

7ig& '&%&% Memory One 4ayout Overvie

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/%/ P&001-p Networ2

7ig& '&'&1 Pull/Up 0et or1 4ayout

32

7ig& '&'&! Pull/Up 0et or1 4ayout Overvie

/%* Se !e A)p0ifier!

7ig& '&* "ense 2mplifier 4ayout

33

/%3 $&0tip0e4er!

7ig& '&)&1 T o to One MU= 4ayout

34

7ig& '&)&! T o to One MU= 4ayout Overvie

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/%5 Latc(

7ig& '&- 4atc( 4ayout

36

Si6i "

To ac(ieve minimum si5ing, t(e limiting factor must be minimi5ed& ,n t(is case, t(e limiting factor is t(e (eig(t of t(e individual memory cellA t(e smaller it is, t(e smaller t(e $OM ill be& T(is is due to t(e fact t(at t(ere are *% ro s of memory, compared to only 6 columns& T(e smallest t(e memory cell can be is dependent on t(e 0MO" transistor t(at (as to fit it(in itA t(ere is no ay to avoid overlapping cells unless everyt(ing fits inside t(e bloc1 of memory& Minimum si5ing gives us 7ig& *&1&

7ig& *&1 Minimum "i5ed Memory Cell T(is minimum si5ed cell forms t(e basis for everyt(ing elseA to ac(ieve minimum si5e, all of t(e neig(boring components must fit it(in t(e (eig(t or idt( dimensions as ell& T(e Pull/Up 0et or1 and t(e "ense 2mp bot( need to be *&6 micron ide in order to fitA conversely t(e *t( stage of t(e tree decoder and t(e tree line can only be *&6 micron (ig(&

7ig& *&! >eig(t $estricted Tree 4ine 37

7ig& *&# Minimum "i5ed *% bit $OM 38

7ig& *&% Minimum "i5ed !'* bit $OM

39

Pro"ra))i "

To ma1e t(e $OM easier to implement and c(ange, e added some e3tra symbols to (elp in t(e programming& To do t(is, e grouped t(ree bits toget(er into a larger symbol, creating all of t(e values from . to )& T(ese loo1 li1e 7igure )&1&

7ig& )&1 $OM .

7ig& )&! $OM %

40

T(is allo s faster programming and Buic1er modifications& ,t also enables better troubles(ooting as t(ere are fe er cell bloc1s to identify as rong& T(e easiest ay to program, using t(is tec(niBue, is to create an array of *% ro s and # columns of $OM .& T(is ill completely fill up t(e $OM, t(en allo ing you to modify eac( cell individually to c(ange (ic( value you ould li1e& T(is met(od saves a lot of time because t(ere is no longer a reBuirement to line t(ings up correctlyA it is already properly lined up&

41

Te!ti "

Testing as done on every part of t(e $OM, troubles(ooting and c(ec1ing all components to ma1e sure t(at it as fully functional& Only t(ree tests ill be documented (ereA for t(e rest, go to 2nus(a $amanujamDs E$OM for Direct Digital "ynt(esi5erF report at t(e follo ing eb site: (ttp:?? &eece&maine&edu?researc(?vlsi?!..*?$amanujam?ECE'%)G2nus(a&pdf T(e t(ree tests s(o n (ere are testing t(e Tree Decoder and testing t(e "ense 2mplifier& T(e Tree Decoder s(ould s itc( as t(e inputs increment, t(ereby turning on one and only one ro at a time (ile systematically increasing& T(e test is s(o n in 7igure -&1&

7ig& -&1 Testing t(e Tree Decoder

42

"imilarly, t(e Tree 4ine itself s(ould or1 as describedA you s(ould see inputs coming in at a lo er value t(an t(ey s(ould, but leaving at t(e desired value, as in 7igure -&!&

7ig& -&! Testing t(e Tree 4ine

43

2nd finally, to test t(e "ense 2mplifier, t(e output of t(e $OM s(ould travel to t(e "ense 2mp and be broug(t bac1 up to t(e e3pected value& T(is grap( is ta1en from a larger test t(at as done, but t(is particular sense amp as t(e only one t(at c(anged, so t(e ot(ers ere omitted&

7ig& -&# Testing t(e "ense 2mplifer

44

Co)p0ete C(ip

7ig& 6 Complete DD" C(ip

45

7ig& 6 Pin 2ssignments

46

Appe .i4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 ROM D 000000010 000000101 000001000 000001011 000001110 000010001 000010100 000011000 000011011 000011110 000100001 000100100 000100111 000101010 000101101 000110001 000110100 000110111 000111010 000111101 001000000 001000011 001000110 001001001 001001101 001010000 001010011 001010110 001011001 001011100 001011111 001100010 001100101 001101000 001101011 001101110 001110001 001110101 001111000 001111011 ROM C 011000101 011001000 011001011 011001110 011010001 011010011 011010110 011011001 011011100 011011111 011100010 011100100 011100111 011101010 011101101 011101111 011110010 011110101 011111000 011111011 011111101 100000000 100000011 100000101 100001000 100001011 100001101 100010000 100010011 100010101 100011000 100011011 100011101 100100000 100100010 100100101 100101000 100101010 100101101 100101111 47 ROM B 101101010 101101101 101101111 101110001 101110011 101110101 101110111 101111010 101111100 101111110 110000000 110000010 110000100 110000110 110001000 110001010 110001100 110001110 110010000 110010010 110010100 110010110 110011000 110011010 110011011 110011101 110011111 110100001 110100011 110100100 110100110 110101000 110101010 110101011 110101101 110101111 110110001 110110010 110110100 110110101 ROM A 111011001 111011010 111011011 111011100 111011101 111011110 111100000 111100001 111100010 111100011 111100100 111100101 111100110 111100111 111101000 111101001 111101001 111101010 111101011 111101100 111101101 111101110 111101111 111101111 111110000 111110001 111110010 111110010 111110011 111110100 111110100 111110101 111110101 111110110 111110111 111110111 111111000 111111000 111111001 111111001

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

001111110 010000001 010000100 010000111 010001010 010001101 010010000 010010011 010010110 010011001 010011100 010011111 010100010 010100101 010101000 010101011 010101110 010110001 010110100 010110110 010111001 010111100 010111111 011000010

100110010 100110100 100110111 100111001 100111100 100111110 101000001 101000011 101000101 101001000 101001010 101001101 101001111 101010001 101010100 101010110 101011000 101011011 101011101 101011111 101100001 101100100 101100110 101101000

110110111 110111001 110111010 110111100 110111101 110111111 111000000 111000010 111000011 111000101 111000110 111001000 111001001 111001011 111001100 111001101 111001111 111010000 111010001 111010011 111010100 111010101 111010110 111011000

111111010 111111010 111111011 111111011 111111011 111111100 111111100 111111100 111111101 111111101 111111101 111111101 111111110 111111110 111111110 111111110 111111110 111111111 111111111 111111111 111111111 111111111 111111111 111111111

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