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Module 1
Power Semiconductor Devices
Version 2 EE IIT, Kharagpur 1 www.jntuworld.com
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Lesson 1
Power Electronics
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Introduction
This lesson provides the reader the following: (i) (ii) (iii) (iv) (v) Create an awareness of the general nature of Power electronic equipment; Brief idea about topics of study involved, The key features of the principal Power Electronic Devices; An idea about which device to choose for a particular application. A few issues like base drive and protection of PE devices and equipment common to most varieties.
Power Electronics is the art of converting electrical energy from one form to another in an efficient, clean, compact, and robust manner for convenient utilisation. A passenger lift in a modern building equipped with a VariableVoltageVariableSpeed inductionmachine drive offers a comfortable ride and stops exactly at the floor level. Behind the scene it consumes less power with reduced stresses on the motor and corruption of the utility mains.
Fig. 1.1 The block diagram of a typical Power Electronic converter Power Electronics involves the study of Power semiconductor devices  their physics, characteristics, drive requirements and their protection for optimum utilisation of their capacities, Power converter topologies involving them, Control strategies of the converters, Digital, analogue and microelectronics involved, Capacitive and magnetic energy storage elements, Rotating and static electrical devices, Quality of waveforms generated, Electro Magnetic and Radio Frequency Interference, Version 2 EE IIT, Kharagpur 3 www.jntuworld.com
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Thermal Management The typical converter in Fig. 1.1 illustrates the multidisciplinary nature of this subject.
Fig. 1.2 Typical Bipolar transistor based (a) linear (common emitter) (voltage) amplifier stage and (b) switching (power) amplifier
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Fig 1.3 Operating zones for operating a Bipolar Junction Transistor as a linear and a switching amplifier Linear operation Active zone selected: Good linearity between input/output Switching operation Active zone avoided : High losses, encountered only during transients Saturation & cutoff zones avoided: poor Saturation & cutoff (negative bias) zones linearity selected: low losses Transistor biased to operate around No concept of quiescent point quiescent point Common emitter, Common collector, Transistor driven directly at base  emitter common base modes and load either on collector or emitter Output transistor barely protected SwitchingAidNetwork (SAN) and other protection to main transistor Utilisation of transistor rating of secondary Utilisation of transistor rating optimised importance
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An example illustrating the linear and switching solutions to a power supply specification will emphasise the difference. Spec: Input : 230 V, 50 Hz, Output: 12 V regulated DC, 20 W
Ferrite core HF transfr: Light, efficient Series regulator high losses 230 V
230 V
(a)
Highfreq Dutyratio (ON/OFF) control  low losses
(b)
Fig. 1.4 (a) A Linear regulator and (b) a switching regulator solution of the specification above The linear solution, Fig. 1.4 (a), to this quite common specification would first step down the supply voltage to 12012 V through a power frequency transformer. The output would be rectified using Power frequency diodes, electrolytic capacitor filter and then series regulated using a chip or a audio power transistor. The tantalum capacitor filter would follow. The balance of the voltage between the output of the rectifier and the output drops across the regulator device which also carries the full load current. The power loss is therefore considerable. Also, the stepdown ironcore transformer is both heavy, and lossy. However, only twicelinefrequency ripples appear at the output and material cost and technical knowhow required is low. In the switching solution Fig. 1.4 (b) using a MOSFET driven flyback converter, first the line voltage is rectified and then isolated, steppeddown and regulated. A ferritecore highfrequency (HF) transformer is used. Losses are negligible compared to the first solution and the converter is extremely light. However significant high frequency (related to the switching frequency) noise appear at the output which can only be minimised through the use of costly 'grass' capacitors.
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and the high base currents required to switch the Bipolar spawned the Darlington. Three or more stage Darlingtons are available as a single chip complete with accessories for its convenient drive. Higher operating frequencies were obtainable with a discrete Bipolars compared to the 'fast' invertergrade SCRs permitting reduction of filter components. But the Darlington's operating frequency had to be reduced to permit a sequential turnoff of the drivers and the main transistor. Further, the incapability of the Bipolar to block reverse voltages restricted its use. The Power MOSFET burst into the scene commercially near the end seventies. This device also represents the first successful marriage between modern integrated circuit and discrete power semiconductor manufacturing technologies. Its voltage drive capability giving it again a higher gain, the ease of its paralleling and most importantly the much higher operating frequencies reaching upto a few MHz saw it replacing the Bipolar also at the sub10 KW range mainly for SMPS type of applications. Extension of VLSI manufacturing facilities for the MOSFET reduced its price visvis the Bipolar also. However, being a majority carrier device its onstate voltage is dictated by the RDS(ON) of the device, which in turn is proportional to about VDSS2.3 rating of the MOSFET. Consequently, highvoltage MOSFETS are not commercially viable. Improvements were being tried out on the SCR regarding its turnoff capability mostly by reducing the turnon gain. Different versions of the Gateturnoff device, the Gate turnoff Thyristor (GTO), were proposed by various manufacturers  each advocating their own symbol for the device. The requirement for an extremely high turnoff control current via the gate and the comparatively higher cost of the device restricted its application only to inverters rated above a few hundred KVA. The lookout for a more efficient, cheap, fast and robust turnoffable device proceeded in different directions with MOS drives for both the basic thysistor and the Bipolar. The Insulated Gate Bipolar Transistor (IGBT) basically a MOSFET driven Bipolar from its terminal characteristics has been a successful proposition with devices being made available at about 4 KV and 4 KA. Its switching frequency of about 25 KHz and ease of connection and drive saw it totally removing the Bipolar from practically all applications. Industrially, only the MOSFET has been able to continue in the sub 10 KVA range primarily because of its high switching frequency. The IGBT has also pushed up the GTO to applications above 25 MVA. Subsequent developments in converter topologies especially the threelevel inverter permitted use of the IGBT in converters of 5 MVA range. However at ratings above that the GTO (6KV/6KA device of Mitsubishi) based converters had some space. Only SCR based converters are possible at the highest range where linecommutated or loadcommutated converters were the only solution. The surge current, the peak repetition voltage and I2t ratings are applicable only to the thyristors making them more robust, specially thermally, than the transistors of all varieties.
Presently there are few hybrid devices and Intelligent Power Modules (IPM) are marketed by some manufacturers. The IPMs have already gathered wide acceptance. The 4500 V, 1200 A Version 2 EE IIT, Kharagpur 7 www.jntuworld.com
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IEGT (injectionenhanced gate transistor) of Toshiba or the 6000 V, 3500 A IGCT (Integrated Gate Commutated Thyristors) of ABB which are promising at the higher power ranges. However these new devices must prove themselves before they are accepted by the industry at large. Silicon carbide is a wide band gap semiconductor with an energy band gap wider than about 2 eV that possesses extremely high thermal, chemical, and mechanical stability. Silicon carbide is the only wide band gap semiconductor among gallium nitride (GaN, EG = 3.4 eV), aluminum nitride (AlN, EG = 6.2 eV), and silicon carbide that possesses a highquality native oxide suitable for use as an MOS insulator in electronic devices The breakdown field in SiC is about 8 times higher than in silicon. This is important for highvoltage power switching transistors. For example, a device of a given size in SiC will have a blocking voltage 8 times higher than the same device in silicon. More importantly, the onresistance of the SiC device will be about two decades lower than the silicon device. Consequently, the efficiency of the power converter is higher. In addition, SiCbased semiconductor switches can operate at high temperatures (~600 C) without much change in their electrical properties. Thus the converter has a higher reliability. Reduced losses and allowable higher operating temperatures result in smaller heatsink size. Moreover, the high frequency operating capability of SiC converters lowers the filtering requirement and the filter size. As a result, they are compact, light, reliable, and efficient and have a high power density. These qualities satisfy the requirements of power converters for most applications and they are expected to be the devices of the future. Ratings have been progressively increasing for all devices while the newer devices offer substantially better performance. With the SCR and the pindiodes, so called because of the sandwiched intrinsic ilayer between the p and n layers, having mostly linecommutated converter applications, emphasis was mostly on their static characteristics  forward and reverse voltage blocking, current carrying and overcurrent ratings, onstate forward voltage etc and also on issues like paralleling and series operation of the devices. As the operating speeds of the devices increased, the dynamic (switching) characteristics of the devices assumed greater importance as most of the dissipation was during these transients. Attention turned to the development of efficient drive networks and protection techniques which were found to enhance the performance of the devices and their peak power handling capacities. Issues related to paralleling were resolved by the system designer within the device itself like in MOSFETS, while the converter topology was required to take care of their series operation as in multilevel converters. The range of power devices thus developed over the last few decades can be represented as a tree, Fig. 1.5, on the basis of their controllability and other dominant features.
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UNCONTROLLED
CONTROLLED
RECTIFIERS
ACCESSORIES
Power Diodes
diF /dt
t0
t1
t2
SNAPPY
SOFT to Q1 Q2
IRM
VRM
Fig. 1.6 Typical turnoff dynamics of a soft and a 'snappy' diode' Silicon Power diodes are the successors of Selenium rectifiers having significantly improved forward characteristics and voltage ratings. They are classified mainly by their turnoff (dynamic) characteristics Fig. 1.6. The minority carriers in the diodes require finite time  trr (reverse recovery time) to recombine with opposite charges and neutralise. Large values of Qrr (= Q1 + Q2)  the charge to be dissipated as a negative current when the and diode turns off and trr (= t2  t0)  the time it takes to regain its blocking features, impose strong current stresses on the controlled device in series. Also a 'snappy' type of recovery of the diode effects high di/dt voltages on all associated power device in the converter because of load or stray inductances present in the network. There are broadly three types of diodes used in Power electronic applications: Linefrequency diodes: These PIN diodes with generalpurpose rectifier type applications, are available at the highest voltage (~5kV) and current ratings (~5kA) and have excellent overcurrent (surge rating about six times average current rating) and surgevoltage withstand capability. They have relatively large Qrr and trr specifications.
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Fast recovery diodes: Fast recovery diffused diodes and fast recovery epitaxial diodes, FRED's, have significantly lower Qrr and trr (~ 1.0 sec). They are available at high powers and are mainly used in association with fast controlleddevices as freewheeling or DCDC choppers and rectifier applications. Fast recovery diodes also find application in induction heating, UPS and traction. Schottky rectifiers: These are the fastest rectifiers being majority carrier devices without any Qrr.. However, they are available with voltage ratings up to a hundred volts only though current ratings may be high. Their conduction voltages specifications are excellent (~0.2V). The freedom from minority carrier recovery permits reduced snubber requirements. Schottky diodes face no competition in low voltage SPMS applications and in instrumentation.
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MOSFET
The Power MOSFET technology has mostly reached maturity and is the most popular device for SMPS, lighting ballast type of application where high switching frequencies are desired but operating voltages are low. Being a voltage fed, majority carrier device (resistive behaviour) with a typically rectangular Safe Operating Area, it can be conveniently utilized. Utilising shared manufacturing processes, comparative costs of MOSFETs are attractive. For low frequency applications, where the currents drawn by the equivalent capacitances across its terminals are small, it can also be driven directly by integrated circuits. These capacitances are the main hindrance to operating the MOSFETS at speeds of several MHz. The resistive characteristics of its main terminals permit easy paralleling externally also. At high current low voltage applications the MOSFET offers best conduction voltage specifications as the RDS(ON) specification is current rating dependent. However, the inferior features of the inherent antiparallel diode and its higher conduction losses at power frequencies and voltage levels restrict its wider application.
The IGBT
It is a voltage controlled fourlayer device with the advantages of the MOSFET driver and the Bipolar Main terminal. IGBTs can be classified as punchthrough (PT) and nonpunchthrough (NPT) structures. In the punchthrough IGBT, a better tradeoff between the forward voltage drop and turnoff time can be achieved. Punchthrough IGBTs are available up to about 1200 V. NPT IGBTs of up to about 4 KV have been reported in literature and they are more robust than PT IGBTs particularly under short circuit conditions. However they have a higher forward voltage drop than the PT IGBTs. Its switching times can be controlled by suitably shaping the drive signal. This gives the IGBT a number of advantages: it does not require protective circuits, it can be connected in parallel without difficulty, and series connection is possible without dv/dt snubbers. The IGBT is presently one of the most popular device in view of its wide ratings, switching speed of about 100 KHz a easy voltage drive and a square Safe Operating Area devoid of a Second Breakdown region.
The GTO
The GTO is a power switching device that can be turned on by a short pulse of gate current and turned off by a reverse gate pulse. This reverse gate current amplitude is dependent on the anode current to be turned off. Hence there is no need for an external commutation circuit to turn it off. Because turnoff is provided by bypassing carriers directly to the gate circuit, its turnoff time is short, thus giving it more capability for highfrequency operation than thyristors. The GTO symbol and turnoff characteristics are shown in Fig. 30.3. GTOs have the I2t withstand capability and hence can be protected by semiconductor fuses. For reliable operation of GTOs, the critical aspects are proper design of the gate turnoff circuit and the snubber circuit.
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CONVERSION FROM/TO
NAME
FUNCTION
SYMBOL
DC to DC
Chopper
DC to AC
Inverter
~ ~ ~
AC to DC
Rectifier
AC to AC
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IGBT
Vref
COMPARATOR
TIMER
Fig. 1.7 Simple gatedrive and protection circuit for a standalone IGBT and a SCR
Semiconductor devices of all types exhibit similar responses to most of the stresses, however there are marked differences. The SCR is the most robust device on practically all counts. That it has an I2t rating is proof that its internal thermal capacities are excellent. A HRC fuse, suitably selected, and in coordination with fast circuit breakers would mostly protect it. This sometimes becomes a curse when the cost of the fuse becomes exorbitant. All transistors, specially the BJT and the IGBT is actively protected (without any operating cost!) by sensing the Main Terminal voltage, as shown in Fig. 1.7. This voltage is related to the current carried by the device. Further, the transistors permit designed gate current waveforms to minimise voltage spikes as a consequence of sharply rising Main terminal currents. Gate resistances have significant effect on turnon and turnoff times of these devices  permitting optimisation of switching times for the reduction of switching losses and voltage spikes.
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Protection schemes for overvoltages  the prolonged ones and those of short duration  are guided by the energy content of the surges. Metal Oxide Varistors (MOV's), capacitive dynamic voltageclamps and crowbar circuits are some of the strategies commonly used. For high dv/dt stresses, which again have similar effect on all devices, RC or RCD clamps are used depending on the speed of the device. These 'snubbers' or 'switchingaidnetworks', additionally minimise switching losses of the device  thus reducing its temperature rise. Gates of all devices are required to be protected against overvoltages (typically + 20 V) specially for the voltage driven ones. This is achieved with the help of Zener clamps  the zener being also a very fastacting device. Protection against issues like excessive case temperatures and ESD follow wellset practices. Forcedcooling techniques are very important for the higher rated converters and whole environments are aircooled to lower the ambient.
Qs#2 An SCR requires 50 mA gate current to switch it on. It has a resistive load and is supplied from a 100 V DC supply. Specify the Pulse transformer details and the circuit following it, if the driver circuit supply voltage is 10 V and the gatecathode drop is about 1 V. Ans: The most important ratings of the Pulse transformer are its voltsecs rating, the isolation voltage and the turns ratio. The voltsecs is decided by the product of the primary pulsevoltage multiplied by the period for which the pulse is applied to the winding If the primary pulse voltage = (Supply voltage drive transistor drop) The turnon time of he SCR may be in the range 50 secs for an SCR of this rating. Consequently the volt secs may be in the range of 9 x 50 = 450 voltsecs = 2.5 KV, IM = 150 mA The Pulse transformer may be chosen as: 1:1, 450 Vs, Visol The circuit shown in Fig. 1.7 may be used. Diodes 1N4002 Series resistance = (Supply voltage drive transistor drop gatecathode drop)/100mA = (10 1 1) / 100 E3 = 80 Ohm = 49 or 57 Ohm (nearest available lower value) Version 2 EE IIT, Kharagpur 14 www.jntuworld.com
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Module 1
Power Semiconductor Devices
Version 2 EE IIT, Kharagpur 1 www.jntuworld.com
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Lesson 2
Constructional Features, Operating Principle, Characteristics and Specification of Power Semiconductor Diode
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Instructional Objective
On Completion the student will be able to 1. Draw the spatial distribution of charge density, electric field and electric potential in a step junction pn diode. 2. Calculate the voltage drop across a forward biased diode for a given forward current and viceverse. 3. Identify the constructional features that distinguish a power diode from a signal level diode. 4. Differentiate between different reverse voltage ratings found in a Power Diode speciation sheet. 5. Identify the difference between the forward characteristic of a power diode and a signal level diode and explain it. 6. Evaluate the forward current specifications of a diode for a given application. 7. Draw the Turn On and Turn Off characteristics of a power diode. 8. Define Forward recovery voltage, Reverse recovery current Reverse Recovery charge as applicable to a power diode.
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(a)
(b)
(c)
Fig 2.1: Space change density the electric field and the electric potential in side a pn junction under (a) thermal equilibrium condition, (b) reverse biased condition, (c) forward biased condition. When an external voltage is applied with p side move negative then the n side the junction is said to be under reverse bias condition. This reverse bias adds to the height of the potential barrier. The electric field strength at the junction and the width of the space change region (also called the depletion region because of the absence of free carriers) also increases. On the other hand, free minority carrier densities (np in the p side and pn in the n side) will be zero at the edge of the depletion region on either side (Fig 2.1 (b)). This gradient in minority carrier density causes a small flux of minority carriers to defuse towards the deletion layer where they are swept immediately by the large electric field into the electrical neutral region of the opposite side. This will constitute a small leakage current across the junction from the n side to the p side. There will also be a contribution to the leakage current by the electron hole pairs generated in the space change layer by the thermal ionization process. These two components of current together is called the reverse saturation current Is of the diode. Value of Is is independent of the reverse voltage magnitude (up to a certain level) but extremely sensitive to temperature variation. When the applied reverse voltage exceeds some threshold value (for a given diode) the reverse current increases rapidly. The diode is said to have undergone reverse break down. Reverse break down is caused by "impact ionization" as explained below. Electrons accelerated by the large depletion layer electric field due to the applied reverse voltage may attain sufficient knick energy to liberate another electron from the covalent bonds when it strikes a silicon atom. The liberated electron in turn may repeat the process. This cascading effect (avalanche) may produce a large number of free electrons very quickly resulting in a large reverse current. The power dissipated in the device increases manifold and may cause its destruction. Therefore, operation of a diode in the reverse breakdown region must be avoided.
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When the diode is forward biased (i.e., p side more positive than n side) the potential barrier is lowered and a very large number of minority carriers are injected to both sides of the junction. The injected minority carriers eventually recombines with the majority carries as they defuse further into the electrically neutral drift region. The excess free carrier density in both p and n side follows exponential decay characteristics. The characteristic decay length is called the "minority carrier diffusion length" Carrier density gradients on either side of the junction are supported by a forward current IF (flowing from p side to n side) which can be expressed as
IF = IS ( exp ( qv/kT ) ) 1
(2.1)
Where Is = Reverse saturation current ( Amps) v = Applied forward voltage across the device (volts) q = Change of an electron k = Boltzmans constant T = Temperature in Kelvin From the foregoing discussion the iv characteristics of a pn junction diode can be drawn as shown in Fig 2.2. While drawing this characteristics the ohmic drop in the bulk of the semiconductor body has been neglected.
Fig 2.2: VoltAmpere ( iv ) characteristics of a pn junction diode Exercise 2.1 (1) Fill in the blanks with the appropriate word(s). (i) The width of the space charge region increases as the applied ______________ voltage increases. (ii) The maximum electric field strength at the center of the depletion layer increases with _______________ in the reverse voltage. (iii) Reverse saturation current in a power diode is extremely sensitive to ___________ variation. Version 2 EE IIT, Kharagpur 6 www.jntuworld.com
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(iv) Donor atoms are _____________________ carrier providers in the p type and _________________ carrier providers in the n type semiconductor materials. (v) Forward current density in a diode is __________________________ proportional to the life time of carriers. Answer: (i) Reverse, (ii) increase, (iii) temperature, (iv) Minority Majority, (v) inversely (2) A pn junction diode has a reverse saturation current rating of 50 nA at 32C. What should be the value of the forward current for a forward voltage drop of 0.5V. Assume VT = KT/q at 32C = 26 mv. Answer
Answer:
VF VT iF = Is e 1
VF Is diF = e dVF VT
VT
N ow I s = 5 10 8 A , V F = 0.5V ,
VT = 26 10
3
at 32o C
V  F dVF V = ra c = T e V T = 2 .3 1 3 m diF Is
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thickness between two heavily doped p and n layers as shown in Fig 2.3(c). Fig 2.3 (a) and (b) shows the circuit symbol and the photograph of a typical power diode respectively.
(b)
Fig. 2.3: Diagram of a power; (a) circuit symbol (b) photograph; (c) schematic cross section. To arrive at the structure shown in Fig 2.3 (c) a lightly doped n epitaxial layer of specified width (depending on the required break down voltage) and donor atom density (NdD) is grown on a heavily doped n+ substrate (NdK donor atoms.Cm 3) which acts as the cathode. Finally the pn junction is formed by defusing a heavily doped (NaA acceptor atoms.Cm3) p+ region into the epitaxial layer. This p type region acts as the anode. Impurity atom densities in the heavily doped cathode (Ndk .Cm 3) and anode (NaA.Cm 3) are approximately of the same order of magnitude (10 19 Cm 3) while that of the epitaxial layer (also called the drift region) is lower by several orders of magnitude (NdD 10 14 Cm3). In a low power diode this drift region is absent. The Implication of introducing this drift region in a power diode is explained next.
Back
As in the case of a low power diode the applied reverse voltage is supported by the depletion layer formed at the p+ n metallurgical junction. Overall neutrality of the space change region dictates that the number of ionized atoms in the p+ region should be same as that in the n region. However, since NdD << NaA, the space charge region almost exclusively extends into the n drift Version 2 EE IIT, Kharagpur 8 www.jntuworld.com
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region. Now the physical width of the drift region (WD) can be either larger or smaller than the depletion layer width at the break down voltage. Consequently two type of diodes exist, (i) non punch through type, (ii) punch through type. In nonpunch through diodes the depletion layer boundary doesnt reach the end of the drift layer. On the other hand in punch through diodes the depletion layer spans the entire drift region and is in contact with the n+ cathode. However, due to very large doping density of the cathode, penetration of drift region inside cathode is negligible. Electric field strength inside the drift region of both these type of diodes at break down voltage is shown in Fig 2.4.
Fig 2.4: Electric field strength in reverse biased power Diodes; (a) Nonpunch through type; (b) punch through type. In nonpunch through type diodes the electric field strength is maximum at the p+ n junction and decrease to zero at the end of the depletion region. Where as, in the punch through construction the field strength is more uniform. In fact, by choosing a very lightly doped n drift region, Electric field strength in this region can be mode almost constant. Under the assumption of uniform electric field strength it can be shown that for the same break down voltage, the punch through construction will require approximately half the drift region width of a comparable non  punch through construction. Lower drift region doping in a punch through diode does not carry the penalty of higher conduction lasses due to conductivity modulation to be discussed shortly. In fact, reduced width of the drift region in these diodes lowers the onstate voltage drop for the same forward current density compared to a nonpunch through diode. Under reverse bias condition only a small leakage current (less than 100mA for a rated forward current in excess of 1000A) flows in the reverse direction (i.e from cathode to anode). This reverse current is independent of the applied reverse voltage but highly sensitive to junction temperature variation. When the applied reverse voltage reaches the break down voltage, reverse current increases very rapidly due to impact ionization and consequent avalanche multiplication process. Voltage across the device dose not increase any further while the reverse current is limited by the external circuit. Excessive power loss and consequent increase in the junction temperature due to continued operation in the reverse brake down region quickly destroies the diode. Therefore, continued operation in the reverse break down region should be avoided. A typical IV characteristic of a power diode under reverse bias condition is shown in Fig 2.5.
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Fig 2.5: Reverse bias iv characteristics of a power Diode. A few other important specifications of a power Diode under reverse bias condition usually found in manufacturers data sheet are explained below. DC Blocking Voltage (VRDC): Maximum direct voltage that can be applied in the reverse direction (i.e cathode positive with respect to anode) across the device for indefinite period of time. It is useful for selecting freewheeling diodes in DCDC Choppers and DCAC voltage source inverter circuits. RMS Reverse Voltage (VRMS): It is the RMS value of the power frequency (50/60 HZ) since wave voltage that can be directly applied across the device. Useful for selecting diodes for controlled / uncontrolled power frequency line commutated AC to DC rectifiers. It is given by the manufacturer under the assumption that the supply voltage may rise by 10% at the most. This rating is different for resistive and capacitive loads. Peak Repetitive Reverse Voltage (VRRM): This is the maximum permissible value of the instantiations reverse voltage appearing periodically across the device. The time period between two consecutive appearances is assumed to be equal to half the power cycle (i.e 10ms for 50 HZ supply). This type of period reverse voltage may appear due to commutation in a converter. Peak NonRepetitive Reverse Voltage (VRSM): It is the maximum allowable value of the instantaneous reverse voltage across the device that must not recur. Such transient reverse voltage can be generated by power line switching (i.e circuit Breaker opening / closing) or lightning surges. Fig. 2.6 shows the relationship among these different reverse voltage specifications.
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Fig. 2.6: Reverse Voltage ratings of a power diode; (a) Supply voltage wave form; (b) Reverse iv characteristics
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Fig 2.7: Characteristics of a forward biased power Diode; (a) Excess free carrier density distribution; (b) iv characteristics. Both Vj and VAK have negative temperature coefficient as shown in the figure. Few other important specifications related to forward bias operation of power diode as found in manufacturers data sheet are explained next. Maximum RMS Forward current (IFRMS): Due to predominantly resistive nature of the forward voltage drop across a forward biased power diode, RMS value of the forward current determines the conduction power loss. The specification gives the maximum allowable RMS value of the forward current of a given wave shape (usually a half cycle sine wave of power frequency) and at a specified case temperature. However, this specification can be used as a guideline for almost all wave shapes of the forward current. Maximum Average Forward Current (IFAVM): Diodes are often used in rectifier circuits supplying a DC (average) current to be load. In such cases the average load current and the diode forward current usually have a simple relationship. Therefore, it will be of interest to know the Version 2 EE IIT, Kharagpur 12 www.jntuworld.com
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maximum average current a diode can conduct in the forward direction. This specification gives the maximum average value of power frequency half cycle sine wave current allowed to flow through the diode in the forward direction. Average current rating of a diode decreases with reduction in conduction angle due to increase in current form factor. Both IFRMS and IFAVM ratings are given at a specified case temperature. If the case temperature increases beyond this limit these ratings has to be reduced correspondingly. Derating curves provide by the manufacturers give the relationship between IFAVM (IFRMS) with allowable case temperature as shown in Fig. 2.8.
Fig 2.8: Derating curves for the forward current of a Power Diode. Average Forward Power loss (PAVF): Almost all power loss in a diode occurs during forward conduction state. The forward power loss is therefore an important parameter in designing the cooling arrangement. Average forward power loss over a full cycle is specified by the manufacturers as a function of the average forward current (IAVF) for different conduction angles as shown in Fig 2.9.
Fig 2.9: Average forward power loss vs. average forward current of a power Diode. Version 2 EE IIT, Kharagpur 13 www.jntuworld.com
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Surge and Fault Current: In some rectifier applications a diode may be required to conduct forward currents far in excess of its RMS or average forward current rating for some duration (several cycles of the power frequency). This is called the repetitive surge forward current of a diode. A diode is expected to operate normally after the surge duration is over. On the other hand, fault current arising due to some abnormality in the power circuit may have a higher peak valve but exists for shorter duration (usually less than an half cycle of the power frequency). A diode circuit is expected to be disconnected from the power line following a fault. Therefore, a fault current is a non repetitive surge current. Power diodes are capable of withstanding both types of surge currents and this capability is expressed in terms of two surge current ratings as discussed next. Peak Repetitive surge current rating (IFRM): This is the peak valve of the repetitive surge current that can be allowed to flow through the diode for a specific duration and for specified conditions before and after the surge. The surge current waveform is assumed to be half sinusoidal of power frequency with current pulses separated by OFF periods of equal duration. The case temperature is usually specified at its maximum allowable valve before the surge. The diode should be capable of withstanding maximum repetitive peak reverse voltage (VRRM) and Maximum allowable average forward current (IFAVM) following the surge. The surge current specification is usually given as a function of the surge duration in number of cycles of the power frequency as shown in figure 2.10
Fig 2.10: Peak Repetitive surge current VS time curve of a power diode. In case the surge current is specified only for a fixed number of cycles m then the surge current specification applicable to some other cycle number n can be found from the approximate formula.
I FRM \ n = m I \ n FRM m
(2.4)
Peak NonRepetitive surge current (IFRM): This specification is similar to the previous one except that the current pulse duration is assumed to be within one half cycle of the power Version 2 EE IIT, Kharagpur 14 www.jntuworld.com
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frequency. This specification is given as a function of the current pulse duration as shown in Fig 2.11. Maximum surge current Integral (i2dt): This is a surge current related specification and gives a measure of the heat energy generated inside the device during a nonrepetitive surge. It is useful for selecting the protective fuse to be connected in series with the diode. This specification is also given as a function of the current pulse duration as shown Fig 2.11
Fig. 2.11: Nonrepetitive surge current and surge current integral vs. current pulse width characteristics of a power Diode. Exercise 2.2 (1) Fill in the blanks with the appropriate word(s). i. ii. iii. iv. v. vi. vii. The ____________ region in a power diode increases its reverse voltage blocking capacity. The maximum DC voltage rating (VRDC) of a power diode is useful for selecting ________________ diodes in a DCDC chopper. The reverse breakdown voltage of a Power Diode must be greater than ________________ . The iv characteristics of a power diode for large forward current is __________ . The average current rating of a power diode _______________ with reduction in the conduction angle due to increase in the current ___________________ . The derating curves of a Power diode provides relationship between the ______________ and the _________________ . 2 i dt rating of a power diode is useful for selecting the ________________ .
Answer: (i) drift, (ii) free wheeling, (iii) VRSM, (iv) linear, (v) decrease, form factor, (vi) IFAVM/IFRM, case temperature, (vii) protective fuse. Version 2 EE IIT, Kharagpur 15 www.jntuworld.com
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For the single phase half wove rectifier shown find out the VRRM rating of D. Will the required VRRM rating change if a inductor is placed between the diode and n capacitor. What will be the required VRRM rating if the capacitor is removed. Assume a resistive load. The source of the single phase rectifier circuit has an internal resistance of 2 . Find out the required Non repetitive peak surge current rating of the diode. Also find the i2t rating of the protective fuse to be connected in series with the diode.
Answer: (a) During every positive half cycle of the supply the capacitor charges to the peak value of the supply voltage. If the load disconnected the capacitor voltage will not change when the supply goes through its negative peak as shown in the associated waveform. Therefore the diode will be subjected to a reverse voltage equal to the peak to peak supply voltage in each cycle. Hence, the required VRRM rating will be
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(c) If the capacitor is removed and the load is resistive the voltage VKN during negative half cycle of the supply will be zero since the load current will be zero. Therefore the reverse voltage across the diode will be equal to the peak supply voltage. So the required VRRM rating will be
VRRM = 2 230V = 325 Volts
(d) Peak surge current will flow through the circuit when the load is accidentally short circuited. The peak surge current rating will be 2 230 I FSM = A = 162.64 A 2 The peak non repetitive surge current should not recur. Therefore, the protective fuse (to be connected in series with the diode) must blow during the negative half cycle following the fault. Therefore the maximum i2t rating of the fuse is
dt
M ax
I 2 F S M S in 2 w td w t =
I 2 F S m = 4 1 .5 5 1 0 3 A 2 s e c
Observed Turn ON behavior of a power Diode: Diodes are often used in circuits with di/dt limiting inductors. The rate of rise of the forward current through the diode during Turn ON has significant effect on the forward voltage drop characteristics. A typical turn on transient is shown in Fig. 2.12.
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Fig. 2.12: Forward current and voltage waveforms of a power diode during Turn On operation. It is observed that the forward diode voltage during turn ON may transiently reach a significantly higher value Vfr compared to the steady slate voltage drop at the steady current IF. In some power converter circuits (e.g voltage source inverter) where a free wheeling diode is used across an asymmetrical blocking power switch (i.e GTO) this transient over voltage may be high enough to destroy the main power switch. Vfr (called forward recovery voltage) is given as a function of the forward di/dt in the manufacturers data sheet. Typical values lie within the range of 1030V. Forward recovery time (tfr) is typically within 10 us. Observed Turn OFF behavior of a Power Diode: Figure 2.13 shows a typical turn off behavior of a power diode assuming controlled rate of decrease of the forward current.
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Fig. 2.13: Reverse Recovery characteristics of a power diode Salient features of this characteristics are: The diode current does not stop at zero, instead it grows in the negative direction to Irr called peak reverse recovery current which can be comparable to IF. In many power electronic circuits (e.g. choppers, inverters) this reverse current flows through the main power switch in addition to the load current. Therefore, this reverse recovery current has to be accounted for while selecting the main switch. Voltage drop across the diode does not change appreciably from its steady state value till the diode current reaches reverse recovery level. In many power electric circuits (choppers, inverters) this may create an effective short circuit across the supply, current being limited only by the stray wiring inductance. Also in high frequency switching circuits (e.g, SMPS) if the time period t4 is comparable to switching cycle qualitative modification to the circuit behavior is possible. Towards the end of the reverse recovery period if the reverse current falls too sharply, (low value of S), stray circuit inductance may cause dangerous over voltage (Vrr) across the device. It may be required to protect the diode using an RC snubber.
During the period t5 large current and voltage exist simultaneously in the device. At high switching frequency this may result in considerable increase in the total power loss. Important parameters defining the turn off characteristics are, peak reverse recovery current (Irr), reverse recovery time (trr), reverse recovery charge (Qrr) and the snappiness factor S. Of these parameters, the snappiness factor S depends mainly on the construction of the diode (e.g. drift region width, doping lever, carrier life time etc.). Other parameters are interrelated and also depend on S. Manufacturers usually specify these parameters as functions of diF/dt for different values of IF. Both Irr and Qrr increases with IF and diF/dt while trr increases with IF and decreases with diF/dt. Version 2 EE IIT, Kharagpur 19 www.jntuworld.com
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The reverse recovery characteristics shown in Fig. 2.13 is typical of a particular type of diodes called normal recovery or soft recovery diode (S>1). The total recovery time (trr) in this case is a few tens of microseconds. While this is acceptable for line frequency rectifiers (these diodes are also called rectifier grade diodes) high frequency circuits (e.g PWM inverters, SMPS) demand faster diode recovery. Diode reverse recovery time can be reduce by increasing the rate of decrease of the forward current (i.e, by reducing stray circuit inductance) and by using snappy recovery (S<<1) diode. The problems with this approach are: i) Increase of diF/dt also increases the magnitude of Irr ii) Large recovery current coupled with snappy recovery may give rise to current and voltage oscillation in the diode due to the resonant circuit formed by the stray circuit inductance and the diode depletion layer capacitance. A typical recovery characteristics of a snappy recovery diode is shown in Fig 2.14 (a).
Fig. 2.14: Diode overvoltage protection circuit; (a) Snappy recovery characteristics; (b) Capacitive snubber circuit; (c) snubber characteristics. Large reverse recovery current may lead to reverse voltage peak (Vrr) in excess of VRSM and destroy the device. A capacitive protection circuit (also called a snubber circuit) as shown in Fig. 2.14 (b) may to used to restrict Vrr. Here the current flowing through Ll at the time of diode current snapping is bypassed to Cs. Ll,Rs & Cs forms a damped resonance circuit and the initial energy stored in Ll is partially dissipated in Rs, thereby, restricting Vrr . Normalized values of Vrr as a function of the damping factor with normalized Irr as a parameter is shown in Fig. 2.14(c). However, it is difficult to correctly estimate the value of Ll and hence design a proper snubber circuit. Also snubber circuits increase the overall power loss in the circuit since the energy stored in the snubber capacitor is dissipated in the snubber resistance during turning ON of the diode. Therefore, in high frequency circuits other types of fast recovery diodes (Inverter grade) are preferred. Fast recovery diodes offer significant reduction in both Irr and trr (10%  20% of a rectifier grade diode of comparable rating). This improvement in turn OFF performance, however, comes at the expense of the steady state performance. It can be shown that the forward voltage drop in a diode is directly proportion to the width of the drift region and inversely proportional to the carrier life time in the drift region. On the other hand both Irr and trr increases with increase in carrier life time and drift region width. Therefore if Irr and trr are reduced by reducing the carrier life time, forward voltage drop increases. On the other hand, if the drift Version 2 EE IIT, Kharagpur 20 www.jntuworld.com
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region width is reduced the reverse break down voltage of the diode reduces. The performance of a fast recovery diode is therefore, a compromise between the steady state performance and the switching performance. In high voltage high frequency circuits switching loss is the dominant component of the overall power loss. Therefore, some increase in the forward voltage drop in the diode (and hence conduction power lass) can be tolerated since the Turn OFF loss associated with reverse recovery is greatly reduced. In some very high frequency applications (fsw >100KHZ), improvement in the reverse recovery performance offered by normal fast recovery diode is not sufficient. If the required reverse blocking voltage is less (<100v) schottky diodes are preferred over fast recovery diodes. Compared to pn junction diodes schottky diodes have very little Turn OFF transient and almost no Turn ON transient. On state voltage drop is also less compared to a pn junction diode for equal forward current densities. However, reverse breakdown voltage of these diodes are less (below 200V) Power schottky diodes with forward current rating in excess of 100A are available. Exerciser 2.3 1. Fill in the blanks with appropriate word(s) i. Forward recovery voltage appears due to higher ohmic drop in the ______________ region of a power diode in the beginning of the Turn On process. ii. The magnitude of the forward recovery voltage is typically of the order of few ______________ of volts. iii. The magnitude of the forward recovery voltage also depends on the _______________ of the diode forward current. iv. The reverse recovery charge of a power diode increases with the _______________ of the diode forward current. v. For a given forward current the reverse recovery current of a Power Diode ______________ with the rate of decrease of the forward current. vi. For a given forward current the reverse recovery time of a Power diode ______________ with the rate of decrease of the forward current. vii. A snappy recovery diode is subjected to _________________ voltage over shoot on recovery. viii. A fast recovery diode has _______________________ reverse recovery current and time compared to a __________________ recovery diode. ix. A Schottky diode has _______________ forward voltage drop and ______________ reverse voltage blocking capacity. x. Schottky diodes have no __________________ transient and very little _________________ transient. Answer: (i) drift, (ii) tens, (iii) rate of rise, (iv) magnitude, (v) increases, (vi) decreases, (vii) large, (viii) lower, (ix) low, law, (x) Turn On, Turn Off. 2. In the buck converter shown the diode D has a lead inductance of 0.2H and a reverse recovery change of 10C at iF =10A. Find peak current through Q.
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Answer: Assuming iL=10A (constant) the above waveforms can be drawn As soon as Q is turned ON. a reverse voltage is applied across D and its lead inductance.
diF 20 = A S ec = 10 7 A S ec dt .2 1 0 6
(s
o)
Q rr = 1
t rr = 1 . 4 1 4 s I rr = diF dt
I rr t rr =
1 diF 2 t rr 2 dt = 1 0 1 0 6 C
t rr = 1 4 . 1 4 A
Q peak
=I
+I
rr
= 24.14 A
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References
1. Ned Mohan, Tore M. Undeland, William P. Robbins, Power Electronics, Converters, Application and Design John Wiley & Sons(Asia), Publishers. Third Edition 2003. 2. P. C. Sen, Power Electronics Tata McGraw Hill Publishing Company Limited, New Delhi, 1987. 3. Jacob Millman, Christos C. Halkias, Integrated Electronics, Analog and Digital Circuits and Systems, Tata McGrawHill Publishing Company Limited, New Delhi, 1991.
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Module Summary
A pn junction diode is a minority carrier, unidirectional, uncontrolled switching device. A power diode incorporates a lightly doped drift region between two heavily doped p type and n type regions. Maximum reverse voltage withstanding capability of a power diode depends on the width and the doping level of the drift region. A power diode should never be subjected to a reverse voltage greater than the reverse break down voltage. The iv characteristics of a forward biased power diode is comparatively more linear due to the voltage drop in the drift region. The forward voltage drop across a conducting power diode depends on the width of the drift region but not affected significantly by its doping density. For continuous forward biased operation the RMS value of the diode forward current should always be less than its rated RMS current at a given case temperature. Surge forward current through a diode should be less than the applicable surge current rating. During Turn On the instantaneous forward voltage drop across a diode may reach a level considerably higher than its steady state voltage drop for the given forward current. This is called forward recovery voltage. During Turn Off the diode current goes negative first before reducing to zero. This is called reverse recovery of a diode. The peak negative current flowing through a diode during Turn Off is called the reverse recovery current of the diode. The total time for which the diode current remains negative during Turn Off is called the reverse recovery time of the diode. A diode can not block reverse voltage till the reverse current through the diode reaches its peak value. Both the reverse recovery current and the reverse recovery time of a diode depends on the forward current during Turn Off, rate of decrease of the forward current and the type of the diode. Normal or slow recovery diodes have smaller reverse recovery current but longer reverse recovery time. They are suitable for line frequency rectifier operation. Fast recovery diodes have faster switching times but comparatively lower break down voltages. They are suitable for high frequency rectifier or inverter free wheeling operation. Fast recovery diodes need to be protected against voltage transients during Turn Off using RC snubber circuit.
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Schottky diodes have lower forward voltage drop and faster switching times but comparatively lower break down voltage. They are suitable for low voltage very high frequency switching power supply applications.
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3. In the voltage commutated chopper T & TA are turned ON alternately at 400 HZ. C is initially charged to 200 V with polarity as shown. Find the IFRMS and VRRM ratings of DI & DF. 4. In the voltage commutated chopper of Problem 5 the voltage on C reduces by 1% due to reverse recovery of DI. Find out Irr & trr for DI. (Assume S = 1 for DI).
5. What precaution must be taken regarding the forward recovery voltage of the free wheeling diodes in a PWM voltage source inverter employing Bipolar Junction Transistors of the npn type?
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Is
102o C
= 2
1 0 2 3 2 10
Is
32o C
= 1 .9 2 m A
Vt at 102 o = 31.97mv
Vt =
KT = 26mv at 32 o C q
V j fo r i F = 2 0 0 A is
V j = Vt
102 C
ln
iF Is
102o C
= 0 .3 7 V
Voltage drop across drift region VR = iF RD = 0.5V Therefore, the total voltage drop across the diode is
VD = VR + V j = 0.87V
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3. Important wave forms of the system are shown in the figure. As soon as T is turned ON the capacitor voltage starts reversing due to the LC resenant circuit formed by CTL & DI. Neglecting all the capacitor voltage reaches a 200V. The current idi is given by
i D I = I D IP S in n
w here I D IP = 200 C L
0 n 7
= 89.44 A
& n =
1 = 22.36103 LC
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Capacitor voltage remains at 200 V till TA is turned ON when it is charged linearly towards +200 V. Time taken for charging is
TC =
2 200 C = 400 s IL
I DIP 2 20
w ith S = 1
Q rr = I rr t rr =
d i dI t rr 2 dt
at n t = ,
di dI = n I DIP = dt
1 C , 200 = 2A s L LC
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Consider turning off operation of Q1. As the current through Q1 reduces D1 turns On. The forward recovery voltage of D1 appears as a reverse voltage across the npn transistor whose base emitter junction must with stand this reverse voltage. Therefore, the forward recovery voltage of the free wheel diodes must be less them the reverse break down voltage of the baseemitter junction of the npn transistors for safe operation of the inverter.
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Module 1
Power Semiconductor Devices
Version 2 EE IIT, Kharagpur 1 www.jntuworld.com
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Lesson 3
Power Bipolar Junction Transistor (BJT)
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Constructional Features, Operating Principles, Characteristics and specifications of Power Bipolar Junction transistors. Objective: On completion the student will be able to 1. Distinguish between, cut off, active, and saturation region operation of a Bipolar Junction Transistor. 2. Draw the input and output characteristics of a junction transistor and explain their nature. 3. List the salient constructional features of a power BJT and explain their importance. 4. Draw the output characteristics of a Power BJT and explain the applicable operating limits under Forward and Reverse bias conditions. 5. Interpret manufacturers data sheet ratings for a Power BJT. 6. Differentiate between the characteristics of an ideal switch and a BJT. 7. Draw and explain the Turn On characteristics of a BJT. 8. Draw and explain the Turn Off characteristics of a BJT. 9. Calculate switching and conduction losses of a Power BJT. 10. Design a BJT base drive circuit.
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3.1 Introduction
Power Bipolar Junction Transistor (BJT) is the first semiconductor device to allow full control over its Turn on and Turn off operations. It simplified the design of a large number of Power Electronic circuits that used forced commutated thyristors at that time and also helped realize a number of new circuits. Subsequently, many other devices that can broadly be classified as Transistors have been developed. Many of them have superior performance compared to the BJT in some respects. They have, by now, almost completely replaced BJTs. However, it should be emphasized that the BJT was the first semiconductor device to closely approximate an ideal fully controlled Power switch. Other transistors have characteristics that are qualitatively similar to those of the BJT (although the physics of operation may differ). Hence, it will be worthwhile studying the characteristics and operation a BJT in some depth. From the point of view of construction and operation BJT is a bipolar (i.e. minority carrier) current controlled device. It has been used at signal level power for a long time. However, the construction and operating characteristics of a Power BJT differs significantly from its signal level counterpart due to the requirement for a large blocking voltage in the OFF state and a high current carrying capacity in the ON state. In this module, the construction, operating principle and characteristics of a Power BJT will be explored.
iE
C (n) + i C
VCC
VCC
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(Emitter) n (E)
(Base) p (B)
(Collector) n (C)
(Emitter) n (E)
(Base) p (B)
(Collector) n (C)
S WBE S BE 0 BE S CB A CB
0 BE
S BE
A BE
A CB
0 CB
A BE
W
A WBE 0 WBE
S CB
0 CB
x
A WBE
S CB
S WBE
A WCB
S CB
0 WCB A WCB
0 WBE
0 WCB
JBE
nS pB
JCB
JBE
pS nB
JCB
pS nE pA nE
n poB p noE n
A pB
pS nC
p noC
nS pE
nA pE p noB
nS pC
n poE
p
A nB
A nC
n poC
nA pC
(a)
(b)
Fig. 3.1: Bipolar junction transistor under different biasing condition. (a) n p n transistor ; (b) p n p transistor. If no external biasing voltages are applied (i.e.; VBB and VCC are open circuited) all transistor currents must be zero. The transistor will be in thermal equilibrium condition with potential o barriers and CB at the base emitter and the base collector functions respectively.
O O Corresponding depletion layer widths will be WBE and WCB . It is clear from the diagram that p type carriers in the base region of an npn transistor are trapped in a potential well and cannot escape. Similarly, in a pnp transistor p type carriers in the emitter and collector regions are separated by a potential hill.
When biasing voltages are applied as shown in the figure, the base emitter junction (JBE) becomes forward biased where as the base collector junction is reverse biased. Potential barrier A and depletion layer width at JBE reduces to and WBE respectively. Both these quantities
A increase at JCB ( A CB , WCB ) . As the potential barrier at JBE is reduced a large number of minority
A carriers are introduced in to Base and the Emitter regions as shown in Fig. 3.1 ( PnE , nA pB for npn
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A transistor and n A pE , p nB for pnp transistor). A portion of the minority carriers reaching the base
recombines with majority carriers. The rest, defuse to the edge of the depletion region at JCB where they are swept away to the collector region by the large electric field. Under this condition the transistor is said to be in the Active region. As VBE is increased injected minority charge into the base region increases and so does the base current and the collector current. For a fixed collector bias voltage VCC, the voltage VCB reduces with increase in collector current due to increasing drop in the external resistance RC. Therefore, the potential barrier at JCB starts reducing. At one point JCB becomes forward biased. The potential barriers and depletion layer widths under this condition are indicated in Fig. 3.1 by variables with a super script s. Due to forward biasing of JCB there will be minority carrier injection into the base from this junction also as shown in Fig. 3.1. The total voltage drop between collector and emitter will be the difference between the forward bias voltage drops at JBE and JCB. Under this condition the transistor is said to be in the saturation region. From the operating principle described above one can form a qualitative idea about the input (iB vs VBE) and output (iC Vs VCE) characteristics of a transistor. In the following section these characteristics of an npn transistor will be discussed qualitatively. Similar explanation applies to a pnp transistor.
B
When a biasing voltage VBB of appropriate polarity is applied across the junction JBE the potential barrier at this junction reduces and at one point the junction becomes forward biased. The current crossing this junction is governed by the forward biased pn junction equation for a given collector emitter voltage. The base current iB is related to the recombination of minority carriers injected into the base from the emitter. The rate of recombination is directly proportional to the amount of excess minority carrier stored in the base. Since, in a normal transistor the emitter is much more heavily doped compared to the base the current crossing JBE is almost entirely determined by the excess minority carrier distribution in the base. Thus, it can be concluded that the relationship between iB and VBE will be similar to the iv characteristics of a pn junction diode. VCE, however have some effect on this characteristic. As VCE increases reverse bias of JCB increases and the depletion region at JCB moves deeper into the base. The effective base width thus reduces, reducing the rate of recombination in the base region and hence the base current. Therefore iB for a given VBE reduces with increasing VCE as shown in Fig. 3.2(a).
B B B
It has been mentioned before that only a fraction (denoted by the letter ) of the total minority carriers injected into the base reaches junction JCB where they are swept in to the collector region by the large electric field at JCB. These minority carriers constitute the major component of the total collector current. The other component of the collector current consists of the small reverse saturation current of the reverse biased junction JCB. Therefore IC = IE + Ics Where Ics is the reverse saturation current of junction JCB But IE = IB + IC
B
(3.1) (3.2)
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IC =
By defining
IC = IB + (+1) Ics
ICS + IB 1 1
(3.3)
(3.4)
is called the large signal common emitter current gain of the transistor and remains fairly constant for a large range of IC, as shown in Fig. 3.2 (c). Fig: 3 (b) shows the complete out put characteristics (ic vs VCE) of an npn transistor.
With VBB = 0 or negative there is little injected minority carrier into the base from the emitter side. Therefore, iB = 0 and iC is negligibly small. The transistor is said to be in the cut off region under this condition.
B
As VBB is increased from zero, base current starts flowing. From equation (3.4) it will be expected that the collector current should increase proportionately independent of VCE. However Fig 3.2 (b) does indicate a slight increase in iC with VCE for a given iB. This is expected because with increasing VCE a larger value of VBE will be required to maintain a given iB (Fig. 3.2 (a)). Therefore, the component IE of collector current will increase. ICS is ,for all practical purpose, independent of VCE. This is the active or amplifier mode of operation of a transistor.
B B
In the active region as iB increases iC also increases. For a given value of VCC, VCE reduces with increasing iC due to increased drop in an external load (i.e., Rc in Fig 3.1). At one point the junction JCB becomes forward biased. VCE, now is just the difference between the voltages across two forward biased junction JBE and JCB (a few handed milli volts). This is when the transistor enters the saturation mode of operation. The ratio iC/iB at the onset of saturation is called Min and is an important parameter for a power transistor. In saturation iC is almost entirely determined by the external load and further increase in iB changes iC or VCE very little.
B B
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iC
Saturation
iB increasing
vCE
(a)
(b)
(c)
Fig. 3.2: Input and output characteristics of an n p n transistor. (a) Input characteristics; (b) Output characteristics; (c) Current gain[] characteristics Exercise 3.1
Fill in the blank(s) with the appropriate word(s) a) Under forward bias condition a large number of ___________________ carriers are introduced in the base region. b) Some minority charge carriers reaching base __________________ with majority carriers there and the rest of them ___________________ to the collector. c) When the baseemitter junction of a BJT is forward biased while the basecollector junction is reverse biased the BJT is said to be in the _______________ region. d) When both BE & CB junction of a BJT are reverse biased it is said to be in the _________________ region. e) When both BE & CB junction of a BJT are forward biased it is said to be in the _______________ region. Version 2 EE IIT, Kharagpur 8
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Answer: (a) minority; (b) recombine, diffuse; (c) active; (d) cutoff; (e) saturation. Exercise 3.2
Why does the collector current of a BJT in the active region increases with increasing collector voltage for a given base current.
Answer: In the active region as the VCE voltage is increased the depletion layer width at the CB junction increases and the effective base width reduces. Therefore, for a given VBE recombination of minority carriers in the base region reduces and base current also reduces. In order to main constant base current with increasing VCE, VBE must increased. Therefore, for a constant base current the number of minority carriers in the base region will increase and consequently, collector current will increase. Exercise 3.3
= 7.95,
A power BJT has a vertically oriented alternating layers of n type and p type semiconductor materials as shown in Fig 3.3(a). The vertical structure is preferred for power transistors because it maximizes the cross sectional area through which the on state current flows. Thus, on state resistance and power lass is minimized. In order to maintain a large current gain (and hence reduce base drive current) the emitter doping density is made several orders of magnitude higher than the base region. The thickness of the base region is also made as small as possible. In order to block large voltage during OFF state a lightly doped collector drift region is introduced between the moderately doped base region and the heavily doped collector region. The function of this drift region is similar to that in a Power Diode. However, the doping density donation of the base region being moderate the depletion region does penetrate considerably into the base. Therefore, the width of the base region in a power transistor can not be made as small as that in a signal level transistor. This comparatively larger base width has adverse effect on the current gain () of a Power transistor which
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typically varies within 520. As will be discusses later the collector drift region has significant effect on the out put characteristics of a Power BJT.
Practical Power transistors have their emitters and bases interleaved as narrow fingers. This is necessary to prevent current crowding and consequent second break down. In addition multiple emitter structure also reduces parasitic ohmic resistance in the base current path.
These constructional features of a Power BJT are shown schematically in Fig 3.3(a). Fig.3.3 (b) shows the photograph of some community available Power transistors in different packages. Emitter contact
Base contact
n+ (emitter)
n+ p (Base)
n+
(a)
Collector contact
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(b) Fig. 3.3: Constructional Features of a Power Bipolar Junction Transistor (a) Schematic of Construction, (b) Photograph of commercial packages. Exercise 3.4
Fill in the blank(s) with the appropriate word(s) a) Doping density of the emitter of a Power BJT is several orders of magnitude ______________ than the base doping density. b) Collector drift region is introduced in a Power BJT to block _______________ voltage. c) Doping density of the base region in a power BJT is ________________. d) Power BJT has ________________ DC current gain compared to signal level transistors. e) In a Power BJT multiple, narrow finger like distributed emitter structure is used to avoid emitter ___________________.
Answer: (a) higher; (b) high reverse; (c) moderate; (d) low; (e) current crowding. Exercise 3.5
What are the constructional features of a power transistor that affect the dc current gain?
Large doping density of the emitter increases dc current gain. Moderately doped base regain of relatively larger width tend to reduce the dc current gain. The base width in a power transistor cannot be reduced below a certain level in order to avoid reach through of the base region under large applied voltage. Multiple, narrow emitter regions distributed uniformly over the entire device cross section also tends to improve dc current gain by minimizing current crowding.
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Power Transistor in the Cut off and Active regions are qualitatively identical to a signal level transistor. Certain quantitative restrictions apply, however, which are discussed next. iC Hard Saturation Quasi Saturation iB10 iB9 iB8 iB7 iB6 iB5 iB4 iB3 iB2 iB1 iB 0 Cut off
CE
In the cut off region (iB 0) the collector current is almost zero. The maximum voltage between collector and emitter under this condition is termed Maximum forward blocking voltage with base terminal open (iB = 0) and is denoted by VCEO. For all practical purpose this is the maximum voltage that can be applied in the forward direction (C positive with respect to E) across a power transistor since a power transistor is expected to see any significant forward voltage only with iB = 0. This blocking voltage can however be increased to a value VCBO by keeping the emitter terminal open. In this case iB < o. Actually VCBO is the breakdown voltage of the collector base junction. However, since the open base configuration is more common the value of VCEO is used by the manufacturers as the maximum voltage rating of a power transistor. Power transistors have poor reverse voltage withstanding capability due to low break down voltage of the baseemitter junction. Therefore, reverse voltage (C negative with respect to E) should not appear across a power transistor.
B B B
In the active region the ratio of collector current to base current (DC current Gain ()) remains fairly constant upto certain value of the collector current after which it falls off rapidly. Manufacturers usually provide a graph showing the variation of as a function of the collector current for different junction temperatures and collector emitter voltages. This graph is useful for designing the base drive of a Power transistor. Typically, the value of the dc current gain of a Power transistor is much smaller compared to their signal level counterpart.
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The maximum collectoremitter voltage that a power transistor can withstand in active region is determined by the Base collector avalanche break down voltage. This voltage, denoted by VSUS in Fig, 3.4 is usually smaller than VCEO. The voltage VSUS can be attained only for relatively lower values of collector current. At higher collector current the limit on the total power dissipation defines the boundary of the allowable active region as shown in Fig 3.4. At still higher levels of collector currents the allowable active region is further restricted by a potential failure mode called the Second Break down. It appears on the output characteristics of the BJT as a precipitous drop in the collectoremitter voltage at large collector currents. The collector voltage drop is often accompanied by significant rise in the collector current and a substantial increase in the power dissipation. Most importantly this dissipation is not uniformly spread over the entire volume of the device but is concentrated in highly localized regions. This localized heating is a combined effect of the intrinsic non uniformity of the collector current density distribution across the cross section of the device and the negative temperature coefficient of resistively of minority carrier devices which leads to the formation of current filamements (localized areas of very high current density) by a positive feedback mechanism. Once current filaments are formed localized thermal runaway quickly takes the junction temperature beyond the safe limit and the device is destroyed. It is in the saturation region that the output characteristics of a Power transistor differs significantly from its signal level counterpart. In fact the saturation region of a Power transistor can be further subdivided into a quasi saturation region and a hard saturation region. Appearance of the quasi saturation region in the output characteristics of a power transistor is a direct consequence of introducing the drift region into the structure of a power transistor. In the quasi saturation region the basecollector junction is forward biased but the lightly doped drift region is not completely shorted out by excess minority carrier injection from the base. The resistivity of this region depends to some extent on the base current. Therefore, in the quasi saturation region, the base current still retains some control over the collector current although the value of decreases significantly. Also, since the resistivity of the drift region is still significant the total voltage drop across the device in this mode of operation is higher for a given collector current compared to what it will be in the hard saturation region. In the hard saturation region base current looses control over the collector current which is determined entirely by the collector load and the biasing voltage VCC. This behavior is similar to what happens in a signal transistor except that the drift region of a power transistor continues to offer a small resistance even when it is completely shorted out (by excess carrier injection from the base). Therefore, for larger collector currents the collectoremitter voltage drop is almost proportional to the collector current. Manufacturers usually provide the plots of the variation of VCE (sat) vs. iC for different values of base current and junction temperature. Curves showing the variation of VCE (sat) with iB for different values of iC and junction temperature are also provided by certain manufacturers.
B
Applicable operating limits on a power transistors are compactly represented in two diagrams called the Forward Bias Safe Operating Area (FBSOA) and the Reverse Bias Safe Operating Area. (RBSOA) applicable to iB > 0 and iB 0 conditions respectively. Typical safe operating areas of power transistors are shown in Fig 3.5.
B B
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iC ICM
Log CE VSUS
(b)
Fig. 3.5: Safe operating areas of a Power Transistor. (a) FBSOA; (b) RBSOA.
The horizontal upper limit of the FBSOA is determined by the maximum allowable collector current (ICM) that should not be exceeded even as a pulse. Exceeding this current limit may cause bonding wire or metallization of the wafer to vaporize or otherwise fail. Since a power transistor does not have any appreciable reverse voltage blocking capacity they are usually not used in ac circuits. However, if the collector current, for some reason is not dc or a pulse, the rms value of the collector current waveform should not exceed this limit. The next applicable limit in the FBSOA (green lines) corresponds to the restriction on the maximum allowable power dissipation and maximum junction temperature. Since FBSOA is shown on a loglog scale constant Power dissipation (Pd = VCE iC) limits appear as straight lines. This limit is different for dc and pulsed operation due to the thermal time constant of the device. The DC limit is applicable to the average power loss if the transistor remains continuously in the conduction state (active, quasi saturation or saturation). On the other hand the pulsed power dissipation limits are applicable to conduction duration up to the value marked on them (the figures on the right of Fig 3.5 (a)). Pulsed power dissipation limits are specified for a low value (1%2%) of duty cycle and are useful for shaping the switching trajectory of the transistor as will be seen later. The third limit of the FBSOA (red line) arises due to the second break down failure mode of a Power transistor. It shows the limiting combinations of collector voltage and current so that second break down does not occur. On the log log scale of the FBSOA this limit also appears as a straight limit. Like the maximum power dissipation limit, the second break down limit is also different for DC and Pulsed operation of different pulse durations. The interpretation of the pulse duration (marked on the right side of Fig 3.5 (a)) corresponding to a particular limit is also same. The final limit of the FBSOA corresponds to the forward biased avalanche break down voltage (VSUS) of the transistor and appear as a vertical line in the FBSOA at VCE = VSuS Version 2 EE IIT, Kharagpur 14
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The FBSOA of a Power transistor is given at a specified case temperature. Both the maximum power dissipation limit and the second break down limits are to be derated as per the derating characteristics provided by the manufacturers when the case temperature exceeds the specified value. In contrast to the FBSOA, the RBSOA (Fig 3.5 (b)) is plotted on a linear scale and has a more rectangular shape. RBSOA is a switching SOA since a transistor can not conduct current for any appreciable duration under reverse biased condition. It essentially shows the limiting permissible combinations of VCE & iC with base emitter junction reverse biased. The upper horizontal limit corresponds to the maximum allowable collector current (ICM) and is same as that in the FBSOA. The right hand side vertical limit corresponds the avalanche break down voltage of the transistor with reverse bias. If the base terminal is open (i,e, iB = 0) then this voltage is VCEO. If a negative voltage is applied across the BE junction the right hand side limit of the RBSOA increases somewhat to the value VCBO at low value of the collector current.
B
In addition to the applicable limits on the output characteristics as represented in the FBSOA and the RBSOA, limiting specification with respect to the base emitter junction is also provided by the manufacturer. Typical specifications that are provided are VEBO : This is maximum allowable reverse bias voltage across the BE junction IB
B
: Maximum allowable average base current at a given case temperature. : Maximum allowable peak base current at a given case temperature and of specified pulse duration.
B
IBM
The input characteristics (iB Vs VBE) at a given case temperature is also provided.
Exercise 3.6
Fill in the blank(s) with the appropriate word(s) a) In the Cut off region collector current of a Power Transistor is _____________. b) In the __________________ region of a Power Transistor the dc current gain remains fairly constant. c) Saturation region of a Power Transistor can be divided into _______________ region and ______________________ region. d) Active region operation of a Power BJT is limited mostly by _______________ consideration. e) Second breakdown in a Power BJT occurs due to ________________ of the collector current distribution. Answer: (a) negligible; (b) active; (c) Quasi saturation, hard saturation; (d) Power dissipation; (e) non uniformity.
3.5
In a power electronic circuit the power transistor is usually employed as a switch i.e. it operates in either cut off (switch OFF) or saturation (switch ON) regions. However, the operating Version 2 EE IIT, Kharagpur 15
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characteristics of a power transistor differs significantly from an ideal controlled switch in the following respects.
It can conduct only finite amount of current in one direction when ON It can block only a finite voltage in one direction. It has a voltage drop during ON condition It carries a small leakage current during OFF condition Switching operation is not instantaneous It requires non zero control power for switching
Of these the exact nature and implication of the first two has been discussed in some depth in the previous section. The third and fourth non idealities give rise to power loss termed the conduction power loss. In this section the nature and implications of the last two non idealities will be discussed in detail.
Exercise 3.7
Fill in the blank(s) with the appropriate word(s) a) An ideal switch can conduct current in ______________ directions. While a power transistor conducts current in _______________ direction. b) In power transistor there will be power loss due to ON state ________________ and OFF state _________________. c) Unlike an ideal switch the switching of a power transistor is not ____________. Answer: (a) two, one; (b) voltage drop, leakage current; (c) instantaneous.
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VCC
iD
IL
iC + RB iB Q VCE
VBE VBB
(a)
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VBB VBE 0
td
tri
tfv1 tfv2
iB t
ic id IL IL t
(b)
Fig 3.6 Turn ON characteristics of a power transistor; (a) Switching circuit, (b) Switching wave forms
The switching wave forms shown in Fig 3.6 (b) are the expanded and to some extent idealized version of the actual waveforms that will be observed in a clamped inductive switching circuit as shown in Fig.3.6 (a). Some simplifying assumptions have been made to draw these waveforms. These are Version 2 EE IIT, Kharagpur 18
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The load inductor has been assumed to be large enough so that the load current does not change during Turn ON period. Reverse recovery characteristics of D has been ignored. All parasitic elements have been ignored.
Before t = 0, the transistor (Q) was in the OFF state. In order to utilize the increased break down voltage (VCBO) the baseemitter junction of a Power Transistor is usually reverse biased during OFF state. Under this condition only negligible leakage current flows through the transistor. Power loss due to this leakage current is negligible compared to other components of power loss in a transistor. Therefore, it is not shown in Fig 3.6 (b). The entire load current flows through the diode and VCE is clamped to VCC (approximately). To turn the transistor ON at t = 0, the base biasing voltage VBB changes to a suitable positive value. This starts the process of charge redistribution at the baseemitter junction. The process is akin to charging of a capacitor. Indeed, the reverse biased base emitter junction is often represented by a voltage dependent capacitor, the value of which is given by the manufacturer as a function of the baseemitter reverse bias voltage. The rising base current that flows during this period can be thought of as this capacitor charging current. Finally at t = td the BE junction is forward biased. The junction voltage and the base current settles down to their steady state values. During this period, called the Turn ON delay time no appreciable collector current flows. The values of iO and VCE remains essentially at their OFF state levels. At the end of the delay time (td ON) the minority carrier density at the base region quickly approaches its steady state distribution and the collector current starts rising while the diode current (id) starts falling. At t = tdON + tri the collector current becomes equal to the load current (and id becomes zero) IL. At this point D starts blocking reverse voltage and VCE becomes unclamped. tri is called the current rise time of the transistor. At the end of the current rise time the diode D regains reverse blocking capacity. The collector voltage VCE which has so far been clamped to VCC because of the conducting diode D starts falling towards its saturation voltage VCE (sat). The initial fall of VCE is rapid. During this period the switching trajectory traverses through the active region of the output characteristics of the transistor. At the end of this rapid fall (tfv1) the transistor enters quasi saturation region. The fall of VCE in the quasi saturation region is considerably slower. At the end of this slow fall (tfv2) the transistor enters hard saturation region and the collector voltage settles down to the saturation voltage level VCE (sat) corresponding to the load current IL. Turn ON process ends here. The total turn on time is thus, TSW (ON) = td (ON) + tri + tfv1 + tfv2. Power loss occurs at all time during the operation of a power transistor. However, the collector leakage current is usually negligibly small and power loss due it can be safely neglected in comparison to the power loss during ON condition. Power loss occurs during Turning ON a Power transistor due to simultaneous existence of nonzero VCE and ic during tri, tfv1, and tfv2. The energy lost during these periods is called the Turn ON loss and given by the area under the Pl curve in Fig 3.6 (b). The average Turn ON loss is obtained by dividing this area by (tri + tfv1 + tfv2). For safe Turn ON this average power loss must be less than the limit set on the maximum
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power dissipation in the FBSOA corresponding to a pulse width greater than tri + tfv1 + tfv2. Similar restriction with respect to second break down should also be observed. Turn ON time can be reduced by increasing the base current. However large base current increases the quantity of excess carrier in the base and collector drift region which has to be removed during Turn Off. As will be seen later this increases the Turn OFF time. The Turn ON delay time can however be reduced by boosting the base current at the beginning of the Turn ON process. This can be achieved by connecting a small capacitance across RB. This increases the rate of rise of VBE & iB. Therefore, Turn ON delay time decreases. However, in steady state iB settle downs to a value determined by RB & VBB and no adverse effect on the Turn OFF time is observed.
B B B B
In figure 3.6 (b) the reverse recovery current of D has been neglected. If this current is not negligible then for safe Turn ON operation the sum of the load current and the diode reverse recovery current must be less than the ICM rating of the transistor. Thermal and second break down limits must also be observed. It should be noted that there is some power loss at the BE junction as well. This power loss depends on the current gain of the transistor during hard saturation. Since current gain reduces during saturation (typically between 5 to 10) this power loss may become significant. Manufacturers usually provide the values of td (ON), tri, tfv as functions of ic for a given base current and case temperature.
Exercise 3.8
Fill in the blank(s) with the appropriate word(s) a) For faster switching of a BJT _______________ carriers are to be swept quickly from the ________________ region. b) The reverse biased base emitter junction can be represented as a ______________ dependent __________________. c) In the quasi saturation region collectoremitter voltage falls at a ______________ rate. d) Turn ON delay can be reduced by __________________ the rate of rise of the base current. Answer: (a) minority, base; (b) voltage, capacitor; (c) slow; (d) increasing.
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VBE(sat) t
iB t
t ts trv1 trv2
(a)
tfi
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log iC ICM
Reverse recovery current of D P P FBSOA RBSOA Forward recovery Voltage of D Turn on Trajectory VCBO
(b)
V(sus) VCEO
log vCE
Fig. 3.7: Turn off, characteristics of a BJT. (a) Switching wave forms (b) Switching trajectory
The Turn OFF process starts with the base drive voltage going negative to a value VBB. The baseemitter voltage however does not change from its forward bias value of VBE(sat) immediately, due to the excess, minority carriers stored in the base region. A negative base current starts removing this excess carrier at a rate determined by the negative base drive voltage and the base drive resistance. After a time ts called the storage time of the transistor, the remaining stored charge in the base becomes insufficient to support the transistor in the hard saturation region. At this point the transistor enters quasi saturation region and the collector voltage starts rising with a small slope. After a further time interval trv1 the transistor completes traversing through the quasi saturation region and enters the active region. The stored charge in the base region at this point is insufficient to support the full negative base current. VBE starts falling forward VBB and the negative base current starts reducing. In the active region, VCE increases rapidly towards VCC and at the end of the time interval trv2 exceeds it to turn on D. VCE remains clamped at VCC, thereafter by the conducting diode D. At the end of trv2 the stored base charge can no longer support the full load current through the collector and the collector current starts falling. At the end of the current fall time tfi the collector current becomes zero and the load current freewheels through the diode D. Turn OFF process of the transistor ends at this point. The total Turn OFF time is given by Ts (OFF) = ts + trv1 + trv2 + tfi As in the case of Turn ON considerable power loss takes place during Turn OFF due to simultaneous existence of ic and VCE in the intervals trv1, trv2 and tfi. The last trace of Fig 3.7 (a) shows the instantaneous power loss profile during these intervals. The total energy last per turn off operation is given by the area under this curve. For safe turn off the average power dissipation during trv1 + trv2 + tfi should be less than the power dissipation limit set by the FBSOA corresponding to a pulse width greater than trv1 + trv2 + tfi.
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Turn OFF time intervals of a power transistor are strongly influenced by the operating conditions and the base drive design. Manufacturers usually specify these values as functions of collector current for given positive and negative base current and case temperatures. Variations of these time intervals as function of the ratio of positive to negative base currents for different collector currents are also specified. In this section and the precious one inductive load switching have been considered. However, if the load is resistive. The freewheeling diode D will not be used. In that case the collector voltage (VCE) and collector current (ic) will fall and rise respectively together during Turn ON and rise and fall respectively together during Turn OFF. Other characteristics of the switching process will remain same. The switching Power loss in this case will also be substantially lower.
Exercise 3.9
Fill in the blank(s) with the appropriate word(s) a) Turn OFF process in a BJT is associated with transition from the _______________ region to the ______________ region. b) Negative _______________ current is required to remove excess charge carriers from the ______________ region of a BJT during Turn OFF process. c) VCE increases rapidly in the ________________ region. Answer: (a) Saturation, Cutoff; (b) base, base; (c) active.
E ON =
Where VCEf1 is the value of VCE at the end of the interval tfv1 Similarly
If the switching frequency of the transistor is fSW, then the average switching power loss is given by
( 3.7 )
Version 2 EE IIT, Kharagpur 23
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On the other hand the conduction energy loss is given by the area hatched black in Fig 3.6 (b) and 3.7(a). From these figures the conduction power loss is given by
( 3.9)
For a given VCC and IL and base drive design, EON and EOFF are constant. Therefore, the switching power loss is proportional to the switching frequency. Being a minority carrier device a BJT has comparatively larger switching times (compared to some other devices broadly categorized as transistors) and hence larger switching power loss for a given frequency. On the other hand a BJT has the lowest ON state voltage drop VCE (sat) among all fully controlled switches. Therefore, a BJT is suitable for switching large current at moderate (around a few KHZ) switching frequency. At high frequency BJT based circuits tend to become inefficient due to increased switching power loss. Even without any restriction on the switching power loss the maximum switching frequency of a BJT is limited by its Turn ON and Turn OFF times. The value of the maximum switching frequency is given by
FSW ( Max ) =
( 3.10 )
For a given collector current and base drive design. For safe switching operation, however it is not sufficient to merely restrict the switching power loss. It will be necessary to restrict the switching trajectory (an instantaneous plot of ic vs VCE during switching with time as a parameter) within the FBSOA /RBSOA region corresponding to a pulse width greater than TSW (ON) or TSW (OFF). Fig 3.7 (b) shows these switching trajectories superimposed on the FBSOA /RBSOA. In this diagram the green line corresponds to the Turn ON trajectory while the blue line corresponds to the Turn OFF trajectory. These trajectories are rectangular in nature. Clearly full voltage (VCEO) or current rating (ICM) of the transistor can not be utilized in such a trajectory. The situation becomes worse a when the reverse recovery current and forward recovery voltage of D is considered. Switching aid circuits or snubbers (as they are popularly known) are used to enhance the switching performance of a power transistor. They serve two specific purpose.
Shape the switching trajectory such that the voltage and current rating of a transistor can be fully utilized. Version 2 EE IIT, Kharagpur 24
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Fig. 3.8 shows a typical snubber circuit for a power transistor and the corresponding switching trajectories. VCC
D IL LS RS iC
DS CS
RB VBB
iB
Q VCE
+
(a)
logic ICM IL
RBSO FBSO A Turn on Turn off log vCE VCE(sus) VCEO VCBO
VCC
(b)
Fig. 3.8: Switching characteristics of a BJT with Snubber (a) Clamped inductive switching circuit with snubber (b) Switching trajectory.
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Fig 3.8 (a) shows the same clamped inductive switching circuit of Fig 3.6 (a) but with the snubber elements. The inductor LS connected between the load and the collector is the Turn ON snubber. In decouples the collector from the supply voltage during Turn ON. Therefore, as the junction VBE becomes forward biased VCE starts falling. At the same time ic also starts rising towards IL. The resultant switching trajectory is shown by the solid green line in Fig 3.8 (b). This should be compared with the unsnubbed Turn ON trajectory (broken green line). In the unsnubbed case, the collector current rises to the maximum value before VCE starts falling from VCC. VCC, therefore, must necessarily be smaller than VCE (SUS). In the snubber assisted trajectory VCE falls substantially before ic rises to any appreciable value. Therefore, VCC can be made larger than VCE(sat) and can be chosen closer to VCEO. Maximum collector current that can be handled is also considerably higher
(I
L Max
maximum IL is restricted essentially by the maximum power dissipation consideration and not by ICM. LS also helps to reduce Irr (D) by restricting the rate of decrease of current through D. This also helps to increase
I L Max
RsCsDs constitute the Turn OFF snubber. This is popularly known as the RCD snubber. During Turn OFF as the base drive of Q is removed ic starts falling and the remaining load current is bypassed to Cs through Ds. Therefore, the collector voltage rises simultaneously giving rise to the Turn OFF trajectory shown by the solid blue line in Fig 3.8 (b). At the end of the Turn OFF process VCE shoots over VCC due to LsCs oscillation. However, by proper design
VCE Max
can be restricted well below VCBO. Therefore, the turn OFF snubber circuit can effectively utilize the enhanced voltage withstanding capability of a power transistor with base reverse biased. Comparison of the switching trajectories with and with out snubber circuit makes it evident that the snubber circuit can considerably enhance the voltage and current capacity utilization of a Power transistor. The area enclosed under the switching trajectories is a measure of the switching loss occurring in the device at each switching. Therefore, it is evident from Fig 3.8 (b) that the snubber circuit reduces the switching power loss inside the device considerably. However, it should be emphasized that the total switching loss (device + snubber resistance) may not reduce. It is also necessary to place the snubber components very close to the transistor since any stray inductance in the Rs Cs Ds loop may give rise to an unacceptably large voltage spike across Q. Components should also be chosen very carefully. Rs must be non inductive and the lead inductances of Ds and Cs must be kept to a minimum Power loss in Rs can be considerably large and its wattage should selected accordingly. To avoid excessive power loss in Rs, lossless (regenerate) snubber circuits have been proposed.
Exercise 3.10
Fill in the blank(s) with the appropriate word(s) a) BJT has large switching times, since it is a _________________ carrier device. b) BJT has _______________ ON state voltage drop. c) BJT is inefficient at ______________ switching frequencies. Version 2 EE IIT, Kharagpur 26
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d) Turn OFF snubber circuit is used to improve _______________ withstand capacity of a BJT. Answer: (a) minority; (b) low; (c) high; (d) voltage.
Exercise 3.11
What are the effects of introducing a drift region in the output iv characteristics of a power transistor?
Answer: The drift region in a power transistor is introduced in order to block large forward voltage. However, one effect of introducing the drift region is the appearance of a quasi saturation region in the output iv characteristics of a power transistor. In the quasi saturation state the drift region is not completely shorted out by conductivity modulation by excess carriers from the base region. In offers a resistance which is a function of the base current. Although the base current retain some control over collector current in this state the value of dc current gain reduces substantially due to increased effective base width.
Another effect of introducing the drift region is to make the VCE saturation voltage depend linearly on the collector current in the hard saturation region due to the ohmic resistance of the conductivity modulated drift region.
Exercise 3.12
Explain the importance of the following manufacturers specifications (a) FBSOA, (b) vs ic characteristics, (c) iB vs VBE characteristics
B
Answer: (a) FBOSOA compactly represents the safe operating limits of a power transistor in terms of maximum forward current, maximum forward voltage, maximum average & instantaneous power dissipation and second break down limits. It is most useful in designing the switching trajectory of a power transistor.
(b) This characteristics gives the amount of base current required so that the transistor can operate in the saturation mode for a given collector current. (c) After the base current is determined, this characteristics is used to design the base drive circuit for a given base power source.
The rate of rise of base current in the beginning of the turn on process determines the turn on delay time. The magnitude of the base current during turn on decides the values of the voltage fall time, current rise time and VCE (sat) for a given collector current. Version 2 EE IIT, Kharagpur 27
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The negative base current during turn off determines the storage time, voltage rise time and current fall time. A negative bias at the base also enhances the voltage withstanding capacity of a power transistor. From the discussion of the switching characteristics of a BJT it is evident that the base drive voltage source should be bipolar and the base drive resistance should be different during turn on and turn off. The following step by step procedure can be followed to arrive at the values.
From the load current value (to be switched) and desired conduction power loss the desired value of VCE (sat) is determined. Using the desired value of VCE (sat) for the given load current, the required value of forward base current (iBP) and the corresponding VBE (sat) is obtained from the manufacturers data sheet.
The forward and reverse base drive voltages (VBB + & VBB ) are decided on the basis of the availability of control power supply. These should be kept as low as possible in order to reduce base drive power requirement.
R BP =
( 3.11)
It has been mentioned earlier that the turn on delay time can be reduced by increasing the rate of rise of iBP at the beginning of the turn ON process. This is achieved by connecting a small capacitor across RBP.
Once iBP is known the turn on loss is fixed. The allowable turn off loss is determined by subtracting the turn on loss for the desired total switching loss. The required current fall and voltage rise times for the calculated turn off loss is determined for the given load current and VCC.
A suitable negative base current (iBN) to give the desired voltage rise time is determined from the manufacturers data sheet. RBN is given
R BN =
( 3.12 )
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Once iBN is fixed the storage time (ts) can be determined from the manufacturers data sheet. The storage time can be reduced by connecting a small capacitor across RBN. The resulting base drive circuit can be realized as shown in Fig 3.9 VBB +
R2
RBN
Electrical Isolation
VBB 
Power transistors have low values of dc current gain () compared to their signal level counterpart. Particularly, if a low value of VCE (sat) is desired at full load current, can be as low as 5. With such low gain large current switching becomes difficult since the base drive circuit is required to handle about 20% of the full load current, Monolithic, Darlington connected transistors can solve this problem. Fig 3.10 shows the circuit connection and the vertical cross section of a Monolithic Darlington pair. The effective current gain of a Darlington pair is given by
= M D + M + D
( 3.13)
So that even when individual s are small effective can still be quite large.
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iCD IBD
C IL
iCM QD iED QM
iBM
(a)
E iED E
n+
n
iCD
n
iCM
n+
n+
C
(b) Fig 3.10: Monolithic Darlington connected power transistor. (a) circuit diagram, (b) schematic cross section.
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In the Darlington configuration the base drive current for the main transistor is derived from the collector biasing power supply through a drive transistor. This drive transistor should have the same voltage rating as the main transistor but lower current rating. In a monolithic design both are fabricated from the same crystal. The silicon protrusion through the p layer (the base region for both transistors) isolates the two bases from each other. A discrete diode D is added (Fig 3.10 (a)) to speed up the turn off time of the main transistor. The major quantitative difference in the operating characteristics of a Power Darlington is due to the fact that the main transistor can not go into hard saturation. The ON state voltage drop of the drive transistor prevents forward biasing of the CB junction of the main transistor. Therefore, the ON state power dissipation of the main transistor will be larger than that of an otherwise comparable single BJT. The switching times will also be somewhat larger for the Darlington transistor.
Exercise 3.13
A Power BJT is used to switch an inductive load carrying 20 A. The supply voltage is 200V, switching frequency and duty cycle are 1 KHZ and 0.5 respectively. Switching times are as follows. td = 1s, tri = tfv1 = 8 s, tfv2 = 0, ts = 12 s, tfi = trv2 = 8 s, trv1 = 0. VCE sat = 1.0V at i c = 20 A Calculate switching and conduction losses in the transistor.
Answer: Turn on energy loss is given by.
E ON = 1 V I ( t + t ) = 32 mJ 2 CC L ri fv1
E off = 1
( D fsw  t
 t ri  t fv + t s = 9.9 mJ
With reference to Fig. 3.9 determine the values of the base resistors RBP & RBN for the following data VBB+ = 10 volts, VBB = 10 V, IBP = 2.5 A, IBN = 1.5 A, VBE drive transistors) = 0.3 V
sat
= 0.7 V , VCE
sat
(of
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Answer: R BP =
sat
= 3.6 ohms.
R BN =
VBE
sat
 VCE I BN
sat
 VBB
= 6.93 ohms
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References
1) Jacob Millman, Christos C. Halkis, Integrated Electronics, Analog and Digital circuit and systems, Tata McGrowHill publishing Company Limited, New Delhi, 1991. 2) Ned Mohan, Tore M. Undeland, William P. Robbins, Power Electronics, Converters, Application and Design. John Willey & Sons (Asia) Publishers, Third Edition, 2003.
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Lesson Summary
A Bipolar Junction Transistor is a minority carrier, current controlled unidirectional device. A BJT can be of npn or pnp type with three terminals called the collector, the base and the emitter. A BJT can operate in cutoff, active or saturation regions. In the cutoff region the base emitter junction is reverse biased and the collector current is almost zero. In the active region the ratio of collector current to base current is fairly constant. This ratio is called the dc current gain (). A transistor can be driven into saturation by increasing the base current for a given collector current. In saturation the VCE voltage drop of a transistor is very low. For power application normally, npn type transistor in the common emitter configuration with the base as the control terminal is used. They operate either in the cutoff, or saturation mode. For safe operation power transistors must observe maximum current, maximum voltage, maximum power dissipation and second break down limits. Operating restrictions applicable to a power transistor under forward and reverse bias conditions are represented compactly in FBSOA & RBSOA diagrams respectively. Power transistor output iv characteristics exhibits a quasi saturation region not found in their signal level counterpart. It is the direct consequence of introducing a lightly doped n drift region in the structure of a power transistor which enhances its forward voltage blocking capacity. Switching of Power transistors from ON (saturation) to OFF (cutoff) state involves considerable redistribution of minority carriers. Therefore, switching operation is not instantaneous. Switching characteristics of a power transistor is greatly influenced by the external load circuit and the base drive circuit. Energy loss takes place during each switching operation of a power transistor due to simultaneous existence of collector current and voltage. This is called switching loss. Energy loss taking place during ON condition of the transistor is called the conduction loss. Conduction loss during the OFF state of a Power transistor is negligibly small. Switching power loss is proportional to the switching frequency while the conduction power loss is proportional to the duly cycle. BJT being a minority carrier device have low on state voltage drop and longer switching delay times compared to some majority carrier transistors. Consequently, BJT has higher switching loss and lower conduction loss. A Power transistor is suitable for large current switching at low to moderate (a few kHZ) frequency. Version 2 EE IIT, Kharagpur 34
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Switching aid circuits (snubbers) are used for enhancing the capacity utilization of a power transistor. They also reduce switching loss internal to the device. Ordinary LRCD snubber circuits may not reduce total switching loss. For that purpose lossless (regenerative) snubber circuits are used. Proper design of the base drive circuit helps to reduce both conduction and switching losses. For optimal operation, base drive voltage should be bipolar and have different output resistance for Turn ON and Turn OFF operations. Power transistors have relatively small current gain () and hence require large base drive current. Monolithic Power Darlingtons can solve the problem of low current gain. But they have larger ON state voltage drop and longer switching times.
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VCC = 200V
RL = 20
RB + VBB = 12V 1. In the transistor switching circuit VBE sat = 0.75 V, VCE sat = 0.2 V 10 40 . Find out the value of RB and Power requirement of the base source.
B
VCC = 200V
RL = 20 D3 RB + D1 VBB = 12V 2. In the transistor switching circuit shown VBE sat = 0.75 v, VD1 = VD2 = VD3 = 0.7 v, 10 40 Find maximum allowable value of RB and power output of the base source. Also compare conduction power loss with the circuit shown in Problem 1.
B
D2
3. The transistor of Problem 1 has the following switching time specifications. td = 1s, tri = tfv = 2.5 s, ts = 5 s, tfi = trv = 2.5 s. The transistor is switched at a frequency of 10 KHZ with duty ratio d = 0.5. Find out, (i) conduction power loss, (ii) switching power loss. Version 2 EE IIT, Kharagpur 37
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VBB
50s
50s
iC
10 A
ts
tfi
200v
PSW (on)
t 4. Figure shows practical implementation of a power transistor base drive circuit. The comparator has an output voltage swing of 12 V. Also For QP
VBE
sat
= 0.7V, VCE
sat
= 0.2V,
For QN
VBE
For Q
sat
=  0.7 V, VCE
sat
=  0.2 V,
VBE
sat
= 0.75 V.
Min
5. Explain why the dc current gain of a Power BJT is considerably lower compared to its Signal level counterpart. What adverse effect does it have on the switching performance of a BJT? Suggest one solution to this problem. Version 2 EE IIT, Kharagpur 38
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6. Differentiate between the voltage ratings VSUS, VCEO & VCBO of a Power BJT. How can these three voltage ratings of a BJT be utilized in an inductive switching circuit. 7. The pulsed FBSOA of a Power BJT is usually specified for a very low duty cycle. Then now does it help to extend the usable voltage and current rating of a BJT?
VCE
200  VCE sat 10 Amps 20 sat = 0.2V, which indicates that the transistor is in hard saturation. Therefore = min = 10.
= 1 amps 10 R B = VBB  VBE sat = 11.25 ic
VBE
sat
= 0.75 volts
Power drawn from base source is 12 1 = 12 watts. 2. In this case VCE = VBE
sat
since VCB is positive. So = max = 40 200 1.45 IL = ic = = 9.93 Amps. 20 i i B = c = 0.25 Amps. For maximum value of RB current through D3 will be zero V V V V So R B = BB D1 D2 BE sat = 39.4 iB Power Drawn from base source is 12 0.25 = 3 watts. Conduction power lass in 1st problem was 10 0.2 = 2 watts Conduction power lass in this case is 9.93 1.45 = 14.4 watts
B
Note: This circuit is known as the antisaturation clamp or the Bakers clamp.
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VCC
IL = 50 A iB1 10 K comp 0 Rl A iE2 QN iC2 RBN  12v  15v 3. Figure shows switching waveforms of the transistor. Major difference with clamped inductive switching waveform is that in this case rise and fall of ic & VCE are simultaneous. In the interval t ri ( or t fv ) iC1 QP iE1 iB B
QP E
iB2
ic
= 10
t = 4106 t t ri
In the interval
t fi ( or t rv )
5 i c = 10 1 t t = 10 (1  4 10 t ) fi VCE = 200 t = 80 10 6 t t rv
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E SW ( ON ) =
t ri
2.5106
= 0.83 mJ E SW ( OFF ) =
t fi o
VCE i c dt =
2.5106
= 0.83 mJ
I L ( TON  td  t ri + t s )
Min
= 10 , & ic = 50 A.
required positive i BP = 50
10
= 5 Amps
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So
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iCD
iL
iBD D
QD
iCM M QM
iED
i L = Di BD + Mi BD + M Di BD =
( M
equivalent (eqv) can be increased considerably due to multiplication of M & D. Power Darlington has one problem, however. The main transistor (QM) does not go into hard saturation due to VCE drop of QD. Therefore, the conduction loss is higher. 6. The voltage rating VSUS is the maximum allowable voltage across C & E when the transistor is in active region with iB > 0 and collector current above a minimum value. With both iB and iC greater than zero, there is considerable supply of minority carriers which are accelerated by the large CB junction electric field to start avalanche breakdown at a relatively lower voltage. Therefore, the voltage rating VSUS is the lowest of the three.
B B
The rating VCEO is the maximum allowable voltage between C & E terminals when the transistor is in cut off region with iB = 0 or iC is less than a specified value. Under this condition the supply of minority carriers at the CB junction is much less compared to the previous case. Therefore, avalanche breakdown of the CB junction occurs at a higher voltage. Thus VCEO > VSUS.
B
The rating VCBO is the maximum allowable voltage between C & E terminals when the transistor is in cut off with iB < 0 and iC less than a specified value. With iB = 0 the EB junction is still forward biased and there is small injection of minority carriers from the emitter to the CB junction. However, with iB < 0 base emitter junction is reverse biased and there is no supply of minority carriers to the CB junction from the emitter. Thus avalanche
B B B
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break down of this junction occurs at a relatively higher voltage making the rating VCBO largest of the three. Therefore, in general for a power transistor.
However, if a snubber circuit is not used the applicable voltage limit will always be VSUS since in this case VCE does not fall till iC rises to its full value during turn ON. Similarly during turn off iC does not fall till VCE rises to steady state blocking voltage level. log iC
ICM CP CD DC BD
BP
Pulsed
AD AP
log vCE
7. The main difference between the DC and pulsed FBOSA is in the boundary corresponding to maximum power dissipation and second break down. With only DC FBSOA the switching trajectory has to be restricted to something similar to AD BD CD. However, with pulsed FBSOA applicable limits of power dissipation and second break down increases considerably. Both these limits require simultaneous existence of nonzero VCE & iC which for a power transistor occurs only during switching. Therefore, the increases FBSOA can be utilized and the switching trajectory improved to AP BP CP provided total switching time is less than the pulse period for which the increased FBSOA is applicable.
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In addition pulsed FBSOA s are usually specified for a very low duty ratio. This condition can be easily satisfied provided total turn on and turn off times of the transistor expressed as a percentage of total ON and OFF periods of the transistor is less than this duty ratio since during ON or OFF period the transistor remain well within DC FBSOA. In practice this condition is satisfied by specifying a minimum ON and OFF period of the transistor.
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Module 1
Power Semiconductor Devices
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Lesson 4
Thyristors and Triacs
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Instructional objects
On completion the student will be able to Explain the operating principle of a thyristor in terms of the two transistor analogy. Draw and explain the iv characteristics of a thyristor. Draw and explain the gate characteristics of a thyristor. Interpret data sheet rating of a thyristor. Draw and explain the switching characteristics of a thyristor. Explain the operating principle of a Triac.
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4.1 Introduction
Although the large semiconductor diode was a predecessor to thyristors, the modern power electronics area truly began with advent of thyristors. One of the first developments was the publication of the PNPN transistor switch concept in 1956 by J.L. Moll and others at Bell Laboratories, probably for use in Bells Signal application. However, engineers at General Electric quickly recognized its significance to power conversion and control and within nine months announced the first commercial Silicon Controlled Rectifier in 1957. This had a continuous current carrying capacity of 25A and a blocking voltage of 300V. Thyristors (also known as the Silicon Controlled Rectifiers or SCRs) have come a long way from this modest beginning and now high power light triggered thyristors with blocking voltage in excess of 6kv and continuous current rating in excess of 4kA are available. They have reigned supreme for two entire decades in the history of power electronics. Along the way a large number of other devices with broad similarity with the basic thyristor (invented originally as a phase control type device) have been developed. They include, inverter grade fast thyristor, Silicon Controlled Switch (SCS), light activated SCR (LASCR), Asymmetrical Thyristor (ASCR) Reverse Conducting Thyristor (RCT), Diac, Triac and the Gate turn off thyristor (GTO). From the construction and operational point of view a thyristor is a four layer, three terminal, minority carrier semicontrolled device. It can be turned on by a current signal but can not be turned off without interrupting the main current. It can block voltage in both directions but can conduct current only in one direction. During conduction it offers very low forward voltage drop due to an internal latchup mechanism. Thyristors have longer switching times (measured in tens of s) compared to a BJT. This, coupled with the fact that a thyristor can not be turned off using a control input, have all but eliminated thyristors in high frequency switching applications involving a DC input (i.e, choppers, inverters). However in power frequency ac applications where the current naturally goes through zero, thyristor remain popular due to its low conduction loss its reverse voltage blocking capability and very low control power requirement. In fact, in very high power (in excess of 50 MW) AC DC (phase controlled converters) or AC AC (cycloconverters) converters, thyristors still remain the device of choice.
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A A
p n
G K (a) G
n+
p
n+
K (b)
(c)
Fig. 4.1: Constructional features of a thysistor (a) Circuit Symbol, (b) Schematic Construction, (c) Photograph As shown in Fig 4.1 (b) the primary crystal is of lightly doped n type on either side of which two p type layers with doping levels higher by two orders of magnitude are grown. As in the case of power diodes and transistors depletion layer spreads mainly into the lightly doped nregion. The thickness of this layer is therefore determined by the required blocking voltage of the device. However, due to conductivity modulation by carriers from the heavily doped p regions on both side during ON condition the ON state voltage drop is less. The outer n+ layers are formed with doping levels higher then both the p type layers. The top p layer acls as the Anode terminal while the bottom n+ layers acts as the Cathode. The Gate terminal connections are made to the bottom p layer. As it will be shown later, that for better switching performance it is required to maximize the peripheral contact area of the gate and the cathode regions. Therefore, the cathode regions are finely distributed between gate contacts of the p type layer. An Involute structure for both the gate and the cathode regions is a preferred design structure.
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A p n

A p n J2
n+

A IA Q1 (1) iC2 np
n+
J1
iC1 IG G
p
n+
J3
(2) Q2 J2 J3 IK K
G K (a) (b)
K (c)
Fig. 4.2: Two transistor analogy of a thyristor construction. (a) Schematic Construction, (b) Schematic division in component transistor (c) Equivalent circuit in terms of two transistors. a) Schematic construction, b) Schematic division in component transistor c) Equivalent circuit in terms of two transistors. Let us consider the behavior of this p n p n device with forward voltage applied, i.e anode positive with respect to the cathode and the gate terminal open. With this voltage polarity J1 & J3 are forward biased while J2 reverse biased. Under this condition.
( 4.1) ( 4.2 )
Where 1 & 2 are current gains of Q1 & Q2 respectively while Ico1 & Ico2 are reverse saturation currents of the CB junctions of Q1 & Q2 respectively. Now from Fig 4.2 (c). i c1 + i c2 = I A
( 4.3) ( 4.4 ) ( I G = 0 )
( 4.5 )
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I co1 + I co2 I co = 1 ( 1 + 2 ) 1 ( 1 + 2 )
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Where I co I co1 + I co2 is the total reverse leakage current of J2 Now as long as VAK is small Ico is very low and both 1 & 2 are much lower than unity. Therefore, total anode current IA is only slightly greater than Ico. However, as VAK is increased up to the avalanche break down voltage of J2, Ico starts increasing rapidly due to avalanche multiplication process. As Ico increases both 1 & 2 increase and 1 + 2 approaches unity. Under this condition large anode current starts flowing, restricted only by the external load resistance. However, voltage drop in the external resistance causes a collapse of voltage across the thyristor. The CB junctions of both Q1 & Q2 become forward biased and the total voltage drop across the device settles down to approximately equivalent to a diode drop. The thyristor is said to be in ON state. Just after turn ON if Ia is larger than a specified current called the Latching Current IL, 1 and 2 remain high enough to keep the thyristor in ON state. The only way the thyristor can be turned OFF is by bringing IA below a specified current called the holding current (IH) where upon 1 & 2 starts reducing. The thyristor can regain forward blocking capacity once excess stored charge at J2 is removed by application of a reverse voltage across A & K (ie, K positive with respect A). It is possible to turn ON a thyristor by application of a positive gate current (flowing from gate to cathode) without increasing the forward voltage across the device up to the forward breakover level. With a positive gate current equation 4.4 can be written as
IK = IA + IG
( 4.6 )
2 I G + I co 1 ( 1 + 2 )
( 4.7 )
Obviously with sufficiently large IG the thyristor can be turned on for any value of Ico (and hence VAK). This is called gate assisted turn on of a Thyristor. This is the usual method by which a thyristor is turned ON. When a reverse voltage is applied across a thyristor (i.e, cathode positive with respect to anose.) junctions J1 and J3 are reverse biased while J2 is forward biased. Of these, the junction J3 has a very low reverse break down voltage since both the n+ and p regions on either side of this junction are heavily doped. Therefore, the applied reverse voltage is almost entirely supported by junction J1. The maximum value of the reverse voltage is restricted by a) The maximum field strength at junction J1 (avalanche break down) b) Punch through of the lightly doped n layer. Since the p layers on either side of the n region have almost equal doping levels the avalanche break down voltage of J1 & J2 are almost same. Therefore, the forward and the reverse break down voltage of a thyristor are almost equal.Up to the break down voltage of J1 the reverse current of the thyristor remains practically constant and increases sharply after this voltage. Thus, the reverse characteristics of a thyristor is similar to that of a single diode. Version 2 EE IIT, Kharagpur 7 www.jntuworld.com
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If a positive gate current is applied during reverse bias condition, the junction J3 becomes forward biased. In fact, the transistors Q1 & Q2 now work in the reverse direction with the roles of their respective emitters and collectors interchanged. However, the reverse 1 & 2 being significantly smaller than their forward counterparts latching of the thyristor does not occur. However, reverse leakage current of the thyristor increases considerably increasing the OFF state power loss of the device. If a forward voltage is suddenly applied across a reverse biased thyristor, there will be considerable redistribution of charges across all three junctions. The resulting current can become large enough to satisfy the condition 1 + 2 = 1 and consequently turn on the thyristor. This is called dv turn on of a thyristor and should be avoided. dt Exercise 4.1 1) Fill in the blank(s) with the appropriate word(s) i. A thyristor is a ________________ carrier semi controlled device. ii. A thyristor can conduct current in ________________ direction and block voltage in ________________ direction. iii. A thyristor can be turned ON by applying a forward voltage greater than forward ________________ voltage or by injecting a positive ________________ current pulse under forward bias condition. iv. To turn OFF a thyristor the anode current must be brought below ________________ current and a reverse voltage must be applied for a time larger than ________________ time of the device. v. A thyristor may turn ON due to large forward ________________. Answers: (i) minority; (ii) one, both; (iii) break over, gate; (iv) holding, turn off; (v) dv dt 2. Do you expect a thyristor to turn ON if a positive gate pulse is applied under reverse bias condition (i. e cathode positive with respect to anode)? Answer: The two transistor analogy of thyristor shown in Fig 4.2 (c) indicates that when a reverse voltage is applied across the device the roles of the emitters and collectors of the constituent transistors will reverse. With a positive gate pulse applied it may appear that the device should turn ON as in the forward direction. However, the constituent transistors have very low current gain in the reverse direction. Therefore no reasonable value of the gate current will satisfy the turn ON condition (i.e.1 + 2 = 1). Hence the device will not turn ON.
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4.4 Steady State Characteristics of a Thyristor 4.4.1 Static output iv characteristics of a thyristor
IA VBRF
VAK
IA ig
VBRR Is IH
VAK VH ig4 > ig3 > ig2 > ig1 > ig = 0 ig4 > ig3 > ig2 > ig1 > ig = 0
Fig. 4.3: Static output characteristics of a Thyristor The circuit symbol in the left hand side inset defines the polarity conventions of the variables used in this figure. With ig = 0, VAK has to increase up to forward break over voltage VBRF before significant anode current starts flowing. However, at VBRF forward break over takes place and the voltage across the thyristor drops to VH (holding voltage). Beyond this point voltage across the thyristor (VAK) remains almost constant at VH (11.5v) while the anode current is determined by the external load. The magnitude of gate current has a very strong effect on the value of the break over voltage as shown in the figure. The right hand side figure in the inset shows a typical plot of the forward break over voltage (VBRF) as a function of the gate current (Ig) After Turn ON the thyristor is no more affected by the gate current. Hence, any current pulse (of required magnitude) which is longer than the minimum needed for Turn ON is sufficient to effect control. The minimum gate pulse width is decided by the external circuit and should be long enough to allow the anode current to rise above the latching current (IL) level.
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The left hand side of Fig 4.3 shows the reverse iv characteristics of the thyristor. Once the thyristor is ON the only way to turn it OFF is by bringing the thyristor current below holding current (IH). The gate terminal has no control over the turn OFF process. In ac circuits with resistive load this happens automatically during negative zero crossing of the supply voltage. This is called natural commutation or line commutation. However, in dc circuits some arrangement has to be made to ensure this condition. This process is called forced commutation. During reverse blocking if ig = 0 then only reverse saturation current (Is) flows until the reverse voltage reaches reverse break down voltage (VBRR). At this point current starts rising sharply. Large reverse voltage and current generates excessive heat and destroys the device. If ig > 0 during reverse bias condition the reverse saturation current rises as explained in the previous section. This can be avoided by removing the gate current while the thyristor is reverse biased. The static output iv characteristics of a thyristor depends strongly on the junction temperature as shown in Fig 4.4. VBRF IA
VAK
Tj = 125 75 25
135 150
Fig. 4.4: Effect of junction temperature (Tj) on the output i v characteristics of a thyristor.
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Vg E
Vg max c d Rg ig Vg Pgm e
S2
Load line Vg min Vng g Ig min b h
E Pgav Max
S1 f Ig max Ig
Fig. 4.5: Gate characteristics of a thyristor. Each thyristor has maximum gate voltage limit (Vgmax), gate current limit (Igmax) and maximum average gate power dissipation limit ( Pgav Max ) . These limits should not be exceeded in order to avoid permanent damage to the gate cathode junction. There are also minimum limits of Vg (Vgmin) and Ig (Igmin) for reliable turn on of the thyristor. A gate non triggering voltage (Vng) is also specified by the manufacturers of thyristors. All spurious noise signals should be less than this voltage Vng in order to prevent unwanted turn on of the thyristor. The useful gate drive area of a thyristor is then b c d e f g h. Referring to the gate drive circuit in the inset the equation of the load line is given by Vg = E  Rgig A typical load line is shown in Fig 4.5 by the line S1 S2. The actual operating point will be some where between S1 & S2 depending on the particular device. For optimum utilization of the gate ratings the load line should be shifted forwards the Pgav curve without violating Vg
Max Max
optimum load line from which optimum values of E & Rg can be determined. It is however customary to trigger a thyristor using pulsed voltage & current. Maximum power dissipation curves for pulsed operation (Pgm) allows higher gate current to flow which in turn reduces the turn on time of the thyristor. The value of Pgm depends on the pulse width (TON) of the gate current pulse. TON should be larger than the turn on time of the thyristor. For TON larger Version 2 EE IIT, Kharagpur 11 www.jntuworld.com
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than 100 s, average power dissipation curve should be used. For TON less than 100 s the following relationship should be maintained.
Pgm Pgav
Max
( 4.9 )
Rg G E K E K
(a)
(b)
Fig. 4.6: Gate Cathode reverse voltage protection circuit. Exercise 4.2 1) i. ii. iii. iv. v. Fill in the blank(s) with the appropriate word(s) Forward break over voltage of a thyristor decreases with increase in the ________________ current. Reverse ________________ voltage of a thyristor is ________________ of the gate current. Reverse saturation current of a thyristor ________________ with gate current. In the pulsed gate current triggering of a thyristor the gate current pulse width should be larger than the ________________ time of the device. To prevent unwanted turn ON of a thyristor all spurious noise signals between the gate and the cathode must be less than the gate ________________ voltage.
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Answer: (i) gate; (ii) break down, independent; (iii) increases; (iv) Turn ON; (v) nontrigger. 2) A thyristor has a maximum average gate power dissipation limit of 0.2 watts. It is triggered with pulsed gate current at a pulse frequency of 10 KHZ and duly ratio of 0.4. Assuming the gate cathode voltage drop to be 1 volt. Find out the allowable peak gate current magnitude. Answer: On period of the gate current pulse is
TON = TS =
fs
Therefore, pulsed gate power dissipation limit Pgm can be used. From Equation 4.9
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Peak working reverse voltage (VDWM): It is the maximum reverse voltage (i.e, anode negative with respect to cathode) that a thyristor can with stand continuously. Normally, it is equal to the peak negative value of the ac supply voltage. Peak repetitive reverse voltage (VRRM): It specifies the peak reverse transient voltage that may occur repeatedly during reverse bias condition of the thyristor at the maximum junction temperature. Peak nonrepetitive reverse voltage (VRSM): It represents the peak value of the reverse transient voltage that does not repeat. Its value is about 130% of VRRM. However, VRSM is less than reverse break down voltage VBRR.
Fig 4.7 shows different thyristor voltage ratings on a comparative scale. IA VBRR VRSM VRRM VRWM
VBRF
VAK
Maximum average current (Iav): It is the maximum allowable average value of the forward current such that i. ii. Peak junction temperature is not exceeded RMS current limit is not exceeded
Manufacturers usually provide the forward average current derating characteristics which shows Iav as a function of the case temperature (Tc ) with the current conduction angle as a parameter. The current wave form is assumed to be formed from a half cycle sine wave of power frequency as shown in Fig 4.8. Version 2 EE IIT, Kharagpur 14
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Iav Amps
= 180
120 100 80 60 40 20 0
= 120 = 60 = 30
60
80 TC (C)
100
120
140
Fig. 4.8: Average forward current derating characteristics Maximum Surge current (ISM): It specifies the maximum allowable non repetitive current the device can withstand. The device is assumed to be operating under rated blocking voltage, forward current and junction temperation before the surge current occurs. Following the surge the device should be disconnected from the circuit and allowed to cool down. Surge currents are assumed to be sine waves of power frequency with a minimum duration of cycles. Manufacturers provide at least three different surge current ratings for different durations.
For example
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Average power dissipation Pav): Specified as a function of the average forward current (Iav) for different conduction angles as shown in the figure 4.9. The current wave form is assumed to be half cycle sine wave (or square wave) for power frequency.
Pav 60 90
= 180
30
iF t
Iav
Fig. 4.9: Average power dissipation vs average forward current in a thyristor.
( 4.10 ) ( 4.11)
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Average Gate Power dissipation (PGAR): Average power dissipated in the gatecathode junction should not exceed this value for gate current pulses wider than 100 s. Peak forward gate current (IGRM): The forward gate current should not exceed this limit even on instantaneous basis. Exercise 4.3
1)
Fill in the blank(s) with the appropriate word(s) i. Peak nonrepetitive over voltage may appear across a thyristor due to ________________ or ________________ surges in a supply network.
ii. VRSM rating of a thyristor is greater than the ________________ rating but less than the ________________ rating. iii. Maximum average current a thristor can carry depends on the ________________ of the thyristor and the ________________ of the current wave form. iv. The ISM rating of a thyristor applies to current waveforms of duration ________________ than half cycle of the power frequency where as the i2dt rating applies to current durations ________________ than half cycle of the power frequency. v. The gate nontrigger voltage specification of a thyristor is useful for avoiding unwanted turn on of the thyristor due to ________________ voltage signals at the gate. Answer: (i) switching, lightning; (ii) VRRM, VBRR; (iii) case temperature, conduction angle; (iv) greater, less; (v) noise 2. A thyristor has a maximum average current rating 1200 Amps for a conduction angle of 180. Find the corresponding rating for = 60. Assume the current waveforms to be half cycle sine wave.
Answer: The form factor of half cycle sine waves for a conduction angle is given by
I F.F = RMS = Iav 1 2 1 2
Sin d Sin d
2 o o
 1 Sin 2 2 1 Cos
= 1885 Amps.
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1200 3 3 4
= 679.00 Amps.
ig Vi R
Firing angle Vi iA
Expanded scale
Fig 4.10 shows the waveforms of the gate current (ig), anode current (iA) and anode cathode voltage (VAK) in an expanded time scale during Turn on. The reference circuit and the associated waveforms are shown in the inset. The total switching period being much smaller compared to the cycle time, iA and VAK before and after switching will appear flat. As shown in Fig 4.10 there is a transition time tON from forward off state to forward on state. This transition time is called the thyristor turn of time and can be divided into three separate intervals namely, (i) delay time (td) (ii) rise time (tr) and (iii) spread time (tp). These times are shown in Fig 4.10 for a resistive load.
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Delay time (td): After switching on the gate current the thyristor will start to conduct over the portion of the cathode which is closest to the gate. This conducting area starts spreading at a finite speed until the entire cathode region becomes conductive. Time taken by this process constitute the turn on delay time of a thyristor. It is measured from the instant of application of the gate current to the instant when the anode current rises to 10% of its final value (or VAK falls to 90% of its initial value). Typical value of td is a few micro seconds. Rise time (tr): For a resistive load, rise time is the time taken by the anode current to rise from 10% of its final value to 90% of its final value. At the same time the voltage VAK falls from 90% of its initial value to 10% of its initial value. However, current rise and voltage fall characteristics are strongly influenced by the type of the load. For inductive load the voltage falls faster than the current. While for a capacitive load VAK falls rapidly in the beginning. However, as the current increases, rate of change of anode voltage substantially decreases.
If the anode current rises too fast it tends to remain confined in a small area. This can give rise to local hot spots and damage the device. Therefore, it is necessary to limit the rate of rise of the di ON state current A by using an inductor in series with the device. Usual values of maximum dt allowable di A is in the range of 20200 A/s. dt
Spread time (tp): It is the time taken by the anode current to rise from 90% of its final value to 100%. During this time conduction spreads over the entire cross section of the cathode of the thyristor. The spreading interval depends on the area of the cathode and on the gate structure of the thyristor.
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iA
di A dt
vAK
vi t vi
trr
tq
tgr
The anode current becomes zero at time t1 and starts growing in the negative direction with the same di A till time t2. This negative current removes excess carriers from junctions J1 & J3. At dt time t2 excess carriers densities at these junctions are not sufficient to maintain the reverse current and the anode current starts decreasing. The value of the anode current at time t2 is called the reverse recovery current (Irr). The reverse anode current reduces to the level of reverse saturation current by t3. Total charge removed from the junctions between t1 & t3 is called the reverse recovery charge (Qrr). Fast decaying reverse current during the interval t2 t3 coupled with the di limiting inductor may cause a large reverse voltage spike (Vrr) to appear across the dt device. This voltage must be limited below the VRRM rating of the device. Up to time t2 the voltage across the device (VAK) does not change substantially from its on state value. However, after the reverse recovery time, the thyristor regains reverse blocking capacity and VAK starts following supply voltage vi. At the end of the reverse recovery period (trr) trapped charges still exist at the junction J2 which prevents the device from blocking forward voltage just after trr. These trapped charges are removed only by the process of recombination. The time taken for this recombination process to complete (between t3 & t4) is called the gate recovery time (tgr). The time interval tq = trr + tgr is called device turn off time of the thyristor. No forward voltage should appear across the device before the time tq to avoid its inadvertent turn on. A circuit designer must provide a time interval tc (tc > tq) during which a reverse voltage is applied across the device. tc is called the circuit turn off time. Version 2 EE IIT, Kharagpur 20
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The reverse recovery charge Qrr is a function of the peak forward current before turn off and its di for rate of decrease A . Manufacturers usually provide plots of Qrr as a function of di A dt dt different values of peak forward current. They also provide the value of the reverse recovery current Irr for a given IA and di A . Alternatively Irr can be evaluated from the given Qrr dt characteristics following similar relationships as in the case of a diode. As in the case of a diode the relative magnitudes of the time intervals t1 t2 and t2 t3 depends on the construction of the thyristor. In normal recovery converter grade thyristor they are almost equal for a specified forward current and reverse recovery current. However, in a fast recovery inverter grade thyristor the interval t2 t3 is negligible compared to the interval t1 t2. This helps reduce the total turn off time tq of the thyristor (and hence allow them to operate at higher switching frequency). However, large voltage spike due to this snappy recovery will appear across the device after the device turns off. Typical turn off times of converter and inverter grade thyristors are in the range of 50100 s and 550 s respectively. As has been mentioned in the introduction thyristor is the device of choice at the very highest power levels. At these power levels (several hundreds of megawatts) reliability of the thyristor power converter is of prime importance. Therefore, suitable protection arrangement must be made against possible overvoltage, overcurrent and unintended turn on for each thyristor. At the highest power level (HVDC transmission system) thyristor converters operate from network voltage levels in excess of several hundreds of kilo volts and conduct several tens of kilo amps of current. They usually employ a large number of thyristors connected in series parallel combination. For maximum utilization of the device capacity it is important that each device in this series parallel combination share the blocking voltage and on state current equally. Special equalizing circuits are used for this purpose.
Exercise 4.4
Fill in the blank(s) with the appropriate word(s) A thyristor is turned on by applying a ________________ gate current pulse when it is ________________ biased. Total turn on time of a thyristor can be divided into ________________ time ________________ time and ________________ time. During rise time the rate of rise of anode current should be limited to avoid creating local ________________. A thyristor can be turned off by bringing its anode current below ________________ current and applying a reverse voltage across the device for duration larger than the ________________ time of the device.
v.
Reverse recovery charge of a thyristor depends on the ________________ of the forward current just before turn off and its ________________. Version 2 EE IIT, Kharagpur 21
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vi.
Inverter grade thyristors have ________________ turn off time compared to a converter grade thyristor.
Answer: (i) positive, forward; (ii) delay, rise, spread; (iii) hot spots (iv) holding, turn off; (v) magnitude, rate of decrease (vi) faster 2. With reference to Fig 4.10 find expressions for (i) turn on power loss and (ii) conduction power loss of the thyristor as a function of the firing angle . Neglect turn on delay time and spread time and assume linear variation of voltage and current during turn on period. Also assume constant on state voltage VH across the thyristor. Answer: (i) For a firing angle the forward bias voltage across the thyristor just before turn on is VON = 2Vi Sin ; Vi = RMS value of supply voltage. Current after the thyristor turns on for a resistive load is
I ON = VON R = 2 Vi R Sin
Neglecting delay and spread time and assuming linear variation of voltage and current during turn on
Vak = 2 Vi Sin 1  t t . where VH has been neglected. ON
t ON
v ak i a dt =
EON occurs once every cycle. If the supply frequency is f then average turn on power loss is given by.
PON = E ON f = Vi 2 Sin 2 t ON f 3R
(ii) If the firing angle is the thyristor conducts for  angle. Instantaneous current through the device during this period is 2 Vi Sin t ia = R <t R Where tON & VH have been neglected for simplicity. total conduction energy loss over one cycle is
Version 2 EE IIT, Kharagpur 22
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E C = Vak i a dt =
1 V H
2 Vi Sin d = R
2 Vi VH (1 + Cos ) R
2 Vi VH (1 + Cos ) 2R
Fuse i1 Vi if 220 V 50 HZ
3. In the ideal single phase fully controlled converter T1 & T2 are fired at a firing angle after the positive going zero crossing of Vi while T3 & T4 are fired angle after the negative going zero crossing of Vi, If all thyristors have a turn off time of 100 s, find out maximum allowable value of . Answer: As T1 & T2 are fired at an angle after positive going zero crossing of Vi, T3 & T4 are subjected to a negative voltage of Vi. Since this voltage remain negative for a duration () angle (after which Vi becomes positive) for safe commutation 0 (  Max) t off Max = 178.2 .
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N3 and P2 regions by metallic contact. Similarly MT1 is connected to N2 and P2 regions while MT2 is connected to N4 and P1 regions. MT1 MT2
N3 N2 N2
P2
P2 N1 P1
N3 G MT1
(a)
P2 N1
N4
P1
MT2
(b)
Fig. 4.12: Circuit symbol and schematic construction of a Triac (a) Circuit symbol (b) Schematic construction.
Since a Triac is a bidirectional device and can have its terminals at various combinations of positive and negative voltages, there are four possible electrode potential combinations as given below 1. MT2 positive with respect to MT1, G positive with respect to MT1 2. MT2 positive with respect to MT1, G negative with respect to MT1 3. MT2 negative with respect to MT1, G negative with respect to MT1 4. MT2 negative with respect to MT1, G positive with respect to MT1 The triggering sensitivity is highest with the combinations 1 and 3 and are generally used. However, for bidirectional control and uniforms gate trigger mode sometimes trigger modes 2 and 3 are used. Trigger mode 4 is usually averded. Fig 4.13 (a) and (b) explain the conduction mechanism of a triac in trigger modes 1 & 3 respectively.
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IG
IG P2 N1
P1
N4
MT2 (+)
MT2 ()
(a)
(b)
Fig. 4.13: Conduction mechanism of a triac in trigger modes 1 and 3 (a) Mode 1 , (b) Mode 3 .
In trigger mode1 the gate current flows mainly through the P2 N2 junction like an ordinary thyristor. When the gate current has injected sufficient charge into P2 layer the triac starts conducting through the P1 N1 P2 N2 layers like an ordinary thyristor. In the trigger mode3 the gate current Ig forward biases the P2 P3 junction and a large number of electrons are introduced in the P2 region by N3. Finally the structure P2 N1 P1 N4 turns on completely.
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Ig3 > Ig2 > Ig1 > Ig = 0 VBO VBO Ig3 < Ig2 < Ig1 V
Ig = 0
From a functional point of view a triac is similar to two thyristors connected in anti parallel. Therefore, it is expected that the VI characteristics of Triac in the 1st and 3rd quadrant of the VI plane will be similar to the forward characteristics of a thyristors. As shown in Fig. 4.14, with no signal to the gate the triac will block both half cycle of the applied ac voltage provided its peak value is lower than the break over voltage (VBO) of the device. However, the turning on of the triac can be controlled by applying the gate trigger pulse at the desired instance. Mode1 triggering is used in the first quadrant where as Mode3 triggering is used in the third quadrant. As such, most of the thyristor characteristics apply to the triac (ie, latching and holding current). However, in a triac the two conducting paths (from MT1 to MT2 or from MT1 to MT1) interact with each other in the structure of the triac. Therefore, the voltage, current and frequency ratings of triacs are considerably lower than thyristors. At present triacs with voltage and current ratings of 1200V and 300A (rms) are available. Triacs also have a larger on state voltage drop compared to a thyristor. Manufacturers usually specify characteristics curves relating rms device current and maximum allowable case temperature as shown in Fig 4.15. Curves relating the device dissipation and RMS on state current are also provided for different conduction angles.
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A 200
Bidirectional ON state current (RMS)
20
40
60
80
100
120
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LOAD
R1 D1 R
R2 V1 C1
In this circuit as Vi increases voltage across C1 increases due to current flowing through load, R1, R2 and C1. The voltage drop across diac D1 increases until it reaches its break over point. As D1 conducts a large current pulse is injected into the gate of the triac. By varying R2 the firing can be controlled from zero to virtually 100%.
Exercise 4.5
1) i. ii. iii.
Fill in the blank(s) with the appropriate word(s) A Triac is a ________________ minority carrier device A Triac behaves like two ________________ connected thyristors. The gate sensitivity of a triac is maximum when the gate is ________________ with respect to MT1 while MT2 is positive with respect to MT1 or the gate is ________________ with respect to MT1 while MT2 is negative with respect to MT1
iv. v.
A Triac operates either in the ________________ or the ________________ quadrant of the iv characteristics. In the ________________ quadrant the triac is fired with ________________ gate current while in the ________________ quadrant the gate current should be ________________.
vi.
The maximum possible voltage and current rating of a Triac is considerably ________________ compared to thyristor due to ________________ of the two current carrying paths inside the structure of the triac.
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vii.
dt
viii.
For clean turn ON of a triac the ________________ of the gate current pulse should be as ________________ as possible.
Answer: (i) bidirectional; (ii) anti parallel; (iii) positive, negative; (iv) first, third; (v) first, positive, third, negative (vi) lower, interaction; (vii) RC shubbers; (viii) rise time, small.
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References
1. Dr. P.C. Sen, Power Electronics; Tata McGrow Hill Publishing Company Limited; New Delhi. 2. Dr. P.S. Bimbhra, Power Electronics Khanna Publishers
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Lesson Summary
Thyristor is a four layer, three terminal, minority carrier, semicontrolled device. The three terminals of a thyristor are called the anode, the cathode and the gate. A thyristor can be turned on by increasing the voltage of the anode with respect to the cathode beyond a specified voltage called the forward break over voltage. A thyristor can also be turned on by injecting a current pulse into the gate terminal when the anode voltage is positive with respect to the cathode. This is called gate triggering. A thyristor can block voltage of both polarity but conducts current only from anode to cathode. After a thyristor turns on the gate looses control. It can be turned off only by bringing the anode current below holding current. After turn on the voltage across the thyristor drops to a very low value (around 1 volt). In the reverse direction a thyristor blocks voltage up to reverse break down voltage. A thyristor has a very low conduction voltage drop but large switching times. For this reason thyristors are preferred for high power, low frequency line commutated application. A thyristor is turned off by bringing the anode current below holding current and simultaneously applying a negative voltage (cathode positive with respect to anode) for a minimum time called turn off time. A triac is functionally equivalent to two anti parallel connected thyristors. It can block voltages in both directions and conduct current in both directions. A triac has three terminals like a thyristor. It can be turned on in either half cycle by either a positive on a negative current pulse at the gate terminal. Triacs are extensively used at power frequency ac load (eg heater, light, motors) control applications.
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1. Explain the effect of increasing the magnitude of the gate current and junction temperature on (i) forward and reverse break down voltages, (ii) forward and reverse leakage currents. Th 15 V R
iB
N1 N2
2. The thyristor Th is triggered using the pulse transformer shown in figure. The pulse transformer operates at 10 KHZ with a duty cycle of 40%. The thyristor has maximum average gate power dissipation limit of 0.5 watts and a maximum allow able gate voltage limit of 10 volts. Assuming ideal pulse transformer, find out the turns ratio N1/N2 and the value of R. Fuse i1 Vi if 220 V 50 HZ
3. A thyristor full bridge converter is used to drive a dc motor as shown in the figure. The thyristors are fired at a firing angle = 0 when motor runs at rated speed. The motor has on armature resistance of 0.2 and negligible armature inductance. Find out the peak surge current rating of the thyristors such that they are not damaged due to sudden loss of field excitation to the motor. The protective fuse in series with the motor is designed to disconnect the motor within 1 cycle of fault. Find out the i 2 dt rating of the 2 thyristors. 4. Why is it necessary to maximize the peripheral contact area of the gate and the cathode regions? A thyristor used to control the voltage applied to a load resistance from a 220v, Version 2 EE IIT, Kharagpur 33
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di a
dt
limiting inductor to be connected in series with the load resistance. THM + C THA 20 A
200V 200V
5. In a voltage commutated dc dc thyristor chopper the main thyristor THM is commutated by connecting a precharged capacitor directly across it through the auxiliary thyristor THA as shown in the figure. The main thyristor THM has a turn off time off 50s and maximum dv rating of 500v/ s. Find out a suitable value of C for safe dt commutation of THM.
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1. i. Forward break down voltage reduces with increasing gate current. It increases with junction temperature up to certain value of the junction temperature and then falls rapidly with any further increase in temperature. Reverse break down voltage is independent of the gate current magnitude but decreases with increasing junction temperature. Forward leakage current is independent of the gate current magnitude but increases with junction temperature. Reverse leakage current increases with both the junction temperature and the magnitude of the gate current. THM + C THA 20 A
ii.
200V 200V
2. Figure shows the equivalent gate drive circuit of the thyristor. For this circuit one can write E = R i g + Vg OR Vg = E  R i g The diode D clamps the gate voltage to zero when E goes negative. Now for ig = O, Vg = E. Since Vg
Max
= 10 v
10 = 1.5
E = 10 v
But E =
N2
N1
15
N2
N1
= 15
Gate pulse width = 0.4 104 Sec = 40s. <100s. instantaneous gate power dissipation limit can be used.
0.2 Max = = 0.5 watts 0.4 For maximum utilization of the gate power dissipation limit the gate load line ie Vg = E igR = 10 igR should be tangent to the maximum power dissipation curve Vg ig = 0.5 Vg i g
Max
Pav
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Since Vg = 10 ig R is tangent to Vg ig = 0.5 at Vgo, igo. Slope of the tangent of Vgig = 0.5 at (Vgo, igo) = R
R = R = i go 2
dv g  vg v = =  go di g ( vgo,igo ) i g ( vgo,igo ) i go
R = 0.5
0.5 = 50 .01
Back emf. Va t ia (normal) t
ia (with field loss) t 3. Figure shows the armature voltage (firm line) and armature current of the motor under normal operating condition at rated speed. If there is a sudden loss of field excitation back emf will become zero and armature current will be limited solely by the armature resistance. 220 2 The peak magnitude of the fault current will be = 1556(Amps) . .2 It the thyristors have to survive this fault at least for 1 cycle (after which the fuse blows) IsM > 2 1556 Amps. cycle of the fault occurring. Therefore the thyristors must withstand 2 the fault for at least 1 cycle. 2 2 Therefore, the i t rating of the thyristor should be The fuse blows within 1
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2 i dt =
102
(1556 )
2
102
[1 
Cos 200 t ] dt
4. At the beginning of the turn on process the thyristor starts conducting through the area adjacent to the gate. This area spreads at a finite speed. However, if rate of increase of anode current is lager than the rate of increase of the current conduction are, the current density increases with time. This may lead to thyristor failure due to excessive local heating. However, if the contact area between the gate and the cathode is large a thyristor will be able to handle a di relatively large a without being damaged. dt The maximum
di a dt
L
Since
di a
di a = dt
2 220 Sin 90 0
dt
Max
= 50 10 6 A Sec
min
VC vTHM
toff
200 V
dv / dt
iC 20 Amps. t
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5. As soon as THA is turned on the load current transfer from THM to C. the voltage across THM is the negative of the capacitance voltage. Figure shows the waveforms of voltage across the capacitor (vc), voltage across the main thyristor (VTHM) and the capacitor current ic. From dv i = c figure c dt dv = 500 v s Now ic = 20 Amps & dt Max
Min
ic
dv dt
=
Max
20 8 F = 0.04 F 6 = 4 10 50010
The circuit turn off time is the time taken by the capacitor voltage to reach zero from an initial value of 200v. This time must be greater than the turn off time of the device. Now C
dv c = i c = 20 dt 20 t v c = c
200 =
20 50 10 6 C 20 50 10 6 C = = 5 F 200
For safe commutation of THM the higher value of C must the chosen the required value of C = 5 F.
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Module 1
Power Semiconductor Devices
Version 2 EE IIT, Kharagpur 1 www.jntuworld.com
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Lesson 5
Gate Turn Off Thyristor (GTO)
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Instructional objective
On completion the student will be able to Differentiate between the constructional features of a GTO and a Thyristor. Explain the turn off mechanism of a GTO. Differentiate between the steady state output and gate characteristics of a GTO and a thyristor. Draw and explain the switching characteristics of a GTO. Draw the block diagram of a GTO gate drive unit and explain the functions of different blocks. Interpret the manufacturers data sheet of a GTO.
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Introduction
The thyristor has reigned supreme for well over two decades in the power electronics industry and continues to do so at the very highest level of power. It, however, has always suffered from the disadvantage of being a semicontrolled device. Although it could be turned on by applying a gate pulse but to turn it off the main current had to be interrupted. This proved to be particularly inconvenient in DC to AC and DC to DC conversion circuits, where the main current does not naturally becomes zero. A bulky and expensive commutation circuit had to be used to ensure proper turning off of the thyristor. The switching speed of the device was also comparatively slow even with fast inverter grade thyristor. The development of the Gate Turn off thyristor (GTO) has addressed these disadvantages of a thyristor to a large extent. Although it has made a rather late entry (1973) into the thyristor family the technology has matured quickly to produce device comparable in rating (5000V, 4000Amp) with the largest available thyristor. Consequently it has replaced the forced commutated inverter grade thyristor in all DC to AC and DC to DC converter circuits. Like thyristor, the GTO is a current controlled minority carrier (i.e. bipolar) device. GTOs differ from conventional thyristor in that, they are designed to turn off when a negative current is sent through the gate, thereby causing a reversal of the gate current. A relatively high gate current is need to turn off the device with typical turn off gains in the range of 45. During conduction, on the other hand, the device behaves just like a thyristor with very low ON state voltage drop. Several different varieties of GTOs have been manufactured. Devices with reverse blocking capability equal to their forward voltage ratings are called symmetric GTOs. However, the most poplar variety of the GTO available in the market today has no appreciable reverse voltage (2025v) blocking capacity. These are called Asymmetric GTOs. Reverse conducting GTOs (RCGTO) constitute the third family of GTOs. Here, a GTO is integrated with an antiparallel freewheeling diode on to the same silicon wafer. This lesson will describe the construction, operating principle and characteristic of Asymmetric GTOs only.
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A Anode Short.
p+
n+
p+ n p
n+
p+
p+ n np
n+ n+
G K (a) G
n+
n+
G C (b) (c) C
Fig. 5.1: Circuit symbol and schematic cross section of a GTO (a) Circuit Symbol, (b) Anode shorted GTO structure, (c) Buffer layer GTO structure. Like a thyristor, a GTO is also a four layer three junction pnpn device. In order to obtain high emitter efficiency at the cathode end, the n+ cathode layer is highly doped. Consequently, the break down voltage of the function J3 is low (typically 2040V). The p type gate region has conflicting doping requirement. To maintain good emitter efficiency the doping level of this layer should be low, on the other hand, from the point of view of good turn off properties, resistively of this layer should be as low as possible requiring the doping level of this region to be high. Therefore, the doping level of this layer is highly graded. Additionally, in order to optimize current turn off capability, the gate cathode junction must be highly interdigitated. A 3000 Amp GTO may be composed of upto 3000 individual cathode segments which are a accessed via a common contact. The most popular design features multiple segments arranged in concentric rings around the device center. The maximum forward blocking voltage of the device is determined by the doping level and the thickness of the n type base region next. In order to block several kv of forward voltage the doping level of this layer is kept relatively low while its thickness is made considerably higher (a few hundred microns). Byond the maximum allowable forward voltage either the electric field at the main junction (J2) exceeds a critical value (avalanche break down) or the n base fully depletes, allowing its electric field to touch the anode emitter (punch through). The junction between the n base and p+ anode (J1) is called the anode junction. For good turn on properties the efficiency of this anode junction should be as high as possible requiring a heavily doped p+ anode region. However, turn off capability of such a GTO will be poor with very low maximum turn off current and high losses. There are two basic approaches to solve this problem. In the first method, heavily doped n+ layers are introduced into the p+ anode layer. They make contact with the same anode metallic contact. Therefore, electrons traveling through the base can directly reach the anode metal contact without causing hole injection from the p+ anode. This is the classic anode shorted GTO structure as shown in Fig 5.1 (b). Due to presence of these anode shorts the reverse voltage blocking capacity of GTO reduces to the reverse break down Version 2 EE IIT, Kharagpur 5 www.jntuworld.com
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voltage of junction J3 (2040 volts maximum). In addition a large number of anode shorts reduces the efficiency of the anode junction and degrades the turn on performance of the device. Therefore, the density of the anode shorts are to be chosen by a careful compromise between the turn on and turn off performance. In the other method, a moderately doped n type buffer layer is juxtaposed between the n type base and the anode. As in the case of a power diode and BJT this relatively high density buffer layer changes the shape of the electric field pattern in the n base region from triangular to trapezoidal and in the process, helps to reduce its width drastically. However, this buffer layer in a conventional anode shorted GTO structure would have increased the efficiency of the anode shorts. Therefore, in the new structure the anode shorts are altogether dispensed with and a thin p+ type layer is introduce as the anode. The design of this layer is such that electrons have a high probability of crossing this layer without stimulating hole injection. This is called the Transparent emitter structure and is shown in Fig 5.1 (c). Exercise 5.1 Fill in the blank(s) with the appropriate word(s) i. ii. iii. iv. v. A GTO is a _______________ controlled _______________ carrier device. A GTO has _______________ layers and _______________ terminals. A GTO can be turned on by injecting a _______________ gate current and turned off by injecting a _______________ gate current. The anode shorts of a GTO improves the _______________ performance but degrades the _______________ performance. The reverse voltage blocking capacity of a GTO is small due to the presence of _______________. Answer: (i) current, minority; (ii) four, three; (iii) positive, negative; (iv) turn off, turn on; (v) anode shorts.
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A p p iC1 IG iB2 G n p
A G n p n C (b) G p n p A
Fig 5.2: Current distribution in a GTO (a) During turn on; (b) During turn off. From the two transistor analogy (Fig 5.2 (a)) of the GTO structure one can write.
Combining I A =
n IG + ( iCBO1 + i CBO2 ) 1 ( n + p )
( 5.4 )
With applied forward voltage VAK less than the forward break over voltage both ICBO1 and ICBO2 are small. Further if IG is zero IA is only slightly higher than (ICBO1 + ICBO2). Under this condition both n and p are small and (p + n) <<1. The device is said to be in the forward blocking mode. To turn the device on either the anode voltage can be raised until ICBO1 and ICBO2 increases by avalanche multiplication process or by injecting a gate current. The current gain of silicon transistors rises rapidly as the emitter current increases. Therefore, any mechanism which causes a momentary increase in the emitter current can be used to turn on the device. Normally, this is done by injecting current into the p base region via the external gate contract. As n + p approaches unity the anode current tends to infinity. Physically as n + p nears unity the device starts to regenerate and each transistor drives its companion into saturation. Once in saturation, all junctions assume a forward bias and total potential drop across the device becomes approximately equal to that of a single pn diode. The anode current is restricted only by the external circuit. Once the device has been turned on in this manner, the external gate current is no longer required to maintain conduction, since the regeneration process is selfsustaining. Reversion to the blocking mode occurs only when the anode current is brought below the holding current level.
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To turn off a conducting GTO the gate terminal is biased negative with respect to the cathode. The holes injected from the anode are, therefore, extracted from the p base through the gate metallization into the gate terminal (Fig 5.2 (b)). The resultant voltage drop in the p base above the n emitter starts reverse biasing the junction J3 and electron injection stops here. The process originates at the periphery of the p base and the n emitter segments and the area still injecting electron shrinks. The anode current is crowded into higher and higher density filaments in most remote areas from the gate contact. This is the most critical phase in the GTO turn off process since highly localized high temperature regions can cause device failure unless these current filaments are quickly extinguished. When the last filament disappears, electron injection stops completely and depletion layer starts to grow on both J2 and J3. At this point the device once again starts blocking forward voltage. However, although the cathode current has ceased the anode to gate current continues to flow (Fig 5.2 (b)) as the n base excess carriers diffuse towards J1. This tail current then decays exponentially as the n base excess carriers reduce by recombination. Once the tail current has completely disappeared does the device regain its steady state blocking characteristics. Anode Shorts (or transparent emitter) helps reduce the tail current faster by providing an alternate path to the n base electrons to reach the anode contact without causing appreciable hole injection from anode. Exercise 5.2 Fill in the blank(s) with the appropriate word(s) i. ii. iii. iv. v. After a GTO turns on the gate current can be _______________. A conducting GTO reverts back to the blocking mode when the anode current falls below _______________ current. To turn off a conducting GTO the gate terminal is biased _______________ with respect to the _______________. Current filaments produced during the turn off process of a GTO can destroy the device by creating local _______________. Anode shorts help to reduce the _______________ current in a GTO.
Answer: (i) removed; (ii) holding; (iii) negatively, cathode; (iv) hot spot; (v) tail.
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5.4 Steady state and dynamic characteristics of a GTO 5.4.1Steady state output and gate characteristics
+ VAK IA IA IG IL VBRR VBRF + IL VAK vg (a) vg IG Min Max
(b)
Fig. 5.3: Steady state characteristics of a GTO (a) Output characteristics; (b) Gate characteristics. This characteristic in the first quadrant is very similar to that of a thyristor as shown in Fig. 5.3 (a). However, the latching current of a GTO is considerably higher than a thyristor of similar rating. The forward leakage current is also considerably higher. In fact, if the gate current is not sufficient to turn on a GTO it operates as a high voltage low gain transistor with considerable anode current. It should be noted that a GTO can block rated forward voltage only when the gate is negatively biased with respect to the cathode during forward blocking state. At least, a low value resistance must be connected across the gate cathode terminal. Increasing the value of this resistance reduces the forward blocking voltage of the GTO. Asymmetric GTOs have small (2030 V) reverse break down voltage. This may lead the device to operate in reverse avalanche under certain conditions. This condition is not dangerous for the GTO provided the avalanche time and current are small. The gate voltage during this period must remain negative. Fig 5.3 (b) shows the gate characteristics of a GTO. The zone between the min and max curves reflects parameter variation between individual GTOs. These characteristics are valid for DC and low frequency AC gate currents. They do not give correct voltage when the GTO is turned on dI with high dia and G . VG in this case is much higher. dt dt
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IL 0.9IL VT 0.1IL
VDM
Itail t
IGM
ts IG
tf
ttail
QgQ IgQ digQ dt Fig. 5.4: Switching characteristics of a GTO. Fig 5.4 shows the switching characteristics of a GTO and refers to the resistive dc load switching circuit shown on the right hand side. When the GTO is off the anode current is zero and VAK = Vd. To turn on the GTO, a positive gate current pulse is injected through the gate terminal. A substantial gate current ensure that all GTO cathode segments are turned on simultaneously and within a short time. There is a delay between the application of the gate pulse and the fall of anode voltage, called the turn on delay time td. After this time the anode voltage starts falling while the anode current starts rising towards its steady value IL. Within a further time interval tr they reach 10% of their initial value and 90% of their final value respectively. tr is called the are very current rise time (voltage fall time). Both td and maximum permissible on state di A dt much gate current dependent. High value of I gM and dig at turn on reduces these times and dt di . It should be noted that large value of ig (IgM) increases maximum permissible on state A dt and dig are required during td and tr only. After this time period both vg and ig settles down to dt their steady value. A minimum ON time period tON (min) is required for homogeneous anode current conduction in the GTO. This time is also necessary for the GTO to be able to turn off its rated anode current.
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To turn off a GTO the gate terminal is negatively biased with respect to the cathode. With the application of the negative bias the gate current starts growing in the negative direction. However, the anode voltage,current or the gate voltage does not change appreciably from their on state levels for a further time period called the storage time (ts). The storage time increases di with the turn off anode current and decrease with gQ . During storage time the load current at dt the cathode end is gradually diverted to the gate terminal. At the end of the storage time gate current reaches its negative maximum value IgQ. At this point both the junctions J2 & J3 of the GTO starts blocking voltage. Consequently, both the gate cathode and the anode cathode voltage starts rising towards their final value while the anode current starts decreasing towards zero. At the end of current fall time tf the anode current reaches 10% of its initial value after which both the anode current and the gate current continues to flow in the form of a current tail for a further duration of ttail. A GTO is normally used with a RC turn off snubber. Therefore, VAK does not start to rise appreciably till tf. At this point VAK starts rising rapidly and exceeds the dc voltage Vd (VdM) (due to resonance of snubber capacitor with di limiting inductor) before setting dt down at its steady value Vd . A GTO should not be retriggered within a minimum off period off (min) to avoid the risk of failure due to localized turn ON. GTOs have typically low turn off gain in the range of 45.
A typical gate drive arrangement for a large power GTO is show in Fig 5.5.
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H.F.DC to AC INV.
H.F TXF
H.F. AC to DC Rectifier
Output Stage
E Optical
C F Control Logic
(a) A R1 R2 C2
+ 
ON
T1 G
OFF (b)
T2 + R3 K
Fig. 5.5: Gate drive circuit of a GTO. (a) Block diagram, (b) Circuit diagram of the output stage In the block diagram of Fig 5.5 (a) it is assumed that there is a potential difference of several kVs between the master control and individual gate units. The ON and OFF pulses for a GTO is communicated to individual gate units through fiber optic cables. These optical signals are converted to electrical signals by a optical electrical converter. These electrical signals through the control logic then produces the ON and OFF signal for the out put stage which in turn sends positive and negative gate current to the GTO. Depending on the requirement the control logic may also supervise GTO conduction by monitoring the gatecathode voltage. Any fault is relayed back via fiber optic cable to the master control. Power supply for the Gate drive units are derived from a common power supply through a high frequency SMPS (Blocks A, B & C) arrangement. Fig 5.5 (b) shows the circuit implementation of the output stage. The top switch T1 sends positive gate pulse to the GTO gate. At the instant of turn on of T1 ,C2 acts almost as a short circuit and Version 2 EE IIT, Kharagpur 12 www.jntuworld.com
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the positive gate current is determined by the parallel combination of R1 and R2. However, at steady state only R1 determines the gate current IG. The bottom switch T2 is used for biasing the GTO gate negative with respect to the cathode. Since, relatively large negative gate current flows during turn off, no external resistance is used in series with T2. Instead, the ON state resistance of T2 is utilized for this purpose. In practice, a large number of switches are connected in parallel to obtain the required current rating of T2. A low value resistance R3 is connected between the gate and the cathode terminals of the GTO to ensure minimum forward blocking voltage. Exercise 5.3 Fill in the blank(s) with the appropriate word(s) i. ii. iii. iv. v. vi. vii. viii. ix. x. The _______________ current and forward _______________ current of a GTO are considerably higher compared to a thyristor. If the gate current is insufficient a GTO can operate as a low gain _______________. Reverse blocking voltage of _______________ GTO is small. To ensure that all GTO cathode segments are turned on simultaneously the magnitude of the _______________ current should be _______________. High value of gate current and dig/dt enhances the _______________ capability of a GTO during turn on. During storage time the load current in a GTO is diverted from the _______________ to the _______________ terminal. GTOs have low turn off _______________ gain. After the current fall time during turn off of a GTO the anode current continuous for some more time in the form of a _______________. The gate drive unit of a GTO should provide continuous positive gate _______________ during ON period and continuous negative gate _______________ during OFF period. In the gate drive unit of a GTO a low value resistance is connected between the gate and the cathode terminals to ensure minimum _______________ voltage. Answer: (i) latching, leakage; (ii) transistor; (iii) asymmetric; (iv) gate, high; (v) di/dt; (vi) cathode, gate; (vii) current; (viii) current tail; (ix) current, voltage; (x) forward blocking.
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(a)
(b)
Fig. 5.6: Reverse avalanche capability of a GTO (a) Voltage source inverter phase leg; (b) Voltage, current waveforms. In the voltage source inverter phase leg shown in Fig 5.6 (a), as the GTO G1 is turned off the current through it (IG1) starts reducing. The difference current (IL  IG1) is transferred to the snubber capacitance of G1 and the voltage across G1 (VG1) starts increasing. When if becomes equal to the dc link voltage VD , D2 is forward biased. However, due to the forward recovery voltage of D2 (Vfr) the reverse voltage across G2 may exceed VRRM rating of G2 and drive it into reverse avalanche. This condition is not dangerous for G2 provided the avalanche time and current are small (typically within 10 s and 1000 A respectively). However, the gate voltage must remain negative during this time.
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VDC: This is the maximum continuous DC voltage the device can withstand. Exceeding this voltage does not immediately lead to device failure, but the probability of a cosmic radiation failure increases progressively with the applied dc voltage. IFAVM and IFRMS: These are maximum average and RMS on state current respectively. They are specified at a given case temperature assuming half wave sinusoidal on state current at power frequency. IFSM: This is the maximum allowed peak value of a power frequency half sinusoidal nonrepetitive surge current. The pulse is assumed to be applied at an instant when the GTO is operating at its maximum junction temperature. The voltage across the device just after the surge should be zero.
i dt :
2
This is the limiting value of the surge current integral assuming half cycle sine wave
surge current. The junction temperature is assumed to be at the maximum value before the surge and the voltage across the device following the surge is assumed to be zero. The i2t rating of a semiconductor fuse must be less than this value in order to protect the GTO. Plots of both IFSM and i 2 dt as functions of surge pulse width are usually provided by the manufacturer. VF : This is the plot of the instantaneous forward voltage drop vs instantaneous forward current at different junction temperatures. Pav : For some frequently encountered current waveforms (e.g. sine wave, square wave) the plot of the average on state power dissipation as a function of the average on state current is provided by the manufacturers at a given junction temperature. IH: This is the holding current of the GTO. This current, in case of a GTO1 , is considerably higher compared to a similarly rated thyristor. Serious problem may arise due to anode current variation because the GTO may unlatch at an in appropriate moment. This problem can be avoided by feeding a continuous current into the gate (called the back porch current) during ON period of the device. This DC gate current should be about 20% higher than the gate trigger current (IGT) at the lowest expected junction temperature.
di crit : This is the maximum permissible value of the rate of change of forward current during dt turn on. This value is very much dependent on the peak gate current magnitude and the rate of increase of the gate current. A substantial gate current ensures that all GTO cathode segments are turned ON simultaneously and within a short time so that no local hot spot is created. di The g and IgM values specified in the operating conditions should, therefore, be considered as dt minimum values.
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voltage when the GTO is turned on from high anode voltage with high di/dt and
. Vg in this dt case is much higher. Generally the gate cathode impedance of a GTO is much lower than that of a conventional thyristor.
di g
Vgt, Igt: Igt is the gate trigger current and Vgt , the instantaneous gate cathode voltage when Igt is flowing into the gate. Igt has a strong junction temperature dependence and increases very rapidly with reduced junction temperature. Igt merely specifies the minimum back porch current necessary to turn on the GTO at a low di and maintain it in conduction. dt Vgrm: It is the maximum repetitive reverse gate voltage, exceeding which drives the gate cathode junction into avalanche breakdown. Igrm: Igqm:
It is the peak repetitive reverse gate current at Vgrm and Tj (max).
It is the maximum negative turn off gate current. The gate unit should be designed to di deliver this current under any condition. It is a function of turn off anode current, g during dt turn off and the junction temperature.
td, tr, :
EON : It is the energy dissipated during each turn on operation. Manufacturers specify them as functions of turn on anode current for different turn on di/dt and anode voltage EON reduces with increased IgM . IFgqm : It is the maximum anode current that can be repetitively turned off by a negative gate current. It can be increased by increasing the value of the turn off snubber capacitance which limits the dv/dt at turn off. A large negative dig/dt during turn off also helps to increase IFgqm. ts : The storage time ts is defined as the time between the start of negative gate current and the decrease in anode current. High value of the turn off anode current and junction temperature increases it while a large negative dig/dt during turn off decreases it. tf :
This is the anode current fall time. It can not be influenced much by gate control.
toff(min) : This is the minimum off time before the GTO may be triggered again by a positive gate current. If the device is retriggered during this time, localized turn on may destroy it.
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Eoff : This is the energy dissipated during each turn off operation of the GTO. Eoff increases with increase in the turn off anode current and junction temperature while it reduces with turn off snubber capacitance. Exercise 5.4
Fill in the blank(s) with the appropriate word(s) i. ii. iii. iv. v. vi. vii. viii. A GTO can block rated forward voltage only when the gate is _______________ biased with respect to the _______________. A GTO can operate in the reverse _______________ region for a short time. The holding current of a GTO is much _______________ compared to a thyristor. After a current surge the voltage across a GTO should be reduced to _______________. The gate cathode impedance of a GTO is much _______________ compared to a thyristor. The turn on di/dt capability of a GTO can be increased by in creasing the _______________ magnitude of the gate current and _______________ during turn on. The turn on delay time and current rise time of a GTO can be reduced by increasing the gate current _______________ and _______________ during turn ON. The maximum anode current that can be turned off repetitively can be increased by increasing the turn off snubber _______________ and negative _______________.
Answer: (i) negatively, cathode; (ii) avalanche; (iii) larger; (iv) zero; (v) smaller; (vi) peak, dig/dt; (vii) magnitude, dig/dt; (viii) capacitance, dig/dt.
Reference
1) GTO and GCT product guide, ABB semiconductors AG, 1997. 2) GTO Thyristors , Makoto Azuma and Mamora Kurata, Proceedings of the IEEE, Vol.76, No. 4, April 1988, pp 419427. 3) Power Electronics, P. S. Bimbhra, Khanna Publlishers, 1993.
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Lesson Summary
GTO is a four layer, three terminal current controlled minority carrier device. A GTO can be turned on by applying a positive gate current pulse when it is forward biased and turned off by applying a negative gate current. A GTO has a shorted anode and highly interdigitized gate cathode structure to improve the gate turn off performance. Due to the presence of anode shorts a GTO can block only a small reverse voltage. These are called asymmetric GTOs. The forward iv characteristics of a GTO is similar to that of a thyristor. However, they have relatively larger holding current and gate trigger current. The turn on di/dt capability of a GTO is significantly enhanced by using higher peak gate current and large rate of rise of the gate current. Due to relatively larger holding current of a GTO a continuous low value gate current (called the back porch current) should be injected through out the on period of the GTO. GTOs have relatively low turn off current gain. The GTO gate drive unit should be capable of injecting large positive and negative gate currents with large rate of rise for satisfactory switching of the device. A GTO can block rated forward voltage only when the gate cathode junction is reverse biased. A GTO can operate safely in the reverse avalanche region for a short time provided the gate cathode junction is reverse biased. The switching delay times and energy loss of a GTO can be reduced by increasing the gate current magnitude and its rate of rise. The maximum turn off anode current of a GTO can be increased by increasing the turn off snubber capacitance.
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1. What are the constructional features of a GTO that bestows it with a gate turn off capability? How do they affect the turn on performance of the GTO? 2. What are the main differences in the steady state output characteristics of a GTO and a thyristor? What effect do they have on the gate drive requirement of a GTO? 3. What are the desirable characteristics of the gate drive circuit of a GTO? How do they influence the switching performance of a GTO? 4. What is the significance of the specifications IFAVM and IFRMS in relation to a GTO? Is the specification IFgqm. Same as IFAVM / IFRMS? If not, then which current should one use in a particular application? 5. Which paramers of the gate current waveform reduces the turn on energy loss (EON) of a GTO? How does one reduce the turn off energy lass of a GTO?
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2.
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This mode of operation does not destroy the device provided the gate is negatively biased and the time of such operation is small. Since the holding current of a GTO is considerably higher than that of a thyristor anode current variations can generate serious problem because the GTO might unlatch at an inappropriate moment. To avoid this problem the gate drive unit of a GTO must feed the gate terminal with a continuous back porch current during the entire on period of the GTO. This back porch current must be larger than the gate trigger current. To avoid localized transistor operation during turn on from a high anode voltage with large di/dt, the gate drive unit must inject a peak gate current considerably larger (310 times) than the gate trigger current with fast rate of rise. To ensure that the GTO blocks rated forward voltage and operates safely in the reverse avalanche mode the gate voltage must be maintained negative with respect to the cathode for the entire off duration of the GTO. The gate drive unit of a GTO should. Turn the GTO on with a large (310 times the minimum gate trigger current) positive gate current pulse with high rate of rise. Maintain conduction of the GTO through out the ON period by injecting a positive back porch gate current which is larger than the minimum gate trigger current. Turn the GTO off with a large negative gate current with high rate of fall. The peak magnitude of the negative gate current should be at least 2025% of the maximum anode current during turn off. Reinforce the blocking state of the device by applying a negative voltage to the gate with respect to cathode for the entire off duration of the GTO. Both the turn on delay time (td) and the voltage fall time (tr) of a GTO can be reduced by increasing the peak positive gate current and its rate of rise during turn on. Energy loss per turn on (EON) also reduces. A large negative gate current during turn off with a stiff slope considerably reduces the storage time (ts) and enhances maximum anode current turn off (IFgqm) capability. 4. The specifications of IFAVM and IFRMS are given with reference to power frequency half cycle sine wave anode current. If the GTO is employed in a line commutated phase controlled converter application then these specifications give the maximum allowable average and RMS current through the device respectively. However, in most GTO applications the current waveform is for removed from a sinusoidal shape and the switching losses are a considerable part of the total power losses. IFAVM / IFRMS ratings, in such cases, does not have any practical significance except for comparison of current carrying capacity of different devices. On the other hand, IFgqm rating of a GTO gives the maximum anode current that can be repetitively turned off by gate control. This rating is usually lower than IFAVM / IFRMS. In Version 2 EE IIT, Kharagpur 22 www.jntuworld.com
3.
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high frequency switching application this specification gives the absolute peak value of any desired current waveform the GTO can conduct. 5. Eon is reduced by increasing the peak magnitude of the positive gate current during turn on. Eoff is reduced by increasing the turn off snubber capacitance across the GTO.
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Module 1
Power Semiconductor Devices
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Lesson 6
Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
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Constructional Features, operating principle and characteristics of Power Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
Instructional Objectives
On completion the student will be able to Differentiate between the conduction mechanism of a MOSFET and a BJT. Explain the salient constructional features of a MOSFET. Draw the output iv characteristics of a MOSFET and explain it in terms of the operating principle of the device. Explain the difference between the safe operating area of a MOSFET and a BJT. Draw the switching characteristics of a MOSFET and explain it. Design the gate drive circuit of a MOSFET. Interpret the manufacturers data sheet rating of a MOSFET.
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6.1 Introduction
Historically, bipolar semiconductor devices (i.e, diode, transistor, thyristor, thyristor, GTO etc) have been the front runners in the quest for an ideal power electronic switch. Ever since the invention of the transistor, the development of solidstate switches with increased power handling capability has been of interest for expending the application of these devices. The BJT and the GTO thyristor have been developed over the past 30 years to serve the need of the power electronic industry. Their primary advantage over the thyristors have been the superior switching speed and the ability to interrupt the current without reversal of the device voltage. All bipolar devices, however, suffer from a common set of disadvantages, namely, (i) limited switching speed due to considerable redistribution of minority charge carriers associated with every switching operation; (ii) relatively large control power requirement which complicates the control circuit design. Besides, bipolar devices can not be paralleled easily. The reliance of the power electronics industry upon bipolar devices was challenged by the introduction of a new MOS gate controlled power device technology in the 1980s. The power MOS field effect transistor (MOSFET) evolved from the MOS integrated circuit technology. The new device promised extremely low input power levels and no inherent limitation to the switching speed. Thus, it opened up the possibility of increasing the operating frequency in power electronic systems resulting in reduction in size and weight. The initial claims of infinite current gain for the power MOSFET were, however, diluted by the need to design the gate drive circuit to account for the pulse currents required to charge and discharge the high input capacitance of these devices. At high frequency of operation the required gate drive power becomes substantial. MOSFETs also have comparatively higher on state resistance per unit area of the device cross section which increases with the blocking voltage rating of the device. Consequently, the use of MOSFET has been restricted to low voltage (less than about 500 volts) applications where the ON state resistance reaches acceptable values. Inherently fast switching speed of these devices can be effectively utilized to increase the switching frequency beyond several hundred kHz. From the point of view of the operating principle a MOSFET is a voltage controlled majority carrier device. As the name suggests, movement of majority carriers in a MOSFET is controlled by the voltage applied on the control electrode (called gate) which is insulated by a thin metal oxide layer from the bulk semiconductor body. The electric field produced by the gate voltage modulate the conductivity of the semiconductor material in the region between the main current carrying terminals called the Drain (D) and the Source (S). Power MOSFETs, just like their integrated circuit counterpart, can be of two types (i) depletion type and (ii) enhancement type. Both of these can be either n channel type or pchannel type depending on the nature of the bulk semiconductor. Fig 6.1 (a) shows the circuit symbol of these four types of MOSFETs along with their drain current vs gatesource voltage characteristics (transfer characteristics).
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D ID G G
D ID G
D ID G
D ID
S ID
S ID
S ID
S ID
(b) Fig 6.1: Different types of power MOSFET. (a) Circuit symbols and transfer characteristics (b) Photograph of nchannel enhancement type MOSFET. From Fig 6.1 (a) it can be concluded that depletion type MOSFETs are normally ON type switches i.e, with the gate terminal open a nonzero drain current can flow in these devices. This is not convenient in many power electronic applications. Therefore, the enhancement type MOSFETs (particularly of the nchannel variety) is more popular for power electronics applications. This is the type of MOSFET which will be discussed in this lesson. Fig 6.1 (b) shows the photograph of some commercially available nchannel enhancement type Power MOSFETs.
6.2
As mentioned in the introduction section, Power MOSFET is a device that evolved from MOS integrated circuit technology. The first attempts to develop high voltage MOSFETs were by redesigning lateral MOSFET to increase their voltage blocking capacity. The resulting technology was called lateral double deffused MOS (DMOS). However it was soon realized that Version 2 EE IIT, Kharagpur 5 www.jntuworld.com
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much larger breakdown voltage and current ratings could be achieved by resorting to a vertically oriented structure. Since then, vertical DMOS (VDMOS) structure has been adapted by virtually all manufacturers of Power MOSFET. A power MOSFET using VDMOS technology has vertically oriented three layer structure of alternating p type and n type semiconductors as shown in Fig 6.2 (a) which is the schematic representation of a single MOSFET cell structure. A large number of such cells are connected in parallel (as shown in Fig 6.2 (b)) to form a complete device. Source Gate conductor FIELD OXIDE n+ p(body) n (drain drift) n+ Drain n+ n+ p(body) Gate oxide n+
(a)
Contact to source Source Conductor Gate Oxide
Field oxide
Gate Conductor nn+ p n+ nn+ (b) Fig. 6.2: Schematic construction of a power MOSFET (a) Construction of a single cell. (b) Arrangement of cells in a device. n+ p n+ n+
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The two n+ end layers labeled Source and Drain are heavily doped to approximately the same level. The p type middle layer is termed the body (or substrate) and has moderate doping level (2 to 3 orders of magnitude lower than n+ regions on both sides). The n drain drift region has the lowest doping density. Thickness of this region determines the breakdown voltage of the device. The gate terminal is placed over the n and p type regions of the cell structure and is insulated from the semiconductor body be a thin layer of silicon dioxide (also called the gate oxide). The source and the drain region of all cells on a wafer are connected to the same metallic contacts to form the Source and the Drain terminals of the complete device. Similarly all gate terminals are also connected together. The source is constructed of many (thousands) small polygon shaped areas that are surrounded by the gate regions. The geometric shape of the source regions, to same extent, influences the ON state resistance of the MOSFET.
D Parasitic BJT
MOSFET
Body diode S
Fig. 6.3: Parasitic BJT in a MOSFET cell. One interesting feature of the MOSFET cell is that the alternating n+ n p n+ structure embeds a parasitic BJT (with its base and emitter shorted by the source metallization) into each MOSFET cell as shown in Fig 6.3. The nonzero resistance between the base and the emitter of the parasitic npn BJT arises due to the body spreading resistance of the p type substrate. In the design of the MOSFET cells special care is taken so that this resistance is minimized and switching operation of the parasitic BJT is suppressed. With an effective short circuit between the body and the source the BJT always remain in cut off and its collectorbase junction is represented as an anti parallel diode (called the body diode) in the circuit symbol of a Power MOSFET.
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The gate region of a MOSFET which is composed of the gate metallization, the gate (silicon) oxide layer and the pbody silicon forms a high quality capacitor. When a small voltage is application to this capacitor structure with gate terminal positive with respect to the source (note that body and source are shorted) a depletion region forms at the interface between the SiO2 and the silicon as shown in Fig 6.4 (a). VGS1 Source Electrode n+ Ionized acceptor Depletion layer boundary.
+++ ++++++++
p n
+++ ++++++++
p n
Ionized acceptor
Free electron
(b)
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+++ ++++++++
Gate Electrode Si02 Inversion layer with free electrons Depletion layer boundary.
p nIonized acceptor
(c)
Fig. 6.4: Gate control of MOSFET conduction. (a) Depletion layer formation; (b) Free electron accumulation; (c) Formation of inversion layer. The positive charge induced on the gate metallization repels the majority hole carriers from the interface region between the gate oxide and the p type body. This exposes the negatively charged acceptors and a depletion region is created. Further increase in VGS causes the depletion layer to grow in thickness. At the same time the electric field at the oxidesilicon interface gets larger and begins to attract free electrons as shown in Fig 6.4 (b). The immediate source of electron is electronhole generation by thermal ionization. The holes are repelled into the semiconductor bulk ahead of the depletion region. The extra holes are neutralized by electrons from the source. As VGS increases further the density of free electrons at the interface becomes equal to the free hole density in the bulk of the body region beyond the depletion layer. The layer of free electrons at the interface is called the inversion layer and is shown in Fig 6.4 (c). The inversion layer has all the properties of an n type semiconductor and is a conductive path or channel between the drain and the source which permits flow of current between the drain and the source. Since current conduction in this device takes place through an n type channel created by the electric field due to gate source voltage it is called Enhancement type nchannel MOSFET. The value of VGS at which the inversion layer is considered to have formed is called the Gate Source threshold voltage VGS (th). As VGS is increased beyond VGS(th) the inversion layer gets some what thicker and more conductive, since the density of free electrons increases further with increase in VGS. The inversion layer screens the depletion layer adjacent to it from increasing VGS. The depletion layer thickness now remains constant.
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Exercise 6.1 (after section 6.3) 1. i. ii. iii. iv. v. vi. Fill in the blank(s) with the appropriate word(s) A MOSFET is a ________________ controlled ________________ carrier device. Enhancement type MOSFETs are normally ________________devices while depletion type MOSFETs are normally ________________ devices. The Gate terminal of a MOSFET is isolated from the semiconductor by a thin layer of ________________. The MOSFET cell embeds a parasitic ________________ in its structure. The gatesource voltage at which the ________________ layer in a MOSFET is formed is called the ________________ voltage. The thickness of the ________________ layer remains constant as gate source voltage is increased byond the ________________ voltage.
Answer: (i) voltage, majority; (ii) off, on; (iii) SiO2, (iv) BJT, (v) inversion, threshold; (vi) depletion, threshold. 2. What are the main constructional differences between a MOSFET and a BJT? What effect do they have on the current conduction mechanism of a MOSFET? Answer: A MOSFET like a BJT has alternating layers of p and n type semiconductors. However, unlike BJT the p type body region of a MOSFET does not have an external electrical connection. The gate terminal is insulated for the semiconductor by a thin layer of SiO2. The body itself is shorted with n+ type source by the source metallization. Thus minority carrier injection across the sourcebody interface is prevented. Conduction in a MOSFET occurs due to formation of a high density n type channel in the p type body region due to the electric field produced by the gatesource voltage. This n type channel connects n+ type source and drain regions. Current conduction takes place between the drain and the source through this channel due to flow of electrons only (majority carriers). Where as in a BJT, current conduction occurs due to minority carrier injection across the BaseEmitter junction. Thus a MOSFET is a voltage controlled majority carrier device while a BJT is a minority carrier bipolar device.
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VGS VGS (th) = VDS iD ohmic rDS(ON) Increasing VGS VGS6 Active VGS5 [VGSVGS(th)]<VDS VGS4 VGS3 VGS2 vgs1 Cut off (VGS < VGS (th)) VDSS vDS (a) S n+ Source region resistance Channel p resistance nn+ (b) Drift region resistance Drain resistance G iD
(c)
Electric Field
iD
VGS(th) D (d)
VGS
Fig. 6.5: Output iv characteristics of a Power MOSFET (a) iv characteristics; (b) Components of ONstate resistance; (c) Electron drift velocity vs Electric field; (d) Transfer With gatesource voltage (VGS) below the threshold voltage (vGS (th)) the MOSFET operates in the cutoff mode. No drain current flows in this mode and the applied drain source voltage (vDS) is supported by the bodycollector pn junction. Therefore, the maximum applied voltage should be below the avalanche break down voltage of this junction (VDSS) to avoid destruction of the device. When VGS is increased beyond vGS(th) drain current starts flowing. For small values of vDS (vDS < (vGS vGS(th)) iD is almost proportional to vDS. Consequently this mode of operation is called ohmic mode of operation. In power electronic applications a MOSFET is operated either in the cut off or in the ohmic mode. The slope of the vDS iD characteristics in this mode is called the ON state resistance of the MOSFET (rDS (ON)). Several physical resistances as shown in Fig 6.5 (b) contribute to rDS (ON). Note that rDS (ON) reduces with increase in vGS. This is mainly due to reduction of the channel resistance at higher value of Version 2 EE IIT, Kharagpur 11 www.jntuworld.com
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vGS. Hence, it is desirable in power electronic applications, to use as large a gatesource voltage as possible subject to the dielectric break down limit of the gateoxide layer. At still higher value of vDS (vDS > (vGS vGS (th)) the iD vDS characteristics deviates from the linear relationship of the ohmic region and for a given vGS, iD tends to saturate with increase in vDS. The exact mechanism behind this is rather complex. It will suffice to state that, at higher drain current the voltage drop across the channel resistance tends to decrease the channel width at the drain drift layer end. In addition, at large value of the electric field, produced by the large Drain Source voltage, the drift velocity of free electrons in the channel tends to saturate as shown in Fig 6.5 (c). As a result the drain current becomes independent of VDS and determined solely by the gate source voltage vGS. This is the active mode of operation of a MOSFET. Simple, first order theory predicts that in the active region the drain current is given approximately by
(6.1)
Where K is a constant determined by the device geometry. At the boundary between the ohmic and the active region vDS = vGS  vGS (th) (6.2) Therefore, i D = KvDS2
(6.3)
Equation (6.3) is shown by a dotted line in Fig 6.5 (a). The relationship of Equation (6.1) applies reasonably well to logic level MOSFETs. However, for power MOSFETs the transfer characteristics (iD vs vGS) is more linear as shown in Fig 6.5 (d). At this point the similarity of the output characteristics of a MOSFET with that of a BJT should be apparent. Both of them have three distinct modes of operation, namely, (i)cut off, (ii) active and (iii) ohmic (saturation for BJT) modes. However, there are some important differences as well. Unlike BJT a power MOSFET does not undergo second break down. The primary break down voltage of a MOSFET remains same in the cut off and in the active modes. This should be contrasted with three different break down voltages (VSUS, VCEO & VCBO) of a BJT. The ON state resistance of a MOSFET in the ohmic region has positive temperature coefficient which allows paralleling of MOSFET without any special arrangement for current sharing. On the other hand, vCE (sat) of a BJT has negative temperature coefficient making parallel connection of BJTs more complicated. As in the case of a BJT the operating limits of a MOSFET are compactly represented in a Safe Operating Area (SOA) diagram as shown in Fig 6.6. As in the case of the FBSOA of a Version 2 EE IIT, Kharagpur 12 www.jntuworld.com
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BJT the SOA of a MOSFET is plotted on a loglog graph. On the top, the SOA is restricted by the absolute maximum permissible value of the drain current (IDM) which should not be exceeded even under pulsed operating condition. To the left, operating restriction arise due to the non zero value of rDS(ON) corresponding to vGS = vGS(Max). To the right, the first operating restriction is due to the limit on the maximum permissible junction temperature rise which depends on the power dissipation inside the MOSFET. This limit is different for DC (continuous) and pulsed operation of different pulse widths. As in the case of a BJT the pulsed safe operating areas are useful for shaping the switching trajectory of a MOSFET. A MOSFET does not undergo second break down and no corresponding operating limit appears on the SOA. The final operation limit to the extreme right of the SOA arises due to the maximum permissible drain source voltage (VDSS) which is decided by the avalanche break down voltage of the drain body pn junction. This is an instantaneous limit. There is no distinction between the forward biased and the reverse biased SOAs for the MOSFET. They are identical. Log (iD) IDM 105sec rDS(ON) limit 104sec (VGS = VGS(max)) Max. 103sec Power Dissipation DC Limit (Timax) Primary voltage breakdown limit VDSS Log (vDS) Fig. 6.6: Safe operating area of a MOSFET. Due to the presence of the anti parallel body diode, a MOSFET can not block any reverse voltage. The body diode, however, can carry an RMS current equal to IDM. It also has a substantial surge current carrying capacity. When reverse biased it can block a voltage equal to VDSS. For safe operation of a MOSFET, the maximum limit on the gate source voltage (VGS (Max)) must be observed. Exceeding this voltage limit will cause dielectric break down of the thin gate oxide layer and permanent failure of the device. It should be noted that even static charge inadvertently put on the gate oxide by careless handling may destroy it. The device user should ground himself before handling any MOSFET to avoid any static charge related problem. Exercise 6.2 Fill in the blank(s) with the appropriate word(s) i. A MOSFET operates in the ________________ mode when vGS < vGS(th) Version 2 EE IIT, Kharagpur 13 www.jntuworld.com
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In the ohmic region of operation of a MOSFET vGS vGS (th) is greater than ________________. rDS (ON) of a MOSFET ________________ with increasing vGS. In the active region of operation the drain current iD is a function of ________________ alone and is independent of ________________. The primary break down voltage of MOSFET is ________________ of the drain current. Unlike BJT a MOSFET does not undergo ________________. ________________ temperature coefficient of rDS(ON) of MOSFETs facilitates easy ________________ of the devices. In a Power MOSFET the relation ship between iD and vGS vGS(th) is almost ________________ in the active mode of operation. The safe operating area of a MOSFET is restricted on the left hand side by the ________________ limit.
Answer: (i) Cut off; (ii) vDS; (iii) decreases; (iv) vGS, vDS; (v) independent; (vi) break down; (vii) Positive, paralleling; (viii) linear; (ix) rDS (ON);
second
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S n
+
G Gate oxide
p CDS nn+
CGS
CGD
(a)
D CGD G CGS S (cut off) G
VDS
(b)
D CGD iD = f(vGS) CGS S (Active) G CGS S CGD rDS(ON) (Ohmic) D
(c)
Fig. 6.7: Circuit model of a MOSFET (a) MOSFET capacitances (b) Variation of CGD with VDS (c) Circuit models. Fig 6.7 (a) shows three important capacitances inherent in a MOSFET structure. The most prominent capacitor in a MOSFET structure is formed by the gate oxide layer between the gate metallization and the n+ type source region. It has the largest value (a few nano farads) and remains more or less constant for all values of vGS and vDS. The next largest capacitor (a few hundred pico forwards) is formed by the drain body depletion region directly below the gate metallization in the n drain drift region. Being a depletion layer capacitance its value is a strong function of the drain source voltage vDS. For low values of vDS (vDS < (vGS vGS (th))) the value of CGD (CGD2) is considerably higher than its value for large vDS as shown in Fig 6.7 (b). Although variation of CGD between CGD1 and CGD2 is continuous a step change in the value of CGD at vDS = vGS vGS(th) is assumed for simplicity. The lowest value capacitance is formed between the drain and the source terminals due to the drain body depletion layer away form the gate metallization and below the source metallization. Although this capacitance is important for some design considerations (such as snubber design, zero voltage switching etc) it does not appreciably affect the hard switching performance of a MOSFET. Consequently, it will be neglected in our discussion. From the Version 2 EE IIT, Kharagpur 15 www.jntuworld.com
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above discussion and the steady state characteristics of a MOSFET the circuit models of a MOSFET in three modes of operation can be drawn as shown in Fig 6.7 (c).
Fig. 6.8: Clamped inductive switching circuit using a MOSFET. To turn the MOSFET on, the gate drive voltage changes from zero to Vgg. The gate source voltage which was initially zero starts rising towards Vgg with a time constant 1 = Rg (CGS + CGD1) as shown in Fig 6.9.
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2 1
2 = Rg(CGS+CGD2)
Vgg
1 = Rg(CGS+CGD1)
R g igI0
Vgg
igI0
Rg
iD, if I0 if VDS
iD I0
if
iD
I0ros (ON)
tdON tri
Fig. 6.9: Switching waveforms of a clamped inductive switching circuit using MOSFET Note that during this period the drain voltage vDS is clamped to the supply voltage VD through the free wheeling diode DF. Therefore, CGS and CGD can be assumed to be connected in parallel effectively. A part of the total gate current ig charges CGS while the other part discharges CGD. Till vGS reaches vGS (th) no drain current flows. This time period is called turn on delay time (td(ON)). Note that td(ON) can be controlled by controlling Rg. Byond td(ON) iD increases linearly with vGS and in a further time tri (current rise time) reaches Io. The corresponding value of vGS and ig are marked as VGS Io and ig Io respectively in Fig 6.9. At this point the complete load current has been transferred to the MOSFET from the free wheeling diode DF. iD does not increase byond this point. Since in the active region iD and vGS are linearly related, vGS also becomes clamped at the value vGSIo. The gate current ig now discharges CGD and the drain voltage starts falling.
ig V V I d d d v DS = ( vGS + vGD ) = v GD = = GG GS o dt dt dt CGD CGD R g
( 6.4 )
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The fall of vDS occurs in two distinct intervals. When the MOSFET is in the active region (vDS > (vGS vGS (th)) CGD = CGD1.Since CGD1 << CGD2, vDS falls rapidly. This fast fall time of vDS is marked tfv1 in Fig 6.9. However, once in the ohmic region, CGD = CGD2 >> CGD1. Therefore, rate of fall of vDS slows down considerably (tfv2). Once vDS reaches its on state value (rDS(ON) Io) vGS becomes unclamped and increases towards Vgg with a time constant 2 = Rg (CGS + CGD2). Note that all switching periods can be reduced by increasing Vgg or / and decreasing Rg. The total turn on time is tON = td(ON) + tri + tfv1 + tfv2. To turn the MOSFET OFF, Vgg is reduced to zero triggering the exact reverse process of turn on to take place. The corresponding waveforms and switching intervals are show in Fig 6.9. The total turn off time toff = td(off) + trv1 + trv2 + tfi.
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VD VGG
RG +
R1 (1 +1)
RG VGG
(a) VD
(b)
DF
IL RG D G R
B G S (c)
S RB (d)
Fig. 6.10: MOSFET gate drive circuit. (a) Gate drive circuit; (b) Equivalent circuit during turn on and off; (b) Effect of parasitic BJT; (d) Parallel connection of MOSFETs. To turn the MOSFET on the logic level input to the inverting buffer is set to high state so that transistor Q3 turns off and Q1 turns on. The top circuit of Fig 6.10 (b) shows the equivalent circuit during turn on. Note that, during turn on Q1 remains in the active region. The effective gate resistance is RG + R1 / (1 + 1). Where, 1 is the dc current gain of Q1.
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To turn off the MOSFET the logic level input is set to low state. Q3 and Q2 turns on whole Q1 turns off. The corresponding equivalent circuit is given by the bottom circuit of Fig 6.10 (b) The switching time of the MOSFET can be adjusted by choosing a proper value of RG. Reducing RG will incase the switching speed of the MOSFET. However, caution should be exercised while increasing the switching speed of the MOSFET in order not to turn on the parasitic BJT in the MOSFET structure inadvertently. The drainsource capacitance (CDS) is actually connected to the base of the parasitic BJT at the p type body region. The body source short has some nonzero resistance. A very fast rising drainsource voltage will send sufficient displacement current through CDS and RB as shown in Fig 6.10 (c). The voltage drop across RB may become sufficient to turn on the parasitic BJT. This problem is largely avoided in a modern MOSFET design by increasing the effectiveness of the bodysource short. The devices are now capable of dvDS/dt in excess to 10,000 V/s. Of course, this problem can also be avoided by slowing down the MOSFET switching speed. Since MOSFET on state resistance has positive temperature coefficient they can be paralleled without taking any special precaution for equal current sharing. To parallel two MOSFETs the drain and source terminals are connected together as shown in Fig 6.10 (d). However, small resistances (R) are connected to individual gates before joining them together. This is because the gate inputs are highly capacitive with almost no losses. Some stray inductance of wiring may however be present. This stray inductance and the MOSFET capacitance can give rise to unwanted high frequency oscillation of the gate voltage that can result in puncture of the gate qxide layer due to voltage increase during oscillations. This is avoided by the damping resistance R. Exercise 6.3 1. i. ii. iii. iv. v. Fill in the blank(s) with the appropriate word(s) The GateSource capacitance of a MOSFET is the ________________ among all three capacitances. The GateDrain transfer capacitance of a MOSFET has large value in the ________________ region and small value in the ________________ region. During the turn on delay time the MOSFET gate source voltage rises from zero to the ________________ voltage. The voltage fall time of a MOSFET is ________________ proportional to the gate charging resistance. Unlike BJT the switching delay times in a MOSFET can be controlled by proper design of the ________________ circuit. Answer: (i) largest; (ii) ohmic, active; (iii) threshold; (iv) inversely; (v) gate drive. Version 2 EE IIT, Kharagpur 20 www.jntuworld.com
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2. A Power MOSFET has the following data CGS = 800 pF ; CGD = 150 pF; gf = 4; vGS(th) = 3V; It is used to switch a clamped inductive load (Fig 6.8) of 20 Amps with a supply voltage VD= 200V. The gate drive voltage is vgg = 15V, and gate resistance Rg = 50. Find out maximum dv DS did and during turn ON. value of dt dt Answer: During turn on i D g f ( v gs  v gs (th) )
dv gs di D = gf dt dt dv V v But ( CGS + CGD ) gs = gg gs dt Rg
di D dt
=
Max
R g ( CGS + CGD
gf
(V )
gg
 vgs
Min
)=
iD =
di D =0 dt
di D dt
=
Max
6.6
MOSFET Ratings
Steady state operating limits of a MOSFET are usually specified compactly as a safe operating area (SOA) diagram. The following limits are specified.
VDSS: This is the drainsource break down voltage. Exceeding this limit will destroy the device due to avalanche break down of the bodydrain pn junction.
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IDM: This is the maximum current that should not be exceeded even under pulsed current operating condition in order to avoid permanent damage to the bonding wires. Continuous and Pulsed power dissipation limits: They indicate the maximum allowable value of the VDS, iD product for the pulse durations shown against each limit. Exceeding these limits will cause the junction temperature to rise beyond the acceptable limit.
All safe operating area limits are specified at a given case temperature. In addition, several important parameters regarding the dynamic performance of the device are also specified. These are
Gate threshold voltage (VGS (th)): The MOSFET remains in the cut off region when vGS in below this voltage. VGS (th) decreases with junction temperature. Drain Source on state resistance (rDS (ON)): This is the slope of the iD vDS characteristics in the ohmic region. Its value decreases with increasing vGS and increases with junction temperature. rDS (ON) determines the ON state power loss in the device. Forward Transconductance (gfs): It is the ratio of iD and (vGS vGS(th)). In a MOSFET switching circuit it determines the clamping voltage level of the gate source voltage and thus influences dvDS/dt during turn on and turn off. GateSource breakdown voltage: Exceeding this limit will destroy the gate structure of the MOSFET due to dielectric break down of the gate oxide layer. It should be noted that this limit may by exceeded even by static charge deposition. Therefore, special precaution should be taken while handing MOSFETs. Input, output and reverse transfer capacitances (CGS, CDS & CGD): Value of these capacitances are specified at a given drainsource and gatesource voltage. They are useful for designing the gate drive circuit of a MOSFET.
In addition to the main MOSFET, specifications pertaining to the body diode are also provided. Specifications given are
Reverse break down voltage: This is same as VDSS Continuous ON state current (IS): This is the RMS value of the continuous current that can flow through the diode. Pulsed ON state current (ISM): This is the maximum allowable RMS value of the ON state current through the diode given as a function of the pulse duration. Forward voltage drop (vF): Given as an instantaneous function of the diode forward current. Reverse recovery time (trr) and Reverse recovery current (Irr): These are specified as functions of the diode forward current just before reverse recovery and its decreasing slope (diF/dt).
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Exercise 6.4
Fill in the blank(s) with the appropriate word(s) i. ii. iii. iv. v. The maximum voltage a MOSFET can with stand is ________________ of drain current. The FBSOA and RBSOA of a MOSFET are ________________. The gate source threshold voltage of a MOSFET ________________ with junction temperature while the on state resistance ________________ with junction temperature. The gate oxide of a MOSFET can be damaged by ________________ electricity. The reverse break down voltage of the body diode of a MOSFET is equal to ________________ while its RMS forward current rating is equal to ________________.
Answer: (i) independent; (ii) identical; (iii) decreases, increases; (iv) static; (v) VDSS; IDM.
Reference
[1] Evolution of MOSBipolar power semiconductor Technology, B. Jayant Baliga, Proceedings of the IEEE, VOL.76, No4, April 1988. [2] Power Electronics ,Converters Application and Design Third Edition, Mohan, Undeland, Robbins. John Wiley & Sons Publishers 2003. [3] GE Power MOSFET data sheet.
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Lesson Summary
MOSFET is a voltage controlled majority carrier device. A Power MOSFET has a vertical structure of alternating p and n layers. The main current carrying terminals of an n channel enhancement mode MOSFET are called the Drain and the Source and are made up of n+ type semiconductor. The control terminal is called the Gate and is isolated form the bulk semiconductor by a thin layer of SiO2.
p type semiconductor body separates n+ type source and drain regions.
A conducting n type channel is produced in the p type body region when a positive voltage greater than a threshold voltage is applied at the gate. Current conduction in a MOSFET occurs by flow of electron from the source to the drain through this channel. When the gate source voltage is below threshold level a MOSFET remains in the Cut Off region and does not conduct any current. With vGS > vGS (th) and vDS < (vGS vGS (th)) the drain current in a MOSFET is proportional to vDS. This is the Ohmic region of the MOSFET output characteristics. For larger values of vDS the drain current is a function of vGS alone and does not depend on vDs. This is called the active region of the MOSFET. In power electronic applications a MOSFET is operated in the Cut Off and Ohmic regions only. The on state resistance of a MOSFET (VDS (ON)) has a positive temperature coefficient. Therefore, MOSFETs can be easily paralleled. A MOSFET does not undergo second break down. The safe operating area (SOA) of a MOSFET is similar to that of a BJT except that it does not have a second break down limit. Unlike BJT the maximum forward voltage withstanding capability of a MOSFET does not depend on the drain current. The safe operating area of a MOSFET does not change under Forward and Reverse bias conditions. The drain body junction in a MOSFET structure constitute an anti parallel diode connected between the source and the drain. This is called the MOSFET body diode. The body diode of a MOSFET has the same break down voltage and forward current rating as the main MOSFET. The switching delays in a MOSFET are due to finite charging and discharging time of the input and output capacitors. Switching times of a MOSFET can be controlled completely by external gate drive design.
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The input capacitor along with the gate drive resistance determine the current rise and fall time of a MOSFET during switching. The transfer capacitor (Cgd) determines the drain voltage rise and fall times. rDS (ON) of a MOSFET determines the conduction loss during ON period. rDS (ON) reduces with higher vgs. Therefore, to minimize conduction power loss maximum permissible vgs should be used subject to dielectric break down of the gate oxide layer. The gate oxide layer can be damaged by static charge. Therefore MOSFETs should be handled only after discharging one self through proper grounding. For similar voltage rating, a MOSFET has a relatively higher conduction loss and lower switching loss compared to a BJT. Therefore, MOSFETs are more popular for high frequency (>50 kHz) low voltage (<100 V) circuits.
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Practice Problems
1. How do you expect the gate source capacitance of a MOSFET to varry with gate source voltage. Explain your answer. 2. The gate oxide layer of a MOSFET is 1000 Angstrom thick Assuming a break down field strength of 5 106 V/cm and a safely factor of 50%, find out the maximum allowable gate source voltage. 3. Explain why in a high voltage MOSFET switching circuit the voltage rise and fall time is always greater than current fall and rise times. 4. A MOSFET has the following parameters VGS(th) = 3V, gfs = 3, CGS = 800 PF, CGD = 250 PF. The MOSFET is used to switch an inductive load of 15 Amps from 150V supply. The switching frequency is 50 kHz. The gate drive circuit has a driving voltage of 15V and output resistance of 50. Find out the switching loss in the MOSFET.
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= E BD t gs
where EBD = Break down field strength tgs = thickness of the oxide layer. So v GS Let vgs safety.
BD
Max
= vGS
BD
= 50 V
vgs
50 V 33 Volts. 1.5
( Vgg  vGS ) di D d = g fs vGS = g fs dt dt R g CGS During current rise Vgg >> vGS g fs di Vgg D dt R g CGS
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I t ri t = fi = o t rr t fr VD
CG S g fs CG D
That is current rise and fall times are much shorter than voltage rise and fall times. 4. Referring to Fig 6.9 energy loss during switching occurs during intervals tri , tfv1, tfv2, trv2,trv1, and tfi. For simplicity it will be assumed that tfv2 = trv2 = 0. Also the rise and fall of iD and vDS will be assumed to be linear. During tri i D = g fs (vgs  vgs (th))
Vgg  v gs di D d = g fs v gs = g fs dt dt (CGS + CGD )R g g fs Vgg di D sinceVgg >> v gs during current rise dt (CGS + CGD )R g
Io (CGS + CGD )R g g fs Vgg Energy loss during tri is V I2 1 E ON1 = t ri VD Io = D o (CGS + CGD )R g 2 2g fs Vgg During tfv dVDS Vgg  Vgs, Io = dt CGD R g I But Vgs , Io = o + vgs (th) g fs I Vgg  v gs (th)  o dVDS g fs = dt R g CGD t ri =
t fv =
Io
R g CGD g fs
Energy loss during tfv is E ON2 = 1 t fv Io VD 2 VD 2 Io = R C Io g GD 2 V v (th) gg gs g fs Energy loss during Turn on is
Version 2 EE IIT, Kharagpur 29
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VD Io R g Io ( CGS + CGD ) VD CGD + 2 g fs Vgg V V (th) ( ) gg gs From the symmetry of the Turn ON and the Turn OFF operation of MOSFET (i.e. tri = tfi, tfv = trv) E ON = E ON1 + E ON2 =
E ON = EOFF
Total switching energy lass is Esw = EON + EOFF = 2 EON VD Vgg I g C E sw = VD Io R g CGD o fs 1+ GS + Vgg CGD Vgs (th) Io g fs V Vgg gg
VD Vgg C I g Psw E sw = VD Io R g CGD f sw 1+ GS o fs + v gs (th) Io g fs CGD Vgg 1 Vgg v gg Substituting the values given Psw = 32 mw,
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Module 1
Power Semiconductor Devices
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Lesson 7
Insulated Gate Bipolar Transistor (IGBT)
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Constructional features, operating principle and characteristics of Insulated Gate Bipolar Transistors (IGBT)
Instructional objects
On completion the student will be able to Differentiate between the constructional features of an IGBT and a MOSFET. Draw the operational equivalent circuit of an IGBT and explain its operating principle in terms of the schematic construction and the operational equivalent circuit. Draw and explain the steady state output and transfer characteristics of an IGBT. Draw the switching characteristics of an IGBT and identify its differences with that of a MOSFET. Design a basic gate drive circuit for an IGBT. Interpret the manufacturers date sheet of an IGBT.
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7.1 Introduction
The introduction of Power MOSFET was originally regarded as a major threat to the power bipolar transistor. However, initial claims of infinite current gain for the power MOSFETs were diluted by the need to design the gate drive circuit capable of supplying the charging and discharging current of the device input capacitance. This is especially true in high frequency circuits where the power MOSFET is particularly valuable due to its inherently high switching speed. On the other hand, MOSFETs have a higher on state resistance per unit area and consequently higher on state loss. This is particularly true for higher voltage devices (greater than about 500 volts) which restricted the use of MOSFETs to low voltage high frequency circuits (eg. SMPS). With the discovery that power MOSFETs were not in a strong position to displace the BJT, many researches began to look at the possibility of combining these technologies to achieve a hybrid device which has a high input impedance and a low on state resistance. The obvious first step was to drive an output npn BJT with an input MOSFET connected in the Darlington configuration. However, this approach required the use of a high voltage power MOSFET with considerable current carrying capacity (due to low current gain of the output transistor). Also, since no path for negative base current exists for the output transistor, its turn off time also tends to get somewhat larger. An alternative hybrid approach was investigated at GE Research center where a MOS gate structures was used to trigger the latch up of a four layer thyristor. However, this device was also not a true replacement of a BJT since gate control was lost once the thyristor latched up. After several such attempts it was concluded that for better results MOSFET and BJT technologies are to be integrated at the cell level. This was achieved by the GE Research Laboratory by the introduction of the device IGT and by the RCA research laboratory with the device COMFET. The IGT device has undergone many improvement cycles to result in the modern Insulated Gate Bipolar Transistor (IGBT). These devices have near ideal characteristics for high voltage (> 100V) medium frequency (< 20 kHZ) applications. This device along with the MOSFET (at low voltage high frequency applications) have the potential to replace the BJT completely.
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Gate SiO2 (Gate oxide) Body region Drain drift region Buffer layer Injecting layer
p nn+ p+ Collector
Fig. 7.1: Vertical cross section of an IGBT cell. The major difference with the corresponding MOSFET cell structure lies in the addition of a p+ injecting layer. This layer forms a pn junction with the drain layer and injects minority carriers into it. The n type drain layer itself may have two different doping levels. The lightly doped nregion is called the drain drift region. Doping level and width of this layer sets the forward blocking voltage (determined by the reverse break down voltage of J2) of the device. However, it does not affect the on state voltage drop of the device due to conductivity modulation as discussed in connection with the power diode. This construction of the device is called Punch Trough (PT) design. The NonPunch Through (NPT) construction does not have this added n+ buffer layer. The PT construction does offer lower on state voltage drop compared to the NPT construction particularly for lower voltage rated devices. However, it does so at the cost of lower reverse break down voltage for the device, since the reverse break down voltage of the junction J1 is small. The rest of the construction of the device is very similar to that of a vertical MOSFET (Link to 6.2) including the insulated gate structure and the shorted body (p type) emitter (n+ type) structure. The doping level and physical geometry of the p type body region however, is considerably different from that of a MOSFET in order to defeat the latch up action of a parasitic thyristor embedded in the IGBT structure. A large number of basic cells as shown in Fig 7.1 are grown on a single silicon wafer and connected in parallel to form a complete IGBT device. The IGBT cell has a parasitic pnpn thyristor structure embedded into it as shown in Fig 7.2(a). The constituent pnp transistor, npn transistor and the driver MOSFET are shown by dotted lines in this figure. Important resistances in the current flow path are also indicated.
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Gate Emitter
MOSFET
n+ p
J3
Body spreading resistance
npn
Drift resistance
pnp
nn+ p+ J1
J2
Collector
Collector
Gate
Fig. 7.2: Parasitic thyristor in an IGBT cell. (a) Schematic structure (b) Exact equivalent circuit. (c) Approximate equivalent circuit Fig 7.2(b) shows the exact static equivalent circuit of the IGBT cell structure. The top pnp transistor is formed by the p+ injecting layer as the emitter, the n type drain layer as the base and the p type body layer as the collector. The lower npn transistor has the n+ type source, the p type body and the n type drain as the emitter, base and collector respectively. The base of the lower npn transistor is shorted to the emitter by the emitter metallization. However, due to imperfect shorting, the exact equivalent circuit of the IGBT includes the body spreading resistance between the base and the emitter of the lower npn transistor. If the output current is large enough, the voltage drop across this resistance may forward bias the lower npn transistor and initiate the latch up process of the pnpn thyristor structure. Once this structure latches up the gate control of IGBT is lost and the device is destroyed due to excessive power loss. A major effort in the development of IGBT has been towards prevention of latch up of the parasitic thyristor. This has been achieved by modifying the doping level and physical geometry of the body region. The modern IGBT is latchup proof for all practical purpose. Fig 7.3(a) and (b) shows the circuit symbol and photograph of an IGBT.
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G E (a) (b) Fig. 7.3: Circuit symbol of an IGBT. (a) Circuit symbol. (b) Photograph. Exercise 7.1 Fill in the blank(s) with the appropriate word(s). i. An IGBT is a __________________ device combining the advantages of a __________________ and a __________________. ii. IGBT is suitable for __________________ voltage __________________ frequency applications. iii. In an IGBT cell structure a __________________ type injecting layer is added on top of the drain of an n channel MOSFET. iv. The forward blocking voltage of an IGBT is determined by the __________________ and __________________ of the drain drift layer. v. A punch through IGBT has __________________ reverse break down voltage while the Non punch through IGBT has __________________ voltage blocking capacity. vi. The IGBT cell has a parasitic __________________ structure embedded into it. vii. The parasitic __________________ structure of an IGBT cell can __________________ at large collector current due to imperfect body emitter shorting. viii. The doping level and physical geometry of the IGBT __________________ region is designed to be considerably different from that of a MOSFET to prevent its __________________. Answers: i) hybrid, MOSFET, BJT ; ii) high, medium ; iii) p+ ; iv) thickness, doping level ; v) low, symmetrical ; vi) thyristor; vii) thryistor, latch up ; viii) body, latch up.
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MOSFET. Therefore, when the gate emitter voltage is less then the threshold voltage no inversion layer is formed in the p type body region and the device is in the off state. The forward voltage applied between the collector and the emitter drops almost entirely across the junction J2. Very small leakage current flows through the device under this condition. In terms of the equivalent current of Fig 7.2(c), when the gate emitter voltage is lower than the threshold voltage the driving MOSFET of the Darlington configuration remains off and hence the output pnp transistor also remains off. When the gate emitter voltage exceeds the threshold, an inversion layer forms in the p type body region under the gate. This inversion layer (channel) shorts the emitter and the drain drift layer and an electron current flows from the emitter through this channel to the drain drift region. This in turn causes substantial hole injection from the p+ type collector to the drain drift region. A portion of these holes recombine with the electrons arriving at the drain drift region through the channel. The rest of the holes cross the drift region to reach the p type body where they are collected by the source metallization. From the above discussion it is clear that the n type drain drift region acts as the base of the output pnp transistor. The doping level and the thickness of this layer determines the current gain of the pnp transistor. This is intentionally kept low so that most of the device current flows through the MOSFET and not the output pnp transistor collector. This helps to reduced the voltage drop across the body spreading resistance shown in Fig 7.2 (b) and eliminate the possibility of static latch up of the IGBT. The total on state voltage drop across a conducting IGBT has three components. The voltage drop across J1 follows the usual exponential law of a pn junction. The next component of the voltage drop is due to the drain drift region resistance. This component in an IGBT is considerably lower compared to a MOSFET due to strong conductivity modulation by the injected minority carriers from the collector. This is the main reason for reduced voltage drop across an IGBT compared to an equivalent MOSFET. The last component of the voltage drop across an IGBT is due to the channel resistance and its magnitude is equal to that of a comparable MOSFET.
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VCC RL ic + C VcE E 
iC
G VgE
Increasing Saturation V VgE6 gE VCC Active RL VgE5 Load line A VgE4 VgE3 B VgE2 VgE1
VRM
Cut off
(a)
Fig. 7.4: Static characteristics of an IGBT (a) Output characteristics; (b) Transfer characteristics When the gate emitter voltage is below the threshold voltage only a very small leakage current flows though the device while the collector emitter voltage almost equals the supply voltage (point C in Fig 7.4(a)). The device, under this condition is said to be operating in the cut off region. The maximum forward voltage the device can withstand in this mode (marked VCES in Fig 7.4 (a)) is determined by the avalanche break down voltage of the body drain pn junction. Unlike a BJT, however, this break down voltage is independent of the collector current as shown in Fig 7.4(a). IGBTs of Nonpunch through design can block a maximum reverse voltage (VRM) equal to VCES in the cut off mode. However, for Punch Through IGBTs VRM is negligible (only a few tens of volts) due the presence of the heavily doped n+ drain buffer layer. As the gate emitter voltage increases beyond the threshold voltage the IGBT enters into the active region of operation. In this mode, the collector current ic is determined by the transfer characteristics of the device as shown in Fig 7.4(b). This characteristic is qualitatively similar to that of a power MOSFET and is reasonably linear over most of the collector current range. The ratio of ic to (VgE vgE(th)) is called the forward transconductance (gfs) of the device and is an important parameter in the gate drive circuit design. The collector emitter voltage, on the other hand, is determined by the external load line ABC as shown in Fig 7.4(a). As the gate emitter voltage is increased further ic also increases and for a given load resistance (RL) vCE decreases. At one point vCE becomes less than vgE vgE(th). Under this condition the driving MOSFET part of the IGBT (Fig 7.2(c)) enters into the ohmic region and drives the output pnp transistor to saturation. Under this condition the device is said to be in the saturation mode. In the saturation mode the voltage drop across the IGBT remains almost constant reducing only slightly with increasing vgE. In power electronic applications an IGBT is operated either in the cut off or in the saturation region of the output characteristics. Since vCE decreases with increasing vgE, it is desirable to use the maximum permissible value of vgE in the ON state of the device. vgE(Max) is limited by the maximum collector current that should be permitted to flow in the IGBT as dictated by the latchup condition discussed earlier. Limiting VgE also helps to limit the fault current through Version 2 EE IIT, Kharagpur 9 www.jntuworld.com
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the device. If a short circuit fault occurs in the load resistance RL (shown in the inset of Fig 7.4(a)) the fault load line is given by CF. Limiting vgE to vgE6 restricts the fault current corresponding to the operating point F. Most IGBTs are designed to with stand this fault current for a few microseconds within which the device must be turned off to prevent destruction of the device. It is interesting to note that an IGBT does not exibit a BJTlike second break down failure. Since, in an IGBT most of the collector current flows through the drive MOSFET with positive temperature coefficient the effective temperature coefficient of vCE in an IGBT is slightly positive. This helps to prevent second break down failure of the device and also facilitates paralleling of IGBTs.
Exercise 7.2
Fill in the blank(s) with the appropriate word(s). i. From the input side the IGBT behaves essentially as a __________________. ii. When the gate emitter voltage is below __________________ no __________________ layer is formed in the p type body region. iii. Electrons arriving through the drive MOSFET causes __________________ injection from the __________________ to the drain drift region. iv. In an IGBT most of the collector current flows through the __________________ and not through the __________________. v. When the gateemitter voltage of an IGBT is below threshold if operates in the __________________ region. vi. In the active region of operation the collector current of an IGBT is determined by the __________________ characteristics which is reasonably __________________ over most of the collector current range. vii. For the same load resistance as the vgE of an IGBT is increased it enters __________________ region. viii. The forward voltage drop of an IGBT in the saturation region remains approximately __________________. ix. An IGBT has small __________________ temperature coefficient of on state voltage drop. x. An IGBT does not exhibit __________________ failure mode.
Answers: i) MOSFET; ii) threshold, inversion; iii) hole, collector; iv) MOSFET, BJT; v) cutoff; vi) transfer, linear; vii)saturation; viii) constant; ix) positive; x) second break down.
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iD DF C E (b)
G Q1
+ VCE
D CGD G CgE S E
The switching waveforms of an IGBT is, in many respects, similar to that of a Power MOSFET. This is expected, since the input stage of an IGBT is a MOSFET as shown in Fig 7.5(b). Also in a modern IGBT a major portion of the total device current flows through the MOSFET. Therefore, the switching voltage and current waveforms exhibit a strong similarity with those of a MOSFET. However, the output pnp transistor does have a significant effect on the switching characteristics of the device, particularly during turn off. Another important difference is in the gate drive requirement. To avoid dynamic latch up, (to be discussed later) the gate emitter voltage of an IGBT is maintained at a negative value when the device is off.
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Vgg VgE
VgE(th)
2 = Rg(CGS+CGD2)
VgE(th) VgE,IL
VgE,IL
VCE(sat)
VCC t
iC iD IL IL tfv2
IL
IL tfi2 t
trv1
trv2
tfi1
The switching waveforms of an IGBT is shown in Fig 7.6. Similarity of these waveforms with those of a MOSFET is obvious. To turn on the IGBT the gate drive voltage changes from Vgg to +Vgg. The gate emitter voltage vgE follows Vgg with a time constant 1. Since the drain source voltage of the drive MOSFET is large the gate drain capacitor assumes the lower value CGD1. The collector current ic does not start increasing till vgE reaches the threshold voltage vgE(th). Thereafter, ic increases following the transfer characteristics of the device till vgE reaches a value vgEIL corresponding to ic = iL. This period is called the current rise time tri. The free wheeling diode current falls from IL to zero during this period. After ic reaches IL, vgE becomes clamped at vgE IL similar to a MOSFET. vCE also starts falling during this period. First vCE falls rapidly (tfv1) and afterwards the fall of vCE slows down considerably. Two factors contribute to the slowing down of voltage fall. First the gatedrain capacitance Cgd will increase in the MOSFET portion of the IGBT at low drainsource voltages. Second, the pnp transistor portion of the IGBT traverses the active region to its on state more slowly than the MOSFET portion of the IGBT. Once the pnp transistor is fully on after tfv2, the on state voltage of the device settles down to vCE(sat). The turn ON process ends here. The turn off process of an IGBT follows the inverse sequence of turn ON with one major difference. Once vgE goes below vgE(th) the drive MOSFET of the IGBT equivalent circuit turns off. During this period (tfi1) the device current falls rapidly. However, when the drive MOSFET turns off, some amount of current continues of flow through the output pnp transistor due to stored charge in its base. Since there is no reverse voltage applied to the IGBT terminals that could generate a negative drain current, there is no possibility for removing the stored charge by carrier sweepout. The only way these excess carriers can be removed is by recombination within the IGBT. During this recombination period (tfi2) the remaining current in the IGBT decays relatively slowly forming a current fail. A long tfi2 is undesirable, because the power dissipation Version 2 EE IIT, Kharagpur 12
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in this interval will be large due to full collectoremitter voltage. tfi2 can be reduced by decreasing the excess carrier life time in the pnp transistor base. However, in the process, on state losses will increase. Therefore, judicious design trade offs are made in a practical IGBT to give minimum total loss. The gate drive circuit of an IGBT should ensure fast and reliable switching of the device. In particular, it should.
Apply maximum permissible VgE during ON period. Apply a negative voltage during off period. Control dic dt during turn ON and turn off to avoid excessive Electro magnetic interference (EMI). Control dvce dt during switching to avoid IGBT latch up. Minimize switching loss. Provide protection against short circuit fault.
Detailed discussion on IGBT gate drive circuit is beyond the scope of this lesson. References [4] & [5] provide good discussion on this subject. Fig 7.7(a) shows a simplified IGBT gate drive circuit. +Vcc RC +Vgg Ri Vi (Logic level) Opto isolator + RB
Q1 Q2
IGBT
E Level Shifting Vgg Comparator RB 1 +1 Vcc Totem pole gate drive amplifier
(a)
R G Vgg
R Vgg
RB 2 +1
(b)
Fig. 7.7: IGBT gate drive circuit (a) Gate drive (b) Equivalent circuit of the gate drive during turn on and turn off.
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The logic level gate drive signal is first optoisolated and fed to a level shifting comparator. This stage converts the unipolar (usually positive) out put voltage of the optoisolator to a bipolar (Vgg) signal compatible to the IGBT gate drive levels. The output of the comparator feeds a totem pole output amplifier stage which drives the IGBT. The equivalent circuit of the gate drive during turn on and off are shown in Fig 7.7(b). If VCC > Vgg then both Q1 and Q2 will operate in the active region and reasonably constant value of 1 & 2 of these two transistors can be used for analysis purpose. These equivalent circuits along with the model of the IGBT input MOSFET can be used to analyze the switching performance of the device. Conversely, for a desired switching performance a suitable gate drive circuit can be designed.
Prevent break down of the gate oxide insulation. Restrict collector current to ICM.
Collector leakage current (ICES): This is the leakage collector current during off state of the device at a given junction temperature. This is usually specified at VgE = 0V and vCE = VCES. Gateemitter leakage current (IGES): Usually specified at vCE = 0V & vgE = vgES. Collector emitter saturation voltage (VCE(sat)): This is specified at a given junction temperature, gateemitter voltage and collector current. For more detailed data the output characteristics of the device for different vgE and expanded near the saturation zone is also provided. Gateemitter threshold voltage (vgE(th)): It is specified at a low collector emitter voltage and collector current. Forward Transconductance (gfs): This is again specified at a low value of vCE. For more detailed data the transfer characteristics of the device (ic vs vgE) is also provided.
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Input, output and transfer capacitances (Cies, Coes & Cres): These are, gateemitter, collectoremitter and gatedrain capacitances of the device respectively, specified at a given collectoremitter voltage. Variation of these parameters as functions of vCE are also supplied. Switching times (td(ON) tri, tfv, trv, tfi): These times are specified for inductive load switching as functions of gate charging resistance and collector current. In addition turn on and turn off energy losses per switching operation are also specified. Maximum total power dissipation (Ptmax): This is the maximum allowable power lass in the device (both switching and conduction) on a continuous basis at a given case temperature. Derating curve at other temperatures are also specified.
The IGBT has robust SOA both during turn on and turn off. Fig 7.8 (a) shows the FBSOA. On the left side it is restricted by the forward voltage drop characteristics. Up to maximum continuous collector current this voltage remains reasonably constant at a low value. However, at ICM this voltage starts increasing as the IGBT starts entering active region. On the top the FBSOA is restricted by ICM. iC ICM IC 105sec 104sec 103sec 102sec DC VCES VCE iC ICM 1000V/S 2000V/S 3000V/S
(a)
(b)
VCES
VCE
Fig. 7.8: Safe operating area of an IGBT (a) FBSOA; (b) RBSOA.
The other two limits are formed by the maximum power dissipation limit and the maximum forward voltage limit. Like other devices the maximum power dissipation limit increases with reduction in the on pulse width. The RBSOA for low values of dvCE dt is rectangular. However, for increased dvCE dt the upperright hand corner is progressively cut out. The reason for this restriction on the RBSOA is to avoid dynamic latch up. The device user can easily control dvCE dt by proper choice of Vgg and the gate drive resistance.
Exercise 7.3
Fill in the blank(s) with the appropriate word(s). i. In a modern IGBT most of the collector current flows through the _________________ and not the _________________. Version 2 EE IIT, Kharagpur 15
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ii. iii.
To avoid _________________ the gate emitter voltage of an IGBT is maintained at a _________________ value when the device is off. During turn on of an IGBT the rate of fall of voltage slows down towords the end since the output pnp transistor traverses its _________________ region more _________________ compared to the drive MOSFET. During turn off of an IGBT a _________________ is formed due to excess stored charge in the _________________ region of the output pnp transistor. The gate drive circuit of an IGBT should control _________________.
dvCE dt
dic dt
iv. v.
to avoid excessive
vi.
of an IGBT during turn off should be controlled to prevent _________________ of the device. A specified maximum gate emitter voltage of an IGBT helps to limit the collector current during _________________ fault. Collector emitter saturation voltage of an IGBT _________________ with increasing gateemitter voltage. The FBSOA of an IGBT is similar to that of a _________________ except that the on state voltage drop is much _________________. The upper right hand corner of the IGBT RBSOA is gradually cut out with increasing _________________ to avoid _________________ of the device.
Answer: (i) MOSFET, BJT; (ii) latch up, negative; (iii) active, slowly; (iv) current tail, base; (v) EMI; (vi) Latch up; (vii) short circuit; (viii) decreases; (ix) MOSFET, lower; (x) dvCE dt , latch up.
Reference
[1] [2] [3] B. Jayanta Baliga, Evolution of MOS Bipolar Power Semiconductor Technology, Proceedings of the IEEE, vol. 76, No. 4, April 1988, pp 409418. Power electronics, Converters, Applications and Design, Mohan, Undeland, Robbins; John Wiley & Sons, 2003 B. Jayanta Baliga et. al, The Insulated Gate Transistor: A new ThreeTerminal MOSControlled Bipolar. Power Device, IEEE transaction on Electron Devices, vol. ED31, No. 6 June 1984 pp 421828. Allen R. Hefner, An Investigation of the drive circuit requirements for the Power Insulated Gate Bipolar Transistor, IEEE Transactions on Power Electronics. Vol. 6 No. 2. April 1991.
[4]
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[5] [6]
Carmelo Licitra et. al, A New Driving circuit for IGBT Devices, IEEE Transaction on Power Electronics, Vol. 10, No3 may 1995. SEMIKRON Power Electronics News 2001, SEMIKRON International, Germany.
Lesson Summary
IGBT is a hybrid device which combines the advantages of MOSFET and BJT. An IGBT is formed by adding a p+ collector layer on the drain drift layer of a Power MOSFET. Punch through IGBT has a thin n+ buffer layer between the p+ collector layer and ndrain drift layer. They have significantly lower conduction loss. The IGBT cell structure embeds a parasitic thyristor in it. Latching up of this thyristor is prevented by special structuring of the body region and increasing the effectiveness of the body shorting. From the operational point of view an IGBT is a voltage controlled bipolar device. The operational equivalent circuit of an IGBT has an n channel MOSFET driving a pnp BJT. Like other semiconductor devices on IGBT can also operate in the cut off active and saturation regions. When the gateemitter voltage of an IGBT is below threshold it operates in the cut off region. For a given load resistance the operating point of an IGBT can be moved from cut off to saturation through the active region by increasing the gateemitter voltage. In the active region, the collector current of an IGBT is determined by the gateemitter voltage which can be limited to a given maximum value to limit the fault current through the device in the event of a load short circuit. The IGBTs have a slightly positive temperature coefficient of the onstate voltage drop which makes paralleling of these devices simpler. An IGBT does not exhibit second break down phenomena as in the case of a BJT. The switching characteristics of an IGBT is similar to that of a MOSFET. To avoid dynamic latch up of the parasitic thryrstor in an IGBT, the gate emitter voltage of the device is maintained at a negative value during its off period. During turn off, the collector current of an IGBT can exhibit current tailing due to stored base change in the base region of the output pnp transistor. The forward bias SOA of an IGBT is similar to that of a MOSFET except the on state voltage drop being much lower. The maximum allowable collector current in an IGBT is restricted by the static latch up consideration. Version 2 EE IIT, Kharagpur 17
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CE The RBSOA of an IGBT is rectangular for low values of dt . For higher dvCE dt the upper right half corner of the RBSOA is progressively cutout to prevent dynamic latch up of the device.
dv
The IGBT can switch at moderately high frequency (<20 kHZ) and in this range is likely to replace the BJTs in all medium to high power applications.
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Q1. Q2.
What effects do the width and doping level of the drain drift region of an IGBT have on its performance. (a) In an IGBT a major portion of the collector current flow through the driver MOSFET section which has a voltage rating almost same as the device. Then how does the on state voltage drop of an IGBT remain low compared to an equivalent MOSFET? (b) An IGBT is used to switch a resistive load of 5 from a DC supply of 350 volts as shown in the inset of Fig 7.4 (a). The ON state gate voltage is vgE = 15v. For the IGBT, vgE (th) = 4 volts and gts = 25. Find out the maximum current flowing through the IGBT in the event of a short circuit fault across the load. Also find out the power dissipation inside the device.
What do you under stand by dynamic latch up of an IGBT. How can it be prevented? What steps are taken in the cell structure design of an IGBT to minimize the tail current during turn off operation. In the basic gate drive circuit of an IGBT shown in Fig 7.7 (a) following data are given Vgg = 15 V, Vcc = 20 V, 1 for Q1 = 50, 2 for Q2 = 50. RB = 2.2 K, R = 30, VgE (th) of IGBT = 4V, gfs = 40 CgE = 4nF, CgD = 500pF,
The IGBT is used to switch a clamed inductive load of 50 Amps from a 400 volts supply. Find out maximum values of
dic dt
and
dvCE dt
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The width and doping level of the drain drift layer of an IGBT affects the performance of the IGBT in several ways. They determine the forward break down voltage of the IGBT. Referring to Fig 7.2 (b), the drain drift region constitutes the base of the upper pnp transistor. The width and the doping level of this layer determines the current gain of this transistor. This is intentionally kept low so that most of the device current flows through the MOSFET and not the output pnp transistor collector. This helps to reduce the voltage drop across the body spreading resistance between the base and emitter of the lower pnp transistor. Thus the possibility of turning on this transistor and consequent latch up of the device is minimized. Since the major part of the device current flows through the MOSFET which has a positive temperature coefficient of drain source voltage drop, the collectoremitter voltage drop across the device exhibits a slightly positive temperature coefficient. This eliminates the possibility of second break down failure in IGBTs and simplifies paralleling of these devices.
2. (a) The total voltage drop across a conducting IGBT has three components. The voltage drop across the emitterbase junction of the output pnp transistor follows the usual exponential low of a pn junction. The next component of the voltage drop is due to the drain drift region resistance. In a normal high voltage MOSFET this component of the voltage drop is large due to lower doping level (necessary for blocking high voltage) of this region. However, in a conducting IGBT electrons arriving at the drain drift region through the MOSFET channel causes large minority carrier injection from the p+ collector. The consequent conductivity modulation reduces the resistance (and hence the voltage drop) in this region. The third component of the IGBT voltage drop occurs across the channel of the driving MOSFET and is same as that of an equivalent high voltage MOSFET. Therefore, the reduced voltage drop across a conducting IGBT is due to reduction of the drain drift region resistance by conductivity modulation. (b) In the event of a short circuit across the load the voltage across the device will be 350 volts and the IGBT will operate in the active region. In this region
iC = gfs ( vgE  vgE (th) )
PD = vCE iC
Max
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3.
Static latch up in an IGBT occurs when the continuous ON state current exceeds a critical value. However, under dynamic conditions, when the IGBT is switching from on to off state if may latch up at drain current less than this value. During turn off, the voltage across the driver MOSFET increases rapidly. This voltage is blocked by the drainbody pn junction. To block the rapid build up of the voltage the width of the depletion region in the drain drift layer also increases rapidly. This rapid increase in the depletion layer width temporally increases the current gain of the output pnp transistor and causes latch up of the device at a lower collector current than would have been necessary for static latch up. Punch Through and Nonpunch through IGBTs solve the problem of tail current by two different approaches. Punch through IGBT s attempt to minimize the current tailing problem by shortening the duration of the tailing time. This is done by reducing the excess carrier life time in the n+ buffer layer compared to the n drain drift layer. This n+ buffer layer acts as a sink for excess holes and greatly enhances the removal rate of holes from the drain drift layer. Thus the tail time is reduced. Non punch through IGBTs attack the current tailing problem by minimizing the magnitude of the current during the failing interval. This is done by designing the IGBT so that the MOSFET section carries as much of the total current as possible. Newer NPT IGBT designs have more than 90% of the total current carried by the MOSFET section of the device.
4.
5.
During turn on and turn off the IGBT passes through the active region. When vgE is greater than vgE(th) the collector current is given by
But from the equivalent circuit of the IGBT gate drive circuit during turn on
) )
In the active region Vgg >> vgE Also since Vcc > Vgg, Q1 & Q2 operates in the active region. Substituting the given values
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dic 40 15 = = 1.82 109 A/Sec 12 2200 dt 4500 10 ( 30 + 51 ) dic Since 1 = 2 , during turn off will also have the same value dt dic = 1.82 A/ns So dt Since load current is 50 Amps and gfs = 40
V  v IL dvCE = ig IL = gg gE RB dt R+ +1
dvCE during turn ON is dt Vgg  vgE IL dvCE 15  5.25 = = RB dt 500 1012 ( 30 + 2200 CgD R + +1 51 )
Since Vgg+ =Vgg and 1 = 2 dvCE during turn off will be same dt So
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Module 1
Power Semiconductor Devices
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Lesson 8
Hard and Soft Switching of Power Semiconductors
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Conduction Losses
Conduction losses are caused by the forward voltage drop when the power semiconductor is on and can be described by (with reference to an IGBT)
Fig. 3.1 Approximate forward voltage of IGBT and diode WC = Vce (sat)(Ic).Ic where Ic is the current carried by the device and Vce(sat)(Ic) is the current dependant forward voltage drop. This drop may be expressed as Vce (sat) (Ic) = V0 + R . Ic This relation defines the forward drop of an IGBT in a similar manner to a diode. A part of the drop is constant while another part is collector current dependent. The given data should be used as follows: Using the numerical value is the most simple way to determine conduction losses. The numerical value can be applied if the current in the device is equal or close to the specified current  data sheet numerical values are specified for typical application currents. The graph most accurately determines conduction losses. The conditions in which the data are used should correspond to the application. To estimate if a power semiconductor rating is appropriate, usually the values valid for elevated temperature, close to the maximum junction temperature TJmax , should be used to calculate power losses because this is commonly the operating point at nominal load. Version 2 EE IIT, Kharagpur www.jntuworld.com 4
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Blocking Losses
Blocking losses are generated by a low leakage current through the device with a high blocking voltage. WB = Vb(I).IL Where IL is the leakage current and Vb(I) is the current dependemt blocking voltage. Data sheets indicates leakage current at certain blocking voltage and temperature. The dependence between leakage current and applied voltage typically is exponential; this means that using a data sheet value given for a blocking voltage higher than applied overestimates blocking losses. However in general, blocking losses are small and can often, but not always, be neglected.
Switching Losses
IGBTs are designed for use in switching converters and not for linear operation. This means switching time intervals are short compared to the pulse duration at typical switching frequencies, as can be seen from their switching times, such as rise time tr and fall time tf in the data sheets. Switching losses occur during these switching intervals.
Fig. 3.2 Switching losses (appx) For IGBTs they are specified as an amount of energy, Eon/off for a certain switching operation. Eon/off are the energy dissipated at turnon/turnoff respectively. Using the numerical value is again the most simple way to determine switching losses. The numerical value can be applied if the switching operations are carried out at the same or similar conditions as indicated in the data sheet. Graphs for Eon(IC)/(RG ), Eoff (IC)/(RG) with collector current IC and gate resistance RG are provided. The graphs permit the most accurate determination of switching losses, given the parameters of the converter: RG and converter current IC.
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Diode
A surge voltage occurs when the freewheel diode recovers. Consider a converter leg. The lower device is off and that the load current is circulating through the freewheeling diode of the upper device. Now if the lower device turns on, the current in the freewheel diode of the upper device decreases during the overlap period and the load current begins to commutate to the lower device. It becomes negative during reverse recovery of the upper freewheel diode. When the freewheel diode recovers, the current in the circuit associated to the diode jumps to zero. The parasitic line inductance Lp develops a surge voltage equal to Lp di/dt in opposition to the decreasing current. This di/dt is dictated by the recovery characteristic of the freewheel diode. Fast recovery snappy diodes can develop very high recovery di/dt when they are hard recovered by the rapid turnon of a device in series with it in the same converter leg. These diodes take a smaller time to quench the reverse recovery current compared to a soft recovery diode. The offstate losses of the main device and the turnon dissipation may be neglected for most cases. With an IGBT driven DCDC chopper as an example, the dissipation can be estimated as: IGBT dissipation = Conduction losses + Switching losses = [ .Vce(sat)Ic] +[fc(Eon + Eoff)] Watts Diode dissipation = Conduction losses + Reverse recovery losses = [ (1  FVF]+ [fc Err] where, is the conduction duty ratio, fc the switching frequency and Eon , Eoff , Err are the respective energy losses, Fig 3.2, data for which is provided by the device manufacturer. The values of Eon , Eoff , Err are at the rated values only and have to be adjusted to the working values of voltage (DC bus), VCE (working) and load current, Ic.
Eon / Eoff / Err ( working ) = Eon / Eoff / Err ( working ) VCE ( working ) / VCE ( rated )
a/b/c
The power device in a converter mostly sees an inductive load. A simple circuit illustrating such a situation is shown in Fig. 3.3. Corresponding ideal waveforms are also indicated. The freewheeling diode FWD, across the load is essential for clamping the induced voltages across the inductance when the device switches off. However, its presence causes the supply voltage, Vs to appear across the transistor whenever it carries part of the inductor current in overlap mode with the FWD during both turnon and turnoff modes. This causes the transistor switching dissipation to increase.
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Fig. 3.3 Typical current and voltage transients during turnon and turnoff of a clampedinductive load and transitions in the VI plane.
An RCD Switchingaidnetwork connected across the device reduces turnoff dissipation, Fig. 3.2. The controlled rise of the collector voltage of the transistor aids this process. However, turnoff energy is accumulated in the SAN, which is ultimately dissipated in the resistor. The RCD does not also help reduce turnon dissipation when the reverse recovery current of the diode and the SAN current add up with the load current with Vs again appearing across the device. Example 3.1 Derive the expression for the power dissipation during turnon and turnoff of a transistor unassisted by a SAN. The supply voltage is Vm, peak load current Im, and tr, toff being the turn on and turnoff times. Assume idealised waveforms. Solution The transition of the swichings in the VC  IC plane is rectangular. The energy dissipated in each turnoff switching cycle is
t off 1 W = VT . I T dt = .V .I .t 0 T 2 M M f
If actual waveforms are considered the dissipation is close to about double the above figure. The dissipation at turnon is, similarly 1/2. VM.I M.ton.
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Fig. 3.4 Current and voltage waveforms at the Main Terminals of the switch with an RCD SAN, and in the associated FWD and SAN diode Example 3.2
For a transistor carrying a collector current IM and having a turnoff time tf, find the details of a RCD SAN to restrict the voltage rise at the end of tf to half the supply voltage. Calculate the corresponding losses in the transistor and in the SAN.
Solution
The action of the SAN in restricting the rise of transistor voltage till the current in it is extinguished is illustrated in Fig. 3.4. Since the current is assumed to fall linearly during the period tf, the collector voltage rises as:
t I .t t V = V0 = M f t 2C tf f Where V0 is the voltage at the capacitor at the end of turnoff time tf. Thus,
2 2
2C t i = I M 1 t f The Transistor current can be written as: The dissipation in the transistor is
WT = v.idt =
0 tf tf 2 IM .t f t 1 2C t f
V0 =
IM t f
t tf
2 2 IM .t f 1 dt = . Watts 2C 12
When the transistor switches off, the nearly constant load current linearly charges up the capacitor till it reaches the supply voltage. Subsequently, The FWD is positively biased and there Version 2 EE IIT, Kharagpur
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is a short period of overlap between the FWD and the SAN diode. During this period, the capacitor overcharges to some extent. If V0 is the capacitor voltage when the transistor current is extinguished,
CV0 = i.dt =
t1 t2
1 IMt f 2
The energy dissipated in the SAN resistor which is also the energy shifted to the SAN from the transistor during turnoff is
1 2 CVM F 2 Where F is the switching frequency. The resistance should be able to limit the transistor current to its peak rating. Thus, PR =
R Vs I M I rr
I CM
Irr is the reverse recovery current of the FWD. If the capacitor has to discharge completely during the ON time,
C I M .t f Vs R.I M
In a SinePWM controlled converter with a peak value of the fundamental current equal to Icp, the conduction losses in the IGBT would be
Wc = .T I cVce ( sat ) d
0
2 2 2 =1 I cpVo + I cp .R 2 .T
Where Vo and R are as shown in Fig 3.1. For the diode the dissipation is
WF = 1 2 [1 ]. 2 2 I cpVod + I cp Rd 2
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Soft switching
Fig. 3.5 Basic topologies for a) Hard switch, b) Zerovoltage switch and c) for a Zero current switch
Hard switching and its consequences have been discussed above. Reduction of size and weight of converter systems require higher operating frequencies, which would reduce sizes of inductors and capacitors. However, stresses on devices are heavily influenced by the switching frequencies accompanied by their switching losses. It is obvious that switchingaidnetworks do not mitigate the dissipation issues to a great extent. Turnon snubbers though not discussed, are rarely used. Even if used, it would not be able to prevent the energy stored in the junction capacitance to discharge into the transistor at each turnon. Soft switching techniques use resonant techniques to switch ON at zero voltage and to switch OFF at zero current. There are negligible switching losses in the devices, though there is a significant rise in conduction losses. There is no transfer of dissipation to the resonant network which is nondissipative. The two basic configurations are as shown in Fig. 3.5.
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The switching trajectory in the voltagecurrent plane of a device is illustrated in Fig. 3.6 comparing the paths for that of a Hardswitched operation without any SAN, a Hardswitched with a RCD SwitchingAidNetwork and a resonant converter. It is indicatve of the stresses and losses. A designer would prefer the path to be as close as possible to the origin. A Zero Current Switch based converter is provided as illustration to the soft switching mechanism. It is equivalent to the topology shown above. The input capacitor and the one across the diode may be combined to arrive at this topology.
The ZCS converter is considered to be in stable operation with Load current Itrans flowing through the diode and the inductor Lf. The Capacitor Cr is charged to Vs. On switching the transistor ON the current in it ramps up from zero but the diode continues conduction till this current reaches the load current Iout level. Subsequently, the load current and the resonating current flows through the transistor. This current reaches a natural zero when the negative magnitude of the resonating current equals the load current. The transistor thus switches in the Zero Current mode for both turn on and turn off. The diode, on the other hand switches in the Zero Voltage mode under both situations. It must be noted that the peak current stress on the transistor is high . The peak voltage stress on the diode is also about twice the supply voltage. Both these stresses are significantly higher than that in a comparable Hard switched buck converter. Consequently, Version 2 EE IIT, Kharagpur 11
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while switching losses are practically eliminated in this resonant converter, conduction losses increase along with the device stresses. There is no scope of a SANs in resonant switching.
a) b) c) d)
Ans:
c) turnoff losses
Qs#3 Are resonant converters superior to the hard switched converter on all counts? Ans:
No. The resonant converter reduces switching losses at the cost of higher voltage/current stresses on the devices.
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Module 2
AC to DC Converters
Version 2 EE IIT, Kharagpur 1 www.jntuworld.com
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Lesson 9
Single Phase Uncontrolled Rectifier
Version 2 EE IIT, Kharagpur 2 www.jntuworld.com
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Instructional Objectives
On completion the student will be able to Classify the rectifiers based on their number of phases and the type of devices used. Define and calculate the characteristic parameters of the voltage and current waveforms. Analyze the operation of single phase uncontrolled half wave and full wave rectifiers supplying resistive, inductive, capacitive and back emf type loads. Calculate the characteristic parameters of the input/output voltage/current waveforms associated with single phase uncontrolled rectifiers.
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9.1 Introduction
One of the first and most widely used application of power electronic devices have been in rectification. Rectification refers to the process of converting an ac voltage or current source to dc voltage and current. Rectifiers specially refer to power electronic converters where the electrical power flows from the ac side to the dc side. In many situations the same converter circuit may carry electrical power from the dc side to the ac side where upon they are referred to as inverters. In this lesson and subsequent ones the working principle and analysis of several commonly used rectifier circuits supplying different types of loads (resistive, inductive, capacitive, back emf type) will be presented. Points of interest in the analysis will be. Waveforms and characteristic values (average, RMS etc) of the rectified voltage and current. Influence of the load type on the rectified voltage and current. Harmonic content in the output. Voltage and current ratings of the power electronic devices used in the rectifier circuit. Reaction of the rectifier circuit upon the ac network, reactive power requirement, power factor, harmonics etc. Rectifier control aspects (for controlled rectifiers only)
In the analysis, following simplifying assumptions will be made. The internal impedance of the ac source is zero. Power electronic devices used in the rectifier are ideal switches.
The first assumption will be relaxed in a latter module. However, unless specified otherwise, the second assumption will remain in force. Rectifiers are used in a large variety of configurations and a method of classifying them into certain categories (based on common characteristics) will certainly help one to gain significant insight into their operation. Unfortunately, no consensus exists among experts regarding the criteria to be used for such classification. For the purpose of this lesson (and subsequent lessons) the classification shown in Fig 9.1 will be followed.
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9.2 Terminologies
Certain terms will be frequently used in this lesson and subsequent lessons while characterizing different types of rectifiers. Such commonly used terms are defined in this section. Let f be the instantaneous value of any voltage or current associated with a rectifier circuit, then the following terms, characterizing the properties of f, can be defined. ) : As the name suggests f = f max over all time. Peak value of f ( f Average (DC) value of f(Fav) : Assuming f to be periodic over the time period T 1 T Fav = f(t)dt .(9.1) T 0 RMS (effective) value of f(FRMS) : For f , periodic over the time period T, 1 T 2 FRMS = f (t)dt ..(9.2) T 0 Form factor of f(fFF) : Form factor of f is defined as F f FF = RMS . (9.3) Fav Ripple factor of f(fRF) : Ripple factor of f is defined as
f RF = FRMS  Fav Fav
2 2
= f FF 1 .(9.4)
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Ripple factor can be used as a measure of the deviation of the output voltage and current of a rectifier from ideal dc.
( )
Fundamental component of f(F1): It is the RMS value of the sinusoidal component in the Fourier series expression of f with frequency 1/T. 1 2 2 f A1 + f B1 ....(9.6) F1 = 2 T 2 where f A1 = f ( t ) cos 2 t dt (9.7) T T 0 2 T f B1 = f ( t ) sin 2 t dt .(9.8) T T 0
Kth harmonic component of f(FK): It is the RMS value of the sinusoidal component in the Fourier series expression of f with frequency K/T. 1 2 2 FK = f AK + f BK (9.9) 2 2 T where f AK = f(t) cos2K t T dt ...(9.10) T 0 2 T f BK = f(t) sin2K t T dt (9.11) T 0
Crest factor of f(Cf) : By definition f (9.12) Cf = FRMS Distortion factor of f(DFf) : By definition F DFf = 1 ..(9.13) FRMS Total Harmonic Distortion of f(THDf): The amount of distortion in the waveform of f is quantified by means of the index Total Harmonic Distortion (THD). By definition
Fk THD f = ..(9.14) K=0 F1
K 1 2
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Displacement Factor of a Rectifier (DPF): If vi and ii are the per phase input voltage and input current of a rectifier respectively, then the Displacement Factor of a rectifier is defined as. DPF = cosi (9.16)
Where i is the phase angle between the fundamental components of vi and ii.
Power factor of a rectifier (PF): As for any other equipment, the definition of the power factor of a rectifier is Actual power input to the Rectifier .(9.17) PF = Apparent power input to the Rectifier if the per phase input voltage and current of a rectifier are vi and ii respectively then V I cosi PF = i1 i1 (9.18) ViRMS IiRMS
If the rectifier is supplied from an ideal sinusoidal voltage source then Vi1 = ViRMS I PF = i1 cosi = DFi1 DPF ..(9.19) so, IiRMS In terms of THDii DPF PF = ...(9.20) 2 1+ THDii Majority of the rectifiers use either diodes or thyristors (or combination of both) in their circuits. While designing these components standard manufacturers specifications will be referred to. However, certain terms are used in relation to the rectifier as a system. They are defined next.
Pulse number of a rectifier (p): Refers to the number of output voltage/current pulses in a single time period of the input ac supply voltage. Mathematically, pulse number of a rectifier is given by Time period of the input supply voltage . p= Time period of the minium order harmonic in the output voltage/current. Classification of rectifiers can also be done in terms of their pulse numbers. Pulse number of a rectifier is always an integral multiple of the number of input supply phases. Commutation in a rectifier: Refers to the process of transfer of current from one device (diode or thyristor) to the other in a rectifier. The device from which the current is transferred is called the out going device and the device to which the current is transferred is called the incoming device. The incoming device turns on at the beginning of commutation while the out going device turns off at the end of commutation. Commutation failure: Refers to the situation where the out going device fails to turn off at the end of commutation and continues to conduct current. Firing angle of a rectifier (): Used in connection with a controlled rectifier using thyristors. It refers to the time interval from the instant a thyristor is forward biased to the instant when a gate pulse is actually applied to it. This time interval is expressed in radians by multiplying it with
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the input supply frequency in rad/sec. It should be noted that different thyristors in a rectifier circuit may have different firing angles. However, in the steady state operation, they are usually the same.
Extinction angle of a rectifier (): Also used in connection with a controlled rectifier. It refers to the time interval from the instant when the current through an outgoing thyristor becomes zero (and a negative voltage applied across it) to the instant when a positive voltage is reapplied. It is expressed in radians by multiplying the time interval with the input supply frequency () in rad/sec. The extinction time (/) should be larger than the turn off time of the thyristor to avoid commutation failure. Overlap angle of a rectifier (): The commutation process in a practical rectifier is not instantaneous. During the period of commutation, both the incoming and the outgoing devices conduct current simultaneously. This period, expressed in radians, is called the overlap angle of a rectifier. It is easily verified that + + = radian. Exercise 9.1
Fill in the blank(s) with the appropriate word(s). i) ii) iii) iv) v) vi) vii) In a rectifier, electrical power flows from the _________ side to the ________ side. Uncontrolled rectifiers employ _________ where as controlled rectifiers employ ________ in their circuits. For any waveform Form factor is always _______ than or equal to unity. The minimum frequency of the harmonic content in the Fourier series expression of the output voltage of a rectifier is equal to its _________. THD is the specification used to describe the quality of ___________ waveforms where as Ripple factor serves the same purpose for _________ for waveforms. Input power factor of a rectifier is given by the product of the _________ factor and the ________ factor. The sum of firing angle, Extinction angle and overlap angle of a controlled rectifier is always equal to _________. (iii) greater; (iv) pulse number; (v) ac, dc; (vi)
Answers: (i) ac, dc; (ii) diodes, thyristors; displacement, distortion; (vii)
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Fig 9.2 shows the circuit diagram and the waveforms of a single phase uncontrolled half wave rectifier. If the switch S is closed at at t = 0, the diode D becomes forward biased in the the interval 0 < t . If the diode is assumed to be ideal then For 0 < t v0 = vi = 2 Vi sin t (9.21) vD = vi v0 = 0 Since the load is resistive 2V0 i0 = v0 R = sint ..(9.22) R ii = i0 For t > , vi becomes negative and D becomes reverse biased. So in the interval < t 2 ii = i0 = 0 v0 = i0R = 0...(9.23) vD = vi v0 = vi = 2 Vi sint From these relationships 1 2 1 2Vi .(9.24) V0AV = v 0 d t = 2Vi sintdt = 2 0 2 0 V 1 2 2 VDRMS = 2Vi sin tdt = i ...(9.25) 2 0 2
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It is evident from the waveforms of v0 and i0 in Fig 9.2 (b) that they contain significant amount of harmonics in addition to the dc component. Ripple factor of v0 is given by
VDRM  VDAV 1 2 v0RF = =  4 (9.26) VDAV 2 With a resistive load ripple factor of i0 will also be same.
Because of such high ripple content in the output voltage and current this rectifier is seldom used with a pure resistive load. The ripple factor of output current can be reduced to same extent by connecting an inductor in series with the load resistance as shown in Fig 9.3 (a). As in the previous case, the diode D is forward biased when the switch S is turned on. at t = 0. However, due to the load inductance i0 increases more slowly. Eventually at t = , v0 becomes zero again. However, i0 is still positive at this point. Therefore, D continues to conduct beyond t = while the negative supply voltage is supported by the inductor till its current becomes zero at t = . Beyond this point, D becomes reverse biased. Both v0 and i0 remains zero till the beginning of the next cycle where upon the same process repeats.
From the preceding discussion For 0 t vD = 0 v0 = vi i0 = ii(9.27) for t 2 Version 2 EE IIT, Kharagpur 10
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v0 = 0 i 0 = ii = 0 vD = vi v0 = vi 1 2 1 V0AV = v0 dt = 2Vsin tdt (9.28) i 2 0 2 0 2Vi 1 cos or V0AV = ... (9.29) 2 1 2 2 V0RMS = 2V sin tdt 2 0 i
Vi 1 V  sin2 = i = 2 2 2
2  sin2 ..(9.30) 2
Form factor of the voltage waveform is V 2  sin2 vOFF = 0RMS = .(9.31) 2 V0AV 2(1 cos) The ripple factor.
v0RF = vOFF 1 =
 1 (9.32)
All these quantities are functions of which can be found as follows. For 0 t dio vi = 2Vsin t = L + Ri0 .(9.33) i dt i0 (t = 0) = i0 (t = ) = 0 The solution is given by
t tan
i 0 = I0 e
R + L ..(9.35)
Putting the initial conditions of (9.33) t 2Vi tan i0 = sin e + sin t ( ) (9.36) Z
2Vi tan i 0 (t = ) = + sin (  ) sine =0 Z
tan
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It can be shown that increases with . From Equation (9.29), V0AV decreases with increasing while V0RMS increases with . Therefore, with increasing (and hence increasing L) the form factor and the ripple factor of v0 worsens. However, the ripple factor of i0 decreases with increasing L. Therefore, in certain applications, where a smooth dc current is of prime importance (e.g. the field supply of a dc motor) this configuration of the rectifier is preferred.
The problem of poor form factor (ripple factor) of the output voltage can be solved to some extent by connecting a capacitor across the load resistance of Fig 9.2 (a). This single phase half wave rectifier supplying a capacitive load is shown in Fig 9.5 (a). Corresponding waveforms are shown in Fig 9.5 (b). If the capacitor was initially discharged the diode D is forward biased when the switch S is turned on at t = 0. The output voltage follows the input voltage. The diode D carries both the capacitor charging current and the load current. At t = the sum of these two currents becomes zero and tends to grow in the negative direction. At this point the diode becomes Version 2 EE IIT, Kharagpur 12
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reverse biased and disconnects the load (along with the capacitor) from the supply. The capacitor then discharges with the load current. Diode D does not become forward biased till the input supply voltage becomes equal to the capacitor voltage in the next cycle at t = (2 + ). The same process repeats thereafter.
v0 = vi = 2V1sint ..(9.38) dv v ii = i c + i0 = c 0 + 0 dt R
or
ii = 2Vi [ RCcost + sint ] R 1 2Vi ( 2 2 2 2 ) = 1+ R C cos(t  ) ..(9.39) R 1 1 where = tan RC
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At t = + 2, ii = 0 so = /2 or = + /2 1 1 or = + tan .(9.40) 2 RC Again for t 2 + dv v ii = 0, C 0 + 0 = 0, v 0 ( t = ) = 2Vi cos . dt R (t) tan v 0 = 2Vi cos e ..(9.41) at
t = 2 + , v0 = 2Vsin i
2Vi sin = 2Vi cos e
(2 +  ) tan 2
or sin = cos e
(
3 + ) tan 2
From which can be solved. Peak to peak ripple in v0 is 0pp = 2Vi (1 sin) .(9.43) v
1. Fill in the blank(s) with the appropriate word(s). i) ii) iii) iv) v) The ripple factor of the output voltage and current waveforms of a single phase uncontrolled half wave rectifier is ____________ than unity. With an inductive load, the ripple factor of the output __________ of the half wave rectifier improves but that of the output __________ becomes poorer. In both single phase half wave and full wave rectifiers the form factor of the output voltage approaches _________ with capacitive loads provided the capacitance is ________ enough. The PIV rating of the rectifier diode used in a single phase half wave rectifier supplying a capacitive load is approximately ________ the __________ input supply voltage. The % THD of the input current of the rectifiers supplying capacitive loads is __________.
Answers: (i) greater; (ii) current, voltage; (iii) unity, large; (iv) double, peak; (v) high.
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2. An unregulated dc. power supply of average value 12 V and peak to peak ripple of 20% is to be designed using a single phase half wave rectifier. Find out the required input voltage, the output capacitance and the diode RMS current and PIV ratings. The equivalent load resistance is 50 ohms.
Answer:
Vi = 9.33V
0.818 = cos e (5.67  ) tan or 0.818 e = cos From which 2.035 1 tan = = 0.03553, R = 50, C = 1790 F RC PIV of the diode = 2 2Vi = 26.4V .
RMS. Diode current = V 1 2 1 92.035 2 2 2 2 ii dt = i 2 (1+ R C ) cos (t  )dt 2 R 2 54.9o 1  1 1 = 7.432 + sin2(  )  sin2(  ) = 0.8564 Amps. 2 2 4 4
(3 2 +  ) tan
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Fig 9.6 shows the circuit diagram and waveforms of a single phase split supply, uncontrolled full wave rectifier supplying an R L load. The split power supply can be thought of to have been obtained from the secondary of a center tapped ideal transformer (i.e. no internal impedance). When the switch is closed at the positive going zero crossing of v1 the diode D1 is forward biased and the load is connected to v1. The currents i0 and ii1 start rising through D1. When v1 reaches its negative going zero crossing both i0 and ii1 are positive which keeps D1 in conduction. Therefore, the voltage across D2 is vCB = v2  v1 . Beyond the negative going zero crossing of vi, D2 becomes forward biased and the current i0 commutates to D2 from D1. The load voltage v0 becomes equal to v2 and D1 starts blocking the voltage vAB = v1  v2 . The current i0 however continues to increase through D2 till it reaches the steady state level after several cycles. Steady state waveforms of the variables are shown in Fig 9.6 (b) from t = 0 onwards. It should be noted that the current i0, once started, always remains positive. This mode of operation of the rectifier is called the Continuous conduction mode of operation. This should be compared with the i0 waveform of Fig 9.3 (b) for the half wave rectifier where i0 remains zero for some duration of the input supply waveform. This mode is called the discontinuous conduction mode of operation. From the above discussion For 0 t < v0 = v1 i0 = ii1....(9.45) for t < 2 v0 = v2 i0 = ii2........(9.46) Since v0 is periodic over an interval 1 2Vi 2 2Vi ..(9.47) V0AV = v 0 dt = sintdt = 0 0 1 2 2 V0RMS = 2V sin t dt = Vi ........(9.48) 0 i V .(9.49) v 0FF = 0RMS = V0AV 2 2
8 v 0RF = v 1 = ..(9.50) 2 2 Both the form factor and the ripple factor shows considerable improvement over their half wave counter parts.
2 0FF
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The single phase full wave rectifier still does not offer a smooth dc voltage. With resistive load, considerable ripple current will flow into the load. This problem can be solved by connecting a capacitor across the load resistance just as in the case of a half wave rectifier. If the capacitor was initially discharged, the diode D1 is forward biased when the switch S is turned on at t = 0. The diode D2 remains reverse biased. The output voltage follows the input voltage. D1 carries both the capacitor charging current and the load current. At t = the sum of these two currents becomes zero and tends to grow in the negative direction. At this point the diode D1 becomes reverse biased and disconnects the load along with the capacitor from the supply. The capacitor then discharges through the load until at t = + , v2 becomes greater than v0 and forward biases D2. D1 now remains reverse biased. D2 conducts up to t = + . The same process repeats thereafter. From the discussion above For + t +
v0 = v2 =  2Vsin t i dv v ii2 = i c + i 0 = C 0 + 0 (9.51) dt R 2Vi [ RCcost + sint ] or ii2 = R 1 1 2Vi ( 1 2 2 2 2 ) .(9.52) = 1+ R C cos ( +  t ) where = tan RC R 1 1 at t = + , ii1 = 0 so  = or = + or = + tan (9.53) 2 2 2 RC
Again for t + dv v ii1 = 0 C 0 + 0 = 0 v0 ( t = ) = 2Vsin = 2Vi cos .(9.54) i dt R
v 0 = 2Vi cos e
( t ) tan
.(9.55)
at t = + ,
v0 = 2sin
+   ) tan ( 2
+  ) tan ( 2
From which can be solved. Peak to peak ripple in v0 is 0pp = 2Vi (1 sin) .(9.57) v
0pp given by Equation (9.57) is smaller than that It can be shown that for the same R and C, v
given by Equation (9.43) for the half wave rectifier. The diode PIV ratings remain equal to 2 2Vi however.
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Exercise 9.3
1. Fill in the blank(s) with the appropriate word(s). i) ii) iii) The output voltage form factor of a single phase full wave rectifier is ___________. The output voltage of a single phase full wave rectifier supplying an inductive load is ___________ of the load parameters. The peak to peak output voltage ripple of a single phase split supply full wave rectifier supplying a capacitive load is ___________ compared to an equivalent half wave rectifier.
Answers: (i)
2 2
2. An unregulated dc power supply is built around a single phase split supply full wave rectifier using the same input voltage and output capacitor found in the problem 2 of Exercise 9.2. The load resistance is 50 . Find out the average output voltage, the peak to peak ripple in the output voltage and the RMS current ratings of the diodes.
Answer: From the given data C = 1790 F, R = 50 , = 2.035 From equation 9.56 Sin = cos e(/2 + ) tan
= 0.946316 e Or sin = 0.99937 e From which = 65.33 Vi = 9.33 volts. opp = 2Vi (1 sin ) = 1.20 volts. v V0AV = V0Max 
0.03553(1.5353+ )
0.03553
opp v = 2Vi  0.6V = 13.2  0.6V = 12.6V . 2 % ripple = 9.5% V 1 2+ 2 1 2 2 2 2 ii dt = i 2 (1+ R C ) cos (t  )dt RMS diode current = 2 R 2 1  1 = 7.432  sin2(  ) = 0.533 Amps. 2 2 4
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The split supply full wave single phase rectifier offers as good performance as possible from a single phase rectifier in terms of the output voltage form factor and ripple factor. They have a few disadvantages however. These are
They require a split power supply which is not always available. Each half of the split power supply carries current for only one half cycle. Hence they are underutilized. Version 2 EE IIT, Kharagpur 22
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The ratio of the required diode PIV to the average out put voltage is rather high.
These problems can be mitigated by using a single phase full bridge rectifier as shown in Fig 9.8 (a). This is one of the most popular rectifier configuration and are used widely for applications requiring dc. power output from a few hundred watts to several kilo watts. Fig 9.8 (a) shows the rectifier supplying an RLE type load which may represent a dc. motor or a storage battery. These rectifiers are also very widely used with capacitive loads particularly as the front end of a variable frequency voltage source inverter. However, in this section analysis of this rectifier supplying an RLE load will be presented. Its operation with a capacitive load is very similar to that of a split supply rectifier and is left as an exercise. When the switch S is turned on at the positive going zero crossing of vi no current flows in the circuit till vi crosses E at point A. Beyond this point, D1 & D2 are forward biased by vi and current starts increasing through them till the point B. After point B, vi falls below E and io starts decreasing. Now depending on the values of R, L & E one of the following situations may arise.
io may become zero before the negative going zero crossing of vi at point C. io may continue to flow beyond C and become zero before the point D. io may still be non zero at point D.
It should be noted that if io >0 either D1D2 or D3D4 must conduct. Fig 9.4 (b) shows the waveforms for the third situation. If io >0 at point C the negative going input voltage reverse biases D1 & D2. Current io commutates to D3 and D4 as shown in the associated conduction Diagram in Fig 9.8 (b). It shows pictorially the conduction interval of different devices. The current io continues to decrease up to the point D beyond which it again increases. It should be noted that in this mode of conduction io always remain greater than zero. Consequently, this is called the continuous conduction mode of operation of the rectifier. In the other two situations the mode of operation will be discontinuous. The steady state waveforms of the rectifier under continuous conduction mode is shown to the right of the point t = 0 in Fig 9.4 (b). From this figure and preceding discussion For 0 < t vo = vi = 2Vi sin t ii = io for < t 2 v o =  vi =  2Vi sin t ii =  io
VoAV =
(9.58)
(9.59)
VoRMS
(9.60) (9.61)
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v OFF =
VoRMS = VoAV 2 2
v oRF =
v OFF 1 =
2  8 2 2
(9.62)
Finding out the characterizing quantities for ii will be difficult owing to its complicated waveform. Considerable, simplification is achieved (without significant loss of accuracy) by replacing the actual io waveform by its average value IoAV = VoAV / R. Fig 9.9 shows the approximate input current wave form and its fundamental component.
From Fig 9.9 Displacement angle i = 0 Input displacement factor (DPF) = cos i = 1 I 2 2 Distortion factor (DFil) = il = IoAV Power Factor (PF) = DPF DFil =
% TH Dii = 100
2 2
2  8 2 2
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The exact analytical expression for io (and hence ii) can be obtained as follows. for 0 < t
vi =
2Vi sin t = Ri o +
io
t=0
io
t=
The general solution can be written as  t 2Vi sin i o = Io e tan + sin ( t  ) Z cos L E where tan = ; Z = R 2 + 2 L2 ; sin = R 2Vi From the boundary condition  tan 2Vi sin Io sin + = I e + o Z cos 2Vi 2 sin Io =  Z 1  e tan
(9.68)
io =
From which the condition for continuous conduction can be obtained. for continuous conduction io 0 for all 0 < t hence io Min 0 or io t= 0 Condition for continuous conduction is 2 sin  tan sin e = sin (  ) +  tan cos 1 e
(9.71)
If the parameters of the load (i.e, R, L &E) are such that the left hand side of equation 9.71 is less than the right hand side conduction of the rectifier becomes discontinuous i.e, the load current becomes zero for a part of the input cycle. Discontinuous conduction mode of operation of this rectifier is discussed next.
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Fig. 9.10(b) shows the waveforms of different variables under discontinuous conduction mode of operation. In this mode of operation D1 D2 are not forward biased till vi exceed E at t = . Consequently, no current flows into the load till this time. After t = , the load is connected to the input source through D1 D2 and io starts building up. Beyond t =  , io starts decreasing and becomes zero at t = < . D1 D2 are reverse biased at this point. D3 D4 are forward biased at t = + when io starts increasing again. Thus none of the diodes conduct during the interval < + + and io remains zero during this period. Form the preceding discussion Version 2 EE IIT, Kharagpur 27
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for
(9.73)
other wise
+ 1 2Vi sin t + E d t
(9.74)
VoAV =
vo d t =
OR VoAV =
(9.75)
can be found in the following manner for < t Ldi o v = 2 sin t = R i o + +E dt i o t = = io t= = 0 The general solution is i o = Io e
t  tan
(9.76)
(9.77)
2Vi
= 0
(9.78) (9.79)
io =
Putting i o
sin (  ) + sin cos t t sin sin  e tan tan 1e + sin ( t  ) ( ) cos = 0 in Equation 9.79.
sin (  ) =
 tan
(9.80)
Exercise 9.4
1. Fill in the blank(s) with the appropriate word(s). i) The average output voltage of a full wave bridge rectifier and a split supply full wave rectifier are __________ provided the input voltages are ___________.
Version 2 EE IIT, Kharagpur 28
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For the same input voltage the bridge rectifier uses ___________ the number of diodes used in a split supply rectifier with _________ the PIV rating. For continuous conduction, the load impedance of a bridge rectifier should be __________. In the ___________ conduction mode the output voltage of a bridge rectifier is __________ of load parameters.
Answers: (i) equal, equal; (ii) double, half; (iii) inductive; (iv) continuous, independent.
2. A battery is to be charged using a full bridge single phase uncontrolled rectifier. On full discharge the battery voltage is 10.2 V. and on full charge it is 12.7 volts. The battery internal resistance is 0.1. Find out the input voltage to the rectifier so that the battery charging current under full charge condition is 10% of the charging current under fully discharged condition. Assume continuous conduction under all charging condition and find out the inductance to be connected in series with the battery for this condition.
Answer: Let the rectifier input voltage be Vi and the charging current under fully discharged condition be I. Then assuming continuous conduction 2 2Vi 2 2  0.1I = 10.2 and V  0.01I = 12.7 i 0.09I = 2.5 V I = 27.78 Amps and Vi = 14.415 volts. If conduction is continuous at full charge condition it will be continuous for all other charging conditions. For continuous conduction 2sin  tan sin e = sin(  ) +  tan cos 1 e E From given data sin = = 0.623, = 38.535 2Vi From which = 86.5 tan = L = 16.35 or L = 1.635 ohms R L = 5.2 mH.
References
[1] [2] P.C. Sen, Power Electronics, Tata McGraw Hill Publishing Company Limited. 1995 Muhammad H. Rashid, Power Electronics, circuits, Devices and applications Prentice Hall of India Private Limited, Second Edition, 1994
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Module Summary
A rectifier is a power electronic converter which converts ac voltage or current sources to dc voltage and current. In a rectifier, electrical power flows from the ac input to the dc output. In many rectifier circuits, power can also flow from the dc side to the ac side, where upon, the rectifier is said to be operating in the inverter mode. Rectifiers can be classified based on the type of device they use, the converter circuit topology, number of phases and the control mechanism. All rectifiers produce unwanted harmonies both at the out put and the input. Performance of a rectifier is judged by the relative magnitudes of these harmonies with respect to the desired output. For a given input voltage and load, the output voltage (current) of an uncontrolled rectifier can not be varied. However, the output voltage may vary considerably with load. Single phase uncontrolled half wave rectifier with resistive or inductive load have low average output voltage, high from factor and poor ripple factor of the output voltage waveform. Single phase uncontrolled full wave rectifier have higher average output voltage and improved ripple factor compared to a half wave rectifier with resistive and inductive load. With highly inductive load the output voltage waveform of a full wave rectifier may be independent of the load parameters. With a capacitive load the output voltage form factor approaches unity with increasing capacitance value for both the half wave and the full wave rectifiers. However, THD of the input current also increases. A full wave bridge rectifier generates higher average dc voltage compared to a split supply full wave rectifier. However it also uses more number of diodes.
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Q1.
What will be the load voltage and current waveform when a single phase half wave uncontrolled rectifier supplies a purely inductive load? Explain your answer with waveforms. The split supply of a single phase full wave rectifier is obtained from a single phase transformer with a single primary and a center tapped secondary. The rectifier supplies a purely resistive load. Assuming the transformer to be ideal find out the, displacement factor, distortion factor and the power factor at the primary side of the transformer. A single phase split supply full wave rectifier is designed to supply an inductive load. The average load current is 20 A, and the ripple current is negligible. Can the same rectifier be used with a capacitive load drawing the same 20 Amps average current? Justify your answer. A 200V, 15 Amps, 1500 rpm separately excited dc motor has an armature resistance of 1 and inductance of 50 mH. The motor is supplied from a single phase full wave bridge rectifier with input voltage of 230 V, 50 HZ. Neglecting all no load losses, find out the no load speed of the machine. Also find out the torque and speed at the boundary between continuous and discontinuous conduction.
Q2.
Q3.
Q4.
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Answer 1
Without loss of generality it can be assumed that S is turned ON at t = 0. Since, if it is turned ON anytime after t = 0, the voltsec. across the inductor will dictate that the current through it becomes zero before the next positive going zero crossing of vi . In the region 0 t < D is forward biased and v0 = vi di L 0 = 2Vsin t i 0 (0) = 0 i dt di i0 t or L 0 = 2Vsin =0 i t = 0 dt 2Vi 2Vi cost I0 = i 0 = I0 L L 2Vi (1 cost) i0 = L 2 2Vi i0 = >0 at t = , L D conducts beyond t = until i0 is zero again. Let the extinction angle be t = > . Then for 0 t 2Vi i0 = (1 cost) L 2Vi i0 = (1 cos) for 2 the only solution is = 2 t = L
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v0 = vi for 0 t 2 and
Answer 2
i0 =
Figure shows the secondary voltage and current waveforms of the rectifier. From the given data N vS1 = S 2VP sint NP N V iS1 = S 2 P sint NP R iS1 = 0 otherwise. N vS2 =  S 2VP sint NP N V iS2 =  S 2 P sint NP R iS2 = 0 otherwise
for 0 t
for t 2
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Answer 3
If the load current is 20A with negligible ripple. The required RMS current rating of the rectifier diode, with reference to Fig 9.6 (b) will be I D1RMS = I D2RMS = 20 Amps . 2 However from Fig 9.7 (b) and Problem 2 of Exercise 9.3 the required RMS current for a capacitive load will be much larger than 20 Amps. Therefore the same rectifier can not be used.
Answer 4
Since all no load losses are neglected the developed power at no load and hence the no load torque will be zero. Therefore, the average armature current will also be zero. However, since a diode rectifier can not conduct instantaneous negative load current, zero average current will imply that the instantaneous value of the armature current at all time will be zero at no load.With reference to Fig 9.10 this condition will require the rectifier diodes to remain reverse biased at all time. Hence at no load E 2Vi However E will not exceed 2Vi , since once ia becomes zero when E = 2Vi there will be no developed torque to accelerate the motor. Hence the motor speed and E will not increase any further. Thus at no load E = 2Vi = 325.27 volts . Under the rated condition at 1500 rpm Erated = 200 15 1.0 = 185 volts. E N Now = E rated N rated E 325.27 = 1500 = 2637 rpm . N = N rated E rated 185 At the boundary between the continuous and discontinuous mode of conduction. 2sin  tan sin e = sin(  ) +  tan cos 1 e 2sin tan or = [ cos sin(  ) + sin ] e  tan 1 e
L 100 5010 = = 15.708 R 1 cos = 0.0635 = 1.507 rad. and sin2 = 0.1268
3
where tan =
0.6995 = [ 0.0635 sin(1.507  ) + sin ] e E 1 o from which = sin E = 202.48 V = 38.5 2Vi but E at 1500 RPM = 185 volts. Speed at the junction of continuous and discontinuous condition is 202.48 1500 = 1642 RPM. 185
0.06366
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2 2Vi Average armature current is R = 4.593 Amps. 4.593 100 = 30.62% of rated torque. Torque = 15
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Module 2
AC to DC Converters
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Lesson 10
Single Phase Fully Controlled Rectifier
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Instructional Objectives
On completion the student will be able to Differentiate between the constructional and operation features of uncontrolled and controlled converters Draw the waveforms and calculate their average and RMS values of different variables associated with a single phase fully controlled half wave converter. Explain the operating principle of a single phase fully controlled bridge converter. Identify the mode of operation of the converter (continuous or discontinuous) for a given load parameters and firing angle. Analyze the converter operation in both continuous and discontinuous conduction mode and there by find out the average and RMS values of input/output, voltage/currents. Explain the operation of the converter in the inverter mode.
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10.1 Introduction
Single phase uncontrolled rectifiers are extensively used in a number of power electronic based converters. In most cases they are used to provide an intermediate unregulated dc voltage source which is further processed to obtain a regulated dc or ac output. They have, in general, been proved to be efficient and robust power stages. However, they suffer from a few disadvantages. The main among them is their inability to control the output dc voltage / current magnitude when the input ac voltage and load parameters remain fixed. They are also unidirectional in the sense that they allow electrical power to flow from the ac side to the dc side only. These two disadvantages are the direct consequences of using power diodes in these converters which can block voltage only in one direction. As will be shown in this module, these two disadvantages are overcome if the diodes are replaced by thyristors, the resulting converters are called fully controlled converters. Thyristors are semicontrolled devices which can be turned ON by applying a current pulse at its gate terminal at a desired instance. However, they cannot be turned off from the gate terminals. Therefore, the fully controlled converter continues to exhibit load dependent output voltage / current waveforms as in the case of their uncontrolled counterpart. However, since the thyristor can block forward voltage, the output voltage / current magnitude can be controlled by controlling the turn on instants of the thyristors. Working principle of thyristors based single phase fully controlled converters will be explained first in the case of a single thyristor halfwave rectifier circuit supplying an R or RL load. However, such converters are rarely used in practice. Full bridge is the most popular configuration used with single phase fully controlled rectifiers. Analysis and performance of this rectifier supplying an RLE load (which may represent a dc motor) will be studied in detail in this lesson.
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10.2 Single phase fully controlled halfwave rectifier 10.2.1 Resistive load
Fig.10. 1(a) shows the circuit diagram of a single phase fully controlled halfwave rectifier supplying a purely resistive load. At t = 0 when the input supply voltage becomes positive the thyristor T becomes forward biased. However, unlike a diode, it does not turn ON till a gate pulse is applied at t = . During the period 0 < t , the thyristor blocks the supply voltage and the load voltage remains zero as shown in fig 10.1(b). Consequently, no load current flows during this interval. As soon as a gate pulse is applied to the thyristor at t = it turns ON. The voltage across the thyristor collapses to almost zero and the full supply voltage appears across the load. From this point onwards the load voltage follows the supply voltage. The load being purely resistive the load current io is proportional to the load voltage. At t = as the supply voltage passes through the negative going zero crossing the load voltage and hence the load current becomes zero and tries to reverse direction. In the process the thyristor undergoes reverse recovery and starts blocking the negative supply voltage. Therefore, the load voltage and the load current remains clamped at zero till the thyristor is fired again at t = 2 + . The same process repeats there after. From the discussion above and Fig 10.1 (b) one can write For < t v 0 = vi = 2 Vi sint (10.1)
i0 =
v0 V = 2 i sint R R
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v0 = i0 = 0 otherwise. Therefore
(10.3) (10.4)
(10.5)
Vi2 = 2
= Vi2 2
(1 cos2t)dt
sin2 + 2
1
V sin2 2 = i 1 + 2 2
FFVO =
VORMS VOAV
(10.6)
Similar calculation can be done for i0. In particulars for pure resistive loads FFio = FFvo.
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As in the case of a resistive load, the thyristor T becomes forward biased when the supply voltage becomes positive at t = 0. However, it does not start conduction until a gate pulse is applied at t = . As the thyristor turns ON at t = the input voltage appears across the load and the load current starts building up. However, unlike a resistive load, the load current does not become zero at t = , instead it continues to flow through the thyristor and the negative supply voltage appears across the load forcing the load current to decrease. Finally, at t = ( > ) the load current becomes zero and the thyristor undergoes reverse recovery. From this point onwards the thyristor starts blocking the supply voltage and the load voltage remains zero until the thyristor is turned ON again in the next cycle. It is to be noted that the value of depends on the load parameters. Therefore, unlike the resistive load the average and RMS output voltage depends on the load parameters. Since the thyristors does not conduct over the entire input supply cycle this mode of operation is called the discontinuous conduction mode. From above discussion one can write. t For
v 0 = vi = 2 Vi sint v0 = 0 otherwise
Therefore VOAV = 1 2 v0 dt 2 0 1 2 Vi sint dt = 2
(10.7)
(10.8)
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Vi 2
(cos  cos)
VORMS = =
1 2 2 v0 dt 2 0 1 2 2 2vi sin t dt 2
1
(10.9)
V  sin2  sin2 2 = i + 2 2 V Vi I OAV = OAV = (cos  cos) R 2 R Since the average voltage drop across the inductor is zero.
(10.10)
However, IORMS can not be obtained from VORMS directly. For that a closed from expression for i0 will be required. The value of in terms of the circuit parameters can also be found from the expression of i0.
t di Rio + L o = v0 = 2Vi sint dt The general solution of which is given by (t) 2Vi i 0 = I0 e tan + sin(t  ) Z L Where tan = and Z = R 2 + 2 L2 R
For
(10.11)
(10.12)
i0
t =
=0
0 = I0 +
2Vi sin(  ) Z
i0 =
(10.13)
Equation (10.13) can be used to find out IORMS. To find out it is noted that i0 t= = 0
sin(  )e
 tan
= sin(  )
(10.14)
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In a single phase fully controlled converter the _________ of an uncontrolled converters are replaced by ____________. In a fully controlled converter the load voltage is controlled by controlling the _________ of the converter. A single phase half wave controlled converter always operates in the ________ conduction mode. The voltage form factor of a single phase fully controlled half wave converter with a resistive inductive load is _________ compared to the same converter with a resistive load. The load current form factor of a single phase fully controlled half wave converter with a resistive inductive load is _________ compared to the same converter with a resistive load.
Answers: (i) diodes, thyristors; (ii) firing angle; (iii) discontinuous (iv) poorer; (v) better.
2) Explain qualitatively, what will happen if a freewheeling diode(cathode of the diode shorted with the cathode of the thyristor) is connected across the load in Fig 10.2.(a)
Answer: Referring to Fig 10.2(b), the free wheeling diode will remain off till t = since the positive load voltage across the load will reverse bias the diode. However, beyond this point as the load voltage tends to become negative the free wheeling diode comes into conduction. The load voltage is clamped to zero there after. As a result
i) ii) iii)
Average load voltage increases RMS load voltage reduces and hence the load voltage form factor reduces. Conduction angle of load current increases as does its average value. The load current ripple factor reduces.
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Fig 10.3 (a) shows the circuit diagram of a single phase fully controlled bridge converter. It is one of the most popular converter circuits and is widely used in the speed control of separately excited dc machines. Indeed, the RLE load shown in this figure may represent the electrical equivalent circuit of a separately excited dc motor. The single phase fully controlled bridge converter is obtained by replacing all the diode of the corresponding uncontrolled converter by thyristors. Thyristors T1 and T2 are fired together while T3 and T4 are fired 180 after T1 and T2. From the circuit diagram of Fig 10.3(a) it is clear that for any load current to flow at least one thyristor from the top group (T1, T3) and one thyristor from the bottom group (T2, T4) must conduct. It can also be argued that neither T1T3 nor T2T4 can conduct simultaneously. For example whenever T3 and T4 are in the forward blocking state and a gate pulse is applied to them, they turn ON and at the same time a negative voltage is applied across T1 and T2 commutating them immediately. Similar argument holds for T1 and T2. For the same reason T1T4 or T2T3 can not conduct simultaneously. Therefore, the only possible conduction modes when the current i0 can flow are T1T2 and T3T4. Of coarse it is possible that at a given moment none of the thyristors conduct. This situation will typically occur when the load current becomes zero in between the firings of T1T2 and T3T4. Once the load current becomes zero all thyristors remain off. In this mode the load current remains zero. Consequently the converter is said to be operating in the discontinuous conduction mode. Fig 10.3(b) shows the voltage across different devices and the dc output voltage during each of these conduction modes. It is to be noted that whenever T1 and T2 conducts, the voltage across T3 and T4 becomes vi. Therefore T3 and T4 can be fired only when vi is negative i.e, over the negative half cycle of the input supply voltage. Similarly T1 and T2 can be fired only over the positive half cycle of the input supply. The voltage across the devices when none of the thyristors conduct depends on the off state impedance of each device. The values listed in Fig 10.3 (b) assume identical devices. Under normal operating condition of the converter the load current may or may not remain zero over some interval of the input voltage cycle. If i0 is always greater than zero then the converter is said to be operating in the continuous conduction mode. In this mode of operation of the converter T1T2 and T3T4 conducts for alternate half cycle of the input supply. Version 2 EE IIT, Kharagpur 10
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However, in the discontinuous conduction mode none of the thyristors conduct over some portion of the input cycle. The load current remains zero during that period.
It is assumed that at t = 0 T3T4 was conducting. As T1T2 are fired at t = they turn on commutating T3T4 immediately. T3T4 are again fired at t = + . Till this point T1T2 conducts. The period of conduction of different thyristors are pictorially depicted in the second waveform (also called the conduction diagram) of Fig 10.4.
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The dc link voltage waveform shown next follows from this conduction diagram and the conduction table shown in Fig 10.3(b). It is observed that the emf source E is greater than the dc link voltage till t = . Therefore, the load current i0 continues to fall till this point. However, as T1T2 are fired at this point v0 becomes greater than E and i0 starts increasing through RL and E. At t = v0 again equals E. Depending upon the load circuit parameters io reaches its maximum at around this point and starts falling afterwards. Continuous conduction mode will be possible only if i0 remains greater than zero till T3T4 are fired at t = + where upon the same process repeats. The resulting i0 waveform is shown below v0. The input ac current waveform ii is obtained from i0 by noting that whenever T1T2 conducts ii = i0 and ii =  i0 whenever T3T4 conducts. The last waveform shows the typical voltage waveform across the thyristor T1. It is to be noted that when the thyristor turns off at t = + a negative voltage is applied across it for a duration of . The thyristor must turn off during this interval for successful operation of the converter. It is noted that the dc voltage waveform is periodic over half the input cycle. Therefore, it can be expressed in a Fourier series as follows.
v 0 = VOAV + [ v an cos2nt + v bn sin2nt ]
n =1
Where
v bn =
Therefore the RMS value of the nth harmonic 1 2 VOnRMS = v an + v2 bn 2 RMS value of v0 can of course be completed directly from. 1 + 2 VORMS = v0 dt = Vi
(10.20)
(10.21)
Fourier series expression of v0 is important because it provides a simple method of estimating individual and total RMS harmonic current injected into the load as follows: The impedance offered by the load at nth harmonic frequency is given by
Z n = R 2 + (2nL) 2
(10.22)
1 2
VonRMS 2 (10.23) ; IOHRMS = IonRMS Zn n =1 From (10.18) (10.23) it can be argued that in an inductive circuit IonRMS 0 as fast as 1/n2. So in practice it will be sufficient to consider only first few harmonics to obtain a reasonably accurate estimate of IOHRMS form equation 10.23. This method will be useful, for example, while calculating the required current derating of a dc motor to be used with such a converter. IonRMS =
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However to obtain the current rating of the device to be used it is necessary to find out a closed form expression of i0. This will also help to establish the condition under which the converter will operate in the continuous conduction mode. To begin with we observe that the voltage waveform and hence the current waveform is periodic over an interval . Therefore, finding out an expression for i0 over any interval of length will be sufficient. We choose the interval t + . In this interval
(10.24)
sin (10.25) sin(t  )  cos L Z = R 2 + 2 L2 ; tan = ; E = 2Vi sin; R = Zcos Where, R Now at steady state i 0 t= = i0 t = + since i0 is periodic over the chosen interval. Using this + 2Vi Z
(10.26)
The input current ii is related to i0 as follows: ii = i 0 for t + ii =  i0 otherwise. Fig 10.5 shows the waveform of ii in relation to the vi waveform.
(10.27)
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It will be of interest to find out a Fourier series expression of ii. However, using actual expression for ii will lead to exceedingly complex calculation. Significant simplification can be made by replacing i0 with its average value I0. This will be justified provided the load is highly inductive and the ripple on i0 is negligible compared to I0. Under this assumption the idealized waveform of ii becomes a square wave with transitions at t = and t = + as shown in Fig 10.5. ii1 is the fundamental component of this idealized ii. Evidently the input current displacement factor defined as the cosine of the angle between input voltage (vi) and the fundamental component of input current (ii1) waveforms is cos (lagging). It can be shown that
Ii1RMS = 2 2 I0
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and
IiRMS = I0
(10.29) (10.30)
Ii1RMS 2 2 = IiRMS VI cos Actual Power = i i1RMS The input power factor = Apparent Power Vi IiRMS
2 2 cos (lagging)
(10.31)
Therefore, the rectifier appears as a lagging power factor load to the input ac system. Larger the poorer is the power factor. The input current ii also contain significant amount of harmonic current (3rd, 5th, etc) and therefore appears as a harmonic source to the utility. Exact composition of the harmonic currents can be obtained by Fourier series analysis of ii and is left as an exercise.
Exercise 10.2
Fill in the blank(s) with the appropriate word(s). i) ii) iii) iv) v) A single phase fully controlled bridge converter can operate either in the _________ or ________ conduction mode. In the continuous conduction mode at least _________ thyristors conduct at all times. In the continuous conduction mode the output voltage waveform does not depend on the ________ parameters. The minimum frequency of the output voltage harmonic in a single phase fully controlled bridge converter is _________ the input supply frequency. The input displacement factor of a single phase fully controlled bridge converter in the continuous conduction mode is equal to the cosine of the ________ angle.
Answer: (i) continuous, discontinuous; (ii) two; (iii) load; (iv) twice; (v) firing.
2. A single phase fully controlled bridge converter operates in the continuous conduction mode from a 230V, 50HZ single phase supply with a firing angle = 30. The load resistance and inductances are 10 and 50mH respectively. Find out the 6th harmonic load current as a percentage of the average load current.
Answer: The average dc output voltage is 2 2 VOAV = Vi cos = 179.33 Volts V Average output load current = OAV = 17.93 Amps RL From equation (10.18) Va3 = 10.25 Volts From equation (10.19) Vb3 = 35.5 Volts
3 2 V03RMS = 26.126 Volts, Z3 = R 2 L + (6 2 505010 ) = 94.78 ohms
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I3RMS =
 sin(  ) 
sin 0 cos
(10.32)
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Fig 10.6 shows waveforms of different variables on the boundary between continuous and discontinuous conduction modes and in the discontinuous conduction mode. It should be stressed that on the boundary between continuous and discontinuous conduction modes the load current is still continuous. Therefore, all the analysis of continuous conduction mode applies to this case as well. However in the discontinuous conduction mode i0 remains zero for certain interval. During this interval none of the thyristors conduct. These intervals are shown by hatched lines in the conduction diagram of Fig 10.6(b). In this conduction mode i0 starts rising from zero as T1T2 are fired at t = . The load current continues to increase till t = . After this, the output voltage v0 falls below the emf E and i0 decreases till t = when it becomes zero. Since the thyristors cannot conduct current in the reverse direction i0 remains at zero till t = + when T3 and T4 are fired. During the period t + none of the thyristors conduct. During this period v0 attains the value E. Performance of the rectifier such as VOAV, VORMS, IOAV, IORMS etc can be found in terms of , and . For example Version 2 EE IIT, Kharagpur 18
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VOAV = Or
+ 1 + 1 (10.33) v d t = 2V sin t d t + 0 i 2Vi sin dt 2Vi (10.34) VOAV = [cos  cos + sin( +  )] V  E VOAV  2Vi sin (10.35) IOAV = OAV = R Zcos
Or
IOAV =
(10.36)
It is observed that the performance of the converter is strongly affected by the value of . The value of in terms of the load parameters (i.e, , and Z) and can be found as follows. In the interval t di L o + Rio + E = 2Vi sint dt i 0 t = = 0 From which the solution of i0 can be written as ( )  t 2Vi ( ) sin tan  t i0 = sin( )e + sin(t  ) tan Z cos 1 e
(10.37)
(10.38)
Now
i0
t=
=0
 tan
 sin tan + sin(  ) = 0 cos 1 e Given , and , the value of can be found by solving equation 10.39.
sin(  )e
(10.39)
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Therefore for sustained inverter mode of operation the connection of E must be reversed as shown in Fig 10.7(b). Fig 10.8 (a) and (b) below shows the waveforms of the inverter operating in continuous conduction mode and discontinuous conduction mode respectively. Analysis of the converter remains unaltered from the rectifier mode of operation provided is defined as shown.
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Exercise 10.3
Fill in the blank(s) with the appropriate word(s) i) ii) iii) In the discontinuous conduction mode the load current remains __________ for a part of the input cycle. For the same firing angle the load voltage in the discontinuous conduction mode is __________ compared to the continuous conduction mode of operation. The load current ripple factor in the continuous conduction mode is _______ compared to the discontinuous conduction mode. Version 2 EE IIT, Kharagpur 21
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iv) v)
In the inverter mode of operation electrical power flows from the ________ side to the __________side. In the continuous conduction mode if the firing angle of the converter is increased beyond _________ degrees the converter operates in the _______ mode.
Answers: (i) zero; (ii) higher; (iii) lower; (iv) dc, ac; (v) 90, inverter.
2. A 220 V, 20A, 1500 RPM separately excited dc motor has an armature resistance of 0.75 and inductance of 50mH. The motor is supplied from a 230V, 50Hz, single phase supply through a fully controlled bridge converter. Find the no load speed of the motor and the speed of the motor at the boundary between continuous and discontinuous modes when = 25.
Answer: At no load the average motor torque and hence the average motor armature current is zero. However, since a converter carries only unidirectional current, zero average armature current implies that the armature current is zero at all time. From Fig 10.6(b) this situation can occur only when = /2, i.e the back emf is equal to the peak of the supply voltage. Therefore, E b no load = 2 230 V = 325.27 V, Under rated condition E b 1500 = 205 V
325.27 1500 = 2380 RPM 205 At the boundary between continuous and discontinuous conduction modes from equation 10.32 1+ e /tan sin = cossin(  ) 1 e/tan From the given data = 87.27, = 25 sin = 0.5632 E b = 2Vi sin = 183.18 Volts 183.18 Motor speed N = 1500 = 1340 RPM . 205 N no load =
Summary
Single phase fully controlled converters are obtained by replacing the diodes of an uncontrolled converter with thyristors. In a fully controlled converter the output voltage can be controlled by controlling the firing delay angle () of the thyristors. Single phase fully controlled half wave converters always operate in the discontinuous conduction mode. Half wave controlled converters usually have poorer output voltage form factor compared to uncontrolled converter. Single phase fully controlled bridge converters are extensively used for small dc motor drives.
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Depending on the load condition and the firing angle a fully controlled bridge converter can operate either in the continuous conduction mode or in the discontinuous conduction mode. In the continuous conduction mode the load voltage depends only on the firing angle and not on load parameters. In the discontinuous conduction mode the output voltage decreases with increasing load current. However the output voltage is always greater than that in the continuous conduction mode for the same firing angle. The fully controlled bridge converter can operate as an inverter provided (i) > 2 , (ii) a dc power source of suitable polarity exists on the load side.
References
1) Power Electronics P.C.Sen; Tata McGrawHill 1995 2) Power Electronics; Circuits, Devices and Applications, Second Edition, Muhammad H.Rashid; PrenticeHall of India; 1994. 3) Power Electronics; Converters, Applications and Design Third Edition, Mohan, Undeland, Robbins, John Wileys and Sons Inc, 2003.
Q3.
Q4. Q5.
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Answers
1. As explained in section 10.3.3, the load circuit must contain a voltage source of proper polarity. Such a load circuit and the associated waveforms are shown in the figure next.
Figure shows that it is indeed possible for the half wave converter to operate in the inverting mode for some values of the firing angle. However, care should be taken such that i0 becomes zero before vi exceeds E in the negative half cycle. Otherwise i0 will start increasing again and the thyristor T will fail to commutate. 2. For the machine to deliver full load torque with rated field the armature current should be 20 Amps. 2 2 230 Assuming continuous conduction v 0 = cos30o = 179.33 volts. For 20 Amps armature current to flow the back emf will be Eb = Va IaRa = 179.33 20 0.75 = 164.33 volts E = 0.505 . sin = b 2Vi
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L a = 20.944, = 87.266o . Ra
Now from equation (10.32) 2sin(  )  sin(  ) = 11.2369. 1 e/tan sin and = 10.589 cos the conduction is continuous. At 1500 RPM the back emf is 220 20 0.75 = 205 volts. The speed at which the machine delivers rated torques 164.33 is N r = 1500 = 1202 RPM . 205 3. To maintain constant load torque equal to the rated value the armature voltage should be N Va = ra I a rated + E b rated N rated N = 0.75 20 + 205 = 0.137 N + 15 V 1500 In a fully controlled converter operating in the continuous conduction mode 2 2 Va = Vi cos = 207.073 cos cos = 6.616 10 4 N + 0.0724 Now the power factor from equation 10.31 is 2 2 pf = cos = 5.9565 10 4 N + 0.0652 This gives the input power factor as a function of speed. 4. At 2000 RPM, E b = sin = Eb 2000 205 = 273.33 volts 1500
2Vi From equation 10.32 it can be shown that the conduction will be discontinuous. Now from equation 10.39
 tan
sin (  )  (  ) + e
or
sin sin cos + sin (  ) = cos .0477(  ) o e [17.61+ .8412]  sin 57.266 + (  ) = 17.61
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from equation 10.36 2Vi Ioav = [cos  cos + sin(  )] = 2.676 Amps Zcos 2.676 the load torque should be 100 = 13.38% of the full load torque. 20 5. Referring to Fig 10.8 (a) let there be a commutation failure of T1 at t = . In that case the conduction mode will be T3 T2 instead of T1 T2 and v0 will be zero during that period. As a result average value of V0 will be less negative and the average armature current will increase. However the converter will continue to operate in the inverter mode and the motor will be braked.
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Module 2
AC to DC Converters
Version 2 EE IIT, Kharagpur 1 www.jntuworld.com
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Lesson 11
Single Phase Half Controlled Bridge Converter
Version 2 EE IIT, Kharagpur 2 www.jntuworld.com
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Instructional Objectives
On completion the student will be able to Draw different topologies of single phase half controlled converter. Identify the design implications of each topology. Construct the conduction table and thereby draw the waveforms of different system variables in the continuous conduction mode of operation of the converter. Analyze the operation of the converter in the continuous conduction mode to find out the average and RMS values of different system variables. Find out an analytical condition for continuous conduction relating the load parameters with the firing angle. Analyze the operation of the converter in the discontinuous conduction mode of operation.
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11.1 Introduction
Single phase fully controlled bridge converters are widely used in many industrial applications. They can supply unidirectional current with both positive and negative voltage polarity. Thus they can operate either as a controlled rectifier or an inverter. However, many of the industrial application do not utilize the inverter mode operation capability of the fully controlled converter. In such situations a fully controlled converter with four thyristors and their associated control and gate drive circuit is definitely a more complex and expensive proposition. Single phase fully controlled converters have other disadvantages as well such as relatively poor output voltage (and current for lightly inductive load) form factor and input power factor. The inverter mode of operation of a single phase fully controlled converter is made possible by the forward voltage blocking capability of the thyristors which allows the output voltage to go negative. The disadvantages of the single phase fully controlled converter are also related to the same capability. In order to improve the output voltage and current form factor the negative excursion of the output voltage may be prevented by connecting a diode across the output as shown in Fig 11.1(a). Here as the output voltage tries to go negative the diode across the load becomes forward bias and clamp the load voltage to zero. Of course this circuit will not be able to operate in the inverter mode. The complexity of the circuit is not reduced, however. For that, two of the thyristors of a single phase fully controlled converter has to be replaced by two diodes as shown in Fig 11.1 (b) and (c). The resulting converters are called single phase half controlled converters. As in the case of fully controlled converters, the devices T1 and D2 conducts in the positive input voltage half cycle after T1 is turned on. As the input voltage passes through negative going zero crossing D4 comes into conduction commutating D2 in Fig 11.1 (b) or T1 in Fig 11.1 (c). The load voltage is thus clamped to zero until T3 is fired in the negative half cycle. As far as the input and output behavior of the circuit is concerned the circuits in Fig 11.1 (b) and (c) are identical although the device designs differs. In Fig 11.1 (c) the diodes carry current for a considerably longer duration than the thyristors. However, in Fig 11.1 (b) both the thyristors and the diodes carry current for half the input cycle. In this lesson the operating principle and characteristics of a single phase half controlled converter will be presented with reference to the circuit in Fig 11.1 (b).
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It is observed that whenever D2 conducts the voltage across D4 is vi and whenever D4 conducts the voltage across D2 is vi. Since diodes can block only negative voltage it can be concluded that D2 and D4 conducts in the positive and the negative half cycle of the input supply respectively. Similar conclusions can be drawn regarding the conduction of T1 and T3. The operation of the converter can be explained as follows when T1 is fired in the positive half cycle of the input voltage. Load current flows through T1 and D2. If at the negative going zero crossing of the input voltage load current is still positive it commutates from D2 to D4 and the load voltage becomes zero. If the load current further continuous till T3 is fired current commutates from T1 to T3. This mode of conduction when the load current always remains above zero is called the continuous conduction mode. Otherwise the mode of conduction becomes discontinuous. Exercise 11.1 Fill in the blanks(s) with the appropriate word(s) i. ii. iii. iv. v. In a half controlled converter two ___________________ of a fully controlled converter are replaced by two ___________________. Depending on the positions of the ___________________ the half controlled converter can have ___________________ different circuit topologies. The input/output waveforms of the two different circuit topologies of a half controlled converter are ___________________ while the device ratings are ___________________. A half controlled converter has better output voltage ___________________ compared to a fully controlled converter. A half controlled converter has improved input ___________________ compared to a fully controlled converter.
Answer: (i) thyristors, diodes; (ii) diodes, two; (iii) same, different; (iv) form factor; (v) power factor.
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2. Find out an expression of the ration of the thyristor to diode RMS current ratings in the single phase half controlled converter topologies of Fig. 11.1(b) & (c). Assume ripple free continuous output current. Answer
In the first conduction diagram the diodes and the thyristors conduct for equal periods, since the load current is constant. The ration of the thyristors to the diode RMS current ratings will be unity for the circuit of Fig 11.1 (b). From the second conduction diagram the thyristors conduct for  radians while the diodes conduct for + radians. Since the load current is constant. Thyristor RMS current rating 1 / = Diode RMS current rating 1+ / in this case
11.2.1 Single phase half controlled converter in the continuous conduction mode
From the conduction table and the discussion in the previous section it can be concluded that the diode D2 and D4 conducts for the positive and negative half cycle of the input voltage waveform respectively. On the other hand T1 starts conduction when it is fired in the positive half cycle of the input voltage waveform and continuous conduction till T3 is fired in the negative half cycle. Fig. 11.3 shows the circuit diagram and the waveforms of a single phase half controlled converter supplying an R L E load.
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Referring to Fig 11.3 (b) T1 D2 starts conduction at t = . Output voltage during this period becomes equal to vi. At t = as vi tends to go negative D4 is forward biased and the load current commutates from D2 to D4 and freewheels through D4 and T1. The output voltage remains clamped to zero till T3 is fired at t = + . The T3 D4 conduction mode continues upto t = 2. Where upon load current again free wheels through T3 and D2 while the load voltage is clamped to zero. From the discussion in the previous paragraph it can be concluded that the output voltage (hence the output current) is periodic over half the input cycle. Hence
2Vi 1 1 vo dt = 2Vi sin t dt = (1+ cos) o V E 2Vi Iov = oav = (1+ cos  sin) R R Voav =
(11.1) (11.2)
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Clearly in addition to the average component, the output voltage (and current) contains a large number of harmonic components. The minimum harmonic voltage frequency is twice the input supply frequency. Magnitude of the harmonic voltages can be found by Fourier series analysis of the load voltage and is left as an exercise. The Fourier series representation of the load current can be obtained from the load voltage by applying superposition principle in the same way as in the case of a fully controlled converter. However, the closed form expression of io can be found as explained next. In the period t
dio + Rio + E = 2Vi sin t dt (t) 2Vi sin io = I1e tan + sin(t  ) Z cos E L ; Z = R2 + 2 L2 ; tan = Where sin = R 2Vi L
(11.3) (11.4)
io = I1 + io
(11.5) (11.6)
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io = io e io = I1 e io

(t ) tan
(t) tan
(t ) 2Vi sin  tan 1 e Z cos (t ) 2Vi sin tan + sin e Z cos
= I1e
tan
2Vi + Z
I1 =
2Vi Z
sin(  ) + sin e 1 e
tan
tan
(11.11)
For t
(t) 2Vi e tan sin tan io = + sin(t  ) sin(  ) + sine Z cos tan 1 e
(11.12)
For
t +
(t) (t ) 2Vi e tan sin tan tan io = + sin e sin(  ) + sine Z cos tan 1 e
(11.13)
(11.14)
However, it will be very difficult to find out the characteristic parameters of ii using equation 11.14 since the expression of i0 is considerably complex. Considerable simplification can however be obtained if the actual ii waveform is replaced by a quasisquare wave current waveform with an amplitude of Ioav as shown in Fig 11.5.
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IiRMS = 1 / Ioav
The displacement factor = cos /2
Vi Ii1 cos = Vo I oav = 2 Ii1 = 2 2 IOAV cos 2 2Vi (1+ cos)I OAV
Distortion factor =
Ii1 IiRMS
=2
(11.19)
(11.20)
Exercise 11.2
Fill in the blank(s) with the appropriate word(s). i. ii. In a half controlled converter the output voltage can not become ___________________ and hence it can not operate in the ___________________ mode. For the same firing angle and input voltage the half controlled converter gives ___________________ output voltage form factor compared to a fully controlled converter. For ripplefree continuous output current the input current displacement factor of a half controlled converter is given by ___________________. For the same supply and load parameters the output current form factor of a half controlled converter is ___________________ compared to a fully controlled converter. Version 2 EE IIT, Kharagpur 11
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iii. iv.
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The free wheeling operating mode of a half controlled converter helps to make the output current ___________________. Answer: (i) negative, inverter; (ii) lower; (iii) cos ; (iv) lower; (v) continuous. 2 2. A single phase half controlled converter is used to supply the field winding of a separately excited dc machine. With the rated armature voltage the motor operates at the rated no load speed for a fining angle =0. Find the value of which will increase the motor no load speed by 30%. Neglect lasses and saturation. Assume continuous conduction. v.
Answer:
N NO load 1
or f
1 N NO load
In order to increase Nno load by 30% f should be reduced by 23%. Therefore the applied field voltage must by 23%. Now by (11.1) Vf ( ) = Vf ( = 0 )
1
1 + cos 2
11.2.2 Single phase half controlled converter in the discontinuous conduction mode.
So far we have discussed the operating characteristics of a single phase half controlled converter in the continuous conduction mode without identifying the condition required to achieve it. Such a condition exists however and can be found by carefully examining the way this converter works. Referring to Fig 11.3 (b), when T1 is fired at t = the output voltage (instantaneous value) is larger than the back emf. Therefore, the load current increases till vo becomes equal to E again at t = . There, onwards the load current starts decreasing. Now if io becomes zero before T3 is fired at t = + the conduction becomes discontinuous. So clearly the condition for continuous conduction will be
io
=0
(11.21)
sin(  ) + sin e 1 e
tan
tan
 sin(  )
sin cos
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or
sin(  )e
tan
+ sin e
tan
1 e
tan
sin cos
(11.22)
If the condition in Eq. 11.22 is violated the conduction will become discontinuous. Clearly, two possibilities exist. In the first case the load current becomes zero before t = . In the second case io continuous beyond t = but becomes zero before t = + . In both cases however, io starts from zero at t = . Fig. 11.6 shows the wave forms in these two cases.
Of these two cases the second one will be analyzed in detail here. The analysis of the first case is left as an exercise. For this case vo = vi vo = 0 vo = E for t for t for t +
(11.23)
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Therefore
VOAV =
1 + v o dt + 1 2vi sin dt = 2vi sint dt + 2Vi = [1+ cos + ( +  )sin ] IOAV = VORMS VOAV  E 2Vi = [1+ cos + (  )sin] R Z cos 1 + 2 = vo dt
+ 1 2 = 2vi2 sin 2 t dt + 2vi2 sin 2 dt 1
(11.24)
(11.25)
(11.26)
However IORMS cannot be computed directly from VORMS. For this the closed form expression for io has to be obtained. This will also help to find out an expression for the conduction angle . For t 2Vi sin t = Ri o + L The general solution is given by di o +E dt (11.27)
(t) tan
(11.28)
2Vi sin + sin(  ) Z cos t  tan 2Vi sin sin io = + sin( ) e + sin( t ) Z cos cos  2Vi sin sin + sin(  ) e tan + sin io at t = = Z cos cos Io =
For t O = Ri o + L di o +E dt
(11.32)
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io
io = I1 e
t =
t tan
(11.33)
= I1 
 tan sin sin + sin( ) e + sin = cos cos  tan 2Vi sin I1 = + sin( ) e + sin Z cos t t  tan 2Vi sin sin io = + sin(  ) e + sine tan Z cos cos
2Vi Z
Equations (11.30) and (11.36) gives closed from expression of io in this conduction mode. To find out we note that at t = , io = 0. So from equation (11.36)
(11.37)
sin tan sin tan e = sin e tan + sin(  ) e tan + e cos cos
(11.38)
Given the values of , and the value of can be obtained from equation 11.38.
Exercise 11.3 (After section 11.2.2)
Fill in the blank(s) with the appropriate word(s). i. ii. At the boundary between continuous and discontinuous conduction the value of the output current at t = is ___________________. The output voltage and current waveform of a single phase fully controlled and half controlled converter will be same provided the extinction angle is less than ___________________. For the same value of the firing angle the average output voltage of a single phase half controlled converter is ___________________ in the discontinuous conduction mode compared to the continuous conduction mode. Single phase half controlled converters are most suitable for loads requiring ___________________ voltage and current.
iii.
iv.
2. A single phase half controlled converter charges a 48v 50Ah battery from a 50v, 50Hz single phase supply through a 50mH line inductor. The battery has on interval resistance of 0.1. The Version 2 EE IIT, Kharagpur 15
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firing angle of the converter is adjusted such that the battery is charged at C/5 rate when it is fully discharged at 42 volts. Find out whether the conduction will be continuous or discontinuous at this condition. Up to what battery voltage will the conduction remain continuous? If the charging current of the battery is to become zero when it is fully charged at 52 volts what should be the value of the firing angle.
Answer: From the given data assuming continuous conduction the output voltage of the converter to charge the battery at C/5 (10 Amps) rate will be
Vo = E + Ib rb = 42 + 0.110 = 43volts
= tan 1 L = 89.63o , tan = 157.08, sin = 0.99998 cos = 6.3 103 R
= 24.43o
Putting these values in equation (11.22) one finds that the conduction will be continuous. The conduction will remain continuous till
sin =
E = 2vi
cos sin ( ) e
tan
tan 1 + sin 2 e 2
1 e
tan
References
[1] [2] [3] Power Electronics; P.C. Sen; Tata McGraw Hill Publishing Company Limited 1995. Power Electronics, circuits, devices and applications; Second Edition; Muhammad H. Rashid; Prentice Hall of India; 1994. Power Electronics, converters, applications and design; Third Edition; Mohan, Undeland, Robbins; John Wiley and Sons Inc., 2003.
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Lesson Summary
Single phase half controlled converters are obtained from fully controlled converters by replacing two thyristors by two diodes. Two thyristors of one phase leg or one group (top or bottom) can be replaced resulting in two different topologies of the half controlled converter. From the operational point of view these two topologies are identical. In a half controlled converter the output voltage does not become negative and hence the converter cannot operate in the inverter mode. For the same firing angle and input voltage the half controlled converter in the continuous conduction mode gives higher output voltage compared to a fully controlled converter. For the same input voltage, firing angle and load parameters the half controlled converter has better output voltage and current form factor compared to a fully controlled converter. For the same firing angle and load current the half controlled converter in the continuous conduction mode has better input power factor compared to a fully controlled converter. Half controlled converters are most favored in applications requiring unidirectional output voltage and current.
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Figure above explains the operation of the circuit following the fault. T1 is tired at t = and the load current commutates from T3 to T1. The conduction periods T1 D2 & T1 D4 commences as usual. However at t = + when T3 is fired it fails to turn ON and as a consequences T1 does not commutate. Now if the load is highly inductive T1 D4 will continue to conduct till t = 2 and the load voltage will be clamped to zero during this period. However, since T1 does not stop conduction fining angle control on it is lost after words. Hence T1 D2 conduction period starts right after t = 2 instead of at t = 2 + . Thus the full positive half cycle of supply voltage is applied across the load followed by a entire half cycle of zero voltage. Thus the load voltage becomes a half wave rectified sine wave and voltage control through fining angle is last. This is the effect of the fault. [Note: This phenomenon is known as half cycle brusting. It can be easily verified that this possibility does not existion the circuit shown in Fig 11.1 (c)] 2. For a separately excited dc motor
NO load
Vf =
1 1 f Vf
Vf rated for boosting no load speed by 150% 1.5 Vf 1 + cos 1 = = but Vf rated 2 1.5
= 70.53o
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3. sin =
From
the
given
data,
tan
E 14 220 20 1.0 = = 0.578 substituting these values in equation 11.22 it can be 2Vi 15 2 230 conducted that the conduction is continuous
L = 15.7, = 86.36o R
Va = 193.2V, E = 186.7V V E Ia = a = 6.53A ra 6.53 Motor torque will be 100 = 32.67% of full load torque. 20
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Module 2
AC to DC Converters
Version 2 EE IIT, Kharagpur 1 www.jntuworld.com
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Lesson 12
Single Phase Uncontrolled Rectifier
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Instructional Objectives
On completion the student will be able to Draw the conduction table and waveforms of a three phase half wave uncontrolled converter supplying resistive and resistive inductive loads. Calculate the average and RMS values of the input / output current and voltage waveforms of a three phase uncontrolled half wave converter. Analyze the operation of a three phase full wave uncontrolled converter to find out the input / output current and voltage waveforms along with their RMS and Average values. Find out the harmonic components in the input / output voltage and current waveforms of a three phase uncontrolled full wave converter. Analyze the operation of a three phase full wave uncontrolled converter supplying a Capacitive Resistive load.
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12.1 Introduction
Single phase rectifiers, as already discussed, are extensively used in low power applications particularly for power supplies to electronic circuits. They are also found useful for supplying small dc loads rarely exceeding 5 KW. Above this power level three phase ac dc power supplies are usually employed. Single phase ac dc converters have several disadvantages such as Large output voltage and current form factor. Large low frequency harmonic ripple current causing harmonic power loss and reduced efficiency. Very large filter capacitor for obtaining smooth output dc voltage. Low frequency harmonic current is injected in the input ac line which is difficult to filter. The situation becomes worse with capacitive loads.
Many of these disadvantages are mitigated to a large extent by using three phase ac dc converters. In a way it is also natural that bulk loads are supplied by three phase converters since bulk electrical power is always transmitted and distributed in three phases and high power should load three phases symmetrically. Polyphase rectifiers produce less ripple output voltage and current compared to single phase rectifiers. The efficiency of polyphase rectifier is also higher while the associated equipments are smaller. A three phase supply gives the choice of a number of circuits. These can be placed in one of two groups according to whether three or six diodes are used. These topologies will be analyzed in detail in this section.
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For simplicity the load current (io) has been assumed to be ripple free. As shown in Fig. 12.1 (a), in a three phase half wave uncontrolled converter the anode of a diode is connected to each phase voltage source. The cathodes of all three diodes are connected together to form the positive load terminal. The negative terminal of the load is connected to the supply neutral. Fig. 12.1 (b) shows the conduction table of the converter. It should be noted that for the type of load chosen the converter always operates in the continuous conduction mode. The conduction diagram for the diodes (as shown in Fig. 12.1 (c) second waveform) can be drawn easily from the conduction diagram. Since the diodes can block only negative voltage it follows from the conduction table that a phase diode conducts only when that phase voltage is maximum Version 2 EE IIT, Kharagpur 5 www.jntuworld.com
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of the three. (In signal electronics the circuit of Fig. 12.1 (a) is also known as the maximum value circuit). Once the conduction diagram is drawn other waveforms of Fig. 12.1 (c) are easily obtained from the supply voltage waveforms in conjunction with the conduction table. The phase current waveforms of Fig. 12.1 (c) deserve special mention. All of them have a dc component which flows through the ac source. This may cause dc saturation in the ac side transformer. This is one reason for which the converter configuration is not preferred very much in practice. From the waveforms of Fig. 12.1 (c)
VOAV =
(12.1)
1
VORMS
(12.2)
VORMS = 1.01 VOAV
(12.3)
IO av =
VOAV , R
IO 3
(12.4)
3 6 Vi IO 3 AV = 2 = Input power factor = (12.5) IO 3Vi Ii RMS 2 3Vi 3 The harmonics present in vo and ii can be found by Fourier series analysis of the corresponding waveforms of Fig. 12.1 (c) and is left as an exercise. VO av IO
Exercise 12.1
Fill in the blank(s) with the appropriate word(s). i) ii) Three phase half wave uncontrolled rectifier uses ________ diodes. Three phase half wave uncontrolled rectifier requires ________ phase ______ wire power supply.
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iii) iv) v)
In a three phase half wave uncontrolled rectifier each diode conduct for _________ radians. The minimum frequency of the output voltage ripple in a three phase half wave uncontrolled rectifier is _________ times the input voltage frequency. The input line current of a three phase half wave uncontrolled rectifier contain ________ component.
Answers: (i) three; (ii) three, four; (iii) 2/3; (iv) three; (v) dc.
2. Assuming ripple free output current, find out the, displacement factor, distortion factor and power factor of a three phase half wave rectifier supplying an R L load. With reference to Fig 12.1 the expression for phase current ia can be written as i a = Id ia = 0 5 t 6 6 otherwise.
i a1 = 2 Ia1 sin(t + )
where
2 2 2 Ia1 = A1 + B1 and = tan 1
A1 B1
A1 =
1 2 i a cost dt 0 1 2 B1 = i a sint dt 0
1 A1 = 6 Id cost dt = 0 6
5
B1 =
1 6 3 Id I d sint dt = 6
2I a1 = B1 =
R.M.S value of ia = Ia =
Distortion factor =
Id 3
Ia1 3 = Ia 2
3 2
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12.3.1 Operation of a 3 phase full wave uncontrolled bridge rectifier supplying an R L E load
This type of load may represent a dc motor or a battery. Usually for driving these loads a variable output voltage is required. This requirement has to be met by using a variable ac source (e.g a 3 phase variable) since the average output voltage of an uncontrolled rectifier is constant for a given ac voltage. It will also be assumed in the following analysis that the load side inductance is large enough to keep the load current continuous. The relevant condition for continuous conduction will be derived but analysis of discontinuous conduction mode will not be attempted. Compared to single phase converters the cases of discontinuous conduction in 3 phase bridge converter are negligible.
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Since the load current is assumed to be continuous at least one diode from the top group (D1, D3 and D5) and one diode from the bottom group (D2, D4 and D6) must conduct at all time. It can be easily verified that only one diode from each group (either top or bottom) conducts at a time and two diodes from the same phase leg never conducts simultaneously. Thus the converter Version 2 EE IIT, Kharagpur 10
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has six different diode conduction modes. These are D1D2, D2D3, D3D4, D4D5, D5D6 and D6D1. Each conduction mode lasts for /3 rad and each diode conducts for 120. Fig. 12.2 (b) shows voltages across different diodes and the output voltage in each of these conduction modes. The time interval during which a particular conduction mode will be effective can be ascertained from this table. For example the D1D2 conduction mode will occur when the voltage across all other diodes (i.e. vba, vca and vcb) are negative. This implies that D1D2 conducts in the interval 0 t /3 as shown in Fig. 12.2 (c). The diodes have been numbered such that the conduction sequence is D1 D2 D3 D4 D5 D6 D1. When a diode stops conduction its current is commutated to another diode in the same group (top or bottom). This way the sequence of conduction modes become, D1D2 D2D3 D3D4 D4D5 D5D6 D6D1 D1D2 . The conduction diagram in Fig. 12.2 (c) is constructed accordingly. The output dc voltage can be constructed from this conduction diagram using appropriate line voltage segments as specified in the conduction table. The input ac line currents can be constructed from the conduction diagram and the output current. For example for 0 t /3 and 5/3 t 2 ia = io for 2/3 t 4/3 ia =  io otherwise. (12.6) ia = 0 The line current wave forms and their fundamental components are shown in Fig. 12.2 (c). It is clear from Fig 12.2 (c) that the dc voltage output is periodic over one sixth of the input ac cycle. For /3 t 2/3 v o = 2VL sin t
3 2/3 3 2 2VL sin t dt = VL /3
3 2/3 2 2VL sin 2 t dt /3
(12.7) (12.8)
VOAV =
VORMS =
3 3 = 1 + 2 VL
(12.9)
Ii RMS =
2 IOAV ; 3
IOAV =
VOAV E R
(12.10)
(12.11)
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Ii1 =
(12.12)
(12.13)
(12.14)
io = I1e
Where tan =
t  /3 tan
L ; R
(12.15)
Now since the current waveform is periodic over one sixth of the input ac cycle
2 i o t = = i o t = 3 3
(12.16)
2VL I1 + Z
I1 = 2VL Z
(12.17)
sin 1 e
3tan
(12.18)
(12.19)
Exercise 12.2
Fill in the blank(s) with the appropriate word(s). i) ii) iii) Three phase full wave uncontrolled rectifier uses _________ diodes. Three phase full wave uncontrolled rectifier does not require ________ wire connection. In a three phase full wave uncontrolled rectifier each diode conducts for _______ radians. Version 2 EE IIT, Kharagpur 12
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iv) v)
The minimum frequency of the output voltage ripple in a three phase full wave rectifier is _________ times the input voltage frequency. The input ac line current of a three phase full wave uncontrolled rectifiers supplying an R L E load contain only ________ harmonics but no ________ harmonic or __________ component. A three phase full wave uncontrolled rectifier supplying an R L E load normally operates in the ________ conduction mode.
vi)
Answers: (i) six; (ii) neutral; (iii) 2/3; (iv) six; (v) odd, tripler, dc; (vi) continuous.
2. A 220 V, 1500 rpm 20 A separately excited dc motor has armature resistance of 1 and negligible armature inductance. The motor is supplied from a three phase full wave uncontrolled rectifier connected to a 220 V, 3 phase, 50 Hz supply through a /Y transformer. Find out the transformer turns ratio so that the converter applies rated voltage to the motor. What is the maximum torque as a percentage of the rated torque the motor will be able to supply without over heating. Assume ideal transformer and continuous conduction.
Answer: Average output voltage of the converter is
3 2 VL = 220V VL = 163 Volts. This is the line voltage of the secondary side of the transformer. The secondary is star connected. So 163 Secondary phase voltage = = 94 volts . 3 Primary side is delta connected. So Primary phase voltage = 220 V. 220 = 2.34 :1 The required turns ratio = 94 V0 =
i0 =
I 0RMS
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2 = I 0AV +
To prevent over heating I0RMS = 20 A 2 V0RMS 2 For the given converter FF = = 1.00176 V0AV
2 202 = I 0AV +
2 I 0AV
In a separately excited dc machine Te I0AV Maximum allowable torque = 17.743 100 = 88.715 % of full load torque. 20
12.3.2 Operation of a three phase uncontrolled bridge rectifier supplying a capacitive load
A three phase uncontrolled bridge rectifier supplying a capacitive load is a very popular power electronic converter. It is very widely used as the front end of a variable voltage variable frequency dc ac inverter. Fig. 12.3 (a) shows the power circuit diagram of such a converter. Operation of the converter can be explained as follows. The top group diodes (D1, D3, D5) form a Maximum value circuit and therefore the maximum of the phase voltages van, vbn, vcn appears at the positive dc bus. On the other hand, the bottom group diodes (D2, D4, D6) form a Minimum value circuit. Therefore the minimum of the phase voltages van, vbn and vcn appears at the negative dc bus. Therefore, the output voltage waveform at any instant is equal to the maximum of the six line voltages vab, vbc, vca, vba, vcb and vac provided at least one diode from the top group and one from the bottom group conducts at that instant. None of the diodes will conducts, however if the output capacitor voltage is larger than the maximum line voltage. All the six operating modes of a 3 phase bridge rectifier namely, D1D2, D2D3, D3D4, D4D5, D5D6 and D6D1 appear in that order. In addition an additional operating mode in which none of the diodes conduct appears in the conduction diagram as shown in Fig. 12.3 (b). During these periods the output capacitor discharges through the load. As the capacitor voltage decreases its voltage becomes equal to the incoming line voltage. At this instant the appropriate diodes from both the top and the bottom group starts conducting and continuous to do so till the sum of the capacitor charging current and the load current becomes zero.
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v o = 2VL sin t
dvo = 2VL c cos t dt v V i o = o = 2 L sin t R R VL ii = i o + i c = 2 [ RC cos t + sin t ] R V = 2 L 1+ 2 R 2 C2 cos (t  ) R 1 Where tan = RC ic = c At t = , ii = 0 cos (  ) = 0 in the interval t + /3 c dvo v o + =0 dt R
RC 1+ 2 R 2 C 2
(12.23)
or =
+ 2
(12.24)
(12.25)
vo = vo e
= 2VL
RC 1+ 2 R 2 C 2
(t  ) RC
(12.26)
at t = + /3
v o = 2VL RC 1+ 2 R 2 C 2 e
/6  + RC
(12.27)
Also at t = + /3
v o = 2VL sin t  3 t = +
= 2VL sin
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sin =
RC 1+ R C
2 2 2
1 /6  + tan 1 RC
RC
(12.28)
From which the value of can be found. Equation 12.23 gives the expression of the output current ii of the rectifier. It is observed that ii is discontinuous and contains large ripple. This is a major disadvantage of this converter. This ripple is also reflected in the input current of the rectifier as shown in Fig 12.3 (b). However, the displacement factor of the converter still remains unity. The current ii can be made continuous by connecting an inductor of appropriate value between the rectifier and the capacitor. Analysis of such a converter is similar to a converter V supplying an R L E load where the value of E is 3 2 L .
Exercise 12.3
Fill in the blank(s) with the appropriate word(s) i) ii) iii) iv) v) A three phase full wave uncontrolled rectifier supplying a capacitive load can operate in the _________ conduction mode. The output _________ ripple factor of a three phase full wave uncontrolled rectifier supplying a capacitive load is very low. The output _________ ripple factor of a three phase full wave uncontrolled rectifier supplying a capacitive load is very high. The input current displacement factor of a three phase full wave uncontrolled rectifier supplying a capacitive load is ___________. The input current distortion factor of a three phase full wave uncontrolled rectifier supplying a capacitive load is very ________.
Answers: (i) discontinuous; (ii) voltage; (iii) current; (iv) unity; (v) high.
2. A three phase full wave rectifier operates from 220 volts, three phase 50 Hz supply and supplies a capacitive resistive load of 20 Amps. An inductor of negligible resistance is inserted between the rectifier and the capacitor. Assuming the capacitor to be large enough so that the output voltage is almost ripple free. Calculate the value of the inductor so that the rectifier output current is continuous.
Answers: The following figure shows the circuit arrangement and the corresponding waveforms.
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Since the conduction is continuous V0 3 3 2 = or = 72.73 V0 = VL and sin = 2VL In the interval 2 t 3 3 di v0 + L L = 2VL sint dt
3 2 VL
Now
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I0 
3VL 3 2 1 2 3 VL = 20A or I 0 = 20 + L 2 3 2L
2VL 3 3  cost  t L 2 For just continuous conduction iL = 0 at t = 2VL 3 3 0 = 20 +  cos  L 2 or L = 1.0306 or L = 3.28 mH. i L = 20 +
References
[1] [2] Power Electronics, P.C. Sen; Tata MC Grawhill publishing company limited; 1995. Power Electronics, Converters, Applications and Design; Mohan, Undeland, Robbins; John Willey and Sons Ine, Third Edition, 2003.
Lesson Summary
Three phase uncontrolled rectifiers are available in half wave and full wave configuration. Three phase uncontrolled half wave rectifier require three phase four wire power supply. The input ac line current in a three phase uncontrolled half wave rectifier contain dc component which may cause dc saturation of input transformer. Three phase full wave uncontrolled rectifier is most widely used in the medium power applications particularly as the input stage of the dc link inverter. Three phase full wave uncontrolled rectifier uses six diodes instead of three of the half wave rectifier. Full bridge rectifier does not require neutral connection. The output voltage of a three phase full bridge rectifier contains multiplies of 6th harmonic of input cycle. The input ac current of a three phase full bridge rectifier contain only odd harmonics but no dc component or triplen harmonics. The input displacement factor of the three phase bridge rectifier is always unity. Three phase full bridge converter supplying an R L E load usually operate in the continuous conduction mode. Compared to single phase rectifiers, three phase bridge converter require smaller inductor to obtain the same output current ripple factor. Version 2 EE IIT, Kharagpur 19
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Three phase bridge rectifier supplying a capacitive load has very good output voltage form factor but very poor input current THD. Compared to single phase converters three phase bridge rectifier require smaller capacitor to obtain a given output voltage form factor.
Q2.
Q3.
R LOAD
2 V0AV = R LOAD
V0AV =
When the inductor is shorted 2 V0RMS PL = R LOAD Now from Equ. (12.2) V0RMS =
1 3 + VL = 151.01 volts 3 4
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2. To run at rated speed at full load the motor terminal voltage must be 200 volts.
3 2 VL = 200 volts, VL = 148.1 volts Where VL is the secondary line voltage. Secondary is star connected. So secondary phase voltage V0AL =
V2 =
VL = 85.5 volts 3
Primary is delta connected. So primary phase voltage V1 = 220 V V Required turns ratio = 1 = 1: 0.38865 2 At 50% of the full load torque motor current is 25 Amps back Emf = 200 0.5 25 = 187.5 Volts. 187.5 1500 = 1607 RPM . speed at 50% of full load torque = 200  0.550 At 50% of full load torque the motor operates in the continuous conduction mode, with reference to Fig. 12.2 and equation 12.19.
t /3 2VL sin  tan sin e + sin( t ) z cos 3tan 1 e E 187.5 = = 0.9375 Where sin = 200 2VL = 69.64 = 1.2154 rad.
i0 =
i 0 Min = i 0 t = = 0
sin 1 e OR
3tan
(  /3)
tan
+ sin(  ) 
sin =0 cos
( /3  )
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( /3  )
OR
sin2
tan 3tan
 sin(  2) = sin
V0Max = 2VL = 2 220 V = 311 volts From Fig. 12.3, V0Min = 295.943 Volts V0AV = 303.47 V. R = 6.0694 . I0AV = 50 Amps
From Fig. 12.3. V0Min occurs at t = V0Min = 2VLsin = 295.943 sin = 0.9512 or = 72 But from Equation (12.28)
sin = cos e 6 1 where tan = RC from which = 3.5 tan = 0.06116 1 R = 6.0694 RC = = 16.35 , tan C = 2.6938, C = 8575 F. tan  +
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Module 2
AC to DC Converters
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Lesson 13
Operation and Analysis of the Three Phase Fully Controlled Bridge Converter
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Instructional Objectives
On completion the student will be able to Draw the circuit diagram and waveforms associated with a three phase fully controlled bridge converter. Find out the average, RMS valves and the harmonic spectrum of the output voltage / current waveforms of the converter. Find out the closed form expression of the output current and hence the condition for continuous conduction. Find out the displacement factor, distortion factor and the power factor of the input current as well as its harmonic spectrum. Analyze the operation of higher pulse number converters and dual converter. Design the triggering circuit of the three phase fully controlled bridge converter.
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13.1 Introduction
The three phase fully controlled bridge converter has been probably the most widely used power electronic converter in the medium to high power applications. Three phase circuits are preferable when large power is involved. The controlled rectifier can provide controllable out put dc voltage in a single unit instead of a three phase autotransformer and a diode bridge rectifier. The controlled rectifier is obtained by replacing the diodes of the uncontrolled rectifier with thyristors. Control over the output dc voltage is obtained by controlling the conduction interval of each thyristor. This method is known as phase control and converters are also called phase controlled converters. Since thyristors can block voltage in both directions it is possible to reverse the polarity of the output dc voltage and hence feed power back to the ac supply from the dc side. Under such condition the converter is said to be operating in the inverting mode. The thyristors in the converter circuit are commutated with the help of the supply voltage in the rectifying mode of operation and are known as Line commutated converter. The same circuit while operating in the inverter mode requires load side counter emf. for commutation and are referred to as the Load commutated inverter. In phase controlled rectifiers though the output voltage can be varied continuously the load harmonic voltage increases considerably as the average value goes down. Of course the magnitude of harmonic voltage is lower in three phase converter compared to the single phase circuit. Since the frequency of the harmonic voltage is higher smaller load inductance leads to continuous conduction. Input current wave shape become rectangular and contain 5th and higher order odd harmonics. The displacement angle of the input current increases with firing angle. The frequency of the harmonic voltage and current can be increased by increasing the pulse number of the converter which can be achieved by series and parallel connection of basic 6 pulse converters. The control circuit become considerably complicated and the use of coupling transformer and / or interphase reactors become mandatory. With the introduction of high power IGBTs the three phase bridge converter has all but been replaced by dc link voltage source converters in the medium to moderately high power range. However in very high power application (such as HV dc transmission system, cycloconverter drives, load commutated inverter synchronous motor drives, static scherbius drives etc.) the basic B phase bridge converter block is still used. In this lesson the operating principle and characteristic of this very important converter topology will be discussed in source depth.
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For any current to flow in the load at least one device from the top group (T1, T3, T5) and one from the bottom group (T2, T4, T6) must conduct. It can be argued as in the case of an uncontrolled converter only one device from these two groups will conduct. Then from symmetry consideration it can be argued that each thyristor conducts for 120 of the input cycle. Now the thyristors are fired in the sequence T1 T2 T3 T4 T5 T6 T1 with 60 interval between each firing. Therefore thyristors on the same phase leg are fired at an interval of 180 and hence can not conduct simultaneously. This leaves only six possible conduction mode for the converter in the continuous conduction mode of operation. These are T1T2, T2T3, T3T4, T4T5, T5T6, T6T1. Each conduction mode is of 60 duration and appears in the sequence mentioned. The conduction table of Fig. 13.1 (b) shows voltage across different devices and the dc output voltage for each conduction interval. The phasor diagram of the line voltages appear in Fig. 13.1 (c). Each of these line voltages can be associated with the firing of a thyristor with the help of the conduction table1. For example the thyristor T1 is fired at the end of T5T6 conduction interval. During this period the voltage across T1 was vac. Therefore T1 is fired angle after the positive going zero crossing of vac. Similar observation can be made about other thyristors. The phasor diagram of Fig. 13.1 (c) also confirms that all the thyristors are fired in the correct sequence with 60 interval between each firing. Fig. 13.2 shows the waveforms of different variables (shown in Fig. 13.1 (a)). To arrive at the waveforms it is necessary to draw the conduction diagram which shows the interval of conduction for each thyristor and can be drawn with the help of the phasor diagram of fig. 13.1 (c). If the converter firing angle is each thyristor is fired angle after the positive going zero crossing of the line voltage with which its firing is associated. Once the conduction diagram is drawn all other voltage waveforms can be drawn from the line voltage waveforms and from the conduction table of fig. 13.1 (b). Similarly line currents can be drawn from the output current and the conduction diagram. It is clear from the waveforms that output voltage and current waveforms are periodic over one sixth of the input cycle. Therefore this converter is also called the six pulse converter. The input current on the other hand contains only odds harmonics of the input frequency other than the triplex (3rd, 9th etc.) harmonics. The next section will analyze the operation of this converter in more details.
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Exercise 13.1
Fill in the blank(s) with the appropriate word(s) i) The three phase fully controlled bridge converter is obtained by replacing six _________ of an uncontrolled converter by six __________. Version 2 EE IIT, Kharagpur 7 www.jntuworld.com
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ii) The pulse number of a three phase fully controlled bridge converter is _________. iii) In a three phase fully controlled converter each device conducts for an interval of __________ degrees. iv) In a three phase fully controlled converter operating in continuous conduction there are ________ different conduction modes. v) The output voltage of a three phase fully controlled converter operating in the continuous conduction mode consists of segments of the input ac ________ voltage. vi) The peak voltage appearing across any device of a three phase fully controlled converter is equal to the ________ input ac ________ voltage. vii) The input ac current of a three phase fully controlled converter has a ________ step waveform. viii) The input ac current of a three phase fully controlled converter contains only _________ harmonics but no _________ harmonic. ix) A three phase fully controlled converter can also operate in the _________ mode. x) Discontinuous conduction in a three phase fully controlled converter is _________. Answers: (i) diodes, thyristors; (ii) six; (iii) 120; (iv) six; (v) line; (vi) peak, line; (vii) six; (viii) odd, tripler; (ix) inverting; (x) rare.
v0 = V0 +
V0 =
=
K=1,2
AK
cos 6 Kt +
K=1,2
BK
sin 6 Kt
(13.1)
+ 3 + 3 2 3 3 v d t = V sin t + dt 0 L 3
3 2 VL cos
(13.2)
VAK
(13.3)
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VBK =
(13.4)
1
V0RMS =
3 3 2 2 v0 dt = VL 1+ cos2 4
ia = 0
2 4 t + 3 3 5 + t + 2 3 otherwise
From Fig. 13.2 it can be observed that i0 itself has a ripple at a frequency six times the input frequency. The closed from expression of i0, as will be seen later is some what complicated. However, considerable simplification in the expression of ia can be obtained if i0 is replaced by its average value I0. This approximation will be valid provided the ripple on i0 is small, i.e, the load is highly inductive. The modified input current waveform will then be ia which can be expressed in terms of a fourier series as
I A0 i a ia = + I An cos nt + I Bn sin nt 2 n=1 n=1
(13.5)
Where
I A0 = I An 1 +2 i a d t = 0 2 1 +2 = i a cos nt n0 4I n n = 0 cos sin cos n n 6 2
K
(13.6)
(13.7)
I An = ( 1)
2 3I 0 sin K cos ( 6K 1) 2 ( 6K 1)
(13.8)
for n = 6K 1, K = 0, 1, 2, 3 ....
IAn = 0
otherwise.
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I Bn =
(13.9)
I Bn = ( 1)
2 3I 0 sin K sin ( 6K 1) 2 ( 6K 1)
(13.10)
for n = 6K 1, K = 0, 1, 2, ....
IBn = 0
otherwise. (13.11)
(13.12)
2 3 I0 = 3
(13.16)
The closed form expression for i0 in the interval t + in this interval di Ri 0 + L 0 + E = v0 = 2VLsin t + dt 3
i 0 = I1e
(13.17) (13.18)
Where
( t  )
(13.19)
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( t  )
(13.20)
i 0 t= = i 0 t = +
I1 + = I1e

(13.21)
2VL Z
3tan
OR
I1 =
(13.22)
(13.23)
To find out the condition for continuous conduction it is noted that in the limiting case of continuous conduction. then i0 is minimum at t = . Condition i 0 min=0 , Now if + 3 for continuous conduction is i0 t= 0 . However discontinuous conduction is rare in these conversions and will not be discussed any further.
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Analysis of the converter in the inverting mode is similar to its rectifier mode of operation. The same expressions hold for the dc and harmonic compounds in the output voltage and current. The input supply current Fourier series is also identical to Equation 13.8. In particular 3 2 VL cos 2 3 i a1 = I0 cos(t  ) V0 = (13.24) (13.25)
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For values of in the range 90 < < 180 it is observed from Fig. 13.3(b) that the average dc voltage is negative and the displacement angle of the fundamental component of the input ac line current is equal to > 90. Therefore, power in the ac side flows from the converter to the source. It is observed form Fig. 13.3(b) that an outgoing thyristor (thyristor T6 in Fig. 13.3(b)) after commutation is impressed with a negative voltage of duration = . For successful commutation of the outgoing thyristor it is essential that this interval is larger than the turn off time of the thyristor i.e,
tq , tq is the thyristor turn off time
Therefore
 tq or  tq .
Which imposes an upper limit on the value of . In practice this upper value of is further reduced due to commutation overlap.
Exercise 13.2
1. A three phase fully controlled bridge converter operating from a 3 phase 220 V, 50 Hz supply is used to charge a battery bank with nominal voltage of 240 V. The battery bank has an internal resistance of 0.01 and the battery bank voltage varies by 10% around its nominal value between fully charged and uncharged condition. Assuming continuous conduction find out. (i) (ii) (iii) The range of firing angle of the converter. The range of ac input power factor. The range of charging efficiency.
When the battery bank is charged with a constant average charging current of 100 Amps through a 250 mH lossless inductor.
Answer: The maximum and minimum battery voltages are, VB Min = 0.9 VB Nom = 216 volts and VB Max = 1.1 VB Nom = 264 volts respectively.
Since the average charging current is constant at 100 A. V0 Max = VB Max + 100 RB = 264 + 100 0.01 = 265 volts V0 Min = VB Min + 100 RB = 216 + 100 0.01 = 217 volts. (i) But
V0 Max = 3 2 VL cos Min V0 Min = 3 2 VL cos Max
(ii)
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Max
(iii)
But I
2 0RMs
For = Min VA1 = 0.439 V, VA2 = 10.76, VB1 = 48.48 V, VB2 = 20.15 V, I1 = 0.073 Amps I2 = 0.017 Amps.
At Min,
Charging efficiency =
2 2 I0RMs I0
Charging efficiency =
2. A three phase fully controlled converter operates from a 3 phase 230 V, 50 Hz supply through a Y/ transformer to supply a 220 V, 600 rpm, 500 A separately excited dc motor. The motor has an armature resistance of 0.02 . What should be the transformer turns ratio such that the converter produces rated motor terminal voltage at 0 firing angle. Assume continuous conduction. The same converter is now used to brake the motor regeneratively in the reverse direction. If the thyristors are to be provided with a minimum turn off time of 100 s, what is the maximum reverse speed at which rated braking torque can be produced.
Answer: From the given question 3 2 V = 220 VL = 162.9 V L Where VL is the secondary side line and also the phase voltage since the secondary side is connected.
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Primary side phase voltage = 230 V = 132.79 V 3 132.79 Turns ratio = = 1:1.2267 . 162.9 During regenerative braking in the reverse direction the converter operates in the inverting mode.
tq
Min
= 100S
Min = tq
Min
= 1.8o
Max = 180 Min = 178.2 Maximum negative voltage that can be generated by the converter is
3 2 V cos 178.2o =  219.89 V L For rated braking torque Ia = 500 A
Eb = Va Iara =  229.89 V. At 600 RPM Eb = 220 500 0.02 = 210 V. Max reverse speed is 229.89 600 = 656.83 RPM . 210
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Fig. 13.4(a) schematically represents series connection of two six pulse converters where as Fig. 13.4(b) can be considered to be a parallel connection. The inductance in between the converters has been included to limit circulating harmonic current. In both these figures CONV I and CONV II have identical construction and are also fired at the same firing angle . Their input supplies also have same magnitude but displaced in phase by an angle . Then one can write 3 2 v 01 = VL cos + VAK cos 6 Kt + VBK sin 6 Kt (13.26) K=1 K=1
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v02 =
(13.27)
6 2 VL cos +
(13.28)
Now if cos 3K = 0 for some K then the corresponding harmonic disappear from the fourier series expression of v0. In particular if = 30 then cos 3K = 0 for K = 1, 2, 3, 5. This phase difference can be obtained by the arrangement shown in Fig. 13.4(c). Then
v0 =
(13.29)
It can be seen that the frequency of the harmonics present in the output voltage has the form 12, 24, 36 .. Similarly it can be shown that the input side line current iABC have harmonic frequency of the form 11, 13, 23, 25, 35, 37, . Which is the characteristic of a 12 pulse converter. In a similar manner more number of 3 phase 6 pulse converters can be connected in series / parallel and the angle can be adjusted to obtain 18 and 24 pulse converters. One of the shortcomings of a three phase fully controlled converter is that although it can produce both positive and negative voltage it can not supply current in both directions. However, some applications such as a four quadrant dc motor drive require this capability from the dc source. This problem is easily mitigated by connecting another three phase fully controlled converter in anti parallel as shown in Fig. 13.5 (a). In this figure converterI supplies positive load current while converterII supplies negative load current. In other words converterI operates in the first and fourth quadrant of the output v i plane whereas converterII operates in the third and fourth quadrant. Thus the two converters taken together can operate in all four quadrants and is capable of supplying a four quadrant dc motor drive. The combined converter is called the Dual converter.
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Obviously since converterI and converterII are connected in antiparallel they must produce the same dc voltage. This requires that the firing angles of these two converters be related as 2 = 1 (13.30)
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Although Equations 13.30 ensures that the dc voltages produced by these converters are equal the output voltages do not match on an instantaneous basis. Therefore to avoid a direct short circuit between two different supply lines the two converters must never be gated simultaneously. ConverterI receives gate pulses when the load current is positive. Gate pulses to converterII are blocked at that time. For negative load current converterII thyristors are fired while converterI gate pulses are blocked. Thus there is no circulating current flowing through the converters and therefore it is called the noncirculating current type dual converter. It requires precise sensing of the zero crossing of the output current which may pose a problem particularly at light load due to possible discontinuous conduction. To overcome this problem an interphase reactor may be incorporated between the two converters. With the interphase reactor in place both the converters can be gated simultaneously with 2 = 1. The resulting converter is called the circulating current type dual converter.
13.4 Gate Drive circuit for three phase fully controlled converter
Several schemes exist to generate gate drive pulses for single phase or three phase converters. In many application it is required that the output of the converter be proportional to a control voltage. This can be achieved as follows. In either single or three phase converters V0 cos or = cos1 V0 K1 To get V0 v c = cos 1 Vc K
(13.31) (13.32)
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In the circuit of Fig. 13.6(a) a phase shift network is used to obtain a waveform leading vi by 90. The phasor diagram of the phase shift circuit is shown in Fig. 13.6(b). The output of the phase shift waveform (and its inverse) is compared with vc. The firing pulse is generated at the point when these two waveforms are equal. Obviously atthis instant
vc Vs cos
or
= cos1 vc Vs
(13.33)
Therefore this method of generation of converter firing pulses is called inverse cosine control. The output of the phase shift network is called carrier waveform. Similar technique can be used for three phase converters. However the phase shift network here consists of a three phase signal transformer with special connections as shown in Fig. 13.7.
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The signal transformer uses three single phase transformer each of which has two secondary windings. The primary windings are connected in delta while the secondary windings are connected in zigzag. From Fig. 13.1 (c) T2 is fired angle after the positive going zero crossing of vbc. Therefore, to implement inverse cosine the carrier wave for T2 must lead vbc by 90. This waveform is obtained from zigzag connection of the winding segments a1a2 and c1c2 as shown in Fig. 13.7(a). The same figure also shows the zigzag connection for other phase. The voltage across each zigzag phase can be used to fire two thyristors belonging to the same phase leg using a circuit similar to Fig. 13.6 (a). The phase shift network will not be required in this case.
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Exercise 13.3
1. Fill in the blank(s) with the appropriate word(s) i) Higher pulse number converters can be realized by __________ and _______ connection of six pulse converters. ii) Constituent six pulse converters of a 12 pulse converter have _________ firing angles. iii) The input supply voltages to the converters of a 12 pulse converter have ________ magnitudes and are phase shifted from one another by _________ degrees. iv) The input supply to a 12 pulse converter can be obtained through a _________ connected transformer. v) Dual converters are used for supplying ________ quadrant dc motor drives. vi) In a dual converter if one converter is fired at an angle the other has to be fired at _________. vii) In ___________ current dual converter only one converter conducts at any time. viii) In a circulating current type dual converter an __________ is used between the converters to limit the circulating current. ix) To obtain a linear control relation between the control voltage and the output dc voltage of a converter ___________ control logic is used. x) In a three phase fully controlled converter the carrier waves for firing pulse generation are obtained using three ___________ connected single phase transformers.
Answers: (i) Series, parallel; (ii) same, (iii) equal, 30, (iv) star star delta; (v) four; (vi)  , (vii) noncirculating ; (viii) inductor, (ix) inversecosine; (x) deltazigzag.
2. A 220V, 750 RPM, 200A separately excited dc motor has an armature resistance of 0.05 . The armature is fed from a three phase non circulating current dual converter. If the forward converter operates at a firing angle of 70 i) At what speed will the motor deliver rated torque. ii) What should be the firing angle in the regenerative braking mode when the motor delivers half the rated torque at 600 rpm. Assume continuous conduction. Supply voltage is 400 V.
Answer:
i) The output voltage = 3 2 400 cos 70o = 184.7 V Version 2 EE IIT, Kharagpur 24
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ii) E b
600RPM
3. What will happen if the signal transformers generating the carrier wave have delta double star connection instead of deltazigzag connection.
Answer: With deltadouble star connection of the signal transformers the carrier wave forms will be in phase with the line voltage waveforms. Therefore, without a phase shift network it will not be possible to generate carrier waveforms which are in quadrature with the line voltages. Hence inverse casine control law cannot be implemented.
References
1. Power Electronics; P.C. Sen; TataMcGrawhill publishing company limited; 1995. 2. Power Electronics, Converters, Applications and Design, Mohan, Undeland, Robbins; John Willey and Sons Inc; Third Edition, 2003.
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Lesson Summary
A three phase fully controlled converter is realized by replacing the diodes of an uncontrolled converter with thyristors. A three phase fully controlled converter can operate either as a rectifier or as an inverter. The output voltage of a three phase fully controlled converter contains multiple of sixth harmonic of the input frequency in addition to the dc component. The input current of a three phase fully controlled converter contains only odd harmonics other than tripler harmonics. The input current displacement factor of a three phase fully controlled converter is cos . being the firing angle. In the continuous conduction mode a three phase fully controlled converter may operate in the inverting mode by increasing beyond 90. In the inverting mode the firing angle should be less than 180 for safe commutation of the thyristors. Several units of three phase fully controlled converters can be connected in series parallel to form higher pulse number (12, 18, 24 etc) converters. In higher pulse number converters all component converters are fired at the same firing angle while their input supplies are phase shifted from one another by a predetermined angle. Two three phase fully controlled converter can be connected in anti parallel to form a dual converter which can operate in all four quadrants of the VI plane. Dual converters can be of circulating and non circulating current type. Fully controlled converters employ inverse casine control strategy for generating firing pulses which gives linear relationship between the output voltage and the control voltage. In a three phase fully controlled converter, a three phase delta/zigzag connected signal transformer is used to generate the required carrier waves for this purpose.
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1.
The figure above shows the output voltage with = 90 and a resistive load. Since the load is resistive the load current becomes zero when the voltage becomes zero. Both the voltage and amount remains zero thereafter till the next thyristor is fired. Therefore for 5 t 6 Version 2 EE IIT, Kharagpur 27
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P0 =
V0
2 RMS
= VL 1 3 5 cos2t dt 2 6
= 183 Watts
= VL 1 3 3 2 4 = 67.65 V
2. To hold the overhauling load the motor must operate in the regenerative braking mode. At 1000 RPM Eb = 220  50 0.2 1000 = 140 volts 1500 To supply full load torque, the motor armature current = 50 A. Supply voltage = Va = Eb + Iara = 140 + 50 0.2 = 150 V in the reverse direction.
3 2 VL cos =  150V
= 118.9.
3. With reference to the conduction diagram of problem 1 it can be seen that the load current becomes zero 30 after a new thyristor is fired (for example, T2). Therefore, both the conducting thyristor (T1 and T2 in this case) turns off. However, when T3 is fired the converter will be unable to resume operation from T2T3 mode unless T2 is fired simultaneously. Similar explanation holds for all other thyristor firing. Therefore, to ensure that the converter operates properly even under discontinuous load current condition the final gate pulse for a particular thyristors must be generated by logically ANDing the outputs of its own firing circuit with the output of the firing circuit of the thyristor in the commutation sequence as shown in the table next below To generate the gate pulse of : T1 T2 T3 T4 T5 T6 AND the outputs of : T1 & T2 T2 & T3 T3 & T4 T4 & T5 T5 & T6 T6 & T1
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Module 2
AC to DC Converters
Version 2 EE IIT, Kharagpur 1 www.jntuworld.com
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Lesson 14
Operation and Analysis of Three Phase Half Controlled Converter
Version 2 EE IIT, Kharagpur 2 www.jntuworld.com
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Instructional Objectives
On completion the student will be able to Draw the circuit diagram and waveforms of different variables associated with a three phase half controlled converter. Identify the constructional and operational difference between a three phase fully controlled and half controlled converter. Calculate the average and RMS value of the output dc voltage. Calculate the displacement factor, distortion factor and power factor of the input ac line current. Calculate the Fourier series components of the output voltage and input current waveforms. Derive the closed form expression for output dc current and hence identify continuous or discontinuous conduction mode of the converter.
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14.1 Introduction
Three phase fully controlled converters are very popular in many industrial applications particularly in situations where power regeneration from the dc side is essential. It can handle reasonably high power and has acceptable input and output harmonic distortion. The configuration also lends itself to easy series and parallel connection for increasing voltage and current rating or improvement in harmonic behavior. However, this versatility of a three phase fully controlled converters are obtained at the cost of increased circuit complexity due to the use of six thyristors and their associated control circuit. This complexity can be considerably reduced in applications where power regeneration is not necessary. In that case three thyristors of the top group or the bottom group of a three phase fully controlled converter can be replaced by three diodes. The resulting converter is called a three phase half controlled converter. Replacing three thyristors by three diodes reduces circuit complexity but at the same time prevents negative voltage appearing at the output at any time. Therefore the converter cannot operate in the inverting mode. The three phase half controlled converter has several other advantages over a three phase fully controlled converter. For the same firing angle it has lower input side displacement factor compared to a fully controlled converter. It also extends the range of continuous conduction of the converter. It has one serious disadvantage however. The output voltage is periodic over one third of the input cycle rather than one sixth as is the case with fully controlled converters. This implies both input and output harmonics are of lower frequency and require heavier filtering. For this reason half controlled three phase converters are not as popular as their fully controlled counterpart. Although, from the point of view of construction and circuit complexity the half controlled converter is simpler compared to the fully controlled converter, its analysis is considerably more difficult. In this lesson the operating principle and analysis of a three phase half controlled converter operating in the continuous conduction mode will be presented.
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Now consider the conducting and blocking state of D2. In the blocking state the voltage across D2 is either vac or vbc. Hence, D2 can block only when these voltages are negative. Taking vbc as the reference phasor (i.e., v bc = 2VL sint ) D2 will block during 2/3 t 2 and will conduct in the interval 0 t 2/3 . Similarly it can be shown that D4 and D6 will conduct during 2/3 t 4 /3 and 4/3 t 2 respectively. Next consider conduction of T1. The firing sequence of the thyristor is T1 T3 T5. Therefore before T1 comes into conduction T5 conducts and voltage across T1 is v ac = 2VL sin (t + /3) . If the firing angle of T1 is then T1 starts conduction at t =  /3 and conducts upto + /3 . Similarly T3 and T5 conducts during + /3 t + and + t 2 +  /3 . From this discussion the following conduction diagrams can be drawn for continuous conduction mode.
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Exercise 14.1
Fill in the blanks(s) with appropriate word(s). i. A three phase half controlled converter has ________________ thyristors and ________________ diodes. ii. A three phase half controlled converter has ________________ conduction modes as compared to ________________ of a fully controlled converter. iii. A three phase half controlled converter can not operate in the ________________ mode. iv. Unlike a three phase fully controlled converter the devices in the ________________ phase leg of a half controlled converter can conduct at a given time. These conduction modes are called ________________ modes. v. In a three phase half controlled converter only ________________ conduction modes appear at the same time. Version 2 EE IIT, Kharagpur 6 www.jntuworld.com
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vi. ________________ modes appear only when the firing angle of the converter is greater than ________________ degrees. vii. In a three phase half controlled converter the diodes conduct in a manner similar to a ________________ converter where as the thyristors conducts similar to a ________________ converter. viii. The input current of a three phase half controlled converter does not have ________________ cycle symmetry. Answer: (i) three, three; (ii) nine, six; (iii) inverter; (iv) same, free wheeling; (v) six; (vi) free wheeling, 60; (vii) uncontrolled, controlled; (viii) quarter.
Conduction interval T1D6 exists only if 3 Conduction interval T1D4 exists only if > 3 So for 3 In the interval  t 0 3 v0 = vab = 2VL sin t + 2 3 0 t + 3 v0 = vac = 2VL sin t + 3 + 3 2VL 0 3 V0 = sin t + 2 d t+ sin t + d t  0 2 3 3 3
(14.1)
(14.2)
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= or, For
for
3 2VL cos +  cos 2 + cos  cos + 2 2 3 3 3 3 3 2 V0 = VL (1 + cos) 2 In the interval  t 2 > , 3 3 3 v0 = vac = 2VL sin t + 3 2 t + 3 3 v0 = 0
(14.3) (14.4)
(14.5)
(14.6)
V0 =
RMS value of v0 can be found in a similar manner and is left as an exercise. From the waveforms of Fig. 14.2, v0 is periodic over one third of the input cycle. Therefore one can write
For From equations 14.1 and 14.2 3 0 + 3 VAn = 2VL sin t + 2 cos3ntdt + 2VL 3 sin t + cos3ntdt 0 3 3 3 0  sin (3n + 1)t + 2 + sin (1  3n)t + 2 dt 3 3 3 2VL 3 = 2 + 3 sin (3n + 1)t +  sin (3n 1)t  dt + 0 3 3
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0 3 cos (3n + 1) t + 2 /3 cos {(3n  1)t  2 /3} { } + 3n + 1 3n  1 0 3 2VL 3 = 2 0 + cos {(3n + 1)t + /3} cos {(3n  1)t  /3} 3 + + 3n + 1 3n  1 + 0 3
(14.11)
Therefore
1 + cos [ (3n + 1)(  /3) + 2 /3]  cos [ (3n + 1)( + /3) + /3] 3 2VL 3n + 1 VAn = 2 cos [ (3n  1)( + /3)  /3]  cos [ (3n  1)(  /3)  2/3] 1 + 3n  1 1  2sin [ (3n + 1) + /2] sin [ /6  (3n + 1) /3] 3 2VL 3n + 1 = 2 1 + 2sin [ (3n  1)  /2] sin [ /6 + (3n  1) /3] 3n  1 3 2VL 1+ 2sin(6n + 1) /6 cos(3n + 1) 1 2sin(6n  1) /6 cos(3n  1) = 2 3n + 1 3n  1
=
Similarly,
(14.12)
VBn =
(14.13)
or,
0  cos (3n  1)t  2  cos (3n + 1)t + 2 dt 3 3 3 2VL 3 VBn = 2 + 3 cos (3n  1)t   cos (3n + 1)t + dt + 3 3 0
0 sin {(3n  1)t  2/3} 0 sin {(3n + 1)t + 2/3} 3n  1 3n + 1 3 2VL 3 3 = 2 + + + sin {(3n  1)t  /3} 3  sin {(3n + 1)t + /3} 3 3n  1 3n + 1 0 0
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sin [ (3n  1)( + /3)  /3]  sin [ (3n  1)(  /3)  2/3] 3 2VL 3n  1 = 2 sin [ (3n + 1)( + /3) + /3]  sin [ (3n + 1)(  /3) + 2 /3] 3n + 1 cos [ (3n  1)  /2] sin [ /6 + (3n  1) /6] 3 2VL 3n  1 = cos [ (3n + 1) + /2] sin [ (3n + 1) /6  /6] 3n + 1 3 2VL sin(3n + 1) sin(3n  1) n = + sin 3n + 1 3n  1 2
VBn = 3 2 n sin(3n + 1) sin(3n  1) VL sin + 2 3n + 1 3n  1 (14.14)
Similar analysis can be done for > 3 To find out the Fourier series of the input ac line current the load may be replaced by a constant current source having the same value as the average load current. This approximation will be valid provided the load current ripple is relatively small. With this assumption the last waveform of Fig. 14.2(b) can be redrawn as follows.
 t 2 3 3 + t 4 3 3 otherwise
ia = I0 ia =  I0 ia = 0
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i a = [ I an cos nt + I bn sin nt ]
n=1
2 I an = 1 i a cos nt dt 0 2 = 1 3 I 0 cos nt dt  3
(14.15)
I0 cos nt dt 4 I0 sin nt 2 3 3 sin n t = n  n + 3 3 I0 2n = sin  sin n  + sin n +  sin 4n n 3 3 3 3 2I0 2n = sin + cos n sin n n 3 3
+ 3
4 3
( )
or,
Ian =
(14.16)
2 I bn = 1 i a sin nt dt 0 2 = 1 3 I 0 sin nt dt  3
+ 3
4 3
( )
(14.17)
(14.18) (14.19)
(14.20)
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(14.21)
A closed form expression for i0 can be found as follows v0 = vac In the interval 0 < t + 3 di L 0 + Ri0 + E = vac = 2VL sin t + dt 3 t 2VL i 0 = Ie tan + sin t +   sin cos Z 3 Where tan = L , Z = R 2 + 2 L2 and E = 2VL sin R At t = + 3 ( + /3) 2VL i 0 = I1 = Ie tan + sin  + 2  sin cos Z 3
(14.25)
In the interval + t 2 3 3 L
v0 = vbc
(14.26) (14.27)
2VL sin (  ) Z ( t ) ( t   /3) 2VL sin tan i 0 = Ie + sin (  ) e tan + sin ( t  ) Z cos
I2 = Ie
tan
( + /3)
i0
t = 2 3
= Ie
2 3tan
2VL Z
i0
t =
2 3
= i0
t = 0
= I+
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 2 I 1  e 3tan =
(  /3) 2VL sin (  ) e tan + sin Z for 0 < t + 3 ( t   /3)  t tan 2VL sin e tan e sin i0 = sin (  ) + + sin t +   2  2 cos Z 3 3tan 3tan 1e 1e (14.33)
for
+ t 2 3 3
 t sin e tan s in + sin ( t  ) +  2 c os 1 e 3tan
i0 =
(14.34)
Exercise 14.2
1. Fill in the blank(s) with the appropriate word(s).
i. In a three phase half controlled converter each thyristor and diode conduct for ________________ degrees. ii. The output voltage waveform of a three phase half controlled converter is periodic over ________________ of the input voltage cycle. iii. The output voltage waveform of a three phase half controlled converter operating with > /3 and /3 are ________________ and have ________________ formula for the average voltage. iv. The output voltage and current of a three phase half controlled converter contain ________________ harmonics of the input ac frequency. v. The ac input current of a half controlled three phase converter can be zero for larger than ________________ of the input ac cycle provided the value of is ________________ than 60. vi. The input ac current of a three phase half controlled converter contain ________________ harmonics but no ________________ harmonics. vii. For the same output load current and firing angle the three phase half controlled converter has better ________________ factor but poorer ________________ factor compared to a fully controlled converter.
Answer: (i) 120; (ii) one third; (iii) different, same; (iv) triplen; (v) one third, greater; (vi) even, triplen; (vii) displacement, distortion.
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2. A 200V, 1450 RPM, 100A separately excited dc machine has an armature resistance of 0.04. The machine is driven by a three phase half controlled converter operating from a three phase 220V, 50Hz supply. The motor operates at the rated speed and rated load torque. Assuming continuous conduction find out (i) the firing angle of the converter; (ii) RMS fundamental component of the input current, (iii) Input current displacement factor and distortion factors.
Answer: (i) Under rated operating condition the motor must be supplied with rated voltage. 3 2 Therefore Vo = VL (1+ cos ) = 200V 2
Where VL = 230V 70o (ii) Io = 100A From equation (14.18) 6 Ii1 = I o cos = 63.87 amps 2 (iii) From equation (14.19) Input displacement factor = cos = 0.819 2 From equation (14.20) 6 cos = 0.712 Input distortion factor = 2 ( )
References
1. Power Electronics P.C. Sen, Tata McGrawhill publishing company limited, 1995. 2. Power Electronics, Converters, Applications and Design; Mohan, Undeland, Robins; John Willey and Sons Inc, Third Edition, 2003.
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Lesson Summary
Three phase half controlled converters are obtained by replacing three thyristors of either the top group or the bottom group of fully controlled converters by three diodes. Three phase half controlled converters can not operate in the inverting mode. Three phase half controlled converters have nine operating modes as compared to six of a fully controlled converter. The three free wheeling modes of a half controlled converters appears only when the firing angle is larger than 60. The output voltage and current waveforms of a three phase half controlled converter consist of a dc component and triplen harmonics of the input voltage frequency. For the same input ac voltage and firing angle a half controlled converter has higher output average dc voltage compared to a fully controlled converter. The input ac line current of a three phase half controlled converter contains harmonics of all (odd and even) order except triplen harmonics. For the same average dc load current and firing angle the half controlled converter has better input current displacement factor but poorer distortion factor compared to a fully controlled converter. The triggering circuit of a three phase half controlled converter is similar to that of a fully controlled converter. However, only three are required.
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ii)
2)
12 = 156 V E b 1200 = 195 15 Torque is rated, Ia = 50 A, V1200 = 156 + 0.5 50 = 181 volts = 49.87 181 = 3 2 163(1 + cos) 2
(b) V1500 at half rated torque = 195 + 0.5 25 = 207.5V = 27.7 207.5 = 3 2 163(1 + cos) 2 The output voltage of the converter should be V0 = 200 + 20 10 103 = 200.2 V (i) with a fully controlled converter = 47.64 200.2 = 3 2 220 cos Displacement factor = cos = 0.674 Distortion factor = 3 = 0.955 Power factor = Displacement factor Distortion factor = 0.6436 Version 2 EE IIT, Kharagpur 17
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3)
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(ii)
with a half controlled converter = 69.65 200.2 = 3 2 220 (1 + cos) 2 Displacement factor = cos = 0.82 2 6 cos = 0.8166 Distortion factor = () 2 Power factor = 0.6695 Displacement factor and power factor of a half controlled converter are better compared to a fully controlled converter while the distortion factor is poorer.
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Module 2
AC to DC Converters
Version 2 EE IIT, Kharagpur 1 www.jntuworld.com
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Lesson 15
Effect of Source Inductance on the Performance of AC to DC Converters
Version 2 EE IIT, Kharagpur 2 www.jntuworld.com
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Instructional Objectives
On completion the student will be able to Draw the voltage and current waveforms associated with a converter taking into account the effect of source inductance. Find the average output voltage of the converter as a function of the firing angle and overlap angle. Estimate overlap angles under a given operating condition and hence determine the turn off time available for the thyristors. Draw the dc equivalent circuit of a converter and parameterize it. Find out the voltage stress on the thyristors due to commutation overlap.
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15.1 Introduction
In the previous lessons the input ac power sources supplying an ac to dc power converter have been assumed to be ideal with no source impedance. Although this assumption simplifies the analysis of the converters, in most practical situations, they are not fully justified. Most ac dc converters are supplied from transformers. The series impedance of the transformer can not always be neglected. Even if no transformer is used, the impedance of the feeder line comes in series with the source. In most cases this impedance is predominantly inductive with negligible resistive component. The presence of source inductance does have significant effect on the performance of the converter. With source inductance present the output voltage of a converter does not remain constant for a given firing angle. Instead it drops gradually with load current. The converter output voltage and input current waveforms also change significantly. In this lesson a quantitative analysis of these effects will be taken up in some detail.
fully
controlled
converter
with
source
Fig. 15.1(a) shows a single phase fully controlled converter with source inductance. For simplicity it has been assumed that the converter operates in the continuous conduction mode. Further, it has been assumed that the load current ripple is negligible and the load can be replaced by a dc current source the magnitude of which equals the average load current. Fig. 15.1(b) shows the corresponding waveforms. It is assumed that the thyristors T3 and T4 were conducting at t = 0. T1 and T2 are fired at t = . If there were no source inductance T3 and T4 would have commutated as soon as T1 and T2 are turned ON. The input current polarity would have changed instantaneously. However, if a source inductance is present the commutation and change of input current polarity can not be instantaneous. Therefore, when T1 and T2 are turned ON T3 T4 does not commutate immediately. Instead, for some interval all four thyristors continue to conduct as shown in Fig. 15.1(b). This interval is called overlap interval.
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During this period the load current freewheels through the thyristors and the output voltage is clamped to zero. On the other hand, the input current starts changing polarity as the current through T1 and T2 increases and T3 T4 current decreases. At the end of the overlap interval the current through T3 and T4 becomes zero and they commutate, T1 and T2 starts conducting the full load current. The same process repeats during commutation from T1 T2 to T3T4 at t = + . Version 2 EE IIT, Kharagpur 5 www.jntuworld.com
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From Fig. 15.1(b) it is clear that, commutation overlap not only reduces average output dc voltage but also reduces the extinction angle which may cause commutation failure in the inverting mode of operation if is very close to 180. In the following analysis an expression of the overlap angle will be determined.
for
t +
ii(t = ) =  I0
2Vi ii = I cost L ii
t =
=I
2Vi cos =  I0 L
I= ii =
at t = + ii = I0
I0 =
cos  cos( + ) =
or
V0 = I V0 = I
vi dt 2vi sint dt
= =
(15.10)
V0 = 2 2
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The simple equivalent circuit of Fig. 15.3 represents the single phase fully controlled converter with source inductance as a practical dc source as far as its average behaviour is concerned. The open circuit voltage of this practical source equals the average dc output voltage of an ideal converter (without source inductance) operating at a firing angle of . The voltage drop across the internal resistance RC represents the voltage lost due to overlap shown in Fig. 15.1(b) by the hatched portion of the v0 waveform. Therefore, this is called the Commutation resistance. Although this resistance accounts for the voltage drop correctly there is no power loss associated with this resistance since the physical process of overlap does not involve any power loss. Therefore this resistance should be used carefully where power calculation is involved.
fully
controlled
converter
with
source
In lesson 13 the three phase fully controlled converter was analyzed with ideal source with no internal impedance. When the source inductance is taken into account, the qualitative effects on the performance of the converter is similar to that in the case of a single phase converter. Fig. 15.4(a) shows such a converter. As in the case of a single phase converter the load is assumed to be highly inductive such that the load can be replaced by a current source.
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As in the case of a single phase converter, commutations are not instantaneous due to the presence of source inductances. It takes place over an overlap period of 1 instead. During the overlap period three thyristors instead of two conducts. Current in the outgoing thyristor gradually decreases to zero while the incoming thyristor current increases and equals the total load current at the end of the overlap period. If the duration of the overlap period is greater than 60 four thyristors may also conduct clamping the output voltage to zero for sometime. However, this situation is not very common and will not be discussed any further in this lesson. Due to the conduction of two devices during commutation either from the top group or the bottom group the instantaneous output voltage during the overlap period drops (shown by the hatched portion of Fig. 15.4 (b)) resulting in reduced average voltage. The exact amount of this reduction can be calculated as follows. In the time interval < t + , T6 and T2 from the bottom group and T1 from the top group conducts. The equivalent circuit of the converter during this period is given by the circuit diagram of Fig. 15.5.
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but
at t = , at t = + , ib = 0 Or, ib =  I0
ib = C 
2VL cost 2 L
C=
ib =
2VL cos  I0 2 L
(15.19) (15.20)
Equation 15.20 holds for 60. It can be shown that for this condition to be satisfied
I0 VL cos  3 2L
(15.21)
(15.22)
for + t +
v0 = vac
+ V0 = 3 3 va dt + 2
3 + +
vac dt
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(15.23)
or
3 2VL V0 = 3 2 VL cos 2
sint dt
(15.24)
(15.25)
Equation 15.25 suggests the same dc equivalent circuit for the three phase converter with source inductance as shown in Fig. 15.3 with
VOC = 3 2 VL cos
It should be noted that RC is a loss less resistance, since the overlap process does not involve any active power loss. Exercise 15.1 1. i. ii. iii. iv. v. vi. vii. Fill in the blank(s) with appropriate word(s) The internal impedance of an ac source supplying a converter is largely ______________ in nature. Due to the presence of source ______________ commutation in a converter is not ______________. The period over which the commutation process continues is called the ______________ period. Length of the overlap period depends on the valve of the source inductance and load ______________. In a single phase converter ______________ thyristors conduct during the overlap period. In a three phase converter ______________ thryistors conduct during the overlap period provided the overlap angle is less than ______________ degrees. The average output voltage of a acdc converter ______________ as a result of commutation overlap.
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viii. ix. x.
In the dc equivalent circuit of a converter the input ac source inductor appears as a loss less resistance called the ______________ resistance. Commutation overlap decreases the ______________ angle of a converter and may cause commutation failure during ______________ mode of operation. Commutation overlap introduces ______________ in the supply voltage waveform.
Answer: (i) inductive; (ii) inductance, instantaneous; (iii) overlap; (iv) current ; (v) four; (vi) three, sixty; (vii) decreases; (viii) commutation; (ix) inverter, (x) notches. 2. A 220V, 1450 RPM, 100A separately excited dc motor has an armature resistance to 0.1. It is supplied from a 3 phase fully controlled converter connected to a 3 phase 50 Hz ac source. The ac source has an inductive reactance of 0.5 at 50 Hz. The line voltage is adjusted such that at = 0; the motor operates at rated speed and torque. The motor is to be braked regeneratively in the reverse direction at rated speed using the converter. What is the maximum braking torque the motor will be able to produce under this condition without causing commutation failure?
Answer: Under rated operating condition, the motor terminal voltage is 220V and it draws 100 Amps current. Therefore from eqn. 15.25.
3 2 3 VL  .5100 VL = 198 volts 220 =
or
Eb
rated speed
Under regenerative braking in the reverse direction at rated speed 3 2 3 198cos 0.5 + 0.1 Io = 210V Also from equation 15.20 2 0.5 Io cos cos ( + ) = 198 At the limiting condition of commutation failure
+ 180o
cos = Io 1 198 2
Io = 152.24 Amps
Maximum braking torque will be approximately 150% of the rated motor torque. Version 2 EE IIT, Kharagpur 11 www.jntuworld.com
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References
1. Muhammad H. Rashid; Power Electronics, Circuits, Devices and Applications Second Edition, Prentice Hall of India, New Delhi, 1994. 2. P.C. Sen; Power Electronics, Tata McGrawhill publishing company limited, 1995. 3. Power Electronics, Converters, Applications and Design; Mohan, Undeland, Robbins; John Willey and Sons Inc, Third Edition, 2003.
Lesson Summary
Ac power sources supplying an acdc converter have internal impedances which are not always negligible. The internal impedance of an ac source is predominantly inductive with negligible resistive component. Due to the presence of the source inductance in the ac line the thyristors in a acdc converter can not commutate instantaneously. The period over which the commutation process continuous is called the overlap period. The length of the overlap period increases with increasing source inductance and load current. In a single phase converter all four thyristors conduct during the overlap period. In a three phase converter, three thyristors conduct during the overlap period provided it is less than 60. The average output voltage of a converter decreases as a result of commutation overlap. The voltage drop due to commutation overlap can be represented as a drop across a commutation resistance the value of which is proportional to the ac line reactance per phase. The commutation resistance is loss less since the actual process of overlap does not involve any real power loss. Commutation overlap reduces the margin angle () of a converter and may cause commutation failure. Commutation overlap introduces notches in the ac supply voltage waveform which may affect other equipment connect to the same power source.
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Module 2
AC to DC Converters
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Lesson 16
Power Factor Improvement, Harmonic Reduction, Filter
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Instructional Objectives
Study of the following: Schemes for the improvement of power factor in ACDC converters. Methods for harmonic reduction in the current waveforms of the converters. Types of filters used to obtain ripple free (dc) output voltage and currents, reducing the harmonics.
2.8.1 Introduction
After the discussion of various types of ac to dc converters (rectifiers), both single and threephase, in the lessons (#2.12.6) of this module (# 2), the drop in the output voltage due to the commutation overlap in the converter, was presented, the inductance on the source (ac) side being taken into account, in the previous lesson (#2.7). In this (last) lesson (#2.8), three important points power factor improvement, harmonic reduction, and filters, as applicable to converters, are described. The three schemes for power factor improvement are discussed. Then, the use of various filters to reduce the harmonics in the output voltage and current waveforms, are presented. Lastly, the harmonic reduction techniques are taken up, in brief. In all these cases, the circuit of a single phase full wave half (semi) controlled bridge converter (acdc) is used mostly as an example.
t = ( 2 ) . The output voltage is controlled by varying the extinction angle, . Fig. 16.1(b) shows the waveforms for input voltage, output voltage, input current, and the current through thyristor switches. The fundamental component of input current leads the input voltage, and the
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displacement factor (and power factor) is leading. This feature may be desirable to simulate a capacitive load, thus compensating the line voltage drops. iT1 + S1 + vs D2 D1 iDF (a) Circuit is S2 iT2 DF i 0 = Ia v0 L O A D
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vs Vm 0 v0 0 Ia Ia 0 iT2 iT1
vs = Vmsint 2  2  2 t t
3 
0 iDF 0 is Ia 
2 
t Ia 2 t is1
2  2 
0  Ia Ia 0 io
3 
Load current t
(b) Waveforms for extinction angle control Fig. 16.1 Singlephase forcedcommutated semiconverter. The average output voltage is 2  2 Vdc = 2Vsin t d ( t ) = V (1 + cos ) 2 0 The value of Vdc is varied from (2 2 / )V to 0, as varies from 0 to . The rms value of output voltage is
2 1 1 2  Vo = 2V 2 sin 2 t d ( t ) = V ( ) + sin 2 2 2 0 Here also, Vo varies from V to 0. 1
1 2
This scheme of extinction angle control can also be used for single phase full wave full controlled bridge converter with four switches, instead of two needed in the earlier case. The students are requestedto study this matter form text books, but details are not included here.
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vs Vm 0 v0 Vm 0 is1 Ia 0 is2 Ia 0 is Ia 0  Ia i0 Ia 0 (a) v Ar Ar 0 vg 0 S1 (b) Fig. 16.2 Symmetrical angle control. 2 3 t S2 2 S1 3 t vr vc
 2 + 2
vs = Vmsint t
2 3 t
/2
5 /2
3 /2
2 is1 2
Load current t
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The average output voltage is 2 2 2 ( + ) / 2 Vdc = 2V sin t d ( t ) = V sin ( ) / 2 2 The value of Vdc varies from 2 2 V to 0 as varies from to 0. The rms value of output voltage is
2 2 ( + ) / 2 2 2 1 Vo = 2V sin ( t ) d ( t ) = V ( + sin ) / 2 ( ) 2 1 1 2
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0 v0 m 0 is1 Ia 0 is3 Ia 0 is Ia 0 i0  Ia Ia 0 m m
m m
+ m + m
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v Ar Ac
vr
vc
The details of output voltage and current waveforms of the converter are given. The output voltage (i.e., performance parameters) can be obtained in two steps: (i) by considering only one pair of pulses such that, if one pulse starts at t = 1 , and ends at t = 1 + 1 , the other pulse starts at t = + 1 , and ends at t = ( + 1 + 1 ) , and (2) then by combining the effects of all pairs of pulse. If mth pulse starts at t = m and its width is m , the average output voltage due to p number of pulses is found as p 2V p 2 m +m Vdc = 2V sin t d ( t ) = cos m cos ( m + m ) m m =1 m =1 If the load current with an average value of Ia is continuous and has negligible ripple, the instantaneous input current is expressed in a Fourier series as
is ( t ) = Idc +
n =1,3,5,...
(a
cos nt + b n sin nt )
Due to symmetry of the input current waveform, even harmonics are absent, and Idc is zero. The Fourier coefficients are obtained as 1 2 a n = is ( t ) cos nt d ( t ) 0 p 1 +m +m 1 m +m I a cos nt d ( t ) I a cos nt d ( t ) = 0 = + m m m =1
bn = 1 2 is ( t ) sin nt d ( t ) 0 p 1 + m +m 1 m +m Ia sin nt d ( t ) I a sin nt d ( t ) = + m m m =1 p 2I cos n m cos n ( m + m ) = a n m =1
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2 I n sin ( nt + n )
1 2
2 = bn
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v Ar Ac
Reference signal
Carrier signal vr vc
0 iT1 +Ia 0 iT2 +Ia 0 is +Ia 0  Ia io Ia 0 Fig. 16.4 Sinusoidal pulsewidth modulation control. m m + m + m + m 2 3 + m 2 3 m m 2 3
Load current t
Filters
It is known that the output voltage waveform of a single phase full wave diode (uncontrolled) bridge converter (rectifier) fed from f = 50 Hz (fundamental) supply, contains harmonics of 2f = 100 Hz. So, it is necessary to filter out this and other harmonics from the output voltage to obtain dc component only. The harmonic frequency present in the output voltage waveforms of threephase halfwave and full wave (bridge) diode converters, are 150 Hz (3f) and 300 Hz (6f) respectively. The higher the harmonic frequency, it is easier to filter it. For phasecontrolled thyristor converters, the harmonic frequency remains same, but magnitudes vary, as the firing angle delay, is changed. It may also be noted that the harmonics present in the output current waveforms of the converters with resistive (R) load, remain same. . For simple filter, a capacitor (C) is connected in parallel across the output of the diode converters with resistive (R) load. The reactance of the capacitor should be low, such that harmonics currents pass through it. So, the harmonics in the output voltage decrease. The value of the capacitor chosen varies with the predominant harmonic frequency present. Thus, the capacitor of higher value is needed to filter lower harmonic frequency, say 100 Hz, whereas a lower value of C could be chosen for say, three phase converters. The function of the capacitor Version 2 EE IIT, Kharagpur 12
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may also be explained in the following way. The voltage across the capacitor changes as per the input voltage, which is the output voltage of the converter, fed to it, and the capacitor voltage tries to stabilize at the overage value of the output voltage, as the capacitor voltage decreases, load resistance being connected across it. Same is the case with the filter used to reduce the harmonic content of the output current waveform for the above converters with resistive (R) load. Instead of a capacitor in parallel, an inductor (L) is connected in series with the load. The reactance of the inductor increases, thus reducing the harmonic component in the current waveform. Here, a smaller value of the inductor is needed to filter higher harmonics, for example a threephase bridge converter. These are all simple cases, known to those, who have studied the circuit (network) theory. Also, by Faradays laws, induced voltage (emf) appears across the inductor, L, when the current through it changes, and the sign of it opposes the cause, thus opposing the changes in current. So, the current is not allowed to change much, as an inductor is placed in series with the load. In actual practice, a combination of L, C & R is needed to get an optimum filter needed to reduce or eliminate the harmonics in both output voltage and current waveforms.
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+ A
iL L
1 + Supply (50Hz) 
D1 G is
D2 C H L O A D RL
D4 
D3 B (a)
A R C1
E RL, L L O A D
C2
(b)
Fig. 16.5 (a) Low pass (LC) filter, (b) Twostage filter
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Harmonic Reduction
The harmonic reduction schemes are presented in brief. The important point to be noted is that, recently due to increasing use of power electronic units, utility or electricity supply agencies (boards), have restricted that the power is drawn by the consumers, so as to decrease the harmonic content in the input current, or make it sinusoidal, and at the same time, improved load power factor is achieved. Two schemes (a) passive (filter) circuits and (b) Active shaping of input line current, are presented, in brief.
is Ia
0 Ia
(T/2)
2(T)
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+ iS + C L1 L2 G H
B Fig. 16.6 (b) Low pass (LC) filter on source (AC) side
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Iload +
s ) vd (Vd > V
(b) vs iL 0 (c) Fig. 16.7 Active harmonic filtering: (a) stepup converter for current shaping; (b) line waveforms; (c) vs and iL. t
The control used is constant toleranceband one. Here, the current. iL, is controlled, such that peaktopeak ripple Irip in iL remains constant. The reference input, i* L , is made sinusoidal having same (line) frequency. With a preselected value of Irip, iL is forced to be in tolerance band (iL + Irip/2) and (iL Irip/2) by controlling the status of the switch, S. So, the input current, iL, follows the reference input, i* L , which is sinusoidal. As described later (module #3), the switch, S may be a selfcommutated switching device, power transistor or MOSFET. For detail, any text book may be used by the student, as only a brief discussion is presented here. In this lesson, last one in this module, three important points power factor (pf) improvement, harmonic reduction and filters, are presented. Firstly, three methods, viz extinction angle control, symmetrical angle control and pulse width modulation (PWM) control, are described in detail with relevant waveforms. Then, various types of filters (C, LC & RC) used for the reduction in harmonic content of output voltage and current waveforms of the acdc Version 2 EE IIT, Kharagpur 17
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converters, are discussed, with the equations for the value of the filter components needed. Lastly, in brief, harmonic reduction aspect is taken up. In this module of acdc converter consisting of eight lessons, all types of singlephase and threephase converters, with other relevant points, have been thoroughly discussed.
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Module 3
DC to DC Converters
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Lesson 17
Types of Basic DCDC Converters
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Instructional Objectives
Study of the following: Three basic types of dcdc converter circuits buck, boost and buckboost The expressions for the output voltage in the above circuits, with inductive (RL) and battery (or back emf = E) load
Introduction
In the last module (#2) consisting of eight lessons, the various types of circuits used in both singlephase and threephase acdc converters, were discussed in detail. This includes halfwave and fullwave, and also halfcontrolled and fullcontrolled ones. In this lesson the first one in this module (#3), firstly, three basic types of dcdc converter circuits buck, boost and buckboost, are presented. Then, the expressions for the output voltage in the above circuits, with inductive (RL) and battery (or back emf = E), i.e., RLE, load, are derived, assuming continuous conduction. The different control strategies employed are briefly described. Keywords: DCDC converter circuits, Thyristor choppers, Buck, boost and buckboost converters (dcdc), Stepdown (buck) and stepup (boost) choppers, Output voltage and current.
DCDC Converters
There are three basic types of dcdc converter circuits, termed as buck, boost and buckboost. In all of these circuits, a power device is used as a switch. This device earlier used was a thyristor, which is turned on by a pulse fed at its gate. In all these circuits, the thyristor is connected in series with load to a dc supply, or a positive (forward) voltage is applied between anode and cathode terminals. The thyristor turns off, when the current decreases below the holding current, or a reverse (negative) voltage is applied between anode and cathode terminals. So, a thyristor is to be forcecommutated, for which additional circuit is to be used, where another thyristor is often used. Later, GTOs came into the market, which can also be turned off by a negative current fed at its gate, unlike thyristors, requiring proper control circuit. The turnon and turnoff times of GTOs are lower than those of thyristors. So, the frequency used in GTObased choppers can be increased, thus reducing the size of filters. Earlier, dcdc converters were called choppers, where thyristors or GTOs are used. It may be noted here that buck converter (dcdc) is called as stepdown chopper, whereas boost converter (dcdc) is a stepup chopper. In the case of chopper, no buckboost type was used. With the advent of bipolar junction transistor (BJT), which is termed as selfcommutated device, it is used as a switch, instead of thyristor, in dcdc converters. This device (NPN transistor) is switched on by a positive current through the base and emitter, and then switched off by withdrawing the above signal. The collector is connected to a positive voltage. Nowadays, MOSFETs are used as a switching device in low voltage and high current applications. It may be noted that, as the turnon and turnoff time of MOSFETs are lower as compared to other switching devices, the frequency used for the dcdc converters using it (MOSFET) is high, thus, reducing the size of filters as stated earlier. These converters are now being used for applications, one of the most important being Switched Mode Power Supply (SMPS). Similarly, when application requires high voltage, Insulated Gate Bipolar Transistors (IGBT) are preferred over Version 2 EE IIT, Kharagpur 3 www.jntuworld.com
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BJTs, as the turnon and turnoff times of IGBTs are lower than those of power transistors (BJT), thus the frequency can be increased in the converters using them. So, mostly selfcommutated devices of transistor family as described are being increasingly used in dcdc converters.
t Fig. 17.1(b): Output voltage and current waveforms The output voltage and current waveforms of the circuit (Fig. 17.1a) are shown in Fig. 17.1b. The output voltage is same as the input voltage, i.e., v0 = Vs , when the switch is ON, during the period, TON t 0 . The switch is turned on at t = 0 , and then turned off at t = TON . This is Version 2 EE IIT, Kharagpur 4 www.jntuworld.com
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called ON period. During the next time interval, T t TON , the output voltage is zero, i.e.,
v0 = 0 , as the diode, D F now conducts. The OFF period is TOFF = T TON , with the time period being T = TON + TOFF . The frequency is f = 1 / T . With T kept as constant, the average value of the output voltage is,
V0 = 1 1 v0 dt = T 0 T
T TON
V
0
T dt = Vs ON = k Vs T
The duty ratio is k = (TON / T ) = [TON / (TON + TOFF )] , its range being 1.0 k 0.0 . Normally, due to turnon delay of the device used, the duty ratio (k) is not zero, but has some positive value. Similarly, due to requirement of turnoff time of the device, the duty ratio (k) is less than 1.0. So, the range of duty ratio is reduced. It may be noted that the output voltage is lower than the input voltage. Also, the average output voltage increases, as the duty ratio is increased. So, a variable dc output voltage is obtained from a constant dc input voltage. The load current is assumed to be continuous as shown in Fig. 17.1b. The load current increases in the ON period, as the input voltage appears across the load, and it (load current) decreases in the OFF period, as it flows in the diode, but is positive at the end of the time period, T.
Vs
V0
L O A D
TON TOFF
2T
Fig. 17.2(b): Waveforms of source current (iS) Version 2 EE IIT, Kharagpur 5 www.jntuworld.com
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The operation of the circuit is explained. Firstly, the switch, S (i.e., the device) is put ON (or turned ON) during the period, TON t 0 , the ON period being TON . The output voltage is zero ( v0 = 0 ), if no battery (back emf) is connected in series with the load, and also as stated earlier, the load inductance is small. The current from the source ( i s ) flows in the inductance L. The value of current increases linearly with time in this interval, with ( d i d t ) being positive. As the current through L increases, the polarity of the induced emf is taken as say, positive, the left hand side of L being +ve. The equation for the circuit is, di d i s Vs = Vs = L s or, dt dt L The switch, S is put OFF during the period, T t TON , the OFF period being
TOFF = T TON . ( T = TON + TOFF ) is the time period. As the current through L decreases, with its direction being in the same direction as shown (same as in the earlier case), the induced emf reverses, the left hand side of L being ve. So, the induced emf (taken as ve in the equation given later) is added with the supply voltage, being of the same polarity, thus, keeping the current ( is = i0 ) in the same direction. The current ( is = i0 ) decreases linearly in the time interval, TOFF , as the output voltage is assumed to be nearly constant at v0 V0 , with ( d i s d t ) being negative, as Vs < V0 , which is derived later. The equation for the circuit is, di d i s (Vs V0 ) Vs = V0 + L s = or, dt dt L The source current waveform is shown in Fig. 17.2b. As stated earlier, the current varies linearly from I 1 ( I min ) to I 2 ( I max ) during the time interval, TON . So, using the expression for d i s d t during this time interval, I 2 I 1 = I max I min = (Vs / L ) TON . Similarly, the current varies linearly from I 2 ( I max ) to I 1 ( I min ) during the time interval, TOFF . So, using the expression for d i s d t during this time interval, I 2 I1 = I max I min = [(V0 Vs ) / L] TOFF . Equating the two equations, (V s / L ) T ON = [(V 0 V s ) / L ] T OFF , from which the average value of the output voltage is, T T 1 1 V0 = V s V = s T T T = Vs 1 (T / T ) = Vs 1 k ON ON OFF The time period is T = TON + TOFF , and the duty ratio is, k = (TON / T ) = [TON / (TON + TOFF )] , with its range as 1.0 k 0.0 . The ON time interval is TON = k T . As stated in the previous case, the range of k is reduced. This is, because the minimum value is higher than the minimum (0.0), and the maximum value is lower than the maximum (1.0), for reasons given there, which are also valid here. As shown, the source current is assumed to be continuous. The expression for the output voltage can be obtained by using other procedures. In this case, the output voltage is higher than the input voltage, as contrasted with the previous case of buck converter (dcdc). So, this is called boost converter (dcdc), when a selfVersion 2 EE IIT, Kharagpur 6 www.jntuworld.com
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commutated device is used as a switch. Instead, if thyristor is used in its place, this is termed as stepup chopper. The variation (range) of the output voltage can be easily computed.
Vs
IL
V0
TON TOFF
2T
Fig. 17.3(b): Inductor current (iL) waveform Then, the switch, S is put OFF. The inductor current tends to decrease, with the polarity of the induced emf reversing. ( d i L d t ) is negative now, the polarity of the output voltage, V0 being opposite to that of the input voltage, Vs . The path of the current is through L, parallel combination of load & C, and diode D, during the time interval, TOFF . The output voltage remains nearly constant, as the capacitor is connected across the load. Version 2 EE IIT, Kharagpur 7 www.jntuworld.com
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The equation for the circuit is, di d i L V0 L L = V0 = or, dt dt L The inductor current waveform is shown in Fig. 17.3b. As stated earlier, the current varies linearly from I L1 to I L 2 during the time interval, TON . Note that I L1 and I L 2 are the minimum and maximum values of the inductor current respectively. So, using the expression for d i L d t during this time interval, I L 2 I L1 = (Vs / L ) TON . the expression for d i L d t during this time interval, I L 2 I L1 = (V0 / L ) TOFF . Equating the two equations, the output voltage is, TON TON V0 = V s T = Vs T T ON OFF The time period is T = TON Similarly, the current varies linearly from I L 2 to I L1 during the time interval, TOFF . So, using
(V s
k = (TON / T ) = [TON / (TON + TOFF )] . The ON time interval is TON = k T . It may be observed that, for the range 0 k > 0.5 , the output voltage is lower than the input voltage, thus, making it a buck converter (dcdc). For the range 0.5 > k 1.0 , the output voltage is higher than the input voltage, thus, making it a boost converter (dcdc). For k = 0.5 , the output voltage is equal to the input voltage. So, this circuit can be termed as a buckboost converter. Also it may be called as stepup/down chopper. It may be noted that the inductor current is assumed to be continuous. The range of k is somewhat reduced due to the reasons given earlier. The expression for the output voltage can be obtained by using other procedures.
Control Strategies
In all cases, it is shown that the average value of the output voltage can be varied. The two types of control strategies (schemes) are employed in all cases. These are: (a) Timeratio control, and (b) Current limit control.
Timeratio Control
In the time ratio control the value of the duty ratio, k = TON / T is varied. There are two ways, which are constant frequency operation, and variable frequency operation.
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v0 TON k = 0.25 t v0
TON T
k = 0.75 t
v0
TOFF T v0 TOFF
TON
k = 0.75 t
Fig. 17.5: Output voltage waveforms for variable frequency system There are major disadvantages in this control strategy. These are: (a) The frequency has to be varied over a wide range for the control of output voltage in frequency modulation. Filter design for such wide frequency variation is, therefore, quite difficult. (b) For the control of a duty ratio, frequency variation would be wide. As such, there is a possibly of interference with systems using certain frequencies, such as signaling and telephone line, in frequency modulation technique. (c) The large OFF time in frequency modulation technique, may make the load current discontinuous, which is undesirable. Thus, the constant frequency system using PWM is the preferred scheme for dcdc converters (choppers).
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I max
i0
I min
t v0
TON TOFF
In this lesson, first one in this module (#3), the three basic circuits buck, boost and buckboost, of dcdc converters (choppers) are presented, along with the operation and the derivation of the expressions for the output voltage in each case, assuming continuous conduction. The different strategies employed for their control are discussed. In the next lesson second one, the expression for the maximum and currents for continuous conduction in buck dcdc converter will be derived.
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Module 3
DC to DC Converters
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Lesson 18
Analysis of Buck Converter (DCDC) Circuit
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Instructional Objectives
Study of the following in respect of the buck converter (dcdc) circuit, with inductive (RL) and battery (or back emf = E) load, assuming continuous conduction Derivation of the expressions for the maximum and minimum load currents Calculation of the following:
(a) the duty ratio for the limit for continuous conduction (b) the average value and the ripple factor of the load current (c) the harmonic components of the output voltage waveform
Introduction
In the last lesson first one in the module (#3), firstly the circuits of the various types of dcdc converters (choppers), such as buck, boost and buckboost, were presented. Then, the operation and the derivation of the expressions for the output voltage for the above dcdc converters, including current waveforms, were described in detail. Lastly, the different control strategies used were briefly discussed. In this lesson the second one in this module, the analysis of the buck converter (dcdc) or stepdown chopper circuit, using thyristor as a switching device, with inductive (RL) and battery (or back emf = E) load, is presented in detail. Starting with the derivation of the expressions for the maximum and minimum load currents, assuming continuous conduction, the procedure for the calculation of following expressions the duty ratio for the limit of continuous conduction, the average value and the ripple factor, of the output (load) current, and the harmonic components of the output voltage waveform, are described in detail. Keywords: Buck converter (dcdc), Stepdown chopper, Output (load) current maximum and minimum values, average value, ripple factor, harmonic analysis.
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0 io Imax Imin 0 iT v0 VS V0 0 TON T (b) Continuous load current Fig. 18.2: Two modes operation of the chopper. TOFF iD
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d i0 di +E or, VS E = R i0 + L 0 dt dt The current is the load current, same as the source current during this time interval. The values of the load current ( i0 ) at t = 0 and t = TON , are I min and I max respectively. The expression for the V S = R i0 + L
load current is, i0 = A e t / + B where A and B are constants, and time constant is, = L / R . At t = 0 , i0 = A + B = I min At t = , i0 = B = [(Vs E ) / R] So, A = I min [(Vs E ) / R] Substituting the values of A & B, the expression for the load current is, (V E ) i0 = s 1 e t / + I min e t / R At t = TON , i0 = I max . So,
(V E ) TON / I max = s + I min e TON / 1 e R (V E ) 1 e TON / or, I max I min e TON / = s R This is the first expression obtained for mode 1 between I max and I min . Similarly, the second one will be derived for mode 2. Mode 2: The equation for the load (output) current in the circuit during this time interval, 0 t TOFF is, di di 0 = R i0 + L 0 + E or, E = R i0 + L 0 dt dt It may be noted here that the time ( t = 0 ) is taken here from the start of mode 2, i.e., the end of mode 1. The current is the load current, and the current through the diode, D F during this time interval. The values of the load current ( i0 ) at t = 0 and t = TOFF , are I max and I min respectively.
The expression for the load current is, i0 = A e t / + B . Version 2 EE IIT, Kharagpur 5 www.jntuworld.com
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At t = 0 , i0 = A + B = I max
At t = , i0 = B = (E / R )
So, A = I max + (E / R ) Substituting the values of A & B, the expression for the load current is, E i0 = 1 e t / + I min e t / R At t = TOFF , i0 = I min . So,
E I min = 1 e TOFF / + I max e TOFF / R E or, I max e TOFF / I min = 1 e TOFF / R This is the second expression obtained for mode 2 between I max and I min .
From these two expressions, the currents, I max and I min are derived as,
T / V 1 e ON E I max = s T / R 1 e R T / Vs e ON 1 E I min = T / R e 1 R
or, or,
As given earlier, the load (output) current varies between the maximum and minimum values ( I max and I min ). Therefore, the ripple content of the current is,
T / (T TON ) / Vs 1 e TON / 1 e TOFF / V 1 e ON 1 e I max I min = s = 1 e T / 1 e T / R R The above expression for ripple content is independent of battery voltage or back emf (E). Using the duty ratio, k = TON / T , the expression becomes,
)(
)(
k T / 1 e (1k ) T / Vs 1 e I max I min = , 1 e T / R its per unit value being, (I max I min ) = 1 e k T / 1 e (1k ) T / (Vs / R ) 1 e T /
)(
)(
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T / eTON / 1 E V e ON 1 E or, = I min = s T / = 0 =g eT / 1 R e 1 R Vs where g = (E / Vs ) So, the duty ratio for limit of continuous conduction is, k = (TON / T ) = ( / T ) log e 1 + g eT / 1 The output (load) current is continuous, if the actual duty ratio, k is more than the above duty ratio, k , and it becomes discontinuous, if k is lower than the above duty ratio, k .
)]
given earlier. The average values of the currents in the thyristor (I T )av and diode (I D )av , can also be computed by using the expressions for the currents separately. These two expressions are not included here, but are available in text book. All these values of the currents can also be obtained by using other procedure.
v0 = Instantaneous value of the output (load) voltage Vs = Source (input) voltage (constant) V0 = Average value of the output voltage T = TON + TOFF = Time period of the thyristor chopper (stepdown)* TON = Time interval for which the thyristor is ON* TOFF = T TON = Time interval for which the thyristor is OFF* f = 1 / T = Frequency (Hz) for the thyristor chopper (stepdown)* = 2 f = Angular frequency (rad/s) = t = Angle (rad) T = 2 = Angle (rad) for time period, T a n & bn are the maximum values of the sine and cosine components of the harmonics of order n, present in the output voltage waveform respectively.
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cn & n are the maximum value (amplitude), and phase angle, of nth harmonic component respectively. 2 2 The relationships are cn = a n , and n = tan 1 (bn / an ) , + bn
and the other relationships are an = cn cos n and bn = cn sin n . The rms value of nth harmonic component = cn / 2 * It may be noted that, when the thyristor (device) in the stepdown chopper (Fig. 18.1), or buck converter (dcdc), is ON, or conducting, the diode, D F is not conducting (OFF), and vice versa, i.e., when the thyristor (device) is OFF, or not conducting, the diode, D F is conducting (ON). The output (load) voltage waveform for one time period T , is, v0 = Vs for TON < t < 0 ; v0 = 0 for T < t < TON In terms of the Fourier components, the expression is,
0 2 k
v
0
cos (n ) d =
TON
Vs Vs cos (n ) d = n sin n
2 k 0
Vs = n
(sin 2 k )
n = tan 1 (cot n k ) = ( 2) ( n k ) The average value (dc) is V0 = k Vs , which has been derived in lesson #17 (module 3). Substituting the above values of cn & n ,
2 Vs v0 = V0 + (sin n k ) (sin (n + ( 2) ( n k )) ) n =1 n 2V 2V = V0 + s (sin n k ) ( cos [ n (n k ) ]) = V0 + s (sin n k ) ( cos[n ( k )]) The n =1 n n =1 n
maximum value of the fundamental component is, c1 = ((2Vs ) ) (sin k ) , and its phase angle (rad) is, 1 = ( 2) ( k ) . The magnitude of the maximum (or rms) value of the harmonic components decreases as its order (n) increases.
2 The rms value of the waveform is, Vor = (V0 ) 2 + (cn / 2 ) 2 = (V0 ) 2 + ( 1 2 ) (cn ) n =1 n =1
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ON T 1 V0 r = (Vs ) 2 dt = ON Vs = k Vs T T 0 It can be observed that the amplitude of the harmonic component depends on the order of the harmonic, n and also on the duty ratio, k. The maximum value of the nth harmonic component occurs, when sin ( n k ) = 1 , and its value (V) is,
2 Vs 0.637 Vs 2 Vs 0.45 Vs = , with its rms value (V) as = n n n n The value of the angle for the above condition, i.e., at which the maximum value of the magnitude of the nth harmonic component of the output voltage occurs, is, n k = (4m + 1) ( / 2) = 2 m + ( / 2) , or n k = (4m + 1) / 2 = 2 m + 1 2 or, ( 2 m + 0.5 ) Firstly, the average value or dc component and the rms values of all harmonic components, of the output (load) voltage, are computed as per the formula given earlier. It may be noted that, the rms values of only a few harmonic components need be computed, because the rms values decrease, as the order of harmonic increases (having an inverse relationship with it), as given earlier. Then, using the expression for the rms value, it (rms value) is computed. Finally, it can be checked from the expression for the rms value given earlier. As first example, the case of fundamental frequency ( n = 1 ) is taken up. The value of duty ratio is ( k = 0.5( 1 2 ) ) as ( k < 1.0 ), at which the magnitude of the output voltage is maximum at the above frequency. If the third harmonic ( n = 3 ) is chosen as another example, more than one 5 value, in this case, three values of the duty ratio ( k = 0.167 ( 1 6 ) & 0.833( 6 ) ), and also the
previous value of ( k = 0.5( 1 2 ) ), as k < 1.0 , are obtained. If first two values of k are substituted, sin ( / 2) = 1 and the results obtained, using the ascending order, are sin (5 / 2) = sin ( / 2) = 1 . But, if the value, ( k = 0.5( 1 2 ) ) is substituted, the results obtained is
cn = sin (3 / 2) = sin ( / 2) = sin ( / 2) = 1 . For this value in this case, 3 k = (3 / 2) or ( / 2) . So, the set of values would be 3 k = (2 m + (3 / 2)) or (2 m ( / 2)) . Earlier, the value of cn is chosen as positive only, assuming that its angle would take care of the sign, i.e., for cn = +1 , n = 0 , and for cn = 1 , n = 180 ( ) . The angle ( n ) can be obtained by using the sign of two components, an & bn . But if a close look at the formula of cn is taken, it can have
both +ve and ve values, i.e., cn = sin ( n k ) = 1 , being square root of a +ve quantity. The value would now be, n k = (4m 1) / 2 = 2 m 1 2 or, ( 2 m 0.5 ). So, for ( n = 3 ), three values of duty ratio, k as given earlier, are obtained. Similarly, for any other odd harmonic ( n = 2 m + 1 ), the duty ratios can be computed. It may also be observed that, for the duty ratio of ( k = 0.5( 1 2 ) ), the magnitudes of the output voltage at all odd harmonics are maximum. Now, for even harmonics ( n = 2 m ), the duty ratios for which the magnitude of the component of output voltage is maximum, are obtained. For second harmonic ( n = 2 ), two values of duty ratio obtained using the formula ( 2 k = 2 m 1 2 ) are,
3 k = 0.25( 1 4 ) & 0.75( 4 ) , as k < 1.0 . If these two values of k are substituted, the results obtained, using the ascending order, are sin ( / 2) = 1 and sin (3 / 2) = sin ( / 2) = 1 . For fourth harmonic ( n = 4 ), the duty ratios obtained are,
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3 5 7 k = 0.125( 1 8 ), 0.375( 8 ),0.625( 8 ) & 0.875( 8 ) , as k < 1.0 . Similarly, for the rms value of any other even harmonic to be maximum (highest), the duty ratios can be computed. To obtain the maximum value of average or dc component as per formula given earlier, the duty ratio is ( k = 1.0 ), it being an ideal one. In this case, the switch or the device is always ON in the time period ( 0 T ), with the output voltage being constant, and also same as the average value, which is equal to the input (source) voltage. In the ideal case, no harmonic component, including fundamental one, is present in the output voltage. But the duty ratio in normal case, for buck converter (dcdc) or stepdown chopper (thyristor) circuit is ( k 1.0 ), due to the turnoff time requirement of the switching device used. For this case, the rms and average values are nearly equal, but the rms value is slightly higher than the average value. Both the above values are also nearly maximum. The ripple content is very low, with the rms values of the harmonic components, starting from fundamental, also being very low. All these can be checked from the formula.
To eliminate a given harmonic or a set of harmonics in the output voltage waveform, the condition to be satisfied is, sin n k = 0 , for which the value of the angle is n k = m , or n k = m . The case of even ( n = 2 m ) harmonics, starting from second ( n = 2 ), is taken up first. The duty ratio required is k = 0.5 , as k < 1.0 , for the elimination of second harmonic component. To eliminate fourth ( n = 4 ) harmonic component, two more values of duty ratio 3 ( k = 0.25( 1 4 ) & 0.75( 4 ) ), including the earlier one ( k = 0.5 ), as k < 1.0 , are required. It may be noted that, with the duty ratio (k = 0.5) , all even harmonic components are eliminated. To make the average value or dc component zero (0), the duty ratio required is ( k = 0.0 ). But this is an ideal case, in which the switch or the device is OFF. In normal case, duty ratio required is very small ( k 0.0 ), due to requirement of both turnon and turnoff times of the switching device used. For this case, the rms and average values are nearly equal, but the rms value is slightly higher than the average value. Both the above values are also nearly minimum. The ripple content is very low, with the rms values of the harmonic components, starting from fundamental, also being very low. All these can be checked from the formula. Now, the case of the elimination of odd ( n = 2 m + 1 ) harmonic components is described. If third ( n = 3 ) harmonic is to be 2 eliminated, two values of duty ratios required are ( k = 0.333( 1 3 ) & 0.667 ( 3 ) ), as k < 1.0 . Similarly, for any other (odd or even) harmonic component to be eliminated, the duty ratios can be computed. The rms value of the nth harmonic component of the output (load) current is, c / 2 , where the load impedance for nth harmonic is Z n = R 2 + ( n L) 2 . In = n Zn As stated earlier, the rms value of the harmonic components of the output voltage decreases and also is inversely proportional to n, as the order of the harmonic (n) is increased. The impedance at the harmonic frequency ( n f ) increases, and also is nearly proportional to n, if the load resistance (R) is assumed to be much smaller than the inductive reactance ( 2 n f L ), as the order of the harmonic is increased. So, the rms value of the nth harmonic component of the output current decreases at a faster rate, and also can be stated as being inversely proportional (nearly) to n 2 , with the increase in the order of the harmonic. If R is very small, and can be neglected, as compared to the inductive reactance, the rms value of the nth harmonic component of the output current is inversely proportional to n 2 , i.e. proportional to ( 1 / n 2 ).
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The harmonic content of the output voltage waveform is the ac ripple voltage ( V r ), which can be easily computed as shown here, without computing the harmonic components. Its rms value is defined as Vr = (V0 r ) 2 (V0 ) 2 , the other symbols having been defined earlier. The average value of the output voltage ( V0 ) is shown in Fig. 18.2b. If the Xaxis is shifted to the average value, the remaining part is the ac ripple voltage, having both positive and negative values in a cycle. The expression for ac ripple voltage is obtained as, after substituting the expressions of two voltages given earlier,
Vr = k (V s ) 2 k 2 (Vs ) 2 = V s k k 2
The ripple factor (RF) is defined as the ratio of ac ripple voltage to the average value, and is obtained as, V 1 k RF = r = V0 k It may be noted that the ac ripple voltage, in terms of rms values of all harmonic components, may also be computed as,
Vr =
(c n / 2 ) 2 =
n =1
2 (1 2 ) (c n )
n =1
This value is same as computed by the expression given earlier. In this lesson the second one in this module, the analysis of the analysis of the buck converter (dcdc) or stepdown chopper circuit, using thyristor as a switching device, with inductive (RL) and battery (or back emf = E) load, is presented in detail The procedure for the derivation of following expressions the maximum and minimum output (load) currents, assuming continuous conduction, the duty ratio for the limit of continuous conduction, the average value and the ripple factor, of the output current, and the harmonic components of the output voltage waveform, are described in detail. Starting with the next lesson the third one in this module, the operation of the additional circuits needed for commutation in thyristorbased choppers, with relevant waveforms, will be taken up in detail.
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Module 3
DC to DC Converters
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Lesson 19
Commutation of ThyristorBased Circuits PartI
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This lesson provides the reader the following: (i) (ii) (iii) (iv) Requirements to be satisfied for the successful turnoff of a SCR The turnoff groups as per the General Electric classification The operation of the turnoff circuits Design of a SCR commutation circuit
A thyristor can be turned ON by applying a positive voltage of about a volt or a current of a few tens of milliamps at the gatecathode terminals. However, the amplifying gain of this regenerative device being in the order of the 108, the SCR cannot be turned OFF via the gate terminal. It will turnoff only after the anode current is annulled either naturally or using forced commutation techniques. These methods of turnoff do not refer to those cases where the anode current is gradually reduced below Holding Current level manually or through a slow process. Once the SCR is turned ON, it remains ON even after removal of the gate signal, as long as a minimum current, the Holding Current, Ih, is maintained in the main or rectifier circuit.
Fig. 3.1 Turnoff dynamics of the SCR In all practical cases, a negative current flows through the device. This current returns to zero only after the reverse recovery time trr, when the SCR is said to have regained its reverse blocking capability. The device can block a forward voltage only after a further tfr, the forward recovery time has elapsed. Consequently, the SCR must continue to be reversebiased for a minimum of tfr + trr = tq, the rated turnoff time of the device. The external circuit must therefore reverse bias the SCR for a time toff > tq. Subsequently, the reapplied forward biasing voltage must rise at a dv/dt < dv/dt (reapplied) rated. This dv/dt is less than the static counterpart. General Electric has suggested six classification methods for the turnoff techniques generally adopted for the SCR. Others have chosen different classification rules. SCRs have turnoff times rated between 8  50 secs. The faster ones are popularly known as 'Inverter grade' and the slower ones as 'Converter grade' SCRs. The latter are available at higher current levels while the faster ones are expectedly costlier.
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Class E An external pulse source for commutation Class F AC line commutation These examples show the classes as choppers. The commutation classes may be used in practice in configurations other than choppers.
Fig. 3.2 A resonant load commutated SCR and the corresponding waveforms When the SCR is triggered, anode current flows and charges up C with the dot as positive. The LCR form a second order underdamped circuit. The current through the SCR builds up and completes a half cycle. The inductor current will then attempt to flow through the SCR in the reverse direction and the SCR will be turned off.
=
and
1 L , n = L , = n 1 2 , = tan 1 2 RC C 2R C
2 n v(t ) = V e t 2 RC sin(t ) + 1 2 1
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The capacitor voltage is at its peak when the SCR turns off and the capacitor discharges into the resistance in an exponential manner. The SCR is reversebiased till the capacitor voltages returns to the level of the supply voltage V.
Problem #1
A Class B turnoff circuit commutates an SCR. The load current is constant at 10 Amps. Dimension the commutating components L and C. The supply voltage is 100VDC.
Soln # 1
The commutating capacitor is charged to the supply voltage = 100 V The peak resonant current is, i peak = V C L Assuming,
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= (15 ) 2 = 0.0225 L 100 The SCR commutates when the total current through it reaches zero.This corresponds to 0.73 rads after the zero crossing of the resonant current. The capacitor voltage at that instant is 75 volts. After the SCR turns off, the capacitor is charged linearly by the load current. C If the SCR is to commutate at twice this load current, for a rated "Inverter grade' SCR turnoff time of 20 secs, (2.I load ).t = 75.C
20.20 F 75 = 15.33 15 C=
L= The reapplied forward voltage has a dV C = 667 700 0.0225
F H
20 = = 1.33 volts/sec rise. dt 15 It can be observed that if the peak of the commutating current is just equal to the load current, the turnoff time would be zero as the capacitor would not be able to impress any negative voltage on the SCR.
Fig. 3.4 Class C turnoff, SCR switched off by another loadcarring SCR
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The circuit shown in Figure 3.3 (Class C) can be converted to Class D if the load current is carried by only one of the SCRs, the other acting as an auxiliary turnoff SCR. The auxiliary SCR would have a resistor in its anode lead of say ten times the load resistance.
Fig. 3.5 Class D turnoff. Class D commutation by a C (or LC) switched by an Auxiliary SCR. Example 2
SCRA must be triggered first in order to charge the upper terminal of the capacitor as positive. As soon as C is charged to the supply voltage, SCRA will turn off. If there is substantial inductance in the input lines, the capacitor may charge to voltages in excess of the supply voltage. This extra voltage would discharge through the diodeinductorload circuit. When SCRM is triggered the current flows in two paths: Load current flows through the load and the commutating current flows through C SCRM LD network. The charge on C is reversed and held at that level by the diode D. When SCRA is retriggered, the voltage across C appears across SCRM via SCRA and SCRM is turned off. If the load carries a constant current as in Fig. 3.4, the capacitor again charges linearly to the dot as positive.
Problem # 2
A Class D turnoff circuit has a commutating capacitor of 10 F. The load consists of a clamped inductive load such that the load current is reasonably constant at 25 amperes. The 'Inverter grade' SCR has a turnoff time of 12 secs. Determine whether the SCR will be satisfactorily commutated. Also dimension the commutating inductor. The supply voltage is 220 VDC.
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Soln # 2
The capacitor is initially charged to the supply voltage 220 V at the end of the conduction period of SCRA. When SCRM is triggered, the 25 Amps load current and the LC ringing current flows through it. Peak current through SCR is Amps L Selecting L such that ipeak ~ 1.5 . load current,
C 25 = 0.0568 2.220 L = 3.1 mH L =
i peak = 25 + 220 C
Assuming that the capacitor charges to 70% of its original charge because of losses in the C SCRM LD network, and it charges linearly when SCRA is again triggered, I load .t q = 10(0.7.220)10 6 = 1540.10 6 tq = 1540 / 25 = 61.6
sec s
The SCR can therefore be successfully commutated. The maximum current that can be commutated with the given Capacitor at the 220 V supply voltage is I load = 1540 / 12 = 128 Amps For the 25 Amps load current the capacitor just enough would have a rating of C = I load .t q /(0.7.220) = (25.12) / 154 = 1.95 2.0
If the supply voltage is reduced by a factor K, the required capacitor rating increases by the same factor K for the same load current.
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SCR
LOAD
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energy trapped in the load inductance is dissipated. During the negative half cycle, therefore, the SCR will turn off when the load current becomes zero 'naturally'. The negative polarity of the voltage appearing across the outgoing SCR turns it off if the voltage persists for the rated turnoff period of the device. The duration of the half cycle must be definitely longer than the turnoff time of the SCR. The rectifier in Fig.3.6 is supplied from an single phase AC supply. The commutation process involved here is representative of that in a three phase converter. The converter has an input inductance Ls arising manly out of the leakage reactance of the supply transformer. Initially, SCRs Th1 and Th1' are considered to be conducting. The triggering angle for the converter is around 600. The converter is operating in the continuous conduction mode aided by the highlyinductive load. When the incoming SCRs, Th2 and Th2' are triggered, the current through the incoming devices cannot rise instantaneously to the load current level. A circulating current Isc builds up in the shortcircuited path including the supply voltage, VsLsTh1' Th2 and Vs LsTh2'Th1 paths. This current can be described by: I sc = Vs sin(t 90 0 ) Vs V cos(t ) Vs + cos = s + cos L s Ls Ls L s
where the triggering angle and Isc and Vs as shown in Fig. 3.6.
This expression is obtained with the simplifying assumption that the input inductance contains no resistances. When the current rises in the incoming SCRs, which in the outgoing Version 2 EE IIT, Kharagpur 10
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ones fall such that the total current remains constant at the load current level. When the current in the incoming ones reach load current level, the turnoff process of the outgoing ones is initiated. The reverse biasing voltage of these SCRs must continue till they reach their forward blocking state. As is evident from the above expression, the overlap period is a function of the triggering angle. It is lowest when ~ 900. These SCRs being 'Converter grade', they have a larger turnoff time requirement of about 3050 secs. The period when both the devices conduct is known as the 'overlap period'. Since all SCRs are in conduction, the output voltage for this period is zero. If the 'fullycontrolled' converter in Fig. 3.7 is used as an inverter with triggering angles > 900, the converter triggering can be delayed till the 'margin angle' which includes the overlap angle and the turnoff time of the SCR  both dependent on the supply voltages.
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Questions
#1
For a Class D turnoff SCR, the load consists of a resistance only. If the supply voltage and SCR turnoff ratings are as in Problem # 1 calculate the required value of the commutating capacitor.
Ans: (Hints): The capacitor would now charge in an exponential manner. The time it takes to discharge from its reverse charged state once SCRA is triggered is the circuit turnoff time which must be in excess of the rated 12 secs. #2
For a Class F converter, will the overlap period rise with the leakage inductance of the converter? What happens to the output voltage?
Ans: Yes. The overlap time is directly related to the commutating inductance. The output voltage decreases. In fact, this inductor limits the maximum output current of the converter. The input current maximum would be as for a shorted network with the leakage inductance only present. #3
Ans: Yes. Most of the above circuits are also called 'forced commutated' DCDC chopper circuits.
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Module 3
DC to DC Converters
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Lesson 20
Commutation of ThyristorBased Circuits PartII
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This lesson provides the reader the following: (i) (ii) (iii) (iv) (v) Practical significance of commutation Limitations of line commutation Ability to determine commutation interval Insight to different methods of commutation Consequences of the commutating methods on device stresses
20.1 Introduction
The commutation process plays an important role in the operation and control of both naturally commutated (or line commutated) and forced commutated SCR based converters. These converters may be either ACDC, DCDC or DCAC converters. The ACDC Phase
Fig. 20.1 Top: A threephase Phase Angle Converter; bottom: The input threephase voltage waveforms Angle Converter, (PAC) continues to be used in much high power and very high power converters where the application is noncritical or the nonstateoftheart is preferred for operational advantages. The following section discusses commutation with respect to this application.
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Fig. 20.2 Significant voltage and current waveforms of a single phase converter highlighting the overlap instants and the corresponding converter terminal and output voltages Subsequently, at the crossover point, VY becomes most negative and SCR2 is more forward biased with respect to SCR6. The incoming SCR does not take the full load current IL, nor does the outgoing SCR turnoff immediately. There ensues an overlap period when three SCRs conduct for a transient period. It is evident that with the simultaneous conduction of SCR2 and SCR6 there is a short circuit at the converter terminals with the short circuit current ISC being limited by the perphase series inductances LS. Line voltage VYB drives this current. With no delay in triggering (as if the SCRs are all replaced by diodes) the SCRs, they would be triggered 600 after the zero crossing of the corresponding line voltage. The triggering on this line voltage is delayed by the trigger angle from this 600 point. There are a few significant effects of the commutation process when three devices conduct. The voltage waveforms at the output and at the converter input terminals reflect the commutation process. AllSCR (fullycontrolled) converters, which are capable of operating with trigger angles between 00 to 1800 ideally, are restricted in the inverter mode to operate within the marginangle. This angle is of the order of 1600 and the output voltage is limited.
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Fig. 20.3 Short circuit currents between incoming and out going SCRs for various trigger angles Example 20.1 A singlephase converter, Fig. 20.2 operates with an input inductance LS = 0.04 mH. Indicate the current waveforms of the outgoing and incoming phase for trigger angles = 450, 900, 1600.Calculate the overlap times for each case and sketch the current waveform in the incoming SCR pair. The input voltage is 230 V, 50 Hz and the level load current is 15 Amps. Solution 20.1 The commutating voltage for a single phase converter is the supply voltage itself, 230 V. When the incoming SCRs (say 2 and 2) are triggered, the SCR pairs 1, 1 and 2, 2 are all conducting. A short circuit of the supply voltage takes place via the SCRs. A shortcircuiting current, ISC flows through the SCRs, in the forward mode in 2, 2 and reverse mode, opposing the load current, IL in 1, 1. Current, ISC is initially zero and rises ultimately to load current level when SCRs 1, 1 turn off and the overlap time is complete.
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For all trigger angles, current, ISC can be separated into two components the steady state part and the transient part. The steady state component is for all cases the current that occurs when the voltage is applied to a pure inductance (LS).
VS = 2300 0
0 0
= 73.21 90 0 Amps 2. 50.0.01 The transient current is a level current = ( the magnitude of I SS at the instant of triggering ) (A current flowing in a shortcircuited pure inductor does not decay it is level)
For = 45 0 , Transient component = 73.21sin(90 0 45 0 ) = 51.77 Amps For = 90 0 , Transient component = 73.21sin(90 0 90 0 ) = 0.00 Amps For = 160 0 , Transient component = 73.21sin(90 0 160 0 ) = 68.80 Amps
In each case the transient current adds up with the steadystate component to give the net current. Since the transients are all level currents, the steady state component can be considered to just being shifted up or down by an amount equal to the transient component. Thus for = 450, the shift is by +51.77, there is no transient for = 900, and for = 1600 the shift is by 68.80. Note the shape of the relevant portions of the current waveform lying between 0 to IL in each case. The expressions for each delay angle is:
I SC1 = 73.21sin(2. .50 90) + 51.77 I SC2 = 73.21sin( 2. .50 90) I SC3 = 73.21sin( 2. .50 90) 68.80
The overlap angle is the period over which the current in each case builds up from zero to the load current IL level. So equating each current expression to 15 Amps, 1 = cos 1 ( 36.77 73.21) + cos 1 ( 51.77 73.21) = 14.85 0 2 = cos 1 (15 73.21) + 90 0 = 11.82 0 3 = cos 1 ( 83.80 73.21) + cos 1 (68.80 73.21) so commutation is not possible for = 160 0 It may be noted that the overlap time decreases and comes to a minimum when the trigger angle reaches 900, but again increases when the delay angle goes beyond 900. Two other overlap Version 2 EE IIT, Kharagpur 6 www.jntuworld.com
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angles are also of interest. First the overlap angle for = 00 and when the delay angle just permits the overlap to be over before the commutating voltage reaches 1800. The peak of ISC occurs at this instant. This angle plus the time period required by the SCRs to complete their turnoff process (refer: turnoff dynamics of SCR) is called the Margin Angle. Assuming zero turnoff time,
= 37.33 0 The two angles are numerically equal as is evident from Fig. Example 20.1.
Fig. 20.4
The overlap time is dependent on the load current existing during the commutation period and also the voltage behind the short circuit current. This commutating voltage magnitude is dictated by the trigger angle. Thus for = 00 this voltage is minimum. At = 1800 too it would have been very low if successful commutation had been possible. However, without any allowance for an overlap time, the SCR current would just start to fall before it rises again. Note at = 1800 the
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converter operates in the inverter mode and if the out going SCR fails to turn off it is effectively triggered at = 00 which pushes the converter from peak inversion to peak rectification mode. The resulting commutation failure can cause severe short circuits. Thus the trigger angle must be restricted to values, which permit successful commutation of the SCRs.
Fig. 20.5 A voltage commutated DCDC Chopper and most significant waveforms
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Fig. 20.5 illustrates voltage commutation. ThM is the main SCR and ThAux is the Auxiliary. As a consequence of the previous cycle, Capacitor C is charged with the dot as positive. When the Main SCR is triggered, it carries the load current, which is held practically level by the large filter inductance, LF and the Freewheeling diode. Additionally, the charged Capacitor swings half a cycle through ThM, L and D ending with a negative at the dot. The reverse voltage may be less than its positive value as some energy is lost in the various components in the path. The half cycle capacitor current adds to the load current and is taken by the Main SCR. With the negative at the dot CThAux is enabled to commutate ThM. When ThAux is triggered the negative charge of the capacitor is impressed onto ThM and it immediately turns off. The SCR does take the reverse recovery current in the process. Thereafter, the level load current charges the capacitor linearly to the supply voltage with the dot again as positive. The Load voltage peaks by the addition of the capacitor voltage to the supply when ThAux is triggered. The voltage falls as the capacitor discharges both changes being linear because of the level load current. When the Capacitor voltage returns to zero, the load voltage equals supply voltage. The turnoff time offered by the commutation circuit to the SCR lasts till this stage starting from the triggering of ThAux. Now the capacitor is progressively positively charged and the load voltage is equally diminished from the supply voltage. ThAux is naturally commutated when the capacitor is fully charged and a small excess voltage switches on the free wheeling diode. With the positive at the dot the capacitor is again ready for the next cycle. Here ThAux must be switched before ThM to charge C to desired polarity. Voltage commutation may be chosen for comparatively fast switching and it can be identified from the steep fall of the SCR current. There is no overlapping operation between the incoming and the outgoing devices and both currents fall and rise sharply. Stresses on all the three semiconductors can be expected to be high here.
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If ThM is triggered first, it immediately takes the load current turning off DF. When ThAux is triggered, it takes a half cycle of the ringing current in the LC circuit and the polarity of the charge across the capacitor reverses. As it swings back, ThAux is turned off and the path through DCL shares the load current which may again be considered to be reasonably level. The Currentshare of THM is thus reduced in a sinusoidal (damped) manner. Turnoff process is consequently accompanied by an overlap between ThM and the diode D in the DCL path. Once the main SCR is turned off, the capacitor current becomes level and the voltage decreases
Fig. 20.7 A current commutated DCDC Chopper and most significant waveforms
linearly. A voltage spike appears across the load when the voltage across the commutating inductance collapses and the capacitance voltage adds to the supply voltage. The freewheeling diode also turns on through a overlap with D when the capacitor voltage just exceeds the supply voltage and this extra voltage drives the commutating current through the path DSupplyDFL. Thus there is soft switching of all devices during this period. Further an additional diode may be connected across the main SCR. It ensures soft turnoff by conducting the excess current in the ringing LC circuit. The low forward voltage appearing across the SCR causes it to turnoff slowly. Consequently switching frequencies have to be low. Note that such a diode cannot be connected across the Main SCR in the voltagecommutated circuit.
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the SCRs rise and fall sharply without any inductance regulating it. The free wheeling diode current also behaves similarly and all devices are stressed by sharp di/dt. The load voltage is of triangular shape with a peak equal to double the supply voltage (average equal to supply voltage for the conduction interval). The capacitor has a symmetric trapezoidal voltage across itself.
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The capacitor charges linearly, and the forward biasing ends when the capacitor discharges to zero. This time should be a greater than or equal to the rated turnoff time of the SCR
Therefore
C = 0.4F
Each time the capacitor conducts a current it requires 2*8 secs to reverse charge. Switching period is thus 4*8 = 32 secs. The corresponding frequency is 31 KHz. The apparent frequency is 62 as the conduction of the SCR pairs is symmetrical.
Q2 For the current commutated circuit with a diode connected antiparallel to the Main SCR estimate the turnoff time permitted as a function of the commutating capacitor and inductor. Sketch important waveforms specially the current through the Main SCR and its antparallel diode.
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Module 3
DC to DC Converters
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Lesson 21
Introduction to SwitchedMode Power Supply (SMPS) Circuits
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After completion of this lesson the reader will be able to: (i) (ii) (iii) (iv) Identify the basic elements in a regulated power supply Explain the basic principle of operation of linear and switched mode power supplies Compare the merits and demerits of SMPS visvis linear power supplies Interpret Power supply specifications
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The step down transformer talked above should be chosen such that the peak value of rectified voltage is always larger than the sum of bare minimum voltage required at the input of the regulator and the worstcase ripple in the capacitor voltage. Thus the transformer turns ratio is chosen on the basis of minimum specified supply voltage magnitude. The end user of the power supply will like to have a regulated output voltage (with voltage ripple within some specified range) while the load and supply voltage fluctuations remain within the allowable limit. To achieve this the unregulated dc voltage is fed to a voltage regulator circuit. The circuit in Fig.21.1 shows, schematically, a linear regulator circuit where a transistor is placed in between the unregulated dc voltage and the desired regulated dc output. Difference between the instantaneous input voltage and the regulated output voltage is blocked across the collector emitter terminals of the transistor. As discussed previously, in such circuits the lowest instantaneous magnitude of the unregulated dc voltage must be slightly greater than the desired output voltage (to allow some voltage for transistor biasing circuit). The power dissipation in the transistor and the useful output power will be in the ratio of voltage drops across the transistor and the load (here the control power dissipated in the base drive circuit of the transistor is assumed to be relatively small and is neglected). The worstcase series voltage drop across the transistor may be quite large if the allowed variation in supply magnitude is large. Worstcase power dissipation in the transistor will correspond to maximum supply voltage and maximum load condition (load voltage is assumed to be well regulated). Efficiency of linear voltage regulator circuits will be quite low when supply voltage is on the higher side of the nominal voltage.
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Unregulated DC source
Load
Fig. 21.3: A schematic switched mode dc to dc chopper circuit Problem 1 An 18V (rms), 50 Hz supply is rectified using a full bridge diode rectifier and is followed by a capacitor filter. The load connected across the capacitor is a simple resistor of 30 ohm. What should be the value of filter capacitor to get only 5 volts peak to peak ripple across the load voltage? Neglect voltage drop across conducting diode. [Hint: The exact solution will involve use of numerical technique or trial and error method. However with some simplifying assumptions, fairly accurate value of capacitance may be found out. It may be assumed that in each half cycle the capacitor charges to the peak of supply voltage (= 18*1.414 =25.456 volts). The ripple in the capacitor voltage may be neglected to calculate load current. Thus capacitor may be assumed to discharge under the influence of 25.456/30 amp. 1 25.456 5 ( I ) for a time duration (t) equal to . Next, use the equality Cos 2 ( freq.) 25.456 C V = I t and find C. Answer: C = approx. 1350 microfarad.] Version 2 EE IIT, Kharagpur 5 www.jntuworld.com
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Problem 2 It is desired to get a regulated 15 volts supply from the utility ac voltage of 50 Hz using a linear regulator circuit. The input ac voltage (rms magnitude) varies from 190 volts to 260volts. The utility voltage is first stepped down using a transformer. The stepped down voltage is rectified using a diode bridge and filtered by placing a capacitor after the rectified output. Assuming peaktopeak ripple in the capacitor voltage to be 10% of the capacitors crest voltage, find the turns ratio of the step down transformer. For proper operation of the linear regulator circuit the input voltage applied to it must always be 2 volts more than the desired output voltage (neglect diode drops). [Answer: Turns ratio = L.V. turns/ H.V. turns = {1.11 (15+2) } / (190* 1.414) = 1 : 14]
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frequency ripple in voltage is effectively filtered using small values of filter capacitors and inductors. A schematic chopper circuit along with the output filter is shown in Fig.21.3. Some other switched mode power supply circuits work in a slightly different manner than the dctodc chopper circuit discussed above. Details of some of these circuits have been discussed in following lessons.
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efficiency, overall weight and size, output power, output regulation, voltage ripple etc. All the topologies listed above are capable of providing isolated voltages by incorporating a high frequency transformer in the circuit. There are many commercially available power supply controller ICs that can readily be used to control the duty ratio of the SMPS switches so that the final output is well regulated. Most of these ICs are capable of driving MOSFET type of switches. They also provide features like under voltage lockout, output overcurrent protection etc. Problem 4 Which among the following power supplies will be most energyefficient if operated under wide input voltage variation and at full load: (i) (ii) (iii) (iv) Linear power supply Switched mode power supply Switched mode followed by linear power supply Linear followed by switched mode power supply
Answer: (ii)
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Module 3
DC to DC Converters
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Lesson 22
FlyBack Type Switched Mode Power Supply
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After completion of this lesson the reader will be able to: (i) (ii) (iii) (iv) Identify the topology of a flyback type switched mode power supply circuit. Explain the principle of operation of flyback SMPS circuit. Calculate the ratings of devices and components used in flyback converter for the specified input and output voltages and for the required output power. Design a simple flyback converter circuit.
22.1 Introduction
Flyback converter is the most commonly used SMPS circuit for low output power applications where the output voltage needs to be isolated from the input main supply. The output power of flyback type SMPS circuits may vary from few watts to less than 100 watts. The overall circuit topology of this converter is considerably simpler than other SMPS circuits. Input to the circuit is generally unregulated dc voltage obtained by rectifying the utility ac voltage followed by a simple capacitor filter. The circuit can offer single or multiple isolated output voltages and can operate over wide range of input voltage variation. In respect of energyefficiency, flyback power supplies are inferior to many other SMPS circuits but its simple topology and low cost makes it popular in low output power range.
The commonly used flyback converter requires a single controllable switch like, MOSFET and the usual switching frequency is in the range of 100 kHz. A twoswitch topology exists that offers better energy efficiency and less voltage stress across the switches but costs more and the circuit complexity also increases slightly. The present lesson is limited to the study of flyback circuit of single switch topology.
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Load
VO
Fig. 22.1 Fly Back Converter secondary windings of the flyback transformer dont conduct simultaneously they are more like two magnetically coupled inductors and it may be more appropriate to call the flyback transformer as inductortransformer. Accordingly the magnetic circuit design of a flyback transformer is done like that for an inductor. The details of the inductortransformer design are dealt with separately in some later lesson. The output section of the flyback transformer, which consists of voltage rectification and filtering, is considerably simpler than in most other switched mode power supply circuits. As can be seen from the circuit (Fig.22.1), the secondary winding voltage is rectified and filtered using just a diode and a capacitor. Voltage across this filter capacitor is the SMPS output voltage. It may be noted here that the circuit shown in Fig.22.1 is rather schematic in nature. A more practical circuit will have provisions for output voltage and current feedback and a controller for modulating the duty ratio of the switch. It is quite common to have multiple secondary windings for generating multiple isolated voltages. One of the secondary outputs may be dedicated for estimating the load voltage as well as for supplying the control power to the circuit. Further, as will be discussed later, a snubber circuit will be required to dissipate the energy stored in the leakage inductance of the primary winding when switch S is turned off. Under this lesson, for ease of understanding, some simplifying assumptions are made. The magnetic circuit is assumed to be linear and coupling between primary and secondary windings is assumed to be ideal. Thus the circuit operation is explained without consideration of winding leakage inductances. ON state voltage drops of switches and diodes are neglected. The windings, the transformer core, capacitors etc. are assumed lossless. The input dc supply is also assumed to be ripplefree. [A brief idea of a more practical flyback converter will be given towards the end of this lesson.]
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+ Edc
Vpri
Vsec VO N1 : N2
Under Mode1, the input supply voltage appears across the primary winding inductance and the primary current rises linearly. The following mathematical relation gives an expression for current rise through the primary winding: d EDC = LPr i iPr i (22.1), dt where EDC is the input dc voltage, LPr i is inductance of the primary winding and iPr i is the instantaneous current through primary winding. Linear rise of primary winding current during mode1 is shown in Fig.22.5(a) and Fig.22.5(b). As described later, the flyback circuit may have continuous flux operation or discontinuous flux operation. The waveforms in Fig.22.5(a) and Fig.22.5(b) correspond to circuit operations in continuous and discontinuous flux respectively. In case the circuit works in continuous flux mode, the magnetic flux in the transformer core is not reset to zero before the next cyclic turning ON of switch S. Since some flux is already present before S is turned on, the primary winding Version 2 EE IIT, Kharagpur 5 www.jntuworld.com
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current in Fig. 22.3(a) abruptly rises to a finite value as the switch is turned on. Magnitude of the currentstep corresponds to the primary winding current required to maintain the previous flux in the core. At the end of switchconduction (i.e., end of Mode1), the energy stored in the magnetic field of 2 2 , where I P denotes the magnitude of the fly back inductortransformer is equal to LPr i I P primary current at the end of conduction period. Even though the secondary winding does not conduct during this mode, the load connected to the output capacitor gets uninterrupted current due to the previously stored charge on the capacitor. During mode1, assuming a large capacitor, the secondary winding voltage remains almost constant and equals to VSec = EDC N 2 / N1 . During mode1, dotted end of secondary winding remains at higher potential than the other end. Under this condition, voltage stress across the diode connected to secondary winding (which is now reverse biased) is the sum of the induced voltage in secondary and the output voltage ( Vdiode = VO + EDC N 2 / N1 ). Mode2 of circuit operation starts when switch S is turned off after conducting for some time. The primary winding current path is broken and according to laws of magnetic induction, the voltage polarities across the windings reverse. Reversal of voltage polarities makes the diode in the secondary circuit forward biased. Fig. 22.3(a) shows the current path (in bold line) during mode2 of circuit operation while Fig. 22.3(b) shows the functional equivalent of the circuit during this mode.
+ Edc
Vpri
Vsec VO
N1: N2
Fig:22.3(a) : Current path during Mode2 of circuit operation
In mode2, though primary winding current is interrupted due to turning off of the switch S, the secondary winding immediately starts conducting such that the net mmf produced by the windings do not change abruptly. (mmf is magneto motive force that is responsible for flux production in the core. Mmf, in this case, is the algebraic sum of the ampereturns of the two windings. Current entering the dotted ends of the windings may be assumed to produce positive mmf and accordingly current entering the opposite end will produce negative mmf.) Continuity of mmf, in magnitude and direction, is automatically ensured as sudden change in mmf is not supported by a practical circuit for reasons briefly given below. [mmf is proportional to the flux produced and flux, in turn, decides the energy stored in the magnetic field (energy per unit volume being equal to B 2 2 , B being flux per unit area and is the permeability of the medium). Sudden change in flux will mean sudden Version 2 EE IIT, Kharagpur 6 www.jntuworld.com
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change in the magnetic field energy and this in turn will mean infinite magnitude of instantaneous power, some thing that a practical system cannot support.] For the idealized circuit considered here, the secondary winding current abruptly rises from zero to I P N1 N 2 as soon as the switch S turns off. N 1 and N 2 denote the number of turns in the primary and secondary windings respectively. The sudden rise of secondary winding current is shown in Fig. 22.5(a) and Fig. 22.5(b). The diode connected in the secondary circuit, as shown in Fig.22.1, allows only the current that enters through the dotted end. It can be seen that the magnitude and current direction in the secondary winding is such that the mmf produced by the two windings does not have any abrupt change. The secondary winding current charges the output capacitor. The + marked end of the capacitor will have positive voltage. The output capacitor is usually sufficiently large such that its voltage doesnt change appreciably in a single switching cycle but over a period of several cycles the capacitor voltage builds up to its steady state value. The steadystate magnitude of output capacitor voltage depends on various factors, like, input dc supply, flyback transformer parameters, switching frequency, switch duty ratio and the load at the output. Capacitor voltage magnitude will stabilize if during each switching cycle, the energy output by the secondary winding equals the energy delivered to the load. As can be seen from the steady state waveforms of Figs.22.5(a) and 22.5(b), the secondary winding current decays linearly as it flows against the constant output voltage (VO). The linear d decay of the secondary current can be expressed as follows: LSec iSec = VO  (22.2), dt Where, LSec and iSec are secondary winding inductance and current respectively.
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Mode3 ends with turn ON of switch S and then the circuit again goes to Mode1 and the sequence repeats.
+ Edc
VO
+ Edc
VO
Figs.22.4(a) and 22.4(b) respectively show the current path and the equivalent circuit during mode3 of circuit operation. Figs.22.5(a) and 22.5(b) show, the voltage and current waveforms of the winding over a complete cycle. It may be noted here that even though the two windings of the flyback transformer dont conduct simultaneously they are still coupled magnetically (linking the same flux) and hence the induced voltages across the windings are proportional to their number of turns.
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IP Io I pri
0
tON
IP X N1 / N2
Time
Io X N1 / N2 I sec
0
tON EDC
Time
V pri
0 MODE1
VO X N1 / N2 tON
MODE2 T MODE1
Time
V load
VO Time
Fig.22.5(a): Flyback circuit waveforms under continuous magnetic flux
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core (made of ferrite material) must have low hysteresis loss even at high frequency operation. Since the ferrite cores have very low conductivity, the eddy current related loss in the core is generally insignificant.
IP I pri
0
tON IP X N1 / N2
Time
I sec
0
tON EDC
Time
V pri
VO X N1 / N2 tON
MODE1 MODE2 MODE3 T
Time
MODE1
V load 0
VO Time
Fig.22.5(b): Flyback circuit waveforms under discontinuous flux
With the turning ON of the switch, the primary winding current starts building up linearly from zero and at the end of mode1 the magnetic field energy due to primary winding current rises to 1 2 . This entire energy is transferred to the output at the end of mode2 of circuit operation. L pri I P 2 Under the assumption of lossless operation the output power (Po) can be expressed as: Po =
1 2 fswitch (22.7), L pri I P 2
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where fswitch (=1/T) is the switching frequency of the converter. It may be noted that output power Po is same as V0 ILoad used in Eqn.(22.4). The volttime area equation as given in Eqn.(22.5) gets modified under discontinuous flux mode of operation as follows: Edc (N1 / N2) V0 (1) (22.8) Average voltage across windings over a switching cycle is still zero. The inequality sign of Eqn.22.8 is due to the fact that during part of the OFF period of the switch [= (1)T], the winding voltages are zero. This zero voltage duration had been identified earlier as mode3 of the circuit operation. The equality sign in Eqn.(22.8) will correspond to justcontinuous case, which is the boundary between continuous and discontinuous mode of operation. The expression for Vswitch and Vdiode, as given in Eqns.(22.6) and (22.6a), will hold good in discontinuous mode also.
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taken close to 0.6 for first design iteration. Similarly one needs to counter the effects of the nonideal coupling between the windings. Due to the nonideal coupling between the primary and secondary windings when the primary side switch is turnedoff some energy is trapped in the leakage inductance of the winding. The flux associated with the primary winding leakage inductance will not link the secondary winding and hence the energy associated with the leakage flux needs to be dissipated in an external circuit (known as snubber). Unless this energy finds a path, there will be a large voltage spike across the windings which may destroy the circuit. Fig.22.6 shows a practical flyback converter. The snubber circuit consists of a fast recovery diode in series with a parallel combination of a snubber capacitor and a resistor. The leakageinductance current of the primary winding finds a low impedance path through the snubber diode to the snubber capacitor. It can be seen that the diode end of the snubber capacitor will be at higher potential. To check the excessive voltage build up across the snubber capacitor a resistor is put across it. Under steady state this resistor is meant to dissipate the leakage flux energy. The power lost in the snubber circuit reduces the overall efficiency of the flyback type SMPS circuit. A typical figure for efficiency of a flyback circuit is around 65% to 75%. In order that snubber capacitor does not take away any portion of energy stored in the mutual flux of the windings, the minimum steady state snubber capacitor voltage should be greater than the reflected secondary voltage on the primary side. This can be achieved by proper choice of the snubberresistor and by keeping the RC time constant of the snubber circuit significantly higher than the switching time period. Since the snubber capacitor voltage is kept higher than the reflected secondary voltage, the worstcase switch voltage stress will be the sum of input voltage and the peak magnitude of the snubber capacitor voltage. S N U B B E R
N1:N2
Edc
RS
Load
V (o/p)
N3 PWM
Control Block
Current Feedback Fig. 22.6 A Practical Fly Back Converter The circuit in Fig.22.6 also shows, in block diagram, a Pulse Width Modulation (PWM) control circuit to control the duty ratio of the switch. In practical flyback circuits, for closed loop output voltage regulation, one needs to feed output voltage magnitude to the PWM controller. In order to maintain ohmic isolation between the output voltage and the input switching circuit the output voltage signal needs to be isolated before feeding back. A popular way of feeding the isolated voltage information is to use a tertiary winding. The tertiary winding voltage is rectified in a way Version 2 EE IIT, Kharagpur 13 www.jntuworld.com
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similar to the rectification done for the secondary winding. The rectified tertiary voltage will be nearly proportional to the secondary voltage multiplied by the turnsratio between the windings. The rectified tertiary winding voltage also doubles up as control power supply for the PWM controller. For initial powering up of the circuit the control power is drawn directly from the input supply through a resistor (shown as RS in Fig.22.6) connected between the input supply and the capacitor of the tertiary circuit rectifier. The resistor RS is of high magnitude and causes only small continuous power loss. In case, multiple isolated output voltages are required, the flyback transformer will need to have multiple secondary windings. Each of these secondary winding voltages are rectified and filtered separately. Each rectifier and filter circuit uses the simple diode and capacitor as shown earlier for a single secondary winding. In the practical circuit shown above, where a tertiary winding is used for voltage feedback, it may not be possible to compensate exactly for the secondary winding resistance drop as the tertiary winding is unaware of the actual load supplied by the secondary winding. However for most applications the small voltage drop in the winding resistance may be tolerable. Else, one needs to improve the voltage regulation by adding a linear regulator stage in tandem (as mentioned in Chapter21) or by giving a direct output voltage feedback to the control circuit.
Quiz Problems
(i) What kind of output rectifier and filter circuit is used in a fly back converter? (a) a fourdiode bridge rectifier followed by a capacitor (b) a single diode followed by an inductorcapacitor filter (c) a single diode followed by a capacitor (d) will require a centertapped secondary winding followed by a full wave rectifier and a output filter capacitor. (ii) A flyback converter operates in discontinuous conduction mode with fixed ON duration of the switch in each switching cycle. Assuming input voltage and the resistive load at the output to remain constant, how will the output voltage change with change in switching frequency? (Assume discontinuous conduction through out and neglect circuit losses.) (a) Output voltage varies directly with switching frequency. (b) Output voltage varies inversely with switching frequency. (c) Output voltage varies directly with square root of switching frequency. (d) Output voltage is independent of switching frequency. (iii) A flyback converter has primary to secondary turns ratio of 15:1. The input voltage is constant at 200 volts and the output voltage is maintained at 18 volts. What should be the snubber capacitor voltage under steady state? (a) (b) (c) (d) More than 270 volts. More than 200 volts but less than 270 volts. Less than 18 volts. Not related to input or output voltage.
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(iv) A flyback converter is to be designed to operate in justcontinuous conduction mode when the input dc is at its minimum expected voltage of 200 volts and when the load draws maximum power. The load voltage is regulated at 16 volts. What should be the primary to secondary turns ratio of the transformer if the switch duty ratio is limited to 80%. Neglect ONstate voltage drop across switch and diodes. (a) (b) (c) (d) 20 :1 30 :1 25 :2 50 :1
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Module 3
DC to DC Converters
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Lesson 23
Forward Type Switched Mode Power Supply
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After completion of this lesson the reader will be able to: (i) (ii) (iii) (iv) Identify the topology of a forward type switched mode power supply circuit. Explain the principle of operation of a forward dctodc power supply. Calculate the ratings of devices, components, transformer turns ratio for the given input and output voltages and the required output power. Design a simple forward type switched mode power supply circuit.
23.1 Introduction
Forward converter is another popular switched mode power supply (SMPS) circuit that is used for producing isolated and controlled dc voltage from the unregulated dc input supply. As in the case of flyback converter (lesson22) the input dc supply is often derived after rectifying (and little filtering) of the utility ac voltage. The forward converter, when compared with the flyback circuit, is generally more energy efficient and is used for applications requiring little higher power output (in the range of 100 watts to 200 watts). However the circuit topology, especially the output filtering circuit is not as simple as in the flyback converter. Fig. 23.1 shows the basic topology of the forward converter. It consists of a fast switching device S along with its control circuitry, a transformer with its primary winding connected in series with switch S to the input supply and a rectification and filtering circuit for the transformer secondary winding. The load is connected across the rectified output of the transformersecondary. NP : NS
Edc
D1 D2 C
Load
V (o/p)
Control Circuit
Switch S
Fig. 23.1: Basic Topology of a Forward Converter The transformer used in the forward converter is desired to be an ideal transformer with no leakage fluxes, zero magnetizing current and no losses. The basic operation of the circuit is explained here assuming ideal circuit elements and later the nonideal characteristics of the devices are taken care of by suitable modification in the circuit design. In fact, due to the presence of finite magnetizing current in a practical transformer, a tertiary winding needs to be introduced in the transformer and the circuit topology changes slightly. A Version 2 EE IIT, Kharagpur 3 www.jntuworld.com
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The transformer used in the circuit is assumed to be ideal requiring no magnetizing current, having no leakage inductance and no losses. The filter circuit elements like, inductors and capacitors are assumed lossless. For the simplified steadystate analysis of the circuit the switch duty ratio (), as defined in the previous chapters is assumed constant. The input and output dc voltages are assumed to be constant and ripplefree. Current through the filter inductor (L) is assumed to be continuous.
NS Edc NP
N
Load
VO
As can be seen, the output circuit consisting of LC filter and the load gets a voltage equal N to S Edc during mode1. This voltage is shown across points P and N in Fig. 23.2(b) and it is NP the maximum achievable dc voltage across the load, corresponding to = 1. Mode1 can be called as powering mode during which input power is transferred to the load. Mode2, to be called as freewheeling mode, starts with turning off of the switch S.
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Load VO
Fig. 23.3(a) shows the current carrying portion of the circuit in bold line and Fig. 23.3(b) shows the equivalent circuit active during mode2. Points P and N of the equivalent circuit are effectively shorted due to conduction of diode D2. The inductor current continues to flow through the parallel combination of the load and the output capacitor. During mode2, there is no power flow from source to load but still the load voltage is maintained nearly constant by the large output capacitor C. The charged capacitor and the inductor provide continuity in load voltage. However since there is no input power during mode2, the stored energy of the filter inductor and capacitor will be slowly dissipating in the load and hence during this mode the magnitudes of inductor current and the capacitor voltage will be falling slightly. In order to keep the load voltage magnitude within required tolerance band, the converterswitch S is turned on again to end the freewheeling mode and start the next powering mode (mode1). Under steady state, loss in inductor current and capacitor voltage in mode2 is exactly made up in mode1. It may not be difficult to see that to maintain load voltage within the desired tolerance band the filter inductor and capacitor magnitudes should be sufficiently large. However, in order to keep the filter cost and its physical size small these elements should not be unnecessarily too large. Also, for faster dynamic control over the output voltage the filter elements should not be too large. [It may be pointed out here that the filter inductor, capacitor, transformer and the heat sinks for the switching devices together account for nearly 90% of the power supply weight and volume.] One important factor that directly influences the size of the filter circuit elements and the transformer is the converters switching frequency. High frequency operation of switch S will help in keeping the filter and transformer size small. The switching frequency of a typical forward converter may thus be in the range of 100 kHz or more. The higher end limit on the switching frequency comes mainly due to the finite switching time and finite switching losses of a practical switch. Switch limitations have been ignored in the simplified analysis presented here. As mentioned earlier, the switch and the diodes have been assumed to be ideal, with no losses and zero switching time. Control over switch duty ratio, which is the ratio of ON time to (ON + OFF) time, provides the control over the output voltage VO.
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constant input and output voltage, the instantaneous value of inductor voltage (eL) during mode1 can be written as: N eL (t) = S Edc  VO ; for 0 t T,  (23.1) NP Where t = 0 is the time instant when mode1 of any steady state switching cycle starts, T is the switching time period that may be assumed to be constant and is the duty ratio of the switch. It can be seen that T is the time duration of mode1 and (1) T is the time duration of mode2. The inductor voltage during mode2 may similarly be written as: eL (t) =  VO ; for T t T,  (23.2) Now since voltage across an inductor, averaged over a steady state cycle time, must always be zero, one gets: N [ S Edc  VO ] + [ VO ] (1) = 0, NP N Or, VO = S Edc  (23.3) NP Thus according to Eqn. (23.3), the forward converter output voltage is directly proportional to the switch duty ratio. It may be noticed that except for transformer scaling factor the output voltage relation is same as in a simple dctodc buck converter. It is to be noted that the output voltage relation given by Eqn. (23.3) is valid only under the assumption of continuous inductor current. For an improperly designed circuit or for very light load at the converter output, the inductor current may decay to zero in the midst of mode2 resulting into discontinuous inductor current. Once the inductor current becomes zero, diode D2 in Fig. 23.3(a) no longer conducts and the points P and N of the equivalent circuit in Fig. 23.3(b) are no longer shorted. In fact, the output voltage VO will appear across P and N. Thus equation (23.2) remains valid only for a part of (1) T period. In case of discontinuous inductor current, the output voltage, which is the average of voltage across points P and N will have a higher magnitude than the one given by Eqn. (23.3). Under discontinuous inductor current the relation between output voltage and switch duty ratio becomes nonlinear and is load dependent. For better control over output voltage discontinuous inductor current mode is generally avoided. With prior knowledge of the loadrange and for the desired switching frequency the filter inductor may be suitably chosen to keep the inductor current continuous and preferably with less ripple.
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which neglects many of the nonidealities. Another common nonideality is the low frequency ripple and fluctuation in input dc supply voltage. In the simplified analysis input supply has been assumed to be of constant magnitude. In a practical circuit, the variation in input supply is taken care of by modulating the switch duty ratio in such a manner that it offsets the effect of supply voltage fluctuation and continues to give the required quality of output voltage. The nonideality of the transformer, however, cannot simply be overcome by changing the circuit parameters of the simplified circuit shown in Fig. 23.1. A practical transformer will have finite magnetization current and finite energy associated with this magnetization current. Similarly there will be some leakage inductance of the windings. However, windings of the forwardconverter transformer will have much smaller leakage inductances than those of flyback converter transformer. In flyback transformers flux path some airgap is deliberately introduced by creating a gap in the transformer core (refer to lesson22). Introduction of air gap in the mutual flux path increases the magnitude of leakage inductances. Transformer of a forward converter should have no airgap in its flux path. The forwardconverter transformer works like a normal power transformer where both primary and secondary windings conduct simultaneously with opposing magneto motive force (mmf) along the mutual flux path. The difference of the mmfs is responsible for maintaining the magnetizing flux in the core. When primary winding current is interrupted by switching off S, the dotted ends of the windings develop negative potential to oppose the interruption of current (in accordance with Lenzs law). Negative potential of the dotted end of secondary winding makes diode D1 reverse biased and hence it also stops conducting. This results in simultaneous opening of both primary and secondary windings of the transformer. In case the basic circuit of Fig. 23.1 is used along with a practical transformer, turning off of switch S will result in sudden demagnetization of the core from its previously magnetized state. As discussed in Lesson22, a practical circuit cannot support sudden change in flux. Any attempt to change flux suddenly results in generation of infinitely large magnitude of voltage (in accordance with Lenzs law). Such a large voltage in the circuit will have a destructive effect and that should be avoided. Thus, after switch S is turned off, there must exist a convenient path for the trapped energy in the primary due to magnetizing current. One solution could be a snubber circuit across the primary winding, similar to the one shown in Fig.22.6 for a flyback circuit (refer to lesson22). Each time the switch S is turned off the snubber circuit will dissipate the energy associated with the magnetizing flux. This, as has been seen in connection with flyback converter, reduces the powersupply efficiency considerably. A more preferred solution is to recover this energy. For this reason the practical forward converter uses an extra tertiary winding with a series diode, as shown in Fig. 23.4. When both switch S and D1 turnoff together, as discussed above, the magnetization energy will cause a current flow through the closely coupled tertiary winding and the diode D3. The dot markings on the windings are to be observed. Current entering the dot through any of the magnetically coupled windings will produce magnetic flux in the same sense. As soon as switch S is turned off, the dotted end voltages of the windings will become negative in accordance with Lenzs law. The sudden rise in magnitude of negative potential across the windings is checked only by the conduction of current through the tertiary winding. As discussed earlier unless the continuity in transformer flux is maintained the voltages in the windings will theoretically reach infinite value. Thus turning off of switch S and turnon of diode D3 need to be simultaneous. Similarly fall in magnetizing current through primary winding must be coupled with simultaneous rise of magnetization current through the tertiary winding. In order that the entire flux linking the primary winding gets transferred to the tertiary, the magnetic coupling between these two windings must be very good. For this the primary and tertiary winding turns Version 2 EE IIT, Kharagpur 8 www.jntuworld.com
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are wound together, known as bifilar windings. The wires used for bifilar windings of the primary and the tertiary need to withstand large electrical voltage stress and are costlier than ordinary transformer wires. NT : NP : NS
Edc
D1 D2 C
Load V (o/p)
D3
Switch S
Fig. 23.4: Circuit topology of a practical forward converter Fig. 23.5 shows some of the typical current and voltage waveforms of the forward converter shown in Fig. 23.4. For these waveforms, once again, many of the ideal circuit assumptions have been made. In Fig. 23.5, Vload is the converter output voltage that is maintained constant at VO. IL is the current through filter inductor L. The inductor current rises linearly during mode1 as its voltage is maintained constant as per Eqn.23.1. Similarly the inductor current decays at a constant rate in mode2 as it flows against the constant output voltage. Average magnitude of inductor current equals the load current. ISW and VSW are respectively the switch current and switch voltage. VD3 is the voltage across diode D3. Switch conducts only during mode1 and carries the primary winding current (IPr) of the transformer. The transformer magnetization current is assumed to be negligibly small and hence the primary winding essentially carries the reflected inductor current. As switch S turns on, primary winding gets input dc voltage (with its dotted end positive). The induced voltages in other windings are in proportion to their turns ratios. Diode D3 of the tertiary N winding is reverse biased and is subjected to a voltage Edc (1 + T ) . NP As soon as switch S is turnedoff, primary and secondary winding currents fall to zero but diode D3 gets forward biased and the tertiary winding starts conducting to maintain a path for the magnetizing current. While D3 conducts the tertiary winding voltage is clamped to input dc voltage with its dotted end negative. Primary and secondary windings have induced voltages due N to transformer action. Primary winding voltage equals to Edc P , with dotted end at negative NT potential. In Fig. 23.5, VPr denotes the primary winding voltage. The net volttime area of the primary Version 2 EE IIT, Kharagpur 9 www.jntuworld.com
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winding voltage must be zero under steady state. Voltage across switch S can be seen to be the N sum of primary winding voltage and the input voltage and equals Edc (1 + P ) . NT As the tertiary winding current flows against the input dc supply, the magnetization current decays linearly given by the following relation:
NT d m = Edc dt
 (23.4)
Where, m = flux through the transformer core. When the transformer is completely demagnetized, diode D3 turns off and voltage across transformer windings fall to zero. The transformer remains demagnetized for the remaining duration of Mode2. When switch S is again turned on, in the next switching cycle, the transformer flux builds up d m = Edc ,  (23.5) linearly given by the relation: N P dt Under steadystate the increase in flux during conduction of switch S must be equal to fall in flux during conduction of tertiary winding and hence Eqns. 23.4 and 23.5 may be combined to t t show that T = P , where tT and tP are the time durations for which tertiary and primary NT N P windings conduct during each switching cycle. Now, tP = T = onduration of switch S and the tertiary winding conducts only during off duration of switch (during mode2). Hence, (1) T tT . As a result, N NP P , or  (23.6) ( N P + NT ) 1 NT Thus if N P = NT , the duty ratio must be less than or equal to 50% or else the transformer magnetic circuit will not get time to reset fully during mode2 and will saturate. Less duty ratio means less duration of powering mode (mode1) and hence less transfer of power to the output N circuit. On the other hand, as described above, if P is increased for higher duty ratio, the switch NT voltage stress increases.
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V load
VO Imax Time
IL
0
Time
I Pr
0
tON
Edc
Time
V Pr
0
Edc
NP NT
Time
Time
Edc NP ) NT
Edc
V D3
Edc (1 + NT ) NP
Edc (1 +
V sw 0 tON = T
MODE1 MODE2
T
MODE1
Time
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voltage ( Edc ) and the maximum allowable duty ratio (). The maximum duty ratio of the converter, as discussed above, is constrained by the primary to tertiary winding turns ratio (given by Eqn. 23.6) but the choice of primary to tertiary winding turns ratio is often governed by the voltage stress that the switch must withstand. Higher voltage stress will mean higher cost of switch. If the tertiary winding turns is kept very high, the switch voltage stress reduces but allowable duty ratio of switch and the power output of the converter becomes low and diode D3 voltage rating increases. Thus an optimum design needs to be arrived at to maximize the performance of the converter.
 (23.8)
where VO, the output voltage, is assumed to have a fixed magnitude. Input supply voltage, Edc , may itself be varying and the duty ratio is adjusted to keep VO constant in accordance with N Eqn.23.3. Thus even though Edc and are varying, their product ( S Edc ) will be constant NP Version 2 EE IIT, Kharagpur 12
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and equal to VO. [As mentioned earlier, only low frequency variation in supply voltage has been considered. Switching frequency and the switch control dynamics are assumed to be much faster.] Hence, the inductor L magnitude should correspond to minimum value of duty ratio and may be 5VO (1 min )  (23.9) written as L = I rated f SW ,where min is the minimum magnitude of duty ratio and f SW is the constant switching frequency of the converter switch. Now in accordance with Eqn.(23.6) the maximum value of NP duty ratio may be taken as max = . Again to maintain constant output voltage ( N P + NT ) max Edc ,max = .  (23.10) min Edc ,min , where Edc ,max and Edc ,min are maximum and minimum magnitudes of input dc voltage respectively. Thus min =
Edc ,min Edc ,max NP and ( N P + NT )
L=
The inductor magnitude given by Eqn.(23.11) will limit the worst case peak to peak current ripple in the filter inductor (= Imax  Imin) to 20% of rated current. [refer to Eqns.(23.7) and (23.8). It may be noted here that as long as inductor current is continuous the peaktopeak ripple in the inductor current is not affected by the dc value of load current. For constant output voltage and constant current through load, the inductor current ripple depends only on the duty ratio, which in turn depends on the magnitude of input dc voltage] Once inductor magnitude is chosen in accordance with Eqn.(23.11), peak to peak ripple in the capacitor current will also be 20% of the rated current. This is so because the load, under steady state, has been assumed to draw a constant magnitude of current. Even though the output capacitor voltage has been assumed constant in our analysis so far, there will be a minor ripple in capacitor voltage too which however will have only negligible effect on the analysis carried out earlier. The worst case, peak to peak ripple in capacitor voltage I ( vO , p p ) can be given as: vO , p p = rated  (23.12) 20Cf SW , where C is the output capacitance in farad. Capacitance value should be chosen, in accordance with the above equation, based on the allowed ripple in the output voltage.
Quiz
1). If the turns ratio of the primary and tertiary windings of the forward transformer are in the ratio of 1:2, what is the maximum duty ratio at which the converter can be operated? Corresponding to this duty ratio, what should be the minimum ratio of secondary to primary Version 2 EE IIT, Kharagpur 13
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turns if the input dc supply is 400 volts and the required output voltage is 15 volts? Neglect switch and diode conduction voltage drops.
[Answer: 1/3 and 9/80]
2) Find maximum voltage stress of the switch in the primary winding and diode in the tertiary winding if the convertertransformer has 10 primary turns and 15 tertiary turns and the maximum input dc voltage is 300 volts.
[Answer: Switch voltage stress = 500V, diode voltage stress = 750V]
3) Calculate the filter inductor and capacitor values for the forward converter described below: Maximum duty ratio = 0.5, Input dc remains constant at 200 volts, output dc (under steady state) = 10 volts 0.1 volt, primary to secondary turns = 10:1. The load current is expected to vary between 0.5 and 5 amps. Assume just continuous conduction of inductor current at 0.5 amp load current. Take switching frequency = 100 kHz.
[Answer: L = 50 micro Henry and C = 12.5 micro Farad]
(4) What function does the diode D1 of circuit in Fig.(23.4) have? (i) rectifies secondary voltage (ii) blocks back propagation of secondary voltage to transformer (iii) both (i) and (ii) (iv) protects diode D2 from excessive reverse voltage
[Answer: (iii)]
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Module 3
DC to DC Converters
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Lesson 24
C uK and Sepic Converter
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Instructional objective
On completion the student will be able to
and Sepic converters with those of Compare the advantages and disadvantages of CuK three basic converters. and Sepic Draw the circuit diagrams and identify the operating modes of CuK converters. and Sepic converters. Draw the waveforms of the circuit variables associated with CuK converter. Calculate the capacitor voltage ripples and inductor current ripples in CuK
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24.1
Introduction
Switch Mode Power Supply topologies follow a set of rules. A very large number of converters have been proposed, which however can be seen to be minor variations of a group of basic DCDC converters built on a set of rules. Many consider the basic group to consist of the three: BUCK, BOOST and BUCKBOOST converters. The CUK, essentially a BOOSTBUCK converter, may not be considered as basic converter along with its variations: the SEPIC and the zeta converters. The Canonical Cell forms the basis of analyzing switching circuits, but the energy transport mechanism forms the foundation of the building blocks of such converters. The Buck converter may consequently be seen as a Voltage to Current converter, the Boost as a Current to Voltage converter, the BuckBoost as a VoltageCurrentVoltage and the CUK as a CurrentVoltageCurrent converter. All other switching converter MUST fall into one of these configurations if it does not increase the switching stages further for example into a VIVI converter which is difficult to realize through a single controlled switch. It does not require an explanation that a current source must be made to deliver its energy into a voltage sink and viceversa. A voltage source cannot discharge into a voltage sink and neither can a current source discharge into a current sink. The first would cause current stresses while the latter results in voltage surges. This rule is analogous to the energy exchange between a source of Potential Energy (Voltage of a Capacitor) and a sink of Kinetic Energy (Current in an Inductor) and viceversa. Both can however discharge into a dissipative load, without causing any voltage or current amplification. The resonant converters also have to agree to some of these basic rules.
24.2
Analysis of C uK converter
The advantages and disadvantages of three basic nonisolated converters can be summerised as given below. (i) Buck converter 1 2 Vin S1 L iB C
Fig. 24.1: Circuit schematic of a buck converter Features of a buck converter are Pulsed input current, requires input filter. Continuous output current results in lower output voltage ripple. Output voltage is always less than input voltage.
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(ii)
Boost converter
L 2 Vin
1 S1 R C
Fig. 24.2: Circuit schematic of a boost converter Features of a boost converter are Continuous input current, eliminates input filter. Pulsed output current increases output voltage ripple. Output voltage is always greater than input voltage. (iii) Buck  Boost converter 1 S1 Vin L R C 2
Fig. 24.3: Circuit schematic of a buck boost converter Features of a buck  boost converter are Pulsed input current, requires input filter. Pulsed output current increases output voltage ripple Output voltage can be either greater or smaller than input voltage. It will be desirable to combine the advantages of these basic converters into one converter. converter is one such converter. It has the following advantages. CuK Continuous input current. Continuous output current. Output voltage can be either greater or less than input voltage.
CuK converter is actually the cascade combination of a boost and a buck converter. L1 L2 2
S1 Vin 1 + C S2 1' Fig. 24.4: Circuit schematic of a boostbuck converter Version 2 EE IIT, Kharagpur 5 www.jntuworld.com 2' + C2 
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S1 and S2 operate synchronously with same duty ratio. Therefore there are only two switching states. (i) 0 < t DT S1 & S2 to to (1) (1')
Vin
C1
C2
C2
Vin
C2
C2
(b) Fig. 24.5: Circuit topology of a boostbuck converter during different switching intervals (a) 0 t < DT, (b) DT t < T These two topologies can also be obtained from the following circuit which is the so called converter. CuK
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L1 1 Vin
C1 2
L2
R C2 (a)
L1 iL1 Vin iB 1
vc1 C1
L2 iL2 ic2 i0 + C2 R V0
(b)
Fig. 24.6: Schematic and Circuit representation of CuK converter. (a) Schematic diagram, (b) Circuit diagram
C1  L2
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Vin DT + (Vin VC 1 ) (1 D ) T = 0
or
(24.1)
Vin (1 D ) VC 1 = 0
VC1 =
Vin 1 D
(24.2)
(V0 + VC1 ) DT + V0 (1 D ) T = 0
or or
(24.3) (24.4)
V0 + DVC1 = 0
V0 = DVC1 =
DVin 1 D
(24.5)
Expression for average inductor current can be obtained from charge balance of C2
I L 2 + I0 = 0
From power balance
(24.6)
I L 2 = I0 =
V0 V = D in R 1 D R
(24.7)
Vin I L1
2 2 2 v0 Vin D = V0 I 0 = = R (1 D )2 R
(24.8)
I L1 =
D 2 Vin 2 (1 D ) R
(24.9)
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iB
DT
T t
IL1 MAX IL1 iL1 IL1 MIN t IL2 MAX IL2 iL2 IL2 MIN t1 ic1 IL2 MIN  IL1 MIN  IL1 MAX vc1 VC1 MAX VC1 VC1 MIN t t2 IL2 MAX t
ic2
L2 1/2 I
pp
t1 Vc2
t2
1/2 I L2
pp
t Vc2
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(24.10)
p p
= I L1MAX I L1MIN =
(24.11)
(24.12)
(24.13)
(24.14)
(24.15)
p p
= I L 2 MAX I L 2 MIN =
(24.16)
V I L 2 MAX + I L 2 MIN = 2 I 0 = 2 D in 1 D R DVin I L 2 MAX = 1 + RT 1 D 2 L2 R DVin I L 2 MIN = 1 RT 1 D 2 L2 R For calculating voltage ripples it is noted that
DT vc1 = 1 ic1 dt 0 c1
(24.17)
(24.18)
(24.19)
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or
(24.23)
or
(24.24)
V DT Vin DT 2 c = 1 1 T in v = c1 2 2 2 L2 8 L2 C2
(24.25)
converter of given Equations 24.11, 24.16, 24.24 and 24.25 can be utilized to design a CuK specification
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Fig. 24.9(a) is that of a basic Buck converter. From the voltage source C1, the converter charges the current sink constituted by the inductordiode (LD). The current is further converted into voltage without a switching stage (amplification) at C2. The canonical switching cell is approached if the capacitors C1 and C2 are combined to be represented by a single capacitor C. The cell includes TCLD, the basic building block of DCDC converters. The Boost converter is realized if the positions of D and T are interchanged in Fig.24.9 (a). Now power flows in from the right. Here, the energy stored in the inductor during each ON period of switch T is transferred to the Capacitor during its OFF period. The CUK converter as the dual of the BuckBoost converter has current input and current output stages. The basic SEPIC is a modification of the basic Boost and the CuK topologies. Consider the Boost converter in Fig 24.9(b). At steady state, the average voltage across the input inductor is zero. Equating the inductor voltages for the period when the switch T is ON with that when it is OFF, Vin .TON = ( Vout Vin ) .TOFF (24.26) or, Vout = ( 1 ).Vin 1 where, is the duty ratio of the switch.
Fig. 24.10 Modified Boost with load across Diode for BoostBuck Operation. (left) without output filter, (right) with filter.
In the path, VinLDVout, in Fig. 24.9(b), the average voltages across all the elements are known. Thus, that appearing across the diode D is Vout Vin. This voltage from Eqn 1 is: Version 2 EE IIT, Kharagpur 12
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A BoostBuck converter is thus realized. This is the voltage that would appear in an unfiltered form at the load in Fig. 24.10 (left). Now, since the source is a current source, the output stage must be capacitive (voltage sink) which is taken care of by C2D. The voltage across D has high ripples, which can be filtered much like the Buck converter with an L (and a C3). The CUK converter is thus realized. It is a IVI converter. A glaring drawback of this derived converter topology is that the polarity of the output is reversed. This is not acceptable for various reasons. Now it is the turn of the Diode to be interchanged with the filter inductor. The inductor is thus converted to be part of the switching circuit and it not just a filter. The SEPIC results not an entirely different one  but easily derivable from the previous topologies. The SEPIC officially stands for SingleEnded Primary Inductance Converter. However, the unofficial interpretation is more descriptive: Secondary Polarity Inverted Cuk.
Again, the basic inputoutput relation can be derived by considering the two inductors to have average null voltage across themselves. If the link capacitor has a voltage Vc across itself (consider it to be reasonably constant), then for the input inductor, the voltsecs during the ON and OFF periods of the switch are: Vin .TON = (VC Vout Vin )TOFF (24.27) or , VC = Vout Vin (. 1 ) TOFF For the output inductor, VC .TON = V out .TOFF (24.28) Eliminating, Vc and writing TON = . T,
Vout = (
)Vin
(24.29)
Thus the SEPIC is also basically a BOOSTBUCK converter akin to the CUK converter. (The Boost stage comes first followed by the Buck stage and it is also IVI converter) In the practical SEPIC converter, the two inductors are coupled with the polarities as indicated by dots in Fig. 24.11(a). The turns ratio is and the coupling is very tight. For such a coupledtransformer SEPIC, equating the positive and negative voltsecs for the two inductors, (Vin .K .VC ).TON = (Vout + VC Vin K .Vout ).TOFF (24.30) for the input inductor, and Version 2 EE IIT, Kharagpur 13
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(24.31)
Equations (24.28) and (24.29) can be obtained from the above two by substituting both K and K to zero to have no coupling between the two coils.
The above two equations result in an identity to indicate that such a system cannot work. This can be explained by examining the operation of the circuit. Initially when the transistor is OFF, the capacitor C2 charges to the supply voltage Vin. When the transistor is switched ON, the resulting active circuit is shown in Fig 24.12.
Fig. 24.12: Active part of the circuit when transistor is switched with C2 charged toVin
The circuits to the left and right of the transistor are identical and both the windings are induced with the supply voltages, resulting in null emfs on either side, which explains why the ideal circuit will not work. However, neither the coupling between the inductors nor the effective turns ratio can be unity. This results in a circuit with the features of the uncoupled circuit and the circuit performs. The second voltage source, VC, induces N.VC into the primary, where N is the turns ratio. For the interesting case, Vin = VC = V1, if the turns ratio, n, is increased slightly from unity, by 1/k (where k < 1 is the coupling coefficient between windings), then the voltage induced by Vin will increase the voltage at the Drain of the transistor to N. V1, thereby "bootstrapping" the leakage inductance of the input inductor. Because the voltage at each end of this leakage inductance is the same, its inductance is effectively infinite. Consequently, all variations in magnetizing current, (through M) due to a varying V1 is supplied from the secondary winding source. By symmetry, setting n = k causes the secondarywinding current to become constant while the primary source supplies the magnetizingcurrent variations. This effect can be desirable because, for n = 1/k, it results in constant (DC) primary current. Noisy switching current does not appear at the converter input but is diverted instead to the secondary winding. However, typical values of k are slightly less than one, and turns ratios of nearly 1:1 may not be easy to wind. One simplification is to use a 1:1 transformer, such as a lowcost, commodity, commonmode powerline inputfilter choke, and add a small additional inductance in series with the primary winding. This effectively increases the leakage inductance so that the same secondarywinding dominance of magnetizing current is obtained with n = 1. Version 2 EE IIT, Kharagpur 14
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The circuit is an alternative to the Boost converter and outputs an range which includes the input range also being a BoostBuck converter. It is superior to the other converters both in terms of the input current purity and efficiency.
The waveforms in Fig. 24.13 show the voltage at the transistor Drain present on the fly back (Boost) and SEPIC circuits. The fly back transformer leakage inductance produces a voltage spike that adds an additional level to the "flattop" voltage. This level is about 1.5 times the supply voltage for inputs around 20 V. In comparison, the SEPIC FET switching waveform is clamped, and shows very little overshoot, or ringing. This clamping results in less switchingloss, output voltage noise and a power stage that can be operated at a much higher frequency than that of the fly back. Again, the fly back transformer leakage inductance also produces a significant voltage spike relative to the SEPIC at the output diode. A relatively high voltage (~200V) output diode is required for the fly back to handle the large negative ringing compared to the SEPICs 60V Schottky diode. The 0.5 volt forward drop of the SEPICs Schottky diode relative to the one volt forward drop of the flyback's ultrafast diode, results in significant power savings for the SEPIC.
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Module 3
DC to DC Converters
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Lesson 25
Design of Transformer for Switched Mode Power Supply (SMPS) Circuits
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After completion of this lesson the reader will be able to: (i) Explain the underlying principles behind the design of a high frequency transformer and inductor. (ii) Do a preliminary design of a high frequency transformer for some popular configurations of SMPS circuits. (iii) Do a preliminary design of a high frequency inductor. (iv) Estimate the size of an SMPS transformer of some given VA rating. Transformers are required for galvanic isolation between input and output voltages and for voltage and current scaling. It also helps in optimizing the device voltage and current ratings. The switches, diodes and other circuit elements on the high voltage side of the transformer are subjected to higher voltages but only lower currents. Similarly the devices put on the low voltage side are subjected to less voltage stress but higher current stress. The dctodc buck converter shown in Fig. 25.1, which is used to get a low voltage output from a high input dc voltage illustrates this point clearly. The circuit in Fig. 25.1(a) uses a step down transformer with proper turns ratio and has the advantages discussed above. On the other hand the switch and diode and the filter inductor in Fig. 25.1(b) need to withstand both input side voltage and output side current. Also, the switch in case (b) will be constrained to operate in a narrow range, which may cause lesser accuracy in output voltage control. NP: NS D1 Edc D2 L C Load
+ _
S L Edc D C
L O A D
(a)
(b)
Fig. 25.1: DC to DC buck converters: (a) Isolated type (b) Nonisolated type Transformers used in switched mode power supply circuits are significantly different from the power transformers that are used in utility ac supply system. Following are the important differences: (i) The input and output voltages and currents of a SMPS transformer are mostly nonsinusoidal, whereas the transformers connected to utility ac supply are almost always subjected to sinusoidal voltages and currents. The currents and voltages of SMPS transformer are of very high frequency where as utility type transformers are subjected to low frequency supply voltages. SMPS transformers generally handle much smaller power than the utility transformer.
(ii) (iii)
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SMPS transformercore, because of high frequency operation, is generally made of hard magnetic material like ferrites whereas the low frequency power transformers mostly use soft magnetic material like silicon steel. Ferrites have very high ohmic resistance and the area enclosed under the hysteresis loop of their BH magnetization curve is significantly lower than that of silicon steel. As a result, even at very high frequency operation, the hysteresis and eddy current losses are low. [Low hysteresis loss is due to less BH loop area and low eddy current loss is due to very high resistivity of the core material.] The ferrites have low magnetic permeability (typical value of relative permeability is around 100) and low saturating value of flux density (typical value is around 0.4 Tesla) that are considerably less than that of silicon steel. Ferrites are also brittle and fragile. The efforts are on to search for alternatives to ferrites that may have higher permeability, may handle higher flux density and may be more rugged. The fundamental principles concerning emf generation etc. in SMPStransformers and power transformers are identical and hence, in this lesson, many concepts of conventional transformer design have been borrowed.
The peak flux through the core is the product of peak flux density (Bm) and the core area (Ac), i.e., m = Bm Ac  (25.2) The windings are placed around the core and are accommodated in the window of the transformer. The transformer window area (Aw) is related with the windings current rating and the number of turns. For a singlephase transformer the relation between them is given by: Aw kw = 2 N I  (25.3)
,where kw is the window utilization factor and is the current density through the crosssectional area of the transformer windings. Window utilization factor, roughly varies between 0.35 to 0.6 and is dependent on the insulation requirements of the windings. A typical figure for the current density through copper conductors of naturally cooled transformers is 3X106 amps per square meter. If the current density through primary and secondary windings is taken identical, they occupy equal windowspace of the transformer. Some times the current densities through the two windings may differ depending on their physical ability to dissipate heat. The VA rating of a single phase transformer (= N Et I) can now be found from the above equations as: VA rating = 2.22 f Bm kw Ac Aw (25.4)
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For the given operating frequency (f) the product Ac Aw, known as area product is roughly proportional to the VA rating of the transformer as other parameters have nearly fixed magnitudes.
(ii)
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(iii)
Determination of winding current rating and requirement of window area: Let Iom be the peak expected load current. The secondary winding of the transformer should be rated to supply this current. Most SMPS circuits, with low magnitude of output voltage, have a centertapped secondary winding followed by a midpoint rectifier circuit realized using two diodes (instead of bridge rectifier having four diodes). This results in only one diode voltage drop during rectification, unlike two diode drops for the bridge rectifier circuit. For SMPS with low output voltage, saving one diode drop can result in significant increase in the efficiency. For this same reason, the diodes used on the secondary side are Schottky diodes having low onstate voltage drop. Each half of the centertapped secondary winding requires NS turns as determined in (i) above and they carry the load (dc) current only in alternate half cycles. Thus the I rms current rating of each half equals om and the net copper crosssectional area 2 2NS Iom required for the secondary winding is , where is the current density (as described in relation to Eqn.25.3). If the secondary was not centertapped, the rectifier used would be bridge type and the copper area for the secondary would have N I been just S om . The primary side carries the reflected secondary current and the NS Iom required copper area for primary would equal . The total window area requirement for the transformer can now be given as: N I A w k w = S om 1 + 2  (25.6), where Aw is the window area and kw is the window utilization factor (as discussed in Sec.25.1). Expression for VA rating of the transformer: Combining Eqns. (25.5) and (25.6) one gets, N Vmax S Iom 1 + 2 = 4fBm k w A c A w (25.7) NP
(iv)
Using relations derived in (i) above, Eqn.25.7 may be rewritten as: Vo Iom K1K 2 1 + 2 = 4fBm k w A c A w (25.8)
V + VR Vmax , , a factor allowing for input voltage variation and K 2 = 0 Vo Vmin a factor coming due to voltage drop in rectifier diode, filter inductor etc. Vo Iom is the peak output power from the SMPS. The factor 1 + 2 on the L.H.S. of Eqn.27.8
where K1 =
will become 2.0 if the secondary winding is not centertapped. (v) Selection of transformer core and determination of number of turns in the windings:
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Knowing the area product Ac Aw, as given by Eqn.25.8, the appropriate transformer core is to be selected from the coremanufacturers catalog. Once the area product matches, the details of other dimensions of the transformer core are found from the catalog. Knowing window area (Aw) and core area (Ac), the number of turns in the windings can be decided using Eqns. Like (25.5) or (25.6).
Eqn.25.9 may be compared with Eqn.25.5 for a typical value of Dmax = 0.5 (which corresponds to the case when primary and tertiary windings have identical number of turns). Because of unipolar nature of flux the utilization of core (in terms of emf generation) is poorer here. The primary to secondary turns ratio (NP/ NS ) for the forward converter can be estimated as done previously for the Hbridge converter. Accordingly, NP/ NS = Vmin Dmax /(Vo + VR), where Vo is the required output voltage and VR denotes the voltage drop in output rectifier and filter circuit. The maximum rms current through the secondary winding can be equated to Iom D max and the window area (Aw) requirement is given by A w k w = From
Vmax
Eqn.25.9 and 25.10, the VA rating of the transformer NS 1.5 Iom ( D max ) = 0.5fBm k w A c A w , which may be rewritten as NP Vo Iom K1K 2 D max = 0.5fBm k w A c A w
(25.11)
Eqn.25.11 is similar to Eqn.25.8 above. The symbols used also denote the same. Knowing the window area, the transformer core selection and other designs are done as described above in connection with the Hbridge topology. The extra tertiary winding of a forward converter transformer carries only magnetization current, which is a quite small and even a thin gauge wire will serve the purpose. However, with the addition of tertiary winding the insulation requirement Version 2 EE IIT, Kharagpur 7
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of the transformer increases significantly and hence the window utilization factor (kw) becomes low. Voltage +V
DT
T/2 0
DT
3T/2 T V
time
Flux 0
+m  m
time
Fig. 25.2: Winding voltage and coreflux waveforms for a Hbridge type SMPS supply
Voltage +VF
DT
time T
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B2 . For finite magnitude of flux density B, the magnitude of should be small to have higher energy per unit volume. and magnetic reluctance have inverse relation, as decreases the reluctance increases. For a practical inductor the reluctance of its fluxpath should not be zero. For an inductor, working in the linear region of the cores magnetization, the following relation holds good between inductance (L), reluctance (R) and the number of turns (N) of the inductor: N2 L= . However a practical inductor still requires a good core with high permeability to R increase (i) coupling between the windings, (ii) to guide the flux path and hence decrease the stray magnetic field lines and (iii) to keep the inductor size small. However to keep the reluctance of the fluxpath at the desired value, an appropriate length of airgap is introduced in the flux path. Fig.25.4 shows a double E core with windings put around the central limb. After the windings are placed in position, a nonmagnetic material (like, paper) is inserted between the faces of the core and the two Es of the core are clamped together. The nonmagnetic material acts like airgap in the core. A preferred way of creating airgap may be to grind some length from only the central limb of the core. If lg is the length of airgap in the core, the inductance (L) can be expressed as: N 2 A c 0 L=  (25.12) lg density equals 0.5 where Ac is the area of the cores limb on which the windings have been placed and 0 is the permeability of airgap. In the above expression for inductance, the fringing effect of the flux and the reluctance of the flux path through magnetic core have been neglected. The core material should not saturate with the peak expected current (Ip) in the inductor. The peak flux density in the core (Bm) can be related with the peak magnitude of current as
LI p = NA c Bm  (25.13)
Knowing the current shape through the inductor, one calculates its rms magnitude (Ip,rms) and NI p,rms (25.14) determines the window area required as A w k w = Combining Eqns.25.13 and 25.14, one gets
LI p I p,rms = Bm k w A c A w  (25.15)
Eqn.25.15, gives the area product from which rest of the design can be proceeded as in the case of transformer design shown above. LHS of Eqn.25.15 is indicative of the energy holding capacity of the inductor (some what like VA rating of the transformer discussed above). Should there be a couple winding (an inductortransformer) the area product expression needs to be modified to include the window space requirement of the secondary winding as well.
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H A L F P R I
F U L L
S E C
H A L F P R I
H A L F P R I
F U L L
S E C
H A L F P R I
Fig. 25.4: A typical SMPS transformer with a double E type ferrite core and interleaved primary and secondary winding
Quiz Problems
(1) For a high frequency transformer the relation between the transformer size and frequency of voltage waveform can be given as: (a) (b) (c) (d) Size increases with frequency Size decreases with frequency Core size reduces but copper weight increases with increase in frequency Size is independent of frequency
(2) The assembly of flyback and forward type transformer cores may differ in the following sense: (a) (b) (c) (d) Airgap is inserted in flyback type but it is undesirable for forward type. Airgap in the flux path is undesirable for both types Only forward type must have a suitably length of airgap Little airgap is deliberately put for both transformers
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(3) Transformers of forward type and Hbridge type SMPS circuits of identical VA rating and frequency differ in the following sense: (a) (b) (c) (d) The forward type transformer will be bigger The Hbridge circuit will require bigger transformer They will be of identical size Only the window area of Hbridge transformer will be bigger
(4) The size of SMPS transformers operating over large input voltage range will compare with similar rated transformer operating over a narrower input voltage range in the following manner: (a) Larger input voltage range will require larger transformer (b) Larger voltage range requires smaller transformer (c) Size remains independent of voltage range
(Answers: 1b, 2a, 3a, 4a)
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Module 4
AC to AC Voltage Converters
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Lesson 26
AC to AC Voltage Converters
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This lesson provides the reader the following: (i) (ii) (iii) (iv) (v) ACAC power conversion topologies at fixed frequency Power converter options available for the conversion Ability to formulate equations describing the current waveform for the PAC Ability sketch the current waveform by observation of the circuit Ability to assess the performance of the converter of the topologies
26.1 Introduction
AC to AC voltage converters operates on the AC mains essentially to regulate the output voltage. Portions of the supply sinusoid appear at the load while the semiconductor switches block the remaining portions. Several topologies have emerged along with voltage regulation methods, most of which are linked to the development of the semiconductor devices.
Fig 26.1 Some single phase ACAC voltage regulator topologies. (a) Backtoback SCR; (b) One SCR in (a) replaced by a fourdiode full wave diode bridge; (c) A bidirectionally conducting TRIAC; (d) The SCR in (b) replaced by a transistor. The regulators in Fig 26.1 (a), (b) and (c) perform quite similarly. They are called Phase Angle Controlled (PAC) ACAC converters or ACAC choppers. The TRIAC based converter may be considered as the basic topology. Being bidirectionally conducting devices, they act on both polarities of the applied voltage. However, dv dt re applied their ratings being poor, they tend to turnon in the opposite direction just subsequent to their turnoff with an inductive load. The 'Alternistor' was developed with improved features but was not popular. The TRIAC is common only at the low power ranges. The (a) and (b) options are improvements on (c) mostly regarding current handling and turnoffable current rating. A transistorised ACAC regulator is a PWM regulator similar to the DCDC converters. It also requires a freewheeling path across the inductive load, which has also got to be bidirectional. Consequently, only controlled freewheeling devices can be used.
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Fig. 26.2 Operation of a Phase Angle Controlled ACAC converter with a resistive load
The rms voltage Vrms decides the power supplied to the load. It can be computed as Vrms =
2V
sin 2 t dt
= V 1
sin 2 + 2
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Fig. 26.3 The rms output voltage and the most important harmonics versus triggering angle .
As is evident from the current waveforms, the PAC introduces significant harmonics both into the load and the supply. This is one of the main reasons why such controllers are today not acceptable. The ideal waveform as shown in Fig 26.2 is half wave symmetric. However it is to be achieved by the trigger circuits. The controller in Fig. 26.4 ensures this for the TRIAC based circuit. While the TRIAC has a differing characteristic for the two polarities of biasing with the 32V DIAC  a two terminal device triggering is effected when the capacitor voltage reaches 32 V. This ensures elimination of DC and even components in the output voltage.
Fig. 26.4 DIAC based trigger circuit for a TRIAC to ensure symmetrical triggering in the two halves of the supply.
For the SCR based controllers, identical comparators for the two halves of the AC supply, which generates pulses for the two SCRs ensures DC and even harmonic free operation. The PAC operates with a resistive load for all values of ranging from 0o The fundamental current, if can be represented as
if =
2V sin 2 ( + R 2 2
) sin t (
1 cos 2 2 2
) cos t
26.1
In machine drives it is only the fundamental component, which is useful. However, in resistance heating type of application all harmonics are of no consequence. The corrupted supply current nevertheless is undesirable. Version 2 EE IIT, Kharagpur
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power
factor = =
26.2 26.3
VI L1 cos 1 VI L
2V 2 sin 2 t R
dwt
26.4 26.5
The portion within square brackets in Eq. 26.5 is identical to the first part of the expression within brackets in Eq. 26.1, which is called the Fourier coefficient 'B1'. The rms load voltage can also be similarly obtained by integrating between and and the result can be combined with Eq. 26.5 to give power factor = per unit rms load current
B
per unit
1
load
power
= B
p.u..
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Fig 26.7 Load current for a single phase ACAC converter with a R_L load. Vs supply voltage, iss steady state current component , itr  transient current component and iload  load current (= iss + itr).
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With an inductance in the load the distinguishing feature of the load current is that it must always start from zero. However, if the switch could have permanently kept the load connected to the supply the current would have become a sinusoidal one phase shifted from the voltage by the phase angle of the load, . This current restricted to the half periods of conduction is called the 'steadystate component' of load current iss. The 'transient component' of load current itr, again in each half cycle, must add up to zero with this iss to start from zero. This condition sets the initial value of the transient component to that of the steady state at the instant that the SCR/TRIAC is triggered. Fig. 26.6 illustrates these relations. When a device is in conduction, the load current is governed by the equation L di
i load = 2V Z
dt
+ Ri =v s
R t L
sin ( t ) + sin ( )e
Since at t = 0, iload = 0 and supply voltage vs = 2Vsint the solution is of the form The instant when the load current extinguishes is called the extinction angle . It can be inferred that there would be no transients in the load current if the devices are triggered at the power factor angle of the load. The load current I that case is perfectly sinusoidal.
Fig. 26.8 A complete Transitorised ACAC chopper topology of the version shown in Fig. 26.1 and the corresponding load voltage and current waveforms for an inductive load. The output voltage is shown to be about 50% for a 0.5 Duty Ratio chopping.
The ACAC converter shown in Fig 26.1 has to be augmented with two additional controlled devices clamping the load as indicated in Fig. 26.7. A large capacitor across the supply terminals is also to be inserted. These devices which are mostly transistors of the same variety as used for the chopper are necessary to clamp the voltages generated by the switchingoff of the current carrying inductors in the load while the input capacitor takes care of the line inductances. The harmonics in the line current and load voltage waveforms are significantly different from those with the PACs. Mostly switching frequency harmonics are present in both the waveforms.
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Fig. 26.9 Load voltage and current control with a twostage sequence control
Q2 For the load described in Q1, the PAC is triggered by a single pulse at = 60 . Sketch the load current waveform.
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A2
Since < L, the load current should have been continuous. However, the current in the SCR first triggered extinguishes at a the total load current, iL = iss + itr = 0. For this load which can be considered to be highly inductive 360, say 360. Thus the first SCR conducts till that angle. The antiparallel SCR is triggered at = 60 corresponding to a 180 + 60 = 240 when it is still reverse biased. It fails to conduct. The load thus sees only a unipolar current. The load current and voltage waveforms are illustrated in Fig 26. A2. Note that both the load voltage and current waveforms contain DC components.
Fig. 26. A2 The load current waveform and its steadystate and transient components when a highly inductive load is switched using single narrow trigger pulses.
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Module 4
AC to AC Voltage Converters
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Lesson 27
Threephase AC Regulators
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Instructional Objectives
Study of the following: The circuits used for the threephase ac regulators (ac to ac voltage converters)
The operation of the above circuits with threephase balanced resistive (R) load, along with the waveforms The important points of comparison of the performance with different types of circuits
Introduction
In the last lesson first one in the first half of this module, various circuits of the singlephase ac regulators, also termed as ac to ac voltage converters, are described. In the basic circuit, one Triac, or two thyristors, connected back to back, are used. The operation of the above circuits
with different types of loads resistive (R) and inductive (RL), along with the waveforms, is then discussed. Lastly, the output voltage waveform is analysed.
In this lesson the second one in the first half, firstly, the circuits of the threephase ac regulators, also termed as ac to ac voltage converters, are described. The operation of the above
circuits with threephase balanced resistive (R) load, along with the waveforms, is then discussed. The two basic circuits are threephase threewire type with load connected in star and threephase deltaconnected one. Lastly, the important points of comparison of the performance with different types of circuits, including the above two, are presented.
Keywords: Threephase ac regulator circuits, AC to AC voltage converter, balanced threephase star and deltaconnected loads
Threephase AC Regulators
There are many types of circuits used for the threephase ac regulators (ac to ac voltage converters), unlike singlephase ones. The threephase loads (balanced) are connected in star or delta. Two thyristors connected back to back, or a triac, is used for each phase in most of the circuits as described. Two circuits are first taken up, both with balanced resistive (R) load
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direction in the negative half. So, two thyristors connected back to back are needed in each phase. The turning off of a thyristor occurs, if its current falls to zero. To turn the thyristor on, the anode voltage must be higher that the cathode voltage, and also, a triggering signal must be applied at its gate. A + EAN ECN IL + EL + B EBN T6 T3 ib b + T4 T1 ia + Ean R Ebn T2 T5 ic Ecn + R n R c a
+ C
Fig. 27.1 Threephase, threewire ac regulator The procedure for obtaining the expression of the rms value of the output voltage per phase for balanced starconnected resistive load, which depends on range of firing angle, as shown later, is described. If E s is the rms value of the input voltage per phase, and assuming the voltage, E AN as the reference, the instantaneous input voltages per phase are,
e AN = 2 E s sin t , e BN = 2 E s sin ( t 120) and eCN = 2 E s sin ( t + 120) Then, the instantaneous input line voltages are, e AB = 6 E s sin ( t + 30) , e BC = 6 E s sin ( t 90) and eCA = 6 E s sin ( t + 150)
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E 0
EAB /6
EBC
ECA
EAB
EBC
E t 0
EAB
EBC
ECA
EAB
E 0
EAN
EBN
ECN 2
EAN 3 t
E 0
EAN
EBN
ECN 2 t
I g1
0
I g3
I g1
t t t
0
I g5
0 I g3 0
I g5 I g2
t t t t t
5 5 6 611 2 23 34 45 6 6 1 122 3 34 45 56
0
I g2
0 0
0
I g4
t
I g4
0
I g6
t
5 6 6 1 1 2 2 3 3 4 4 5 5 6 6 1
0
I g6
0 4
5
0 Ean 0
E EAB Ean 0
EBC
ECA
EAB
EBC
10.5 EAB
0.5 EAC 0.5 EAB (b) For = 120 Fig. 27.2 Waveforms for threephase threewire ac regulator
t 0.5 EAC
The waveforms of the input voltages, the conduction angles of thyristors and the output voltage of one phase, for firing delay angles ( ) of (a) 60 and (b) 120 are shown in Fig. 27.2. For 0 60 ( / 6) , immediately before triggering of thyristor 1, two thyristors (5 & 6) conduct. Once thyristor 1 is triggered, three thyristors (1, 5 & 6) conduct. As stated earlier, a thyristor turns off, when the current through it goes to zero. The conditions alternate between two and three conducting thyristors. Version 2 EE IIT, Kharagpur 5 www.jntuworld.com
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At any time only two thyristors conduct for 60 90 .Although two thyristors conduct at any time for 90 150 , there are periods, when no thyristors are on. For 150 , there is no period for which two thyristors are on, and the output voltage becomes zero at = 150 (5 / 6) . The range of delay angle is 0 150 . The expressions of the rms value of the output voltage per phase for balanced starconnected resistive load are as follows. Please note that = t . For 0 60 :
1 E0 = 2
2
(e
0
AN
) 2 d
2
1 2
2 = 6 Es 2
1 = 6 Es For 60
/3
sin d + 3
/ 2 +
1 2
/2
sin sin d + d + 4 3 / 3+
2 2
2 / 3
/ 2 + /2
2 sin sin d + d 4 3 2 / 3+ 2
sin 2 + 8 6 4 90 :
5 / 6 / 3 + 2
2 E0 = 6 Es 2
sin d + 4 + / 2 / 3
5 / 6 / 3 +
/ 2 / 3 +
1
2 sin d 4 2
1 = 6 Es For 90
3 sin (2 + 30 2 + 12 8
1 2
2 E0 = 6 Es 2 1 = 6 Es
sin sin d + d 4 / 2 / 3 + / 2 / 3+ 4
2 1
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A +
IL +
ia iab R
T5
R ica c
Fig. 27.3 Delta connected threephase ac regulator Assuming the line voltage E AB as the reference, the instantaneous input line voltages are,
e AB = 2 E s sin t ,
It may be noted that E s is the rms value of the line voltage in this case. The waveforms of the input line voltages, phase and line currents, and the thyristor gating signals, for = 120 are shown in Fig. 27.4.
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E Em 0
I g1
EAB
EBC
ECA
EAB
EBC
0
I g2
t t t t t t t t t
0
I g3 I g4
0 0
I g5
0
I g6 0 iab
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1 2 2 n
B T6
T3
ZL, RL
C T2
T5
ZL, RL
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N A T4 T1 ZL, RL
B T6
T3
ZL, RL
C T2
T5
ZL, RL
T1
T3
T5
Fig. 27.5(c) Control in delta 1. In two circuits (Fig. 27.3 & 27.5b), the individual phase controllers control their own loads independently of the other. As stated earlier, they can, therefore be studied as three singlephase controllers. 2. In other circuits, the individual phase controllers affect the other phase loads also, and they have to be studied as complete threephase circuits, as stated earlier in one case (Fig. 27.1). 3. The peak voltages occur across thyristors at or near the fully off state. In case of two circuits (Fig. 27.3 & 27.5c), the maximum thyristor voltage is the peak of the line voltage, whereas in the circuit (Fig. 27.5b), it is the peak of the phase voltage; in two circuits (Fig. 27.1 & 27.5a), the maximum thyristor voltage will be somewhere between the peak of the phase and line voltages depending on the leakage currents of the thyristors, the method of firing and the presence of voltagesharing resistors across the thyristors. 4. All the five circuits can be used under phase control. Version 2 EE IIT, Kharagpur 10 www.jntuworld.com
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5. The range of phase angle required to achieve full output range from zero to maximum varies between the circuits, and are given in Table 27.1. 6. The maximum current in the thyristors is decided from the fully on condition, and the size of the thyristors to be used should be chosen from this condition. The peak, mean and rms values of the thyristor currents (Table 27.1) are related to the rms value of the input (ac) current, which should be found by applying the full supply voltage to the load circuit. The load impedance per phase is equal in magnitude (Z) and angle ( ), which is taken as positive, as it is mostly inductive (RL). 7. The difference between the two circuits (Fig. 27.1 & 27.5b) is that in the second one, the neutral point is available, making it a 4wire one. 8. The difference between the two circuits (Fig. 27.1 & 27.5a) is that in the second one, the threephase balanced loads are connected in delta, which can be converted into its equivalent star, making it identical to the first circuit (Fig. 27.1). Also, the current in the thyristors in the second case (Fig. 27.5a) are the line currents, which are higher than the phase currents, which are flowing in the thyristors in the first one. 9. The difference between the two circuits (Fig. 27.1 & 27.5c) is that, in the second one, the thyristors connected back to back, are in delta, with the load connected in the three lines. Also, the current in the thyristors in the second case (Fig. 27.c) are the phase currents, which are lower than the line currents, which are flowing in the thyristors in the first one. Table 27.1 summarises the current and voltage rating parameters associated with all these circuits used as threephase ac controllers. E ac and I ac are the rms values of the line voltage and line current respectively. It may be mentioned that other types of circuits for threephase ac regulator can be used, but either the circuits are not bidirectional, i.e. unidirectional, or if they are bidirectional, in one half, only diode connected back to back per phase, instead of thyristor, is used. In the second case, only in one half with the thyristor per phase, controlled output voltage as shown earlier is obtained, but in the other one, uncontrolled output voltage, same as input one, is obtained. In the first case, where only one thyristor per phase is used, in one half, controlled output voltage is obtained, but in the second half, output voltage is zero, as only one device, but not two devices, is used. The readers are requested to refer to text books. In this lesson the second one in the first half, firstly the study of two basic circuits one with star connection and the other with delta connection, for threephase ac regulator (ac to ac voltage converter) are taken up. The operation with threephase balanced resistive load, along with waveforms, is then described. Lastly, the important points of comparison of the performance with different types of circuits, including the above two, are presented. In the next, i.e. third and final lesson in the first half, the control circuit for ac regulators will be described in detail.
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27.1
2 3 I ac R
Peak I ac 1.414
0.816 1.414 1.414 0.816
Mean I ac 0.45
0.26 0.45 0.45 0.26
RMS I ac 0.707
0.408 0.707 0.707 0.408
3 E ac Z 3 E ac Z E ac
3Z E ac 3Z
2 I ac R
2 I ac R
2 3 I ac R
2 3 I ac R
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Module 4
AC to AC Voltage Converters
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Lesson 28
Phase Angle Control in Triacbased Singlephase AC Regulators
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Instructional Objectives
Study of the following: The circuit used for the phase angle control in triacbased singlephase ac regulators (ac to ac voltage converters)
The operation of the various blocks used in the circuit, along with the waveforms
The harmonic analysis of the output voltage of a singlephase ac regulator with resistive load
Introduction
In the last lesson second one in the first half of this module, various circuits of the threephase ac regulators, also termed as ac to ac voltage converters, are described. Two basic circuits starconnected and deltaconnected, are first taken up. The operation of the two circuits with threephase balanced resistive (R) load, along with the waveforms, is then discussed. Lastly, the important points of comparison of the performance with different types of circuits, including the above two, are presented. In this case, the load is balanced inductive (RL) one.
In this lesson the third and final one in the first half, firstly, the circuit used for the phase angle control in triacbased singlephase ac regulator, also termed as ac to ac voltage converter, is presented. Then, the operation of the various blocks used in the above circuit, along with the waveforms, is described. Finally, the harmonic analysis of the output voltage of a singlephase ac regulator with resistive load is, briefly discussed. Keywords: Phase angle controller circuit, Triacbased singlephase ac regulator, or ac to ac voltage converter, harmonic analysis of the output voltage waveform.
TRIAC
A Triac is equivalent to two thyristors connected back to back as shown in Fig. 26.1a. Thus, it is a bidirectional switching device, in contrast to the thyristor, which is a unidirectional device, having reverse blocking characteristic, preventing the flow of current from Cathode to Anode. So, when it (triac) is in conduction mode, current flows in both directions (forward and reverse). This switching device is called as TRIAC (TRIode AC switch), with the circuit symbol shown in Version 2 EE IIT, Kharagpur 3 www.jntuworld.com
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Fig. 28.1. The three terminals of the triac are designated as MT1 , MT2 and gate, G , shown in the same figure. These are similar to the terminals A (Anode), K (Cathode) and G (Gate), of the thyristor The terminal, MT1 is taken as the reference point for the measurement of the voltages and currents at other two terminals, G (gate) and MT2 . The gate (G) is near to the terminal, MT1 . The thyristor conducts with the current direction from Anode to Cathode (positive), when a positive pulse is fed at the Gate terminal with respect to Cathode, and at that time, with positive voltage applied between Anode and Cathode terminals, being connected in series with the load. The triac conducts in the positive direction from MT2 to MT1 , when a positive pulse is applied at the gate (G) terminal with respect to MT1 and at the same time, the positive voltage is applied between two terminals, MT2 (+) and MT1 (). Similarly, the triac conducts in negative direction from MT1 to MT2 , when a negative pulse is applied at the gate (G) terminal with respect to MT1 and at the same time, the positive voltage is applied between two terminals, MT1 (+) and MT2 (). Please note that the voltage between two terminals, MT2 and MT1 , is negative, in this case. So, the triac can conduct in both directions (positive and negative) as given here, whereas the thyristor conducts in one (positive) direction only. Only one triac is needed, whereas it is to be replaced by two thyristors, with consequent change in the control circuit. The VI characteristics of both thyristor and triac, have been discussed in lesson #4 (module 1). A thyristor turns off (nonconducting mode), if the current through it, falls below holding current. Similarly, a triac turns off (nonconducting mode), if the magnitude of the current, irrespective of its direction, falls below holding current. As a triac is connected in an ac circuit, and if the load in the circuit is resistive, the triac turns off at the zero crossing points of the voltage in each half (the supply (input) voltage reaches zero at the end of each half cycle). This will be nearly valid, if the load inductance is small, though the triac in that case turns off, as the current though it goes to zero, after the zero crossing point is reached in each half. The case of higher inductance in the load has been discussed in detail in lesson #26 (module 3). The triac is a low power device, used in voltage control circuits, used as light dimmers, speed control for fan motors (singlephase), etc. Some of the advantages and disadvantages of the triac visavis thyristor are given.
Advantages
1. Triacs are triggered by positive or negative polarity voltages applied at the gate terminal. 2. A triac needs a single heat sink of slightly larger size, whereas antiparallel thyristor pair needs two heat sinks of slightly smaller sizes, but due to the clearance total space required is more for thyristors.
Disadvantages
1. Triacs have low dv / dt rating as compared to thyristors. 2. Triacs are available in lower rating as compared to thyristors. 3. Since a triac can be triggered in either direction, a trigger circuit for triac needs careful consideration. 4. The reliability of triacs is lower than that of thyristors. Version 2 EE IIT, Kharagpur 4 www.jntuworld.com
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DIAC
A Diac is equivalent to two diodes connected back to back. Also, it is a bidirectional device, in contrast to the diode, which is a unidirectional device, having reverse blocking characteristic, preventing the flow of current from Cathode to Anode. So, when it (diac) is in conduction mode, current flows in both directions (forward and reverse). This switching device is called as DIAC (DIode AC switch), with the circuit symbol shown in Fig. 28.1. The two terminals of the diac are designated as T1 and T2 , shown in the same figure. These are similar to the terminals, A (Anode) and K (Cathode), of the diode. The diac conducts, when the breakover voltage is reached in either polarity across its two terminals. When T1 is positive with respect to T2 , and if at that time if the voltage, V12 exceeds VBO1 (breakover voltage), the diac conducts in positive direction from T1 to T2 . Similarly, when T2 is positive with respect to T1 , and if at that time if the voltage, V21 exceeds VBO 2 (breakover voltage), the diac conducts in negative direction from T2 to T1 . So, a diac can conduct in both directions (positive and negative), whereas a diode conducts only in positive direction from Anode (A) to Cathode (K), if, at that time, the voltage, V AK exceeds VBO (breakover voltage). A diode does not conduct in the negative direction, if the voltage, V AK is negative. A diode turns off (nonconducting mode), if the current through it, falls below holding current. Similarly, a diac turns off (nonconducting mode), if the magnitude of the current, irrespective of its direction, falls below holding current. If the VI characteristic of diode is known, as given in lesson #2 (module 1), the VI characteristic of diac, on the lines of the triac can be developed. The students are requested to study the characteristic of diac from a text book, as it is not included here for obvious reason. Now, the operation of the phase angle controller circuit (Fig. 28.1) is presented, with the waveforms at various points shown in Fig. 28.2. The power circuit, the main component of which is the triac, has been described earlier. The diac is symmetrical, unlike the triac, as described earlier. So, the diac (Fig. 28.1) can be connected in opposite direction, with T1 in place of T2 , and vice versa, i.e., T2 , T1 in place of T1 . But the operation here is described with the connection as in the figure. The triac is not symmetrical, though it conducts in both directions like diac. Two reasons are: the presence of third terminal, Gate (G), and the gate signal to be fed between G & MT1 (reference) for triggering. The snubber part ( Rs & C s ), shown in the figure, is used for the protection of the triac the power switching device. The remaining part, including the diac used for triggering of the triac, is the controller for the triac.
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RS TRIAC
CS
Snubber
MT2
1phase ac supply
Rpot. T1 vc
DIAC T2 C 
R1
B Fig. 28.1: Phase angle controller circuit for a singlephase ac regulator using TRIAC
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Vm vL 0 +1 1 /2 3/2 2
5/2 2+1 3
Vm (c) Vm
vL 0 +2 2 2 2+2 3
Vm (d) Fig. 28.2: Waveforms at various points of the controller circuit (a) Input (source) voltage, vAB (b) Voltage across capacitor, c(vc) (c) Output (load) voltage, vDB with Rput = R2 (lower) (d) Output (load) voltage, vDB with Rput = R3 (higher) As soon the input (supply) voltage is given to the circuit, the capacitor, C starts getting charged through the potentiometer resistance, R pot = R2 , the value of which is low and the load resistance. The polarity of the input voltage is important. The start of the input voltage is taken as the positive zerocrossing point (Fig. 28.2a), when the voltage changes from negative to positive. The point, A is now positive with respect to B (Fig. 28.1). The polarity of the voltage across the capacitor, C is that the left hand side is positive, with the right hand side as negative. The capacitor voltage ( vC ) is shown in Fig. 28.2b. As soon as the capacitor voltage, vC reaches the breakover voltage ( VBO ) of the diac (about 30 V), the diac starts to conduct in the positive direction from T1 to T2 . At this point, the triac gets a positive pulse at its gate (G is now positive with respect to MT1 ) and also MT2 is at a higher potential than MT1 . So, the triac is turned on at the angle, = 1 = t1 = 2 f t1 . The current through the triac is in the positive direction from MT2 to MT1 . Please note that the time constant of the charging circuit is related to the potentiometer resistance ( R2 ), which is low. So, the time needed for the capacitor voltage to reach the breakover voltage ( VBO ) is t1 1 . The triac is turned off at = , when the input Version 2 EE IIT, Kharagpur 7 www.jntuworld.com
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voltage reaches the negative zerocrossing point. So, the conduction period (angle in rad) is from 1 to in the positive half. The output (load) voltage ( v L = v DB ) waveform (Fig. 28.2c) is nearly same as the input voltage ( vi = v AB ), neglecting the voltage drop across the triac. The capacitor voltage (Fig. 28.2b) starts decreasing at t = t1 , and reaches zero after some time, the time being small. The discharge path is through diac, the resistance R1 , and the gate, G & MT1 terminals of the triac, the total resistance is quite low. So, the time constant during discharge is quite low, as compared to that during charging. The resistance, R1 is used to decrease the capacitor current during discharge. The pattern is repeated in the negative half of the input voltage, which is briefly described. The capacitor, C starts charging in the opposite direction through the same path as given earlier. The charging starts from the negative zerocrossing of the input voltage (Fig. 28.2a). The polarity of the input voltage is now opposite, with the point, B being positive with respect to A. The polarity of the capacitor voltage (Fig. 28.2b) is also opposite, with the right hand side as positive, and the left hand side as negative. The charging time constant remains same (low), as it was earlier. The capacitor voltage, vC (in magnitude) reaches the breakover voltage ( VBO ) of the diac after time t1 1 , measured from the negative zerocrossing of the input voltage ( = ). The diac now starts to conduct in the negative direction from T2 to T1 . At this point, the triac gets a negative pulse at its gate (G is now negative with respect to MT1 ) and also MT1 is at a higher potential than MT2 . So, the triac is turned on at the angle, ( = + 1 ). The current through the triac is in the negative direction from MT1 to MT2 . The triac is turned off at the next positive zerocrossing point ( = 2 ). The conduction period (Fig. 28.2c) is from ( + 1 ) to ( 2 ) in the negative half, the total conduction time ( 1 ) being same in both half. The output voltage waveform is identical, but it is opposite in this (negative) half. As in the earlier case, the capacitor voltage (Fig. 29.2b) starts decreasing, and reaches zero after some time, the discharge path remaining same. Thus, the diac helps in the turning on of the triac in both directions, making the control circuit simple with few components only (Fig. 28.1). Though the function of the diac could have been performed by using two diodes connected back to back, the control circuit would have to be modified. To change the conduction period, or the start of conduction of the triac, the potentiometer resistance is to be increased from R2 to R3 , which is higher. The capacitor voltage waveform for this case is shown in Fig. 28.2b as dotted line, as the time constant of the charging circuit also increases. So, the time needed for the capacitor voltage (in magnitude, as both halves are considered) to reach the breakover voltage ( VBO ) of the diac is now ( t 2 2 ). The conduction period in the positive half (Fig. 28.2d) is from 2 > 1 to , the total time in both half is ( 2 ). The conduction period decreases. The rms value of the output voltage also decreases. Other conditions, say during discharge of the capacitor voltage remaining same, is not described. The range of phase angle delay, in the ideal case, is 0 < < . But normally, the lower limit is higher than 0 , while the upper limit is lower than (180) . The input voltage (Fig. 28.2a) is zero at the two limits ( 0 & 180 ) in the ideal case. As the input voltage has to exceed at least the voltage drop in the triac, and the capacitor voltage (Fig. 28.2b) also has to reach the breakover voltage of the diac as given earlier, the normal range of phase angle delay is to be used, not the ideal ones. Also, if the load is inductive, the current in the triac has to exceed a threshold value, before the gate pulse can be withdrawn. Otherwise, the triac may not be Version 2 EE IIT, Kharagpur 8 www.jntuworld.com
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triggered, returning to off state again. This point may have been described in the case of phasecontrolled singlephase (bridge) converters (acdc), with inductive load in series with battery or back emf, in lessons #1011 (module 2).
and the other relationships are an = cn cos n and bn = cn sin n . The rms value of nth harmonic component = cn / 2
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Vm vo + 2 (t)
Vm Fig. 28.3: Input and output voltage waveforms of a singlephase ac regulator with resistive load. The output (load) voltage waveform (Fig. 28.3) consists of two parts, the first one is positive in the positive half cycle, while the second part is negative in the next (negative) half cycle. The waveform has halfwave asymmetry, with only odd ( n = 2 m + 1 ) harmonics being present. The even ( n = 2 m ) harmonics are not present in this case, as the second part is cancelled by the first part. Also to be noted that the average value is zero. This can also be computed by the formulas for the harmonic analysis of the output (load) voltage waveform of the buck converter (dcdc) circuit, given in lesson #18 in module 3. It can be observed for the singlephase ac regulator circuit shown in lesson #26 in this module (#4) that the switching device (triac or two thyristors connected back to back) is turned on at the delay angle, = , and then turns off at = , when the input voltage and also the output current goes to zero, in the first (positive) half, as the load is resistive (R). This is repeated in the second (negative) half. The output (load) voltage waveform for one cycle is, v0 = 0 for < < 0 ; v0 = Vm sin = 2 V sin for < < ;
v0 = 0 for ( + ) < < ; v0 = Vm sin = 2 V sin for (2 ) < < ( + ) In terms of the Fourier components, the expression is,
v0 =
n =1, 3, 5, 7 ,
n n =1, 3, 5, 7 ,
sin (n + n )
where, 2 2 an = v0 sin ( n ) d ; bn = v0 cos ( n ) d 0 0 Please note that two formulas given here, differ from two formulas given in lesson #18 (module 3). The expressions for the components of the fundamental and third harmonic, of the output voltage are derived. The students are requested to derive, say the expressions for the other, say fifth harmonic components. 2V 2 2 a1 = v0 ( ) sin d = 2 V (sin ) 2 d = (1 cos 2 ) d 0
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2V 2V 2V 1 ( 1 ( ) = sin 2 ) = ( ) + sin 2 = 2 2 (( ) + 0.5 sin 2 ) 2V = (( ) + sin cos ) 2V 2 2 b1 = v0 ( ) cos d = 2 V sin cos d = sin 2 d 0 2V V V 2 = 2 (cos 2 ) = 2 (1 cos 2 ) = (sin ) 2V 2 2 a3 = v0 ( ) sin 3 d = 2 V sin sin 3 d = (cos 2 cos 4 ) d 0 2V 1 2V 1 = ( 2 sin 2 4 sin 4 ) = 4 (sin 4 2 sin 2 ) 2V 2 2 b3 = v0 ( ) cos 3 d = 2 V sin cos 3 d = (sin 4 sin 2 ) d 0 2V 1 2V 1 = ( 4 cos 4 2 cos 2 ) = 4 (cos 4 2 cos 2 + 1) Using two sets of two expressions given earlier, the rms value ( cn / 2 ) and phase angle
( n ), of the harmonic components of the output (load) voltage, are obtained. As there is no inductance in the load circuit, the rms values of the harmonic components of the output current are proportional to those (the rms values of the harmonic components) of the output voltage. It may be stated that the rms values of the harmonic components of both output voltage and current decrease, though not in inverse proportion to ( n ) as given in lesson #18 (module 3), as the order of harmonic ( n ) increases. The expression for the rms value of the output voltage, as a function of phase angle delay , is given in lesson #26 of this module (4), and not repeated here. The relation between the rms value, V0r and the rms values of all odd harmonic components is,
V0 r =
n n =1, 3, 5, 7 ,
(c
/ 2)2
It may be noted that this expression is different from that given in the section on the harmonic analysis of the output voltage waveform of a buck converter (dcdc) in lesson #18 (module 3). This is, because the average value, V0 is zero, and the rms values of all even harmonic components are also zero, with only odd harmonic components being present, as this waveform has halfwave asymmetry (given earlier). The rms values of all odd harmonic components, including that of fundamental one, can, first, be computed as per the formula given earlier. It may be noted that, the rms values of only a few odd harmonic components need be computed, because the rms values decrease, as the order of harmonic increases, as given earlier. Then, using the expression for the rms value, it (rms value) can be computed. Finally, it can be checked from the expression for the rms value (given in lesson #26).
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The rms value of the fundamental ( n = 1 ) component of the output voltage, ( c1 / 2 ) is maximum (highest) for 0 with > 0 , in normal case, though it reaches maximum at = 0 (ideal case). Also the rms value of the output voltage, V0r is maximum (nearly same as the rms value of input voltage) for 0 , and is slightly higher than the rms value of its fundamental component. If the expression under the square root for the rms value is divided into two parts the rms value of fundamental component and the rms values of other odd harmonic components, starting from third one, the new form is,
V0 r = (c1 / 2 ) 2 +
n = 3, 5, 7 ,
(c
/ 2)2
(c
/ 2 ) 2 = (V0 r ) 2 (c1 / 2 ) 2
From this expression, and also from the expressions given earlier, it can be observed that the rms values of all odd harmonic components, except fundamental one, starting from third, are very low. The rms value of the fundamental component of the output voltage, ( c1 / 2 ) is minimum (lowest) for (180) with < , in normal case, though it is minimum (zero) at = (ideal case). Also the rms value of the output voltage, V0r is minimum (not zero, but nearly zero) for , and is slightly higher than the rms value of its fundamental component. From the expression, using the rms value, and the rms value of fundamental component only, and other expressions given earlier, it can be observed that the rms values of all odd harmonic components, which also includes fundamental one in this case, are very low. This type of harmonic analysis can be performed for the output voltage of controlled (half/full) single/threephase converters (acdc) with resistive load, as discussed in lessons #1011 & 1314 in module 2. In the case of threephase ones, the resistive load is balanced one. Taking the case of a singlephase controlled bridge converter with resistive load, the output voltage waveform obtained is of the same type, except that it is a dc one, with the second half of the periodic waveform being also positive, unlike the case shown in Fig. 28.1. The voltage waveform in that case, has halfwave symmetry (having dc and only even ( n = 2 m ) harmonic components, but no odd harmonic components), unlike the case here, of the voltage waveform having halfwave asymmetry (with only odd ( n = 2 m + 1 ) harmonic components, but no even harmonic and also dc components, as given earlier). In this lesson the third and final one in the first half of this module, the circuit used for the phase angle control in triacbased singlephase ac regulator or ac to ac voltage converter is, first, presented. Then, the operation of the various blocks used in the above circuit, along with the waveforms, is described. Finally, the harmonic analysis of the output voltage of a singlephase ac regulator with resistive load is, briefly discussed. Starting with the next (fourth) lesson first one in the second half, the various types of cycloconverters, used as ac to ac voltage converters, are presented. The power circuit using mostly thyristors, the output voltage waveforms for both singlephase and threephase ones, and the various blocks of control circuit required (in brief), are mostly described in detail.
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Module 4
AC to AC Voltage Converters
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Lesson 29
Introduction to Cycloconverters
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Instructional Objectives
Study of the following: The cycloconverter circuits basic principle of operation The circuit for the singlephase to singlephase cycloconverter using thyristors The operation of the above cycloconverter circuit, along with the voltage waveforms
Introduction
Earlier in the last three (4.14.3) lessons (first half) of this module, the circuit and operation of ac to ac voltage controllers both singlephase and threephase, were described in detail. The devices used are either triac, or thyristors connected back to back. In this lesson (4.4) first one in the second half of this module, the cycloconverter is introduced as a type of power controller, where an alternating voltage at supply frequency is converted directly to an alternating voltage at load frequency (normally lower), without any intermediate dc stage. As will be shown in the last (fifth) module, an alternating voltage at any frequency (output) is obtained using an inverter as a power controller from a dc voltage fed at its input. This input, i.e. dc voltage, is again obtained using a rectifier (converter) with ac voltage (normally at supply frequency) fed at its input. This type has been described in module 2. Note that this is a twostage process with an intermediate dc stage. Nowadays, the power switching devices used in the inverter circuit belong to transistor family (termed as selfcommutated ones), starting with power transistors, whereas thyristors are still being used in the converter (rectifier) circuits. These devices are called forcecommutated ones, when used in dc chopper circuits (described in module 3), but in this case, i.e. converter circuits, line commutation takes place. As stated earlier, the output frequency of the cycloconverter is limited to about onethird of supply (line) frequency of 50 Hz. Initially, the basic principle of operation used in a cycloconverter is discussed. Then, the circuit of a singlephase to singlephase cycloconverter using thyristors is presented. This is followed by describing the operation of the above cycloconverter circuit, along with voltage waveforms. The readers at this stage, have gone through the following lessons singlephase fully controlled converter using thyristors, for obtaining dc output voltage from ac supply (#2.2), and ac to ac voltage controllers both singlephase and threephase, using either triac, or thyristors connected back to back (#4.14.3). In the above cases, the output voltage obtained is, in the form of phasecontrolled one, as can be observed from the waveforms shown in the above lessons. In the present case, the output voltage of the cycloconverter circuit (singlephase) using thyristors, is synthesized from the above phasecontrolled voltage waveforms, so as to obtain an ac waveform (output) of low frequency, with the input being an ac voltage of higher frequency, say line. The angle, at which the thyristors are triggered, is controlled to obtain the desired waveform. Keywords: Singlephase to singlephase cycloconverter using thyristors, Voltage waveforms.
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represented as an alternating voltage source, which corresponds to the fundamental voltage component obtained at its output terminals. The diodes connected in series with each voltage source, show the unidirectional conduction of each converter, whose output voltage can be either positive or negative, being a twoquadrant one, but the direction of current is in the direction as shown in the circuit, as only thyristors unidirectional switching devices, are used in the two converters. Normally, the ripple content in the output voltage is neglected. iP iN
eP = Em sin ot
+
eo ac load
iO
eN = Em sin ot
Positive (P) converter Control Circuit er = Er sin ot Fig. 29.1: Equivalent circuit of cyclovonverter
The control principle used in an ideal cycloconverter is to continuously modulate the firing angles of the individual converters, so that each produces the same sinusoidal (ac) voltage at its output terminals. Thus, the voltages of the two generators (Fig. 29.1) have the same amplitude, frequency and phase, and the voltage of the cycloconverter is equal to the voltage of either of these generators. It is possible for the mean power to flow either to or from the output terminals, and the cycloconverter is inherently capable of operation with loads of any phase angle inductive or capacitive. Because of the unidirectional current carrying property of the individual converters, it is inherent that the positive halfcycle of load current must always be carried by the positive converter, and the negative halfcycle by the negative converter, regardless of the phase of the current with respect to the voltage. This means that each twoquadrant converter operates both in its rectifying (converting) and in its inverting region during the period of its associated halfcycle of current. The output voltage and current waveforms, illustrating the operation of an ideal cycloconverter circuit with loads of various displacement angles, are shown in Fig. 29.2. The displacement angle of the load (current) is 0 (Fig. 29.2a). In this case, each converter carries the load current only, when it operates in its rectifying region, and it remains idle throughout the whole period in which its terminal voltage is in the inverting region of operation. In Fig. 29.2b, the displacement angle of the load is 60 lagging. During the first 120 period of each halfcycle of load current, the associated converter operates in its rectifying region, and delivers power to the load. During the latter 60 period in the halfcycle, the associated converter Version 2 EE IIT, Kharagpur 4 www.jntuworld.com
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operates in its inverting region, and under this condition, the load is regenerating power back into the cycloconverter output terminals, and hence, into the ac system at the input side. These two are illustrative cases only. Any other case, say capacitive load, with the displacement angle as leading, the operation changes with inverting region in the first period of the halfcycle as per displacement angle, and the latter period operating in rectifying region. This is not shown in Fig. 29.2, which can be studied from a standard text book.
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P1 1phase ac supply P4
P2 eO
+
l o a d
iO
N1
N2 1phase ac supply
P3 N4 N3
Bridge 1 (Positive)
Bridge 2 (Negative)
Fig. 29.3: Singlephase to singlephase cycloconverter (using thyristor bridges) When a cycloconverter operates in the noncirculating current mode, the control scheme is complicated, if the load current is discontinuous. The control is somewhat simplified, if some amount of circulating current is allowed to flow between them. In this case, a circulating current limiting reactor is connected between the positive and negative converters, as is the case with dual converter, i.e. two fully controlled bridge converters connected back to back, in circulatingcurrent mode. The readers are requested to refer to any standard text book. This circulating current by itself keeps both converters in virtually continuous conduction over the whole control range. This type of operation is termed as the circulatingcurrent mode of operation. The operation of the cycloconverter circuit with both purely resistive (R), and inductive (RL) loads is explained.
Resistive (R) Load: For this load, the load current (instantaneous) goes to zero, as the input
voltage at the end of each half cycle (both positive and negative) reaches zero (0). Thus, the Version 2 EE IIT, Kharagpur 6 www.jntuworld.com
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conducting thyristor pair in one of the bridges turns off at that time, i.e. the thyristors undergo natural commutation. So, operation with discontinuous current (Fig. 29.4) takes place, as current flows in the load, only when the next thyristor pair in that bridge is triggered, or pulses are fed at respective gates. Taking first bridge 1 (positive), and assuming the top point of the ac supply as positive with the bottom point as negative in the positive half cycle of ac input, the oddnumbered thyristor pair, P1 & P3 is triggered after phase delay ( 1 ), such that current starts flowing through the load in this half cycle. In the next (negative) half cycle, the other thyristor pair (evennumbered), P2 & P4 in that bridge conducts, by triggering them after suitable phase delay from the start of zerocrossing. The current flows through the load in the same direction, with the output voltage also remaining positive. This process continues for one more half cycle (making a total of three) of input voltage ( f 1 = 50 Hz). From three waveforms, one combined positive half cycle of output voltage is produced across the load resistance, with its frequency being onethird of input frequency ( f 2 = f1 / 3 = 16 2 3 Hz). The following points may be noted. The firing angle () of the converter is first decreased, in this case for second cycle only, and then again increased in the next (third) cycle, as shown in Fig. 29.4b. This is, because only three cycles for each half cycle is used. If the output frequency needed is lower, the number of cycles is to be increased, with the firing angle decreasing for some cycles, and then again increasing in the subsequent cycles, as described earlier. es 0 5 2 Mean output voltage 0 2 1 2 3 3 (b) 4 (a) 3 4 6
e0
4 5
Fig. 29.4: Input (a) and output (b) voltage waveforms of a cycloconverter with an output frequency of 16 2 3 Hz for resistive (R) load To obtain negative output voltage, in the next three half cycles of input voltage, bridge 2 is used. Following same logic, if the bottom point of the ac supply is taken as positive with the top point as negative in the negative half of ac input, the oddnumbered thyristor pair, N1 & N3 conducts, by triggering them after suitable phase delay from the zerocrossing. Similarly, the evennumbered thyristor pair, N2 & N4 conducts in the next half cycle. Both the output voltage and current are now negative. As in the previous case, the above process also continues for three consecutive half cycles of input voltage. From three waveforms, one combined negative half cycle of output voltage is produced, having same frequency as given earlier. The pattern of firing angle first decreasing and the increasing, is also followed in the negative half cycle. One positive half cycle, along with one negative half cycle, constitute one complete cycle of output Version 2 EE IIT, Kharagpur 7 www.jntuworld.com
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(load) voltage waveform, its frequency being 16 2 3 Hz as stated earlier. The ripple frequency of the output voltage/ current for singlephase fullwave converter is 100 Hz, i.e., double of the input frequency. It may be noted that the load (output) current is discontinuous (Fig. 29.4c), as also load (output) voltage (Fig. 29.4b). The supply (input) voltage is shown in Fig. 29.4a. Only one of two thyristor bridges (positive or negative) conducts at a time, giving noncirculating current mode of operation in this circuit.
Inductive (RL) Load: For this load, the load current may be continuous or discontinuous
depending on the firing angle and load power factor. The load voltage and current waveforms are shown for continuous and discontinuous load current in Fig. 29.5 and 29.6 respectively. es 0 3 4 (a) 5 6 7 8 (b) 5 7
e0 0
(c) Fig. 29.5: Input (a) and output (b) voltage, and current (c) waveforms for a cycloconverter with discontinuous
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es 0 2 3 4 5 7
e0 0
(a) 5 5 (b) 6 6 7 7 8
i0 0 (c)
i0 0
(d) Fig. 29.6: Input (a) and output (b) voltage, and current (c, d) waveforms for a cycloconverter with continuous load current.
(a)
The load current in this case is discontinuous, as the inductance, L in series with the resistance, R, is low. This is somewhat similar to the previous case, but difference also exists as described. Here, also noncirculating mode of operation takes place, with only one of the bridges #1 (positive), or #2 (negative), conducting at a time, but two bridges do not conduct at the same time, as this will result in a short circuit. In this case, the output frequency is assumed as ( f 2 = 12.5 Hz), the input frequency being same as ( f 1 = 50 Hz), i.e., f 1 = 4 f 2 , or f 2 = f 1 / 4 . So, four positive half cycles, or two full cycles of the input to the fullwave bridge converter (#1), are required to produce one positive half cycle of the output waveform, as the output frequency is onefourth of the input frequency as given earlier. As in the previous case with resistive load, taking bridge 1, and assuming the top point of the ac supply as positive, in the positive half cycle of ac input, the oddnumbered thyristor pair, P1 & P3, is triggered after phase delay ( = t = 1 ), such that current starts flowing the inductive load in this half cycle. But Version 2 EE IIT, Kharagpur 9 www.jntuworld.com
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here, the current flows even after the input voltage has reversed (after = ), till it reaches zero at ( = 1 ) with ( + 2) > 1 > , due to inductance being present in series with resistance, its value being low. It may be noted that the thyristor pair is, thus, naturally commutated. In the next (negative) half cycle, the other thyristor pair (evennumbered), P2 & P4, is triggered at ( + 2) . The current flows through the load in the same direction, with the output voltage also remaining positive. The current goes to zero at ( + 2) , with ( + 3) > 2 > . This procedure continues for the next two half cycles, making a total of four positive half cycles. From these four waveforms, one combined positive half cycle of output voltage is produced across the inductive load. The firing angle () of the converter is first decreased, in this case for second half cycle only, kept nearly same in the third one, and finally increased in the last (fourth) one, as shown in Fig. 29.5b. To obtain negative output voltage, in the next four half cycles of output voltage, bridge 2 is used. Following same logic, if the bottom point of the ac supply is taken as positive in the negative half of ac input, the oddnumbered thyristor pair, N1 & N3 conducts, by triggering them after phase delay ( = 4 + 1 ). The current flows now in the opposite (negative) direction through the inductive load, with the output voltage being also negative. The current goes to zero at ( 4 + 1 ), due to load being inductive as given earlier. Similarly, the evennumbered thyristor pair, N2 & N4 conducts in the next half cycle, after they are triggered at ( 5 + 2 ). The current goes to zero at ( 5 + 2 ). Both the output voltage and current are now negative. As in the previous case, the above process also continues for two more half cycles of input voltage, making a total of four. From these four waveforms, one combined negative half cycle of output voltage is produced with same output frequency. The pattern of firing angle first decreasing and then increasing, is also followed in the negative half cycle. It may be noted that the load (output) current is discontinuous (Fig. 29.5c), as also load (output) voltage (Fig. 29.5b). The supply (input) voltage is shown in Fig. 29.5a. One positive half cycle, along with one negative half cycle, constitute one complete cycle of output (load) voltage waveform, its frequency being 12.5 Hz as stated earlier. The ripple frequency remains also same at 100 Hz, with the ripple in load current being filtered by the inductance present in the load.
(b)
As given above, the load current is discontinuous, as the inductance of the load is low. If the inductance is increased, the current will be continuous. Most of the points given earlier are applicable to this case, as described. To repeat, noncirculating mode of operation is used, i.e., only one of the bridges #1 (positive), or #2 (negative), conducts at a time, but two bridges do not conduct at the same time, as this will result in a short circuit. Also, the ripple frequency in the voltage and current waveforms remains same at 100 Hz. The output frequency is onefourth of input frequency (50 Hz), i.e., 12.5 Hz. So, for each halfcycle of output voltage waveform, four half cycles of input supply are required. Taking bridge 1, and assuming the top point of the ac supply as positive, in the positive half cycle of ac input, the oddnumbered thyristor pair, P1 & P3, is triggered after phase delay ( = t = 1 ), such that current starts flowing the inductive load in this half cycle. But here, the current flows for about one complete half cycle, i.e., up to the angle, ( + 1 ) or ( + 2 ), whichever is higher, even after the input voltage has reversed, due to the high value of load inductance. In the next (negative) half cycle, the other thyristor pair (evennumbered), P2 & P4, is triggered at ( + 2) . At that time, reverse voltage is applied across each of the conducting thyristors, P1/P3, and the thyristors turn off. The current flows through the load in the same direction, with the output voltage also remaining positive. Also, the current Version 2 EE IIT, Kharagpur 10 www.jntuworld.com
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flows for about one complete half cycle, i.e., up to the angle, ( + 2 ) or ( + 3 ), whichever is higher. This procedure continues for the next two half cycles, making a total of four positive half cycles. From these four waveforms, one combined positive half cycle of output voltage is produced across the inductive load. The firing angle () of the converter is first decreased, in this case for second half cycle only, kept nearly same in the third one, and finally increased in the last (fourth) one, as shown in Fig. 29.6b. To obtain negative output voltage, in the next four half cycles of output voltage, bridge 2 is used. Following same logic, if the bottom point of the ac supply is taken as positive in the negative half of ac input, the oddnumbered thyristor pair, N1 & N3 conducts, by triggering them after phase delay ( = 4 + 1 ). The current flows now in the opposite (negative) direction through the inductive load, with the output voltage being also negative. The current flows for about one complete half cycle, i.e., up to the angle, ( 5 . + 1 ) or ( 5 + 2 ), whichever is higher, as the load is inductive. Similarly, the evennumbered thyristor pair, N2 & N4 conducts in the next half cycle, after they are triggered at ( 5 + 2 ). As described earlier, both the conducting thyristors turn off, as reverse voltage is applied across each of them. Both the output voltage and current are now negative. Also, the current flows for about one complete half cycle, i.e. up to the angle, ( 5 + 2 ) or ( 5 + 3 ), whichever is higher. As in the previous case, the above process also continues for two more half cycles of input voltage, making a total of four. From these four waveforms, one combined negative half cycle of output voltage is produced with same output frequency of 12.5 Hz. The pattern of firing angle first decreasing and then increasing, is also followed in the negative half cycle. It may be observed that the load (output) current is continuous (Fig. 29.6c), as also load (output) voltage (Fig. 29.6b). The load (output) current is redrawn in Fig. 29.6d, under steady state condition, while the supply (input) voltage is shown in Fig. 29.6a. One positive half cycle, along with one negative half cycle, constitute one complete cycle of output (load) voltage waveform.
4. Commutation failure causes a short circuit of ac supply. But, if an individual fuse blows off, a complete shutdown is not necessary, and cycloconverter continues to function with somewhat distorted waveforms. A balanced load is presented to the ac supply with unbalanced output conditions.
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5. Cycloconverter delivers a high quality sinusoidal waveform at low output frequencies, since it is fabricated from a large number of segments of the supply waveform. This is often preferable for very low speed applications. 6. Cycloconverter is extremely attractive for large power, low speed drives.
Disadvantages
1. Large number of thyristors is required in a cycloconverter, and its control circuitry becomes more complex. It is not justified to use it for small installations, but is economical for units above 20 kVA. 2. For reasonable power output and efficiency, the output frequency is limited to onethird of the input frequency. 3. The power factor is low particularly at reduced output voltages, as phase control is used with high firing delay angle. Converter 3phase ac supply
+ 
Fig. 29.7: DC link converter The cycloconverter is normally compared with dc link converter (Fig. 29.7), where two power controllers, first one for converting from ac input at line frequency to dc output, and the second one as inverter to obtain ac output at any frequency from the above dc input fed to it. The thyristors, or switching devices of transistor family, which are termed as selfcommutated ones, usually the former, which in this case is naturally commutated, are used in controlled converters (rectifiers). The diodes, whose cost is low, are used in uncontrolled ones. But nowadays, switching devices of transistor family are used in inverters, though thyristors using force commutation are also used. A diode, connected back to back with the switching device, may be a power transistor (BJT), is needed for each device. The number of switching devices in dc link converter depends upon the number of phases used at both input and output. The number of devices, such as thyristors, used in cycloconverters depends on the types of connection, and also the number of phases at both input and output. It may be noted that all features of a cycloconverter may not be available in a dc link converter. Similarly, certain features, like Pulse Width Modulation (PWM) techniques as used in inverters and also converters, to reduce the harmonics in voltage waveforms, are not applied in cycloconverters. The various circuits used and their operational aspects are discussed in detail in the next (last) module (#5) on DC to AC Converters termed as Inverters.
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2. .The control circuit here is simpler, as compared to that used in cycloconverter. 3. It has high input power factor, if diode rectifier is used in the first stage. If phasecontrolled thyristor converter is used, power factor depends upon phase angle delay. 4. It is suitable for higher frequencies, as given earlier.
Disadvantages
1. The conversion is in two stages, using two power controllers one as converter and other as inverter, as stated earlier. 2. Forced commutation is required for the inverter, if thyristors are used, even though phase control is used in converter, where natural commutation takes place. 3. The feature of regeneration is somewhat difficult, and also is involved to incorporate in a dc link converter. 4. The output waveform of the inverter is normally a stepped one, which may cause nonuniform rotation of an ac motor at very low frequencies (< 10 Hz). The distorted waveform also causes system instability at low frequencies. This can be reduced by using PWM technique as given earlier. In this lesson, the first one in the second half of this module (#4), the cycloconverter is first introduced, along with the basic principle of operation. The circuit and the operation of singlephase to singlephase cycloconverter, with both resistive and inductive loads, are described in detail, with voltage and current waveforms. The current is discontinuous, with resistive and inductive (with low value of inductance) loads, but can be continuous, if the inductance is higher. In the next lesson, the circuit and operation of threephase to singlephase cycloconverter, followed by threephase to threephase one, will be described in detail.
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Module 4
AC to AC Voltage Converters
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Lesson 30
Threephase to Singlephase Cycloconverters
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Instructional Objectives
Study of the following: The threephase to singlephase cycloconverter circuit, using two threephase fullwave thyristorised bridge converters The operation of the above cycloconverter circuit, along with the voltage waveforms
Introduction
In the last lesson first one in the second half of this module, firstly, the basic principle of operation of the cycloconverter circuits has been presented. This followed by the discussion of the circuit, and the operation of the singlephase to singlephase cycloconverter circuit with both resistive and inductive loads, in detail. Two fullwave bridge converters (rectifiers) connected back to back, with four thyristors as power switching device in each bridge, are used. Also described are the advantages and disadvantages of the cycloconverter. The dc link converter is introduced briefly, along with its advantages and disadvantages. In this lesson the second one in the second half, firstly, the threephase to singlephase cycloconverter circuit, using two threephase fullwave thyristorised bridge converters, is presented. Then, the operation of the above cycloconverter circuit, with both resistive and inductive loads, is described in detail, along with voltage waveforms. The mode of operation used is the noncirculating current one. The following are discussed in brief .the circulating current mode of operation for the above, and also the cycloconverter circuit, using two threephase halfwave converters. Keywords: Threephase to singlephase cycloconverter, Voltage waveforms, Noncirculating current, and Circulating current modes of operation, Threephase fullwave bridge, and halfwave converters.
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off. This sequence is repeated in cyclic order. So, natural or line commutation takes place in this case. Otherwise, the procedure is similar to the one as discussed in the previous lesson. iP iN
P1 3phase A ac B supply C P4
P3
P5 l o a d
N1
N3
N5 A 3phase B ac C supply
iO
P6 P2
N4
N6
N2
Fig. 30.1: Threephase to singlephase cycloconverter The procedure to be followed in the triggering of the thyristors in sequence in the two bridge converters has been briefly given earlier. The readers are requested to go through two lessons (#2.52.6) in module 2 (ACDC Converters), or any standard text book. As given in the earlier lesson (#4.4), the firing angle () of two converters is first decreased starting from the initial value of 90 to the final value of 0 , and then again increased to the final value of 90 , as shown in Fig. 30.2. Also, for positive half cycle of the output voltage waveform, bridge 1 is used, while bridge 2 is used for negative half cycle. The two half cycles are combined to form one complete cycle of the output voltage, the frequency being decided by the number of half cycles of input voltage waveform used for each half cycle of the output. As more no. of segments of near 60 ( / 6) is used, the output voltage waveform becomes near sinusoidal, with its frequency also being reduced. The initial value of firing angle delay is kept at 1 90 , such the average value (dc) of the output voltage in this interval of near 60 ( / 6) [ Vav cos 1 = cos 90 = 0.0 ], is zero. It may be noted that the next thyristor in sequence is triggered at 2 < 90 , as the firing angle is decreased for each segment, to obtain higher voltage Vav cos 2 = +ve , to form the sine wave at the output. This can be observed from the points, M, N, O, P, Q, R & S, shown in Fig. 30.2. From these segments, the first quarter cycle of the output voltage waveform from 0 to 90 , is obtained. The second quarter cycle of the above waveform from 90 to 180 , is obtained, using the segments starting from the points, T, U, V, W, X &Y (fig. 30.2). It may be noted that the firing angle delay at the point, Y is = 90 , and also the firing angle is increased from 0 (T) to 90 (Y) in this interval. When the firing angle delay is 0 , the average value of the segment is Vav cos = cos 0 = 1.0 . The two quarter cycles form the positive half cycle of the output voltage waveform. In this region, the bridge 1 (positive) is used. To obtain the negative half cycle of the output voltage waveform ( 180 360 ), the other bridge converter (#2) termed negative (N) is used in the same manner as given earlier, i.e. its firing angle delay () is first decreased starting from the initial value of 90 to the final value of 0 , and then again increased Version 2 EE IIT, Kharagpur 4 www.jntuworld.com
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to the final value of 90 , as given earlier. The two half cycles (positive and negative) together give one complete cycle ( 0 360 ) of the output voltage waveform. Fabricated output voltage = 90 e0 R P M N 0 Q ST U V W X = t = 0
= 90
Fig. 30.2 Output voltage waveforms for a threephase to single phase cycloconverter. The load on the output of the cycloconverter is assumed to be inductive (RL). The load can also be capacitive. For inductive load, the output current (Fig. 30.3) lags behind the voltage by its phase angle, (assumed to be positive). The load power factor is also +ve ( cos ). It may be noted that the current is unidirectional in a thyristor converter. As the current, being alternating in nature, flows in both directions in a complete cycle, two converters are connected in antiparallel. The positive (P) converter carries current during positive half cycle of output current, while the other, i.e. negative (N) one carries current in the negative half cycle. As discussed in the previous lesson (#29), Pconverter acts as a rectifier, when the output voltage is positive, and as an inverter, when the output voltage is negative (Fig. 30.3). Similarly, Nconverter acts as a rectifier, when the output voltage is negative, and as an inverter, when the output voltage is positive. It can thus be inferred, in general, that one of two converters would operate as rectifier, if its output voltage and current have the same polarity, and as an inverter, if these are of opposite polarity.
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Fig. 30.3 Voltage (a) and current (b) waveforms for a three phase fullwave (sixpulse) cycloconverter.
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respectively, then these firing angles must be controlled so as to satisfy the condition ( p + n ) = 180 ( ) . IG reactor iP a b P1 3phase A ac B supply C P4 P6 P2 P3 P5 l o a d iN c N1 N3 N5 A 3phase B ac C supply
iO
N4
N6
N2
Fig. 30.4: Cycloconverter (circulating current mode) with Intergroup(IG) reactor The continuous current of each group in the circulating current mode imposes a higher loading on each group compared to the noncirculating current mode of operation. In practice, this mode, i.e. circulating current one, would only be used, when the load current is low, so that continuous load current with a better waveform can be maintained. At the higher levels of load current, the groups would be blocked to prevent circulating current. Control circuits would be used to sense the level of the load current, allowing firing pulses to each group at low current level, but blocking firing pulses to one or the other group at the higher current levels. The reactor would be designed to saturate at higher current levels, when the cycloconverter is operating in the noncirculating current mode, thus permitting a smaller one.
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case is much simpler and cheaper, as only three pulses per each converter are needed. This may be preferred, as only the harmonic content is more, which may not be a demerit in most of the applications. If it is used to drive ac motors, the high impedance at the ripple frequency is expected to make the output current near sinusoidal one, with the result that no additional filtering component is needed. Other conditions, being same, are not described here, and the waveforms also not shown, which is given in standard text book, or may be drawn from the waveforms given in .the earlier case. A B C 3phase supply A B C 3phase supply
P1
P2
P3 + L o a d
N1
N2
N3
Fig. 30.5: Threephase to single phase cycloconverter (two threephase halfwave converter) In this lesson, firstly, the threephase to singlephase cycloconverter, using two threephase fullwave bridge converters, is described, with the circuit and various output voltage and current waveforms. The noncirculating current mode of operation is presented in detail, so as to obtain sinusoidal output voltage waveform. The circulating current mode is briefly discussed, along the change in the circuit. Lastly, the circuit for the same type of cycloconverter, with two threephase halfwave converters, is given, stating briefly the differences for this case. In the next lesson, the threephase to threephase cycloconverter will be taken up first. Three such circuits, as described in this lesson, are needed in this case. Lastly, the analysis of the cycloconverter output waveforms will be presented.
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Module 4
AC to AC Voltage Converters
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Lesson 31
Threephase to Threephase Cycloconverters
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Instructional Objectives
Study of the following: The threephase to threephase cycloconverter circuit, using six threephase halfwave thyristorised converters The operation of the above cycloconverter circuit The analysis of the cycloconverter output waveform
Introduction
In the last lesson second one in the second half of this module, firstly, the circuit and the operation of the threephase to singlephase cycloconverter, with both resistive and inductive loads, are described in detail. Two threephase fullwave bridge converters (rectifiers) connected back to back, with six thyristors as power switching devices in each bridge, are used. The mode of operation is noncirculating current one, in which only one converter is conducting at a time. The following are briefly presented the circulating current mode of operation with both converters conducting at a time, and the same type of cycloconverter, using two threephase halfwave converters, stating mainly the merits. In this lesson the third one in the second half, firstly, the threephase to threephase cycloconverter circuit, using six threephase halfwave thyristorised converters (two per each phase), is described. The operation of the above cycloconverter circuit is briefly discussed. The mode of operation is the noncirculating current one. Lastly, the analysis of the cycloconverter output waveform is presented. The procedure for obtaining the expression for the output voltage (rms) per phase for cycloconverter is described. Keywords: Threephase to threephase cycloconverter, Threephase halfwave converters. Output waveform analysis
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A B C
3 supply
N Phase A
N Phase B
N Phase C
3phase load Fig. 31.1: Threephase to threephase cycloconverter It may be noted that the circuit in each of the three phases is similar to the cycloconverter circuit shown in Fig. 30.5. The firing sequence of the thyristors for the phase groups, B & C are same as that for phase group A, but lag by the angle,120 and 240 , respectively. Thus, a balanced threephase voltage is obtained at the output terminals, to be fed to the threephase load. The average value of the output voltage is changed by varying the firing angles ( ) of the thyristors, whereas its frequency is varied by changing the time interval ( T / 3 = 1 /(3 f 0 ) ), after which the next (incoming) thyristor is triggered. With a balanced load, the neutral connection is not necessary, and may be omitted, thereby suppressing all triplen harmonics. Normally, the output frequency of the cycloconverter is lower than the supply (input) frequency (stepdown region), limited to about onethird of it ( f 0 = f i / 3 ). This is necessary for obtaining reasonable power output, efficiency and harmonic content. If the output frequency is to be increased, the harmonic distortion in the output voltage increases, because its waveform is composed of fewer segments of the supply voltage. Thus, the losses in cycloconverter and also in ac motor become excessive. By using more complex converter circuits with higher pulse numbers, the output voltage waveform is improved, with the maximum useful ratio of output to input frequency is increased to about onehalf.
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( 2 ) radians. Similarly, in a threephase, fullwave (sixpulse) converter (m = 6), the conduction period of the periodic waveform is ( (2 ) / 6 = / 3 = 60 ) radians in one cycle. The output voltage waveform for an mphase converter with firing delay angle , is shown in Fig. 31.2. With the time origin, PP taken at the peak value of the supply voltage, the instantaneous phase voltage is given by e = E m cos t = 2 E ph cos t where, E ph = Supply voltage per phase (rms). ( /m + ) Ec P Em  /m P /m 2/m t (/m + )
Fig. 31.2: Output voltage waveform for mphase converter with firing angle From Fig. 31.2, it can be observed that the conduction period is from ( / m ) to ( / m ), if the firing delay angle is = 0 . For the firing delay angle , the conduction period is from ( ( / m) + ) to ( ( / m) + ). From the above cases, the total conduction period is ( (2 ) / m ). The average value of the output voltage is, (( / m ) + ) m m E dc = 2 E ph cos t d ( t ) = 2 E ph sin cos 2 ( ( / m )+ ) m This expression is obtained for dc to ac converter in module 2, and also available in text book. When the firing delay angle is = 0 , E dc has the maximum value of
m E d 0 = 2 E ph sin m If the delay angle in the cycloconverter is slowly varied as given earlier, the output phase voltage at any point of the low frequency cycle may be calculated as the average voltage for the appropriate delay angle. This ignores the rapid fluctuations superimposed on the average low frequency waveform. Assuming continuous conduction, the average voltage is E dc = E d 0 cos .
If E 0 r is the fundamental component of the output voltage (rms) per phase for the cycloconverter, then the peak output voltage for firing angle of 0 is, m 2 E 0 r = E d 0 = 2 E ph sin m m or, E0 r = E ph sin m However, the firing angle of the positive group, p cannot be reduced to zero ( 0 ), for this value corresponds to a firing angle of ( n = 180 ) in the negative group. It may be noted that the firing delay angles of the two (positive and negative) converters are related by ( P + n = 180 ), or
p = 180 n . In practice, inverter firing cannot be delayed by 180 , because sufficient margin
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must be allowed for commutation overlap and thyristor turnoff time, as given in module 2. Consequently, the delay angle of the positive group cannot be reduced below a certain finite value, min . Therefore, the maximum output voltage per phase is, Edc (max) = Ed 0 cos min = r Ed 0 . where, r = cos min , and is called the voltage reduction factor. Thus, the expression for the fundamental component of the phase voltage (rms) delivered by m the cycloconverter is, E 0 r = r E ph sin m Since min is necessarily greater than zero, the voltage reduction factor is always lower than unity. By deliberately increasing min , and thereby reducing the range of variation of about the value of 90 , the output voltage, E0 r can be reduced, and a static method of voltage control is obtained. In practice, the output voltage is lower than the theoretical value obtained earlier, due to the influence of the commutation overlap and the circulating current between the positive and negative groups. Thus, the expression for the output voltage (rms) per phase for a threephase to threephase or a threephase to singlephase cycloconverter given earlier is obtained. In this lesson, firstly, the circuit, and the operation, in brief, of the threephase to threephase cycloconverter, is described. Six threephase halfwave converters are used in this case, with two converters, connected back to back, per phase. A total of 18 thyristors are needed as power switching devices, having three thyristors for each converter. Lastly, the analysis of the output waveform for the cycloconverter is presented. The procedure for obtaining the expression for the output voltage (rms) per phase for cycloconverter is described. In the next, i.e. last lesson of this module