Seminario Idetic 120120

Seminar in
Practical Application of Direct Digital Synthesis (DDS)
Multimedia Room, Polivalente II, 2nd floor Campus de Tafira, Las Palmas 20th January, 2012
Speaker: Baltasar Prez Daz <bperez@idetic.eu>

Author: Baltasar Prez Daz
www.idetic.eu
Practical Application of Direct Digital Synthesis (DDS) BACKGROUND INFORMATION
Broadband digital HF transceiver

DUC/DDC multichannel (FPGA)
1KW Power amplifier Driver
Wattmeter Broadband Transceiver
20th January
IDeTIC Seminar
Practical Application of Direct Digital Synthesis (DDS) BACKGROUND INFORMATION
ANT
RX OL TX
Control PS
19 subrack 3U form board (100x160mm) with connector DIN41612 Rear: digital signals Front: analog signals Power Supply: 220Vac and 12V DC
20th January
IDeTIC Seminar
Practical Application of Direct Digital Synthesis (DDS) PRESENTATION INDEX

INDEX
INTRODUCTION
1.
DDS Theory
DDS THEORY
a. Block diagram, spurs, topologies
EXAMPLE: AD9954
DDS IN RADIO SUBSYSTEM
2.
Example: AD9954
a. Datasheet
SUMMARY
3.
DDS in radio subsystems
4.
Summary
20th January
IDeTIC Seminar
Practical Application of Direct Digital Synthesis (DDS) DDS THEORY

INDEX
INTRODUCTION
DDS is a method of producing an analog waveform,usually a sine wave, by generating a time-varying signal in digital form converted into analog signals using a DAC NCO (Numeric Controlled Oscillator) also called Advantages Capable of generating a variety of waveforms (sine, triangle, square) Preferred form of signal generation nowadays Fast switching capability (freq. hopping systems (phase-continuous)) High precision sub Hz (mHz) and sub degree phase tuning Digital circuitry Small size (single chip) fraction of analog synthesizer size Fewer components per system - low cost Small low-powered devices portability Easy implementation (no Barkhaussen criterion, PLL (LPF design)) Fewer assembly operations / reduced product reject rates
DDS THEORY
EXAMPLE: AD9954
SUMMARY
20th January
IDeTIC Seminar

INDEX
Typical DDS Architecture
INTRODUCTION
DDS THEORY
Digital Circuits
Frequency Word Sine N Accum W Lookup R D-to-A 14 to 10 to to Fr 24 ulator 16bits 48bits Table 14bits Conv. Ref clk Low Pass Filter
fout=
EXAMPLE: AD9954
fclkFr 2N
Sine Wave
SUMMARY
1/fout
1/fout
1/fout
1/fout
1/fclk
1/fclk
1/fclk
20th January
IDeTIC Seminar

INDEX
Phase Accumulator as a digital phase wheel
INTRODUCTION
DDS THEORY
0 pi 2pi
EXAMPLE: AD9954
SUMMARY
The phase accumulator is actually a modulo-M counter. Increments its stored number each time it receives a clock pulse. Magnitude determined by word (M). This word forms the phase step size between reference-clock updates; it sets how many points to skip around the phase wheel. The larger the jump size, the faster the phase accumulator overflows and completes its equivalent of a sine-wave cycle. The number of discrete phase points contained in the wheel is determined by the resolution of the phase accumulator (n), which determines the tuning resolution of the DDS. IDeTIC Seminar
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20th January

INDEX
Digital to Analog Converter Output
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
SUMMARY

20th January
Sampling theory (sinc(x)) Nyquist: Fundamental signal <= Fclk/2 (1/3 better) Filter required to eliminate unwanted products Lets increase the fundamental signal frequency
IDeTIC Seminar

INDEX
Digital to Analog Converter Output
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
SUMMARY
Sampling theory (sinc(x)) Nyquist: Fundamental signal <= Fclk/2 (1/3 better) Filter required to eliminate unwanted products
20th January
IDeTIC Seminar

INDEX
Super-Nyquist Operation
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
SUMMARY
SNR, SFDR and power reduction SAW filter (narrowband) Change Fs to center sinc envelope peak
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IDeTIC Seminar
10

INDEX
INTRODUCTION
History
Earlier designs 1970s for audio signal applications from sampled values of sine wave in ROM later driving DAC Modern approaches much improved and mostly derivative of the classical approach Practical use in Comms System by 1990s 1980s Highest freq. - < 10 MHz limitation of DAC tech. Current DDS systems 1GHz (new 2.7GHz)
DDS THEORY
EXAMPLE: AD9954
SUMMARY
DDS vs PLL
DDS generates lower frequency than PLL DDS frequency can be controlled in very fine increments. The frequency of a DDS synthesizer can be changed much faster than that of the PLL. DDS occupies a single chip, and PLL several Easy oscillator design in DDS, complex in PLL
20th January
IDeTIC Seminar
11

INDEX
Not only waveforms generator, also modulations
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
SUMMARY
Square-, triangular-, and sinusoidal outputs from a DDS Also Sweep, Chirp, RAM profiles, Amplitud control
FSK
12
20th January
IDeTIC Seminar

INDEX
Not only waveforms generator, also modulations
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
BPSK (2 phases) and QPSK (4 phases)

SUMMARY
IQ generator capability AD9958 (2 DDS cores) AD9959 (4 DDS cores) (beamforming)

20th January
FSK
13
IDeTIC Seminar

INDEX
Spurs !!!
Worst problem in DDS
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
SUMMARY

20th January
AD9835 (fclk=50MHz) Spurs situation and quantity depend on output frequency

IDeTIC Seminar
14

INDEX
Spurs !!!
Worst problem in DDS
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
SUMMARY

20th January
AD9835 (fclk=50MHz) Spurs situation and quantity depend on output frequency

IDeTIC Seminar
15

INDEX
Spurs sources
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
SUMMARY
A DDS have four principal sources of spurs

20th January
IDeTIC Seminar
16

INDEX
Spurs sources: Reference Clock

- A DDS functions like a high-resolution frequency divider with reference clock - The spectral characteristics of the reference clock directly impact those of the output, but at a reduced magnitude due to the frequency division. - The improvement is 20 log(N), where N is the ratio of input to output frequencies. - Tip: Use the highest frequency clock
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
SUMMARY
Figure: 300MHz clock down to 80MHz and 5MHz

20th January
IDeTIC Seminar
17

INDEX
Spurs sources: Reference Clock

- Modulating the clock amplitude generates spurs in its output spectrum.
INTRODUCTION
DDS THEORY
- The limiter stage converts the sine wave to a square wave, and the AM spurs are thus converted to PM (phase modulation) spurs. - The quality of the reference clock imposes limits on DDS performance in ways that are often recognizable (those DDS spurs that maintain their relationship to the carrier as you change the output frequency).
EXAMPLE: AD9954
SUMMARY
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IDeTIC Seminar
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INDEX
Spurs sources: Phase truncation - Consider a 32-bit phase accumulator - If we maintain all 32 bits throughout, the DDS core would occupy a large die area and dissipate significant power. - Truncating the value from the phase accumulator (passing only the accumulator's most significant bits to the angle-to-amplitude mapper) reduces area and power - The phase-truncation spur mechanism models as a noise source summed
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
SUMMARY
Example: 20bits accum to 8 bits As the value in the discarded section accumulates, it eventually overflows into the truncated phase word (effect is phase-modulation spurs)
20th January
IDeTIC Seminar
19

INDEX
Spurs sources: Phase truncation
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
Spurs level= -6.02P P (phase truncated word)
SUMMARY
Example: -6.02x14=-84dBc Note: if no bits in the discarded portion are set to logic one, then no phase-truncation spurs occur
20th January
IDeTIC Seminar
20

INDEX
Spurs sources: DAC error terms

- A DAC's quantization noise and distortion determine its SNR - SNR is proportional to the DAC resolution in bits (SNR=6.02N+1.76(dB))
INTRODUCTION
DDS THEORY
- SNR calculation describes an ideal DAC. Real DACs also have nonlinearities due to process mismatches and imperfect bit-weight scaling. - Harmonic alias because the DAC is a time-sampled system. Well-defined relationship
EXAMPLE: AD9954
SUMMARY
20th January
IDeTIC Seminar
21

INDEX
Spurs sources: DAC error terms

Example: - DDS tuned to 25.153 MHz with a reference clock of 100M samples/sec generates low-order odd harmonics close to the fundamental - DDS has a 14-bit DAC. The SFDR within the 4-MHz bandwidth is better than 73 dBc - Raising Fref to 400M samples/sec eliminates the alias products of the third, fifth, and seventh harmonics within the first Nyquist zone.
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
SUMMARY
20th January
IDeTIC Seminar
22
Practical Application of Direct Digital Synthesis (DDS) DDS THEORY SpurKiller Technology: The Results on a DDS Output Spur
INDEX
INTRODUCTION
BEFORE
DDS THEORY
AFTER
EXAMPLE: AD9954
SUMMARY
500 kHz / DIVISION
500 kHz / DIVISION
OUTPUT FREQUENCY = 166 MHz Fclk = 500 MSPS

20th January
IDeTIC Seminar
23

INDEX
SpurKiller Technology
INTRODUCTION
DDS THEORY
Use an auxiliary DDS channel to add in a signal at the same frequency and amplitude as the spur, but 180 out of phase with the highest spur Its all in the Digital Domain!
DDS Channel for spur reduction
EXAMPLE: AD9954
Frequency Accumulator
FTW
Phase Offset
32
14
COS(X)
DAC
SUMMARY
16
10
AD9911 DDS core
Register
DDS Channel for phase modulation
Register
DDS Channel for amplitude modulation
Register
The frequencies at which spurs appear are simple functions of the sampling rate and the programmed output frequency. Spurs are therefore predictable. In addition, the relative phase of each spur does not change.
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IDeTIC Seminar
24

INDEX
Important parameters for RF: Phase Noise

- Phase noise is a measure (dBc/Hz) of the short-term frequency instability of the oscillator (jitter in time-domain) - Jitter in oscillators is caused by thermal noise, instabilities in the oscillator electronics, external interference through the power rails, ground, and even the output connections. - DDS introduces some jitter/noise (phase truncation/DAC) but overall is reference clock jitter. Its critical! Also take slew-rate into account. - Dividing down the frequency of a high-frequency clock is one way to reduce jitter
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
SUMMARY
Typical output phase noise plot for the AD9834. Output frequency is 2 MHz and M clock is 50 MHz.
Very good phase noise comparable to profesional equipment!!
20th January
IDeTIC Seminar
25

INDEX
Important parameters for RF: SFDR (Spurious-Free Dynamic Range)

- Its the ratio (measured in decibels) between the highest level of the fundamental signal and the highest level of any spurious. - For the very best SFDR, it is essential to begin with a high-quality oscillator. - SFDR is an important specification in an application where the frequency spectrum is being shared with other communication channels and applications. - If a transmitters output sends spurious signals into other frequency bands, they can corrupt, or interrupt neighbouring signals.
AD9834 (10-bit DDS) with a 50MHz master/reference clock Figure (a) fout=16.667MHz (i.e. MCLK/3) SFDR=80 Figure (b) fout=4.8MHz SFDR=50 span=Nyquist
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
SUMMARY
20th January
IDeTIC Seminar
26

INDEX
Synthesizer topologies PLL General Architecture

Phase/ Frequency Detector
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
Loop Filter
VCO
Fref
RF
SUMMARY
FRF N Fref
20th January
IDeTIC Seminar
27

INDEX
Synthesizer topologies DDS Used as PLL Reference
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
Loop Filter
VCO
Fref
DDS
RF
SUMMARY
FRF NM
20th January
Fref 2n
28
IDeTIC Seminar

INDEX
Synthesizer topologies DDS Used in Fractional-N Loop

INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
Loop Filter
VCO
Fref
RF
SUMMARY
DDS
M
FRF 2n
20th January
Fref M
29
IDeTIC Seminar

INDEX
Synthesizer topologies DDS Used in Translation Loop

INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
Loop Filter
VCO
Fref
RF
SUMMARY
N Fclk DDS
F FRF N Fref M clk 2n
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IDeTIC Seminar
30

INDEX
DDS Tools
INTRODUCTION
DDS THEORY
Main website: http://www.analog.com/dds
EXAMPLE: AD9954
Analog Devices DDS product list

SUMMARY
ADISim DDS
DDS configuration assistant
RSonline DDS Prices
20th January
IDeTIC Seminar
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Practical Application of Direct Digital Synthesis (DDS) EXAMPLE: AD9954

INDEX
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
SUMMARY
400 MSPS internal clock speed Integrated 14-bit DAC Programmable phase/amplitude dithering 32-bit frequency tuning accuracy 14-bit phase tuning accuracy Excellent dynamic performance >80 dB narrowband SFDR
Phase noise better than 120 dBc/Hz Serial I/O control Ultrahigh speed analog comparator Automatic linear & nonlinear freq sweeping 4 frequency/phase offset profiles 1.8 V power supply
20th January
IDeTIC Seminar
32

INDEX
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
SUMMARY
400 MSPS internal clock speed Integrated 14-bit DAC Programmable phase/amplitude dithering 32-bit frequency tuning accuracy 14-bit phase tuning accuracy Excellent dynamic performance >80 dB narrowband SFDR
Phase noise better than 120 dBc/Hz Serial I/O control Ultrahigh speed analog comparator Automatic linear & nonlinear freq sweeping 4 frequency/phase offset profiles 1.8 V power supply
AD9954 datasheet
20th January
Freq. resolution = 400MHz/2^32 = 0,093Hz Phase resolution = 360/2^14 = 0,02

IDeTIC Seminar
33

INDEX
AD9833 Evaluation Board (Simple board)
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
SUMMARY
20th January
IDeTIC Seminar
34

INDEX
AD9959 Evaluation Board (Complex board)
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
SUMMARY
20th January
IDeTIC Seminar
35
Practical Application of Direct Digital Synthesis (DDS) DDS IN RADIO SUBSYSTEM

INDEX
Broadband Transceiver oscillator board (v0)
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
SUMMARY
20th January
IDeTIC Seminar
36

INDEX
Comparison: frequency output purity 400MHz Clock vs Agilent Generator
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
SUMMARY
20th January
IDeTIC Seminar
37

INDEX
Comparison: frequency output purity 400MHz Clock vs Agilent Generator
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
SUMMARY
20th January
IDeTIC Seminar
38

INDEX
Broadband receiver block diagram

Antenna
3-30 MHz
ADC
Band Pass Filters 3-30MHz RF Amp Image-rejection Filter 3-30MHz BW = 1.0 MHz 112 MHz 20 dB BW 1 MHz 10.7 MHz 75 dB Low Pass 10.7 MHz
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
82-109 MHz DDS 122.7 MHz Controller CARDS12 AGC

RS232
SUMMARY
Problem: 112MHz (F.I.1) & 10.7MHz (F.I.2) spurs Solution: Narrow filtering
20th January
IDeTIC Seminar
39

INDEX
Broadband Transceiver oscillator board (v1) (Manolo version)
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
SUMMARY
20th January
IDeTIC Seminar
40

INDEX
Comparison: oscillator board v0 (green) vs v1 (blue)
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
SUMMARY
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IDeTIC Seminar
41

INDEX
SDR (Radio Definida por Software)
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
- It moves F.I. (12KHz) inside soundcard bandwidth (96KHz) to avoid spurs - Changes DDS oscillator freq.
SUMMARY
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IDeTIC Seminar
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Practical Application of Direct Digital Synthesis (DDS) SUMMARY

INDEX
Remember:
INTRODUCTION
DDS THEORY
EXAMPLE: AD9954
DDS can be used to obtain a variety of precision waveforms Compared to other frequency generating techniques, a DDS has many advantages. DDS has well known error characteristics Spurious frequency components in the output signal (bad) Bandwidth of the output signal (bad) Output spectrum purity/quality depends largely on reference clock quality
SUMMARY
Future Trends
Higher clock speeds (digital technology also DAC conversion speed) Lower spur levels
20th January
IDeTIC Seminar
43
Seminar in
Practical Application of Direct Digital Synthesis (DDS) Thanks for your attention!! Any question?
En espa, plis!!
Speaker: Baltasar Prez-Daz <bperez@idetic.eu>

www.idetic.eu
Seminar in
Practical Application of Direct Digital Synthesis (DDS) Thanks for your attention!! Any question?
En espa, plis!!
Speaker: Baltasar Prez-Daz <bperez@idetic.eu>

www.idetic.eu

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Seminar in

Practical Application of Direct Digital Synthesis (DDS)

Speaker: Baltasar Prez Daz <bperez@idetic.eu>

Practical Application of Direct Digital Synthesis (DDS) BACKGROUND INFORMATION

Broadband digital HF transceiver

1KW Power amplifier Driver

Wattmeter Broadband Transceiver

Practical Application of Direct Digital Synthesis (DDS) BACKGROUND INFORMATION

Practical Application of Direct Digital Synthesis (DDS) PRESENTATION INDEX

a. Block diagram, spurs, topologies

DDS IN RADIO SUBSYSTEM

DDS in radio subsystems

Practical Application of Direct Digital Synthesis (DDS) DDS THEORY

DDS IN RADIO SUBSYSTEM

Practical Application of Direct Digital Synthesis (DDS) DDS THEORY

Typical DDS Architecture

DDS IN RADIO SUBSYSTEM

Practical Application of Direct Digital Synthesis (DDS) DDS THEORY

Phase Accumulator as a digital phase wheel

DDS IN RADIO SUBSYSTEM

Practical Application of Direct Digital Synthesis (DDS) DDS THEORY

Digital to Analog Converter Output

DDS IN RADIO SUBSYSTEM

Practical Application of Direct Digital Synthesis (DDS) DDS THEORY

Digital to Analog Converter Output

DDS IN RADIO SUBSYSTEM

Practical Application of Direct Digital Synthesis (DDS) DDS THEORY

DDS IN RADIO SUBSYSTEM

Practical Application of Direct Digital Synthesis (DDS) DDS THEORY

DDS IN RADIO SUBSYSTEM

Practical Application of Direct Digital Synthesis (DDS) DDS THEORY

Not only waveforms generator, also modulations

DDS IN RADIO SUBSYSTEM

Practical Application of Direct Digital Synthesis (DDS) DDS THEORY

Not only waveforms generator, also modulations

DDS IN RADIO SUBSYSTEM

BPSK (2 phases) and QPSK (4 phases)

IQ generator capability AD9958 (2 DDS cores) AD9959 (4 DDS cores) (beamforming)

Practical Application of Direct Digital Synthesis (DDS) DDS THEORY

Worst problem in DDS

DDS IN RADIO SUBSYSTEM

AD9835 (fclk=50MHz) Spurs situation and quantity depend on output frequency

Practical Application of Direct Digital Synthesis (DDS) DDS THEORY

Worst problem in DDS

DDS IN RADIO SUBSYSTEM

AD9835 (fclk=50MHz) Spurs situation and quantity depend on output frequency

Practical Application of Direct Digital Synthesis (DDS) DDS THEORY

DDS IN RADIO SUBSYSTEM

A DDS have four principal sources of spurs

Practical Application of Direct Digital Synthesis (DDS) DDS THEORY

Spurs sources: Reference Clock

DDS IN RADIO SUBSYSTEM

Figure: 300MHz clock down to 80MHz and 5MHz

Practical Application of Direct Digital Synthesis (DDS) DDS THEORY

Spurs sources: Reference Clock

DDS IN RADIO SUBSYSTEM

Practical Application of Direct Digital Synthesis (DDS) DDS THEORY

DDS IN RADIO SUBSYSTEM

Practical Application of Direct Digital Synthesis (DDS) DDS THEORY

Spurs sources: Phase truncation

Spurs level= -6.02P P (phase truncated word)

DDS IN RADIO SUBSYSTEM