February 2013
Outline
GSPS ADC Portfolio Overview and Architecture Applications Operating Modes and Features RF vs Non-RF 12-bit GSPS ADCs Key Performance Metrics Tools Overview Common Questions
ADC12D2000/1800/1600/1000/800/500RF
RF Sampling ADCs w/ Industrys Largest Nyquist Zone
Configurable: 4.0/3.6/3.2/2.0/1.6/1.0 GSPS interleaved 2.0/1.8/1.6/1/0.8/0.5 GSPS dual ADC Excellent performance beyond 2.7 GHz Excellent performance beyond 11th Nyquist zone Noise floor: -154/-155/-154.6/-154/-152.2/-150.5dBm/Hz IMD3@2.7GHz: -65/-64/-70/-69/-71/-69 dBc Power: 4.6/4.4/4.0/3.5/2.5/2.0W AutoSync feature for multi-ADC applications* Pin-compatible w/ ADC12D1x00 & ADC10D1x00 RF-Sampling capability replaces entire IF- and ZIF-sampling subsystems of mixers, LO synthesizers, filters, amplifiers, and ADCs Industrys widest Nyquist zone of 2 GHz enables wideband software-defined radio (SDR) and allows combining multiple channels into one Reduction in board area, cost, and complexity Pin-compatible family allows range of resolution and speed-grade end-products
3G/4G basestation receive & DPD Microwave backhaul RF-Sampling, wideband SDR T&M (scopes, data acquisition, analyzers) EVM: ADC12D2000RFRB, ADC12D1800RFRB, ADC12D1600RFRB, ADC12D800RFRB
Key features: Dual channels or single, interleaved channel Internally terminated, buffered input impedance Option for output 1:2 demultiplexing 2x interleave per channel Exception is ADC12D800/500RF: 1x interleave per channel
Pipelined architecture
Often used for highspeed, medium-accuracy ADCs Theory of operation:
Determine MSB Subtract from Vin Amplify and determine LSB
Diagram is from Analog Integrated Circuit Design by Johns and Martin, 1997; Circuit Techniques for Low-voltage and High-speed A/D Converters by Waltari and Halonen, 2002.
Flash-based architectures
Basic Flash Architecture
Can achieve high sampling rates with low conversion latency Basic design requires 2N comparators and latches Drawbacks are high power consumption, die area
What techniques can make a 12-bit 3.6 GSPS ADC practically realizable?
Folding and interpolating to improve power consumption, reduce area Folding-Interpolating Architecture
Diagrams are from Analog Integrated Circuit Design by Johns and Martin, 1997; Circuit Techniques for Low-voltage and High-speed A/D Converters by Waltari and Halonen, 2002.
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Additional techniques:
Calibration Interleaving Error Correction Only one bank is shown, i.e. no interleaving in this diagram
For more details on the GSPS ADC architecture, see A 1.8V 1.0Gsps 10b Self-Calibrating Unified-Folding-Interpolating ADC with 9.1 ENOB at Nyquist Frequency by R. Taft, et al. ISSCC 2009 / Session 4 / High-speed Data Converters.
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Applications
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Applications
Radar
uWave Backhaul
Game Systems
FTTH
Test equipment
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Wireless Basestations
Replaces IF-Sampling
DSP
DSP
RF ADC
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Effective Differential Input Impedance 100 Ohms 100 Ohms 100 Ohms 50 Ohms 50 Ohms DCLK Frequency Fclk/2 Fclk/4
Output Mode
Non-Demux 1:2 Demux
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Control Modes
Feature Control Mode Extended Control Mode DDR Clock Phase Power Down AC/DC Coupled Input Dual Channel / Interleaved Initiate Calibration Full Scale Range Offset LVDS Output Amplitude LVDS Output Common Mode 1:2 Demux/Non-Demux Yes Yes No Yes Yes 15 bits 12 bits + sign 1 bit No No Non-ECM (pin controlled) DDRPh PDI, PDQ Via Vcmo No CAL FSR (High/Low) No No Via Vbg NDM
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Time Stamp
What does this feature do? Time Stamp captures another input signal than the analog input and converts it with the same total latency as the analog input signal. When Time Stamp is enabled, the DCLK_RST+/- inputs are commandeered as the Time Stamp input and the converted signal appears at the LSB of the ADC. Time Stamp is useful for applications which need to capture a trigger signal relative to the analog input signal.
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Saves startup time after system deployment, e.g. ADC12D1000RF: tCAL = 5.2 * 107 Sampling Clock Cycles = 52ms tREAD/WRITE = 240 SPI Write Cycles = 0.35ms Return to precisely same calibration vector, e.g. Rin.
When may this feature be used?
If the expected operating conditions, i.e. FSR, Temperature, DES/Non-DES Mode, Sampling Clock, are constant and result in a static calibration vector.
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AutoSync
What does this feature do? How does AutoSync function? Synchronize multiple ADCs in a system.
1. 2. 3. Align Sampling Clock to each ADC to align DCLK edge. Configure ADCs into Master or Slave. Reference Clock (RCLK) to each ADC aligns DCLK phase.
RCLK generated by ADCs and configured in closed loop. AutoSync runs continuously and any errors can propagate out.
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Available Products
Non-RF 12-bit ADCs RF 12-bit ADCs ADC12D500RF ADC12D800RF ADC12D1000 ADC12D1600 ADC12D1800 ADC12D1000RF ADC12D1600RF ADC12D1800RF ADC12D2000RF Decoder Ring: ADC ADC
12 Number of Bits
D Dual channel
RF Special tag
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Major Enhancements
ADC12Dxx00RF versus ADC12D1x00
Fewer interleaving spurs (ADC12D500/800RF only) New DES mode Noise improvement Linearity improvement
OutI OutQ
Non-DES Spurs & Images Fixed spurs at fS/2 Images around fs/2
DES Spurs & Images Fixed spurs at fS/2, fS/4 Images around fs/2, fS/4
OutI OutQ
ADC12D500RF/800RF
Non-DES
ADC1xD1x00 modes
NEW DESCLKIQ
Noise density
RF parts improve noise floor 1-2 dB versus previous 12-bit GSPS ADCs
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Product
NPR
ADC12D500RF ADC12D800RF
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Tools Overview
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Older reference boards may also include CD with software and reference documents
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Root Cause
The driver failed to install properly
Solution
Watch the Getting Started video Use a band-pass filter after the Signal Generator Turn Signal Generator OFF or remove cable when using INT CLK
The ADC output shows The Signal Generator very large harmonic tones outputs harmonic tones, which the ADC converts Performance issues when Insufficient isolation in switching between relay on RB to entirely INT/EXT Clock block EXT Clock
See the 10-minute video Getting Started with the GSPS ADC Reference Board online in the product folder for help with installing WaveVision5 software, board drivers, test bench setup, and product evaluation.
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Common Questions
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AC-coupled
Max current limit Power limit (dBm)
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Questions?