GPIO Pins
2 GPIO ports
Digital I/O
Ideally the input values to the pins would be exactly 0V or 3.3V In reality there is a low value range, a high value range, and an uncertain range in between
Single variable name corresponds to an entire register Cumbersome to anything other than write an entire register at once
Structure consists of a collection of related member variables of different data types grouped in consecutive memory locations
PeripheralName.RegisterName.all
PeripheralName.RegisterName.half.LSW PeripheralName.RegisterName.half.MSW PeripheralName.RegisterName.bit.FieldName
Example:
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 00
Example:
GpioDataRegs.GPADAT.bit.GPIO7=1
7
EALLOW Protection
EALLOW stands for Emulation Allow Code access to protected registers allowed only when EALLOW = 1 in the ST1 register
EALLOW sets the bit (register access enabled) EDIS clears the bit (register access disabled) EALLOW;
GpioCtrlRegs.GPBMUX1.bit.GPIO40 = ??
GpioCtrlRegs.GPBDIR.bit.GPIO40 = ?? EDIS;
8
Multiplexers (Mux)
Multiplexing
GPAMUX1 for GPIO0 to GPIO15 GPAMUX2 for GPIO16 to GPIO31 GPBMUX1 for GPIO32 to GPIO44
Peripheral 1 GPIO Peripheral 2 Peripheral 3
10 11 00
01
GPxMUX1 GPxMUX2
Pin
11
Multiplexing
Selecting Direction
PB
Output Configuration
Input Configuration
If the push-button is depressed, the GPIO is connected to ground and reads 0 (active low) If the push-button is untouched, the GPIO is connected to Vdd and reads 1
13
Selecting Direction
14
GPIO Read
Use data register for reading from pins: one data register for each port GPxDAT
Each bit in data register reflects the state of corresponding pin irrespective of pin configuration.
15
GPIO Write
Output latch is used as a buffer. Value of 1 is latched If the pin has already been defined as output:
It is driven high
Using the data registers to write to the pins may cause unexpected problems
16
The GPxDAT registers reflect the state of the pins (actual pin values), not the latches There is a lag between when the register is written to and when the new value is actually reflected back into the register This lag can lead to problems when two consecutive statements write to the same GPxDAT register
GpioDataRegs.GPBDAT.bit.GPIO40 = 1; GpioDataRegs.GPBDAT.bit.GPIO41 = 1;
17
Latches 0 0 0 0 0 1 0 0 0
Pins 0 0 0
Before the 1st instruction causes the new value (01) to be written
from the latch to the pin, the 2nd instruction will read the register (actual pin values) into the latch
This will override the 01 in the latch with 00 (the original pin values)
The 2nd instruction will modify the latch values from: 00 to 10 The value 10 will then be written from the latch onto the pins The final pin values will be 10 instead of the 11 we would have expected
1 1
0 0
0 1
18
0 0
GPIO Write
GPxSET
GpioDataRegs.GPASET.bit.GPIO7=1
Writing a 1 forces the corresponding GPIO pin latch high (to digital 1)
GPxCLEAR
GpioDataRegs.GPACLEAR.bit.GPIO7=1
Writing a 1 forces the corresponding GPIO pin latch low (to digital 0)
GPxTOGGLE
GpioDataRegs.GPATOGGLE.bit.GPIO7=1
Writes of 0 to these registers are ignored These registers always read back 0
19
Input Qualification
The
20
Input Qualification
21
Input Qualification
Sampling period is fixed in GPxCTRL (16 bits for 8 pins). Number of samples selected using GPxQSEL1 and GPxQSEL2.
22
2 bits allotted per GPIO pin 00 synchronize to SYSCLKOUT only (Default at reset) 01 qualify using 3 samples (sampling window of 2 qual periods)
If QUALPRD# = 0 If QUALPRD# 0
25
GPxQSEL1/2 = 10
6 sample qualification
GPxCTRL[QUALPRDn] = 1
tw(IQSW) = 5 2 TSYSCLKOUT
For the F2803x, TSYSCLKOUT = 16.67 ns, and the duration of the sampling window is:
To account for the asynchronous nature of the input relative to the sampling period and SYSCLKOUT, up to an additional sampling period may be required to detect a change in the input signal
27
28