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coding format. This format has fields for specifying of up to three registers and a shift amount. For instructions that do not use all of these fields, the unused fields are coded with all 0 bits. All R-type instructions use a 000000 opcode. The operation is specified by the function field. opcode (6) rs (5) rt (5) rd (5) sa (5) function (6)
Alf Instruction Function Opcd Funct Description add rd, rs, rt 100000 0x00 0x20 Add (with overflow) addu and rd, rs, rt 100001 rd, rs, rt 100100 001101 011010 011011 001001 001000 010000 010010 010001 010011 011000 011001 100111 100101 000000 000100 101010 101011 000011 000111 0x00 0x21 0x00 0x24
Numeric Instruction Function Funct Hex sll rd, rt, sa 000000 0x00 srl sra sllv srlv srav rd, rt, sa 000010 rd, rt, sa 000011 rd, rt, rs 000100 rd, rt, rs 000110 rd, rt, rs 000111 001000 001001 001100 001101 010000 010001 010010 010011 011000 011001 011010 011011 100000 100001 100010 100011 0x02 0x03 0x04 0x06 0x07 0x08 0x09 0x0C 0x0D 0x10 0x11 0x12 0x13 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23 0x24 0x25 0x26
break div rs, rt divu rs, rt jalr jr mfhi mflo mthi mtlo mult multu nor or sll sllv slt sltu sra srav srl srlv sub subu syscall xor rd, rs rs rd rd rs rs rs, rt rs, rt rd, rs, rt rd, rs, rt rd, rt, sa rd, rt, rs rd, rs, rt rd, rs, rt rd, rt, sa rd, rt, rs rd, rd, rd, rd,
0x00 0x0D Break (for debugging) 0x00 0x1A Divide 0x00 0x1B Divide unsigned 0x00 0x09 0x00 0x08 0x00 0x10 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x12 0x11 0x13 0x18 0x19 0x27 0x25 0x00 0x04 0x2A 0x2B 0x03 0x07 Jump and link Jump register Move from HI Move from LO Move to HI Move to LO Multiply Multiply unsigned Bitwise nor Bitwise or Shift left logical Shift left logical variable Set on less than (signed) Set on less than unsigned Shift right arithmetic Shift right arithmetic variable Shift right logical Shift right logical variable Subtract
jr rs jalr rd, rs syscall break mfhi mthi mflo mtlo mult multu div divu add addu sub subu and or xor nor slt sltu rd rs rd rs rs, rt rs, rt rs, rt rs, rt rd, rs, rt rd, rs, rt rd, rs, rt rd, rs, rt
rd, rs, rt. 100100 rd, rs, rt 100101 rd, rs, rt 100110 rd, rs, rt rd, rs, rt rd, rs, rt
0x00 0x23 Subtract unsigned 0x00 0x0C System call 0x00 0x26 Bitwise exclusive or
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For the bgez , bgtz , blez , and bltz instructions, the rt field is used as an extension of the opcode field. opcode (6) Alf Instruction rs (5) Opcode Notes rt (5) Opcd Description immediate (16) Numeric Instruction Opcode Notes Opcd
addi rt, rs, immediate 001000 addiu rt, rs, immediate 001001
0x08 Add immediate (with overflow) bltz rs, label 0x09 Add immediate unsigned (no overflow) bgez rs, label rs, rt, label rs, rt, label rs, label
000001 rt=00000 0x01 000001 rt=00001 0x01 000100 0x04 000101 0x05 000110 rt=00000 0x06
andi rt, rs, immediate 001100 0x0C Bitwise and immediate beq beq rs, rt, label 000100 0x04 Branch on equal bne bgez rs, label 000001 rt=00001 0x01 Branch on greater than or equal to zero blez bgtz rs, label blez rs, label bltz rs, label bne lb lbu lh lhu lui lw lwc1 ori sb slti sltiu sh sw swc1 xori 000111 rt=00000 0x07 Branch on greater than zero 000110 rt=00000 0x06 Branch on less than or equal to zero 000001 rt=00000 0x01 Branch on less than zero 0x05 Branch on not equal 0x20 Load byte 0x24 Load byte unsigned 0x21 Load halfword 0x25 Load halfword unsigned 0x0F Load upper immediate 0x23 Load word 0x31 Load word coprocessor 1 0x0D Bitwise or immediate 0x28 Store byte
bgtz rs, label 000111 rt=00000 0x07 addi rt, rs, immediate 001000 0x08 addiu rt, rs, immediate 001001 0x09 slti rt, rs, immediate 001010 sltiu rt, rs, immediate 001011 andi rt, rs, immediate 001100 ori rt, rs, immediate 001101 xori rt, rs, immediate 001110 lui rt, immediate 001111 lb rt, immediate(rs) 100000 lh rt, immediate(rs) 100001 lw rt, immediate(rs) 100011 rt, immediate(rs) 100100 rt, immediate(rs) 100101 rt, immediate(rs) 101000 rt, immediate(rs) 101001 rt, immediate(rs) 101011 rt, immediate(rs) 110001 rt, immediate(rs) 111001 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x20 0x21 0x23 0x24 0x25 0x28 0x29 0x2B 0x31 0x39
rs, rt, label 000101 rt, immediate(rs) 100000 rt, immediate(rs) 100100 rt, immediate(rs) 100001 rt, immediate(rs) 100101 rt, immediate 001111 rt, immediate(rs) 100011 rt, immediate(rs) 110001 rt, rs, immediate 001101 rt, immediate(rs) 101000 rt, rt, rt, rt, rt, rt, rs, immediate 001010 rs, immediate 001011 immediate(rs) 101001 immediate(rs) 101011 immediate(rs) 111001 rs, immediate 001110
lbu 0x09 Set on less than immediate (signed) lhu 0x0B Set on less than immediate unsigned sb 0x29 Store halfword sh 0x2B Store word sw 0x39 Store word coprocessor 1 lwc1 0x0E Bitwise exclusive or immediate swc1
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Instruction Opcode Target Opcd Description j label 000010 coded address of label 0x02 Jump jal label 000011 coded address of label 0x03 Jump and link
Alf Instruction Opcode Format Funct add.s fd, fs, ft 010001 10000 000000 cvt.s.w fd, fs 010001 10100 100000 cvt.w.s fd, fs 010001 10000 100100 div.s fd, fs, ft 010001 10000 000011 mfc1 rd, fs 010001 00000 000000 mov.s fd, fs 010001 10000 000110 mtc1 rs, fd 010001 00100 000000 mul.s fd, fs, ft 010001 10000 000010 sub.s
Opc Form Func 0x11 0x10 0x00 0x11 0x14 0x20 0x11 0x10 0x24 0x11 0x10 0x03 0x11 0x00 0x00 0x11 0x10 0x06 0x11 0x04 0x00 0x11 0x10 0x02
Description Numeric Instruction Function Funct Hex FP add single Convert to single precision FP from integer Convert to integer from single precision FP FP divide single move from coprocessor 1 (FP) move FP single precision FP move to coprocessor 1 (FP) FP multiply single
fd, fs, ft 010001 10000 000001 0x11 0x10 0x01 FP subtract single
Page URL: http://www.cs.sunysb.edu/~lw/spim/MIPSinstHex.pdf from http://www.d.umn.edu/~gshute/spimsal/talref.html Page Author: extensions by Larry Wittie from original no-hex instruction lists by Gary Shute Last Modified: Saturday, 18-Sep-2010 from original of Tuesday, 26-Jun-2007 12:33:40 CDT Comments to: lw AT ic DOT sunysb DOT edu (Original instruction list author was gshute@d.umn.edu)
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