SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

8.1 Introduction
The presence of high voltage power electronic equipment in the transmission system has important consequences on the stability of the power system. However, the conventional multi-machine stability assessment described in the last chapter is inadequate to represent the transient behaviour of some power electronic devices. This problem is particularly important in the case of HVDC converters due to the occurrence of inverter commutation failures that often follow a large disturbance. Only the use of electromagnetic transient programs, described in Chapter 6, can provide accurate information of the power electronic response during and immediately following clearance of the disturbance. Although machine rotor dynamics, as discussed in Chapter 7, could be included in the electromagnetic transient program of Chapter 6 , this is not a practical proposition in the presence of power electronic switching, considering the different time constants involved. For instance, electromagnetic-transient simulations require steps of (typically) 50 ps, whereas the stability programs use steps at least 200 times larger. To reduce the computational requirements, some programs [ 11 contain two separate modes. An instantaneous mode is used to model components in three-phase detail with small time steps in a similar way to the EMTPEMTDC programs [2]. The alternative is a stability mode based on r.m.s. quantities at fundamental frequency only, with increased time-step lengths. The user can switch between the two modes as required while running but, in either mode, the entire system must be modelled in the same way. Thus, when using the instantaneous mode, a system of any substantial size would still be very computationally intensive. A more efficient solution is described here [3,4] which takes advantage of the computationally inexpensive dynamic representation of the a.c. system in the stability program, and the accurate transient simulation of the power electronic devices. The slow dynamics of the a.c. system are adequately modelled by the stability program while the fast dynamic responses of the HVDC and FACTS devices are accurately represented by electromagnetic transient simulation. This hybrid combination is essential to predict the first few swings in stability studies.

298

8 SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

Finally, quasi steady-state models of the power electronic devices are also developed in this chapter for use in longer stability studies as well as system response to small perturbations.

8.2 Description of the Algorithm

Transient stability (TS) studies are normally carried out on the assumptions of balanced and sinusoidal waveforms and such assumptions need to be extended to the voltage and current waveforms at the terminals of the power electronic devices. As explained in the introduction, part of the study requires detailed transient simulation, the results of which cannot be directly incorporated in a TS study. It is therefore necessary to extract fundamental frequency quantities for the TS study from the voltage and current waveforms produced by the electromagnetic transient program (which in this book is the PSCADEMTDC version). The hybrid concept, referred to as TSE and illustrated in Figure 8.1, uses electromechanical simulation as the steering program, and the electromagnetic transient program is called as a subroutine. The interfacing code is written in separate routines to minimize the number of modifications and thus make it easily applicable to any stability and dynamic-simulation programs. Initially, the TSE hybrid reads in the data files and runs the entire network in the stability program, until electromechanical steady state equilibrium is reached. The steady-state representation of the converter, described in Chapter 3, is perfectly adequate as no fault or disturbance has yet been applied. Before placing the network disturbance, the TS network is split into two independent and isolated systems, system 1 and system 2, as shown in Figure 8.2. System 1 contains the a s . part of the system modelled by the stability program TS, and system 2 the part of the system modelled in detail by EMTDC. The snapshot data file is now used to initialize the EMTDC program used, instead of the TS representation of system 2. The two programs are then interfaced and the network disturbance can be applied. The system 2 representation in TS is isolated but kept up to date during the interfacing at each TS time step to allow tracking between programs. The a.c. network of system 1 modelled in the stability program also supplies interface data to the system 2 network in TS, as shown in the lower part of Figure 8.2. During the disturbance, the quasi steady-state representation of system 2 in TS and the EMTDC representation of system 2 are tracked. When both of these system 2

Conventional Stability Analysis

7 -

transient simulation of power electronic

Figure 8.1 The hybrid concept

8.2 DESCRIPTION OF THE ALGORITHM

Stability program ENTDC program

299

Figure 8.2 Interfacing procedure

detailed

sequence data for whole

Loadflow

Stability input

TSlEMTDC hybrid

Outflow

c-y
Interface

Figure 8.3 Data flow

models produce the same results within a predefined tolerance and over a set period, the complete system can then be reconnected and used by TS,and the EMTDC representation terminated. This allows better computational efficiency, particularly for long simulation runs.

8.2.1

Data flow

Data for the EMTDC solution entered in the programme database via the PSCAD graphics. Equivalent circuits are used at each interface point to represent the rest of the system not included in the detailed model. This system is then run until steady

300

8 SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

state is reached and a snapshot is taken. This snapshot holds all the relevant data for the various system components and is used as the starting point when interfacing the detailed model with the stability programme. The stability program is initialized conventionally through power-flow results via a data file. An interface data file is also read by the TSE hybrid that provides the number and location of interface buses, analysis options, and timing information. The data flow diagram is shown in Figure 8.3.

8.2.2 Modifications required to the component programs

The main modification of the TS program is a call of the interfacing routine in the main loop, as shown in Figure 8.4. The complete network is split into system 1 and system 2 at the interface points, but this task is performed using separate code. The only other direct modification inside TS is the inclusion of the interface current injections at each TS network solution. To enable EMTDC to be called as a subroutine from TS requires a few changes to its structure. This is helped by splitting EMTDC into three distinct segments, i.e. an initializing segment, the main time loop, and a termination segment. In this way, TS can call the main time loop for discrete periods as required when interfacing. The EMTDC options, which are normally available at the beginning of a simulation run, are moved to the interface data file and read from there. The equivalent-circuit source values, which TS updates periodically, are located in the user-accessible DSDYN file of the EMTDC (described in Chapter 6).

8.3 TS/EMTDC Interface

The hybrid algorithm involves regular exchanges of information between the transient stability and electromagnetic transient programs. The information to be transferred from one program to the other must be sufficient to determine the power flow in or out of the interface. As shown in Figure 8.5, possible parameters to be used are the real power, P, the reactive power, Q, the voltage, V, and the current, I, at the interface. Phase-angle information is also required to be able to use separate phase frames of reference. Appropriate equivalent circuits are needed to represent the network modelled in the stability program when running the EMTDC and vice versa. These are illustrated in represent the equivalent circuit of system 1 and 7 , and Figure 8.6, where E, and z 2 the equivalent circuit of system 2.

8.3.1 Equivalent circuit components

In Figure 8.6, f, and z 2 represent the detailed part of the system modelled by EMTDC to be used by the TS program since TS is only using the fundamental active power flowing in or out of the interface, the equivalent impedance 2 2 can be selected arbitrarily and the current source 7 , can be varied to provide the correct power flow. Moreover, to avoid numerical instability, a constant value of z2, estimated from the initial power flow results, is used for the duration of the simulation.

8.3 TS5MTDC INTERFACE

301

Yes

Pass information to detailed model

i
Solve EMTDC Extract information from detailed solution and include in stability programme Solve stability equations
T = T + step length

1 1 I

c=
Output results Is T = end time?

Figure 8.4 Modified TS steering routine

No

The EMTDC programme represents system 1 by a Thevenin equivalent (El and as shown in Figure 8.6. The simplest ZI is an R-L series impedance, representing the fundamental frequency equivalent of system 1. This impedance can be derived from the results of a power flow and a fault analysis at the interface bus. The power flow 'provides an initial current through the interface bus and the initial interface bus. A fault analysis is also used to determine the fault current through the

zl)

302

8 SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

f
Figure 8.5 Hybrid interface

System 1

I,

System 2

Figure 8.6 Equivalent circuits at the interface

interface for a short circuit fault to ground. The equivalent Thevenin source Thevenin impedance ZI values shown in Figure 8.7, are obtained as follows: Using the power flow solution:

El and

El = inZl + V ,
and using the fault circuit:

El = I F Z ~ .

Combining Equations (8.1) and (8.2):

can then be found from either Equation (8.1) or Equation (8.2). and During a transient, the impedance of the synchronous machines in system 1 will change. The net effect on the fundamental power in or out of the equivalent circuit, however, can be represented by varying the source and keeping ZI constant.

8.3 TS/EMTDC INTERFACE

303

(a) Loadflow circuit

(b) Fault circuit

Figure 8.7

Derivation of Thevenin equivalent circuit (a) Power-flow circuit. (b) Fault circuit

However, the waveforms obtained from EMTDC involve frequencies other than the fundamental and, therefore, a frequency-dependent equivalent circuit (as described in section 6.4.3)is used to represent the a.c. system. Regarding the equivalent circuits sources, information from the EMTDC model representing system 2 (in Figure 8.6) is used to modify the source of the equivalent circuit of system 2 in the stability programme. Similarly, data from TS are used to modify the source of the equivalent circuit of system 1 in EMTDC. These equiva. 5 ) . From lent sources are normally updated at each TS step length (refer to section 8 Figure 8.6,if both ZI and 2 2 are known, additional information is still necessary to determine update values for the sources 7 , and El. The selection and processing of interface parameters to derive this information is discussed in section 8.4. Moreover, the stability programme requires only positive sequence data so data from the three a.c. phases at the interface(s) is analysed and converted to positive sequence, i.e. for the positive sequence voltage:

v,,

p, + ZVb + Z*V,),
= 1L 120").

(8.4)

where
V,,

V,, = positive sequence voltage,

- - V b , V,

= phase voltage,

Z = 120"forward rotation vector(i.e.a

304

8 SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

Similarly, the positive sequence voltage from TS is converted to three phase data as follows:

Va

= Vps,

(8.5)

Some transient stability programmes have the additional capability of modelling negative and zero sequence networks. If this option is utilized, sequence data from a stability programme can then be converted to three phase through the following formulae:

Va
v b

= Vps

where

+ Vns + Vzs, = a 2 v p s + z v n s + v,,,

-

(8.8)
(8.9)
(8.10)

v, = zvps+ ans + V,,,

Vns = negative sequence voltage, V, = zero sequence voltage.

Similarly, any unbalance in system 2 can be accommodated in the transient stability programme.

8.3.2 Interface variables derivation

As already explained, in Figure 8.6, El and ZI represent the equivalent circuit of system 1 modelled in EMTDC, while 2 2 and 7 , represent the equivalent circuit of system 2 modelled in the stability program. is the interface voltage and 71 the current through the interface which is assumed in the direction shown. The magnitudes of the interface voltage and current, along with the phase angle between them, are derived from the detailed EMTDC simulation. This information is used to update the equivalent circuit source (TC) of system 2 in TS, i.e.: From Figure 8.6:

El = TiZ1

+V ,

(8.11) (8.12) (8.13)

v = i2Z2,

i 2 = i,

+ 7,.

From Equations (8.12) and (8.13):

From Equation (8.1 1):

v =z1z2 + icZ2.

(8.14)

E~ = IIzIL(eII

+ ezl)+ w e V
sin(&

=I121cos(6Il + & l ) + j l l Z l

+ & I ) +Vcos6v+ jVsin6v

(8.15)

8.3 TSEMTDC INTERFACE

305

and
6 1 1 = ev - 9,

(8.16)

where rb is the displacement angle between the voltage and the current. Thus, Equation (8.15) can be written as

EI = IlZl cos(8v

+ B ) + jIlZ1 sin(& + B ) + VcosBv + j v s i n b

(8.17)

=IIZl(cos8vcosB-sinevsinB)+ vcosev

+~ [ I I Z (sin I Ov cos /? + cosev sin /?)+ V sin ev],

where

B = ezI- 9.
If then equating the real terms:

Ei = E l , + j E l i ,
E l , = (7,Zl cosB+ V)cos6v

+ (-1121sinB)sin&,

(8.18)

is known and constant throughout the simulation. where From the EMTDC results, the values of V , I and 4 are also known and, hence, so is j3. El can be determined in the TS phase reference frame from knowledge of and the previous values of interface current and voltage from TS, through the use of Equation (8.1 1). From Equation (8.18), making
A = IlZi
C O S ~

zl

zI

+ V,

(8.19) (8.20)

B =-IIZ~ sin B,
and remembering that
A cos ev

+ B sin ev = J F T 3 c o s ( e v

*),

(8.21)

where

the voltage angle Bv in the TS phase reference frame can be calculated, i.e.:

(+= tan-'
v
22

)I:[

(8.23)

The equivalent current source 7 , can be calculated by rearranging Equation (8.14):

I, = -L(ev - eZ2) -

Lerl,

(8.24)

where 811 is obtained from Equation (8.16).

306

8 SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

In a similar way, data from the transient stability programme simulation can be used to calculate a new Thevenin source voltage magnitude for the equivalent circuit of system 1 in the EMTDC programme. Knowing the voltage and current magnitude at the TS programme interface and the phase difference between them, by a similar analysis the voltage angle in the EMTDC phase reference frame is:

, and where I,, is the real part of 7

V c = -cosez2
2 2

-I,

COS~,

(8.26) (8.27) (8.28)

D = - cosO~2 - I ' sin@,

22

4 = ev -ell,

+ = tan-'

I$[

(8.29)

Knowing the EMTDC voltage angle 8v allows calculation of the EMTDC current angle from Equation (8.28). The magnitude value of El can then be derived from Equation (8.1 1).

8.4 EMTDC to TS Data Transfer

TS assessment is based purely on sinusoidal waveforms, but during faults the actual waveforms are very distorted. However, there is no consensus on a universal definition for power when waveforms are non-sinusoidal [ 5 ] . In the original edition of the book, the total r.m.s. real power was used as the interfacing variable to transfer information. The total r.m.s. power is made up of fundamental power (Ff)and harmonic power (&), i.e.:
prms

= pf

ph.

(8.30)

The r.m.s. power can be extracted directly from the waveforms and, therefore, Fourier transform or curve fitting methods are not necessary, i.e.: (8.31) This method greatly reduces the computing time necessary for the data extraction from EMTDC. The choice of r.m.s. power was made on the basis that harmonic power flow will result only from in-phase components of harmonic voltage and current. The assumption was made that if a system contains only a low resistive component, then the harmonic power flow is not significant [6]. This, however, is not valid for every situation and, particularly, at the inverter end of an HVDC link, the effect of the resistive component of the network is not insignificant.

8.4 EMTDC TO TS DATA TRANSFER

307

Certain harmonic frequencies in a network may also be parallel resonant or close to parallel resonance and exhibit more resistance than reactance. The presence of a transient may excite the resonant frequency and greatly affect the results. It is important, therefore, to model the fundamental power flow accurately. Another factor to consider is that the direction of fundamental power may not necessarily be the same as the direction of harmonic power. With an HVDC link, while fundamental power is drawn into a rectifier, much of the harmonic power flow will be in the reverse direction. The r.m.s. real power measured is the difference between these two powers and is, therefore, not entirely representative of the fundamental power load of the HVDC link. Conversely, at the inverter end the r.m.s. real power will include harmonic power flow into the a.c. system. This may exaggerate the amount of true fundamental power from the inverter. As an illustration of the problem, Figure 8.8 shows an EMTDC simulated result of a single phase fault at the inverter end of the CIGRE HVDC benchmark model [7] The instantaneous power is shown, along with the total r.m.s. power over discrete one cycle intervals. For hybrid interfacing purposes, data is transferred at discrete intervals equal to the stability programme time-step and these are significantly larger than the interval between the discrete output points constituting the instantaneous power. The r.m.s. power is then taken over a fundamental period to represent its use in the hybrid model. Figure 8.9 shows an analysis of the single-phase fault comparing fundamental frequency power with the total r.m.s. power. The fundamental frequency power was derived using the curve fitting method described in section 8.5 to extract both fundamental voltage and current. The comparison shows that, particularly during the
Instantaneous power
lo00

-Rms power over T

800 600

F 3

400
200
0

1 a -200
-400

-600
-800
-1000
, I I I

.O

308

8 SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

1000

900 -

- 700 800

600-

z i

500400200 -

$ 300100

I
1

0-100 -200 0.00

0.04

0.08

0.12

0.16

0.20

0.24

0.28

0.32

0.36

0.40

Figure 8.9 Fundamental power versus total r.m.s. power

fault time, there exists a significant amount of Ph or harmonic r.m.s. power in the total r.m.s. power. When the three phase network is unbalanced the fundamental frequency real power consists of positive, negative and zero sequence components, i.e.: Pf = Pfps

+ Pfns + Pfzs,

(8.32)

and the negative and zero sequence powers cause additional power loss in the network. Figure 8.10 shows the sequence components of the fundamental r.m.s. power of Figure 8.9. Fundamental frequency negative sequence currents, in the presence of damper windings, can produce a braking torque which will retard the rotor [8]. Damper windings, however, also serve to lower the negative sequence impedance of a machine which in turn reduces the negative sequence voltage [9]. Which of these two opposing effects is dominant depends on the resistance of the damper windings. High resistance windings cause the braking torque to be the significant effect. The braking power of the negative sequence current is:

(8.33)

where

I, = negative sequence rotor current, R, = rotor resistance,

I,, = negative sequence stator (or armature) current,

8.4 EMTDC TO TS DATA TRANSFER

309

1000

-.

900
800

z
a

8 I

'

700 600 500

300 200 400 100 r-----d

. . , . . . r
-

0
-100 -200

- ------ ---I

Figure 8.10
rn

Sequence components of fundamental frequency r.m.s. power

= negative sequence resistance of the machine,

rp = positive sequence resistance of the machine.

The negative sequence resistance can be approximated from the rotor and the armature resistance, i.e.: (8.35) rn % ( ~ s

+i ~ r ) ,

where

R, = armature resistance.
Retardation of the rotor can also be caused by d.c. components in the armature windings. Three phase faults at or near machine terminals can cause d.c. components of short circuit armature current which can have a definite braking effect on the machine [9].The braking power in this case is:

(8.36) (8.37)
where
I , = the effective very low frequency value of the armature current,
idc

= instantaneous d.c. component of armature current.

The total r.m.s. power then is not always equivalent toeither the fundamental frequency power or the fundamental frequency positive sequence power. A comparison of these

310

8 SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

1000
900 -

800

700

600-

5 5003

g m

400300-

200

100 -

I c . . *

0-100-

7.-_ I . . .

-200 0.00

d
I
I t I

0.04

0.08

0.12

0.16

0.20

0.24

0.28

0.32

0.36

0. 0

Figure 8.11 Comparison of total r.m.s. power, fundamental frequency power and fundamental frequency positive sequence power

three powers is shown in Figure 8.11. The difference between total r.m.s. power and the positive sequence power can be seen to be highly significant during the fault. The most appropriate power to transfer from EMTDC to TS is then the fundamental frequency positive sequence power. This, however, requires knowledge of both fundamental frequency positive sequence voltage and fundamental frequency positive sequence current. These two variables contain all the relevant information and, hence, the use of any other power variable to transfer information becomes unnecessary.

8.5 Data Extraction from Distorted Waveforms

At each step of the transient stability program power transfer information needs to be derived from the distorted current and voltage waveforms at the points of interface. This can be achieved using the FFT which provides accurate information for the whole frequency spectrum. However, only the fundamental frequency is used in the stability program and a simpler curve fitting approach is described next that provides sufficient accuracy. A curve fitting algorithm (CFA) can be used to extract the fundamental frequency data, based on a least squared error technique. It can be described as follows: Assume a sinewave signal with a frequency of o radians per second and a phase shift of $ relative to some arbitrary time To.
y ( t ) = A sin(@?- $),

(8.38)

where

+=d o .

8.5

DATA EXTRACTION FROM DISTORTED WAVEFORMS

311

This can be rewritten as:

y ( t ) = A sin(wt) cos(wT0) - A cos(ot) sin(wT0).

(8.39)

Letting C1 = A cos(wTo) and C2 = A sin(wT0) and if sin(wt) and cos(ot) are represented by functions F I ( t ) and F2(t), respectively, then:
y(t> = CI FI ( t )

+ C2F2(t).

(8.40)

F l ( t ) and F 2 ( t ) are known if the fundamental frequency w is known. However, the amplitude and phase of this frequency generally need to be found, so the equation has to be solved for C I and C2. If the signal y ( t ) is distorted, then its deviation from a sinusoid can be described by an error function E :
~ ( t= ) y(t)

+E .

(8.41)

For a least squares method of curve fitting, {he size of the error function is measured by the sum of the individual residual squared values such that:

where x; = x(t0 i A t ) and yi = y(t0 From Equation (8.40):

n

i= 1

+ iAr).
(8.43)

E=

C ( x ; - ~ I ~ l ( t-i ~) 2 ~ 2 ( t i ) ) ~ ,
i= I

where the residual value r at each discrete step is defined as: In matrix form: (8.45)

or
The error component can be described in terms of the residual matrix as follows:
E = [rlT[r]

312

SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

This error then needs to be minimized.

(8.48)

If [A] = [FIT[F] and [B] = [FIT[X] then :

[CI = [ A I - m
(8.49)

and hence

Elements of matrix [A] can then be derived as shown:

n-1

(8.50)

Similarly:

and (8.5 1)
(8.52)

From these matrix element equations, CIand C2 can be calculated recursively using
sequential data.

8.6 INTERFACE METHOD

313

2oo

-5.00 0.00

0.02

0.04

0.06

0.08

0.10

0.12

0.14

0.16

0.18

0.20

Time (s)

Figure 8.12 Simulated fault waveform

8.5.1 CFA effectiveness

The accuracy of the CFA algorithm has been compared with the results of an FFT for the voltage waveform of Figure 8.12. This waveform, derived with the EMTDC program, corresponds to a single-phase fault on the rectifier side of the CIGRE benchmark model [7]. Several windows were used to capture the fundamental frequency information. Of these, a discrete rectangular window of full period duration provides the best match when data are only required at intervals of one cycle. However, if data are required at more frequent intervals, a staggered (or overlapping) window producing results twice per cycle is a better choice.

8.6 Interface Method

The data from each program must be interchanged at appropriate points during the hybrid simulation run. The timing of this data interchange between the TS and EMTDC programs is important, particularly around discontinuities caused by fault application and removal. The electromechanical a.c. system solution exhibits a relatively slow dynamic response to any disturbances and the accuracy of a previous time-step information passed from TS to EMTDC is, therefore, an adequate assumption. On the other hand, the HVDC converter exhibits fast dynamic behaviour. Present time-step information is, thus, more appropriate to pass from EMTDC to TS when solving the TS network equation. Therefore, of the different possible interfacing alternatives, the method

314

8 SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

illustrated in Figure 8.13 is selected for the information exchange. It shows the use of the previous time-step data when passing information from TS to EMTDC but present time-step data when passing information from EMTDC to TS. When the two programs are run concurrently, TS passes its information to EMTDC. EMTDC then runs to t + A t , and the information gathered over this present time-step given back to TS at time t . TS now runs to t Ar, using equivalent circuit information derived for that particular time step. However, to cater for TS step lengths below the fundamental period, the above method is modified as shown in Figure 8.14; it relates to the case when the step length is one half of the fundamental period. Following the sequential numbering on Figure 8.14, at a particular point in time, the EMTDC and TS programs are concurrent and the TS information from system 1 is passed to update the system 1 equivalent in EMTDC. This is shown by the arrow marked 1. EMTDC is then called for a length of half a fundamental period (arrow 2) and the curve fitted results over the last full fundamental period processed and passed back to update the system 2 equivalent in TS (arrow 3). The information over this period is passed back to TS at the mid-point of the EMTDC analysis window which is half a period behind the current EMTDC time. TS is then run to catch up

Figure 8.13 Interfacing methods

Stabiliity step length

-4

etc.
I

I I

1-1

TS

-2
6

4 c

II II

Dynamic program step length

Figure 8.14

Normal interaction protocol

8.7 INTERFACE LOCATION

Disturance applied
4
I

315
Stabiliity step length

*
t

I I

- /-I
8

etc.

TS

v p *
r
t

II Dynamic program step length

++

II

Figure 8.15 Interaction protocol around a disturbance

to EMTDC (arrow 4), and the new information over this simulation run used to again update the system 1 equivalent in EMTDC (arrow 5 ) . This protocol continues until any discontinuity in the network occurs. When a network change such as a fault application or removal occurs, the interaction protocol is modified to that shown in Figure 8.15. The curve fitting analysis process is also modified to avoid applying an analysis window over any point of discontinuity. The sequential numbering in Figure 8.15 explains the flow of events. At the fault time, the interface variables are passed from TS to the system 1 equivalent in EMTDC in the usual manner, as shown by the arrow marked 1. Neither system 1 nor system 2 has yet been solved with the network change. The fault is now applied in EMTDC which is then run for a full fundamental period length past the fault application (arrow 2) and the information obtained over this period passed back to TS (arrow 3). The fault is now also applied to the TS program which is then solved for a period until it has again reached EMTDCs position in time (arrow 4). The normal interaction protocol is then followed until any other discontinuity is reached. A full period analysis after the fault is applied is necessary to accurately extract the fundamental frequency component of the interface variables. The mechanically controlled nature of the a.c. system implies a dynamically slow response to any disturbance and so, for this reason, it is considered acceptable to run EMTDC for a full period without updating the system 1 equivalent circuit during this time.

8.7 Interface Location

The original intention of the initial hybrid algorithm [6] was to model the a.c. and d.c. solutions separately. The point of interface location was consequently the converter bus terminal. The detailed d.c. link model included all equipment connected to the converter bus, such as the a.c. filters, and every other a.c. component was modelled within the stability analysis. A fundamental frequency Thevenin equivalent was used to represent the stability program in the detailed solution and vice versa.

316

8 SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

An alternative approach has been proposed [ 101 where the interface location is extended out from the converter bus into the a.c. system. This approach maintains that, particularly for weak a.c. systems, a fundamental frequency equivalent representing the a s . system is not adequate at the converter terminals. In this case, the extent of the a.c. system to be included in the d.c. system depends on phase imbalance and waveform distortion. Although the above concept has some advantages, it also suffers from many disadvantages. The concept is proposed, in particular, for weak a.c. systems. A weak a.c. system, however, is likely to have any major generation capability far removed from the converter terminal bus as local generation serves to enhance system strength. However, when the generation is far away from the converter, then the distance required for an interface location to achieve considerably less phase imbalance and waveform distortion is also likely to be significant. The primary advantage of a hybrid solution is in accurately providing the d.c. dynamic response to a transient stability program, and in efficiently representing the dynamic response of a considerably sized a.c. system to the d.c. solution. Extending the interface some distance into the a.c. system, where the effects of a system disturbance are almost negligible, diminishes the hybrid advantage. If a sizeable portion of the a.c. system requires modelling in detail before an interface to a transient stability program can occur, then one might question the use of a hybrid solution at all and instead use a more conventional approach of a detailed solution with a.c. equivalent circuits at the system cut-off points. Another significant disadvantage in an extended interface is that ax. systems may well be heavily interconnected. The further into the system that an interface is moved, the greater the number of interface locations required. The hybrid interfacing complexity is thus increased and the computational efficiency of the hybrid solution decreased. The requirement for a detailed representation of a significant portion of the a.c. system serves to decrease this efficiency, as does the increased amount of processing required for variable extraction at each interface location. The advantages of using the converter bus are:
0 0 0 0

The detailed system is kept to a minimum. Interfacing complexity is low. Computational expense is minimized. Converter terminal equipment, such as filters, synchronous condensers SVCs, and can still be modelled in detail.

The major drawback of the detailed solution is in not seeing a true picture of the ax. system, since the equivalent circuit is fundamental frequency based. Waveform distortion and imbalance also make it difficult to extract the fundamental frequency information necessary to transfer to the stability program. The problem of waveform distortion for transfer of data from EMTDC to TS is dependent on the accuracy of the technique for extraction of interfacing variable information. If fundamental frequency quantities can be accurately measured under distorted conditions, then the problem is solved. Section 8.5 has described an efficient curve fitting algorithm to extract the required information from distorted waveforms. It has

8.8 STRUCTURE OF THE HYBRID PROGRAM

317

Rectifier

1 Inverter

ESCR=2.0

h + @

Figure 8.16 Test system

been shown that, using the technique described, fundamental frequency quantities can be accurately measured. Moreover, a simple fundamental frequency equivalent circuit is insufficient to represent the correct impedance of the a.c. system at each frequency. Instead, this can be achieved by using a fully frequency-dependent equivalent circuit of the a.c. system [ l 11 at the converter terminal instead of just a fundamental frequency equivalent. A frequency-dependent equivalent avoids the need for modelling any significant portion of the ax. system in detail yet still provides an accurate picture of the system impedance across its frequency spectra. To show the effect of a frequency-dependent equivalent, the test system of Figure 8.16 is used with an inverter effective short circuit ratio of 2. The d.c. link is represented by the CIGRE benchmark model [7]. A three-phase solid short circuit fault is applied at the inverter terminal. Three cases are considered, the first being the entire system represented by the detailed solution. The second and third cases relate to the hybrid solution interfaced at the converter bus, one case with a fundamental frequency Thevenin representation of the stability program in the detailed solution, and the other with a frequency-dependent equivalent. The results of the inverter terminal voltages for the three cases are plotted in Figure 8.17, and they show that the benchmark EMTDC case and the frequencydependent equivalent case are identical. The fundamental frequency equivalent case (Figure 8.17(b)) shows more distortion and prolonged effects from the disturbance than the benchmark EMTDC case. These results show the inadequacy of a fundamental frequency equivalent at the converter terminal, whereas the use of a frequency-dependent equivalent is perfectly adequate.

8.8 Structure of the Hybrid Program

The hybrid algorithm interface is shown in Figure 8.18. It contains the five possible states summarized in Table 8.1. The default state is 0 for the first time that the algorithm is called. This occurs once TS has reached steady state electromechanical equilibrium and is ready for interfacing, prior to a system disturbance. Under the 0 state, EMTDC is called for a full fundamental period ahead of TS and its interfacing variables extracted and converted to positive sequence. The state is now set to -1. Under the - 1 state, TS is run for one half of a fundamental period and the variables at its interface location are compared with those of EMTDC. This is simply to check and ensure that the data in both files is correctly set up. The TS network is then split

318

SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

-1.4

I
,

(a) EMTDC
1.4 1.2 1 .o 0.8 0.6 0.4 0.2
i

&

g) 0.0
-0.2
-0.6 -0.8 -1 .o -1.2 -1.4 I

>o -0.4

(b) TSE Hybrid-Fundamental frequency equivalent

1.4 ,
f

0.96

1.00

1.02

1.04

1.06

1.08

1.10

1.12

1.14

1.16

1.18

Time (s) (c) TSE Hybrid Frequency dependent equivalent

Figure 8.17 Inverter ax. voltage

8.8 STRUCTURE OF THE HYBRID PROGRAM

319

Table 8.1 Interfacing states

State
-1 0 1 2

Event Isolate TS network ready to interface with EMTDC Initial time through interfacing routine Normal interaction between TS and EMTDC System network change signalled-run EMTDC for a full period past the fault and return information to TS TS catching up with EMTDC after a system network change

No

Yes

1
I

Compare variables

I
s = Ts+stepl
I

No 1
1 and2

Set up equivalent circuits

Yes

State=l Ts=O Call EMTDC for a

Convert EMTDC olp

Ts=Ts+steol

Figure 8.18 TSE hybrid algorithm. [step 11 TS program step length. [Ts] TS step length counter. [Tend] Minimum finish time for EMTDC. [K] Time counter for EMTDC and TS comparison of variables. [Tc] Time over which comparison must be within tolerance

320

8 SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

B
Yes

eriod of TI2

variables to TS sys. 1

State=3 Ts=O Ts=Ts+stepl

~~~~~~~~ ~

Extract TS system 2 variables Compare variables of TS sys.2 and EMTDC

lr

+ = + &
K=K+stepl

I No
i

Terminate EMTDC Reconnect TS systems 1 and 2

*
I

C
Figure 8.18 (Continued)

8.8

STRUCTURE OF THE HYBRID PROGRAM

D

321

IC
stop

f
Pass TS,System 1
variables to EMTDC

%
Ts=Ts+step 1

Ts=O

Figure 8.18

(Continued)

into systems 1 and 2, and Norton equivalent circuits set up in each system. The state is now set to 1, representing normal interfacing conditions, and TS is solved until its time is concurrent with EMTDC. Under the normal interfacing of state 1, variable information is given to EMTDC from TS to update its equivalent circuit. The equivalent circuit of system 1 in the TS model of system 2 is updated in the same way. EMTDC is then called for one half a period and the information measured over the last fundamental period of its simulation . . . . . . , used to update the equivalent circuit or system L in 15. In the interface data file, a time can be specified as a minimum termination time for EMTDC, after any network disturbance is cleared. Once this time is reached in the program, the interface variables of both system 2 models are compared at each TS time-step. If they correlate within a predefined tolerance over a set period, then EMTDC can be terminated and the TS representation of system 2 once again takes river nurino the vsriahleq are b the ..." nerinrl y ,. . . , . . thpv -.."J rirp hpino -... rhprkpd -..--.-..-,if _- at anv ,time --.-._-.. -_ - outside the specified tolerance, the checking period time is restarted.
a .

r n "

" 1 1 1 .

Y"1 1 . .

I.w"

I --f

-_---_-I

322

8 SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

When a network admittance change is about to occur, such as a fault being applied or removed, the interfacing routine is entered with a state value of 2. At this point in time, TS is concurrent with EMTDC. The TS interface variables are passed to EMTDC, which is then run for a full period from the network discontinuity time. It is not accurate to apply the analysis window over the network discontinuity, so the staggered window process must be restarted. The variables from EMTDC are passed back to TS at the time of the disturbance and the state is changed to 3. State 3 allows TS to catch up to EMTDC before the normal interfacing procedure of state 1 recommences.

8.9 Test System and Results

The d.c. link of the test system is based on the CIGRE benchmark model [7] described in Appendix 111. However, the rectifier a.c. system is modified as shown in Figure 8.19 to be representative of the New Zealand central South Island primary transmission system. The parameters for this test system are also given in Appendix 111. A threephase short circuit is applied to the rectifier terminals of the d.c. link (at time 1.7 s) and cleared three cycles later. For the EMTDC studies, the a.c. system at the faulted (rectifier) end is replaced by a frequency-dependent equivalent circuit, derived as explained in section 6.4.3, which produced the harmonic impedances, shown in Figure 8.20.

8.9.1 Response of the individual programs

The differences between the TS and EMTDC programs when used independently from each other are illustrated in Figure 8.21 Following fault clearance the rectifier is unblocked at t = 1.8s and a few ms later the inverter takes over conduction from its by-pass valves. After an initial current inrush into the d.c. line capacitance, the power setting is ramped up. At t = 1.97 s the inverter is restated and the link current drops, a reduction which is more pronounced and stays longer in the EMTDC solution.
Clyde Twizel

Livingston

Aviemore

Figure 8.19 Test system on the a.c. side of the rectifier station

8.9 TEST SYSTEM AND RESULTS

323

3 2000r

3000

o 2500-

.-

6
m

t
ii

1500500 -

E 1000-

8 2

1.20

7 1.00
0.800.603 0.400 0 0.20..... 0.00 I I I I I I I I 1.50 1.65 1.80 1.95 2.10 2.25 2.40 2.55 2.70 2.85 3.00 Time (s)
C

Figure 8.21 d.c. current response to a three-phase short circuit at the rectifier end

Following the power ramp, the a.c. current returns to its nominal value and after a small oscillatory settling of the controllers so do the d.c. voltage and current.

8.9.2

TSE hybrid response

The results of the EMTDC and TS simulations show substantial differences and thus their independent use is inadequate to model the transient stability of the a.c. system. Figure 8.22(a) displays the rectifier terminal a.c. voltage levels calculated with the TS and TSE alternatives. The main difference between them is a transient overshoot in the TSE solution immediately after fault clearance. The rectifier d.c. currents, displayed for the three solutions in Figure 8.22(b), show a very similar variation for the TSE and EMTDC solutions, except for the region between I = 2.03 s and t = 2.14 s but the difference with the TS only solution is very pronounced. Figure 8.23 compares the fundamental positive sequence real and reactive powers across the converter interface for the TS and TSE solutions. The main differences in real power occur during the link power ramp. The difference is almost a direct relation to the d.c. current difference between TS and TSE shown in Figure 8.22(b). The oscillation in d.c. voltage and current as the rectifier terminal is de-blocked is also evident.

324

8 SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

................ TS only
1.40 I 1.20
1 .oo

E (TS variable)

0.80
0.60 0.40 0.20 0.00

z
6
0

1.20 1.20 1.00

--

_ I

0.800.600.40 0.20 0.00 I I I I I I I I 1.50 1.65 1.80 1.95 2.10 2.25 2.40 2.55 2.70 2.85 3.00

(b)

Time (s)

Figure 8.22 Hybrid response comparisons. (a) Rectifier end a x . voltage. (b) Rectifier end d.c. current

1200 1000

- TSE

TS
I

5 8

600 400

0
I I

200

z. p 8

-200-

--

..........

...............
~

rg .5 -1OooI a -1200 -1400

I
I I

-400-600-800-

Figure 8.23 Real and reactive power across interface

8.10 QUASI STEADY-STATE CONVERTER SIMULATION

325

5 s
a 0 ,

-30 -50
I

I ~.,~,-I~,.R-,,-~--.
1 ,

--

-_-.- - - - - - -

lo-10-

........... a c -30E 0 -50

pi F, !..,/*\ ,.,..-. . ,i \. !. ..

L........

......................................................................

Figure 8.24

Rotor angle swings using TSE

As for the reactive power Q, prior to the fault, a small amount is flowing into the system due to a surplus MVArs at the converter terminal. The fault reduces this power flow to zero. When the fault is removed and the a.c. voltage overshoots in TSE, the reactive MVArs also overshoot in TSE and since the d.c. link is shut down, a considerable amount of reactive power flows into the system. Finally, Figure 8.24 shows the machine angle swings with respect to the Clyde generator (see test system of Figure 8.19). These indicate that the system is transiently stable.

8.10 Quasi Steady-state Converter Simulation

When analysing small perturbations and dynamic stability, converter equipment is expected to operate in a controlled manner almost instantaneously when compared with the relatively slow a.c. system dynamics. In these cases, it is acceptable to use a modified steady-state (or quasi steady-state) model, the modifications being due to the different constraints imposed by the load flow and stability studies. Such a model is also suitable for representing large rectifier loads during a.c. system disturbances, with further modifications necessary to represent abnormal rectifier operating modes. Further to the basic assumptions listed in Chapter 3, the following need to be made here:
0 0

The implementation of delay angle control is instantaneous. The transformer tap position remains unchanged throughout the stability study unless otherwise specified. The direct current is smooth, though its actual value may change during the study.

8.10.1 Rectifier loads

Large rectifier loads generally consist of a number of series andor parallel connected bridges, each bridge being phase shifted relative to the others. With these configurations, high-pulse numbers can be achieved resulting in minimal distortion of the

326

8 SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

Figure 8.25 Rectifier load equivalent circuit

Reducing aV,,,,cosa Constant current control characteristic

; .
'd*
'd

Figure 8.26 Simple rectifier control characteristic

supply voltage without filtering. Rectifier loads can, therefore, be modelled as a single equivalent bridge with a sinusoidal supply voltage at the terminals but without representation of passive filters. This model is shown in Figure 8.25. Rectifier loads can utilize a number of control methods which can be modelled using a controlled rectifier with suitable limits imposed on the delay angle (a)[12].

Static loads Operating under constant current control, the d.c. equations are:
(8.53)
(8.54)

where A is the constant current controller gain and I d s is the normal d.c. current setting as shown in Figure 8.26. Constant current cannot be maintained during a large disturbance as a limit of delay angle will be reached. In this event, the rectifier control specification will become one

8.10 QUASI STEADY-STATE CONVERTER SIMULATION

327

of constant delay angle and Equation (8.54) becomes:

(8.55)
Protection limits and disturbance severity determine the rectifier operating characteristics during the disturbance. Shutdown occurs if I d reaches a set minimum or zero and the voltage Vload will cause shutdown before the a.c. terminal voltage reaches zero. The action of the rectifier load system is thus described by Equations (3.24), (3.30), (3.34), (3.36), (3.37), (8.53) and either (8.54) or (8.55).

Dynamic loads The basic rectifier load model assumes that current on the d.c. side of the bridge can change instantaneously. For some types of rectifier loads this may
be a valid assumption, but the d.c. load may well have an overall time constant which is significant with respect to the fault clearing time. In order to examine realistically the effects which rectifiers have on the transient stability of the system, this time constant must be taken into account. This requires a more complex model to account for extended overlap angles, when low commutating voltages are associated with large d.c. currents. When the delay angle (a)reaches a limiting value, the dynamic response of the d.c. current is given by (8.56) V d = IdRd Vload Ldpld,

where 4 represents the equivalent inductance in the load circuit. Substituting for using Equation (3.24) gives

Vd

where T d c = L d / R d . The controller time constant may also be large enough to be considered. However, in transient stability studies where large disturbances are usually being investigated, faults close to the rectifier load force the delay angle (a)to minimum very quickly. Provided the rectifier load continues to operate, the delay angle will remain at its minimum setting throughout the fault period and well into the post-fault period until the terminal voltage recovers. The controller will, therefore, not exert any significant control over the d.c. load current. Ignoring the controller time constant can, therefore, be justified in most studies.

Abnormal modes of converter operation The slow response of the d.c. current
when a large disturbance has been applied to the ax. system can cause the rectifier to operate in an abnormal mode. After a fault application near the rectifier, the near normal value of d.c. current ( I d ) needs to be commutated by a reduced a.c. voltage. This causes the commutation angle ( b )to increase and it is possible for it to exceed 60". This mode of operation is beyond the validity of the equations and to model the dynamic load effects accurately it is necessary to extend the model.

328

8 SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

The full range of rectifier operation can be classified into four modes [13]:

Mode 1 -Normal operation. Only two valves in the bridge are involved in simultaneous commutation at any one time. This mode extends up to a commutation angle of 60". Mode 2 -Enforced delay. Although a commutation angle greater than 60" is desired, the forward voltage across the incoming thyristor is negative until either the previous commutation is complete or the firing angle exceeds 30". In this mode, p remains at 60" and a ranges up to 30". Mode 3 -Abnormal operation. In this mode, periods of three-phase short circuit and d.c. short circuit exist when two commutations overlap. During this period, there is a controlled safe short circuit which is cleared when one of the commutations is complete. During the short-circuit periods, four valves are conducting. Commutation cannot commence until 30" after the voltage crossover. Mode 4 -Continuous three-phase and d.c. short circuit caused by two commutations taking place continuously. In this mode, the commutation angle is 120" and the a.c. and d.c. current paths are independent.
The waveforms for these modes are shown in Figure 8.27, and Table 8.2 summarizes the conditions for the different modes of operation. Equations (3.24) and (3.30) do not apply for a rectifier operating in Mode 3 and they must be replaced by:
(8.58)

and
Id

=Vterm(c0sa'- cos y').

45xc

(8.59)

Fourier analysis of the waveform leads to the relationship between ax. and d.c. current given by Equation (3.32), where the factor k is now:

(8.60)
where
a ' = CY - 30"

and
y' = y
( p ) is shown in Figure 8.28.

+ 30".

(8.61)

A graph showing the value of k for various delay angles (a) and commutation angles

Identification of operating mode The mode in which the rectifier is operating can be determined simply by use of a current factor K I . The current factor is defined as:
(8.62)
Substitution in this, using the relevant equations, yields limits for the modes.

8.10 QUASI STEADY-STATE CONVERTER SIMULATION

329

Figure 8.27 Rectifier voltage waveforms showing different modes of operation. (a) Mode 1, g < 60"; (b) Mode 2, p = 60" with enforced delay al; (c) Mode 3, p z 60" with short-circuit 2 period a
Table 8.2 Rectifier modes of operation
Mode
1

Firing angle
0" 5 a 5 90" 0" 5 a 5 30"

Overlap angle

0" 5 /A 5 60"
60" 60" 5 p < 120" 120"

2 3
4

30" 5 (Y 5 90" 30" 5 a 5 90"

330

8 SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

1.2

Figure 8.28 Variation of k in expression I , = k ( 3 , h / n ) I d

Mode 1:

K I 5 COS(~O"- a )
and

(8.63)

K I 5 2 cos a for rectifier operation.

Mode 2.
(8.64)
L

Mode 3:

K I < - when a 5 30,

43
2

K I < -cos(ct - 30") when ct > 30".

43
2
2

(8.65)

Mode 4:

K I = - when a 5 30,

43

K I = -cos(a - 30") when a > 30"

43

(8.66)

This can be demonstrated in the curve of converter operation shown in Figure 8.29. It can thus be seen that the mode of operation can be established prior to solving for the rectifier load equations at every step in the solution.

8.10.2

d.c. link

Provided that it can be safely assumed that a d.c. link is operating in the quasi steadystate (QSS) Mode 1, the equations developed for converters in Chapter 3 can be used. That is, the converters are considered to be controllable and fast acting so that the

8.10 QUASI STEADY-STATE CONVERTER SIMULATION

Mode 4

331

Delay angle, a

Figure 8.29 Converter operation [ 141

normal steady-state type of model can be used at each step in the transient stability study. The initial steady-state operating conditions of the d.c. link will have been determined by a load flow and, in this, the control type, setting and margin will have been established. During the solution process at each iteration, the control mode must be established. This can be done by assuming Mode 1 (i.e. with the rectifier on C.C. control) and, by combining Equations (3.39), (3.45), (8.53) and (8.54), a d.c. current can be determined as: Idsr - [(3fi/n)aiVtermi cos Yicl/Ar (8.67) I d mode I = 1 (Rd - (3/n)xci)/Ar Assuming this current to be valid, then d.c. voltages at each end of the link can be calculated using Equations (3.24) and (3.39). The d.c. link is operating in mode 2 (i.e. with the inverter on C.C. control) i f

Vdr mode I - Vdi mode I =< 0.

The d.c. current for mode 2 operation is given by

(8.68)

For constant power control, under control mode 1, the d.c. current may be determined from the quadratic equation:

where

Pds

is the setting at the electrical mid-point of the d.c. system, i.e.

pds = (Pdsr

+ pdsi)/2*

(8.7 1)

332

8 SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

Table 8.3 Current setting for constant power control from quadratic equation
Id I Id2

Within

Outside
Within

Outside Within Within

Id I
Id2

Greater of I d , and Ir12

I d max I d max I d max

Greater Greater
Less Less

Greater Less Greater Less

Within = within the range / d m i n to / d m a x ; Outside = outside the range l d m i n to l d m a x ; Greater c Greater than I d m a x ; Less = Less than I d m i " .

The correct value for Idm&I can then be found from Table 8.3. Control mode 2 is determined using Equation (8.68) and in this case the following quadratic equation must be solved: k r z : mode 2 - k v l d mode 2 - P d marg - p d s = 0, (8.72) where (8.73) (8.74) If the link is operating under constant power control but with a current margin then for control mode 2:

It is possible for the d.c. link to be operating in control mode 2 despite satisfying the inequality of Equation (8.68). This occurs when the solution indicates that the rectifier firing angle (a,)is less than the minimum value ( a r m i n ) . In this case, the delay angle should be set to its minimum and a solution in mode 2 is obtained. It is also possible that when the link is operating close to the changeover between modes, convergence problems will occur in which the control mode changes at each iteration. This can easily be overcome by retaining mode 2 operation whenever detected for the remaining iterations in that particular time step.

d.c. power modulation It has been shown in the previous section that under the constant power control mode, the d.c. link is not responsive to a.c. system terminal conditions, i.e. the d.c. power transfer can be controlled disregarding the actual a.c. voltage angles. Since, generally, the stability limit of an ax. line is lower than its thermal limit, the former can be increased in systems involving d.c. links, by proper utilization of the fast converter controllability. The d.c. power can be modulated in response to a.c. system variables to increase system damping. Optimum performance can be achieved by controlling the d.c. system

8.10 QUASI STEADY-STATE CONVERTER SIMULATION

333

so as to maximize the responses of the a.c. system and d.c. line simultaneously following the variation of terminal conditions. The dynamic performance under d.c. power modulation is best modelled in three separate levels [14]. These levels, illustrated in Figure 8.30, are (a) the a.c. system controller, (b) the d.c. system controller and (c) the ax.-d.c. network. (a) The ax. system controller uses ax. andor d.c. system information to derive the current and voltage modulation signals. A block diagram of the controller and a.c.-d.c. signal conditioner is shown in Figure 8.31.

(b) The d.c. system controller receives the modulation signals AI and A E and the
steady-state specifications for power PO current I 0 and voltage Eo. Figure 8.32(a) illustrates the power controller model, which develops the scheduled current setting; it is also shown that the current order undergoes a gradual increase during restart, after a temporary blocking of the d.c. link. The rectifier current controller, Figure 8.32(b), includes signal limits and rate limits, transducer time constant, bandpass filtering and a voltage dependent current order limit (VDCOL). The inverter current controller, Figure 8.32(c), includes similar components plus a communications delay and the system margin current ( Z , , , ) . Finally, the d.c. voltage controller, including voltage restart dynamics, is illustrated in Figure 8.32(d). (c) The d.c. current I d and voltage E d derived in the d.c. system controller constitute the input signals for the a.c.-d.c. network model which involves the steady state

ffY
I _

DC control modes AClDC interface

Ed 'd 'd, ' ' d i Qr Ql

(a)

(b)

(4

Figure 8.30 a.c.-d.c. dynamic control structure: (i) a.c. system controller, (ii) d.c. system controller, (iii) ax.-d.c. network

Figure 8.31 a.c. system controller

334

8 SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

3~
'07

N(P)

D(P)

Figure 8.32 d.c. system controller. (a) Power controller; (b) Rectifier current controller; (c) Inverter current controller; (d) d.c. voltage controller

solution of the d.c. system (neglecting the d.c. line dynamics which are included in the d.c. system controller). Here the actual a.c. and d.c. system quantities are calculated, i.e. control angles, d.c. current, voltage, active and reactive power. The converter a.c. system constraints are the open circuit secondary voltages Ear and Eai.

8.10.3 Representation of converters in the network

Rectifiers The static load rectifier model can be included in the overall solution of the transient stability program in a similar manner to the basic loads described in Chapter 7.

8.10 QUASI STEADY-STATE CONVERTER SIMULATION

335

From the initial load flow, nominal bus shunt admittance (yo) can be calculated The for the rectifier. This is included directly into the network admittance matrix [Y]. current injected into the network in the initial steady state is, therefore, zero. In general:

where

and

?;*
30

Yo=Ivrermo12

(8.77)

(8.78)
The static load rectifier model does not depart greatly from an impedance characteristic and is well behaved for low terminal voltages, the injected current tending to zero as the voltage approaches zero. Figure 8.33 compares the current due to a rectifier with that due to a constant impedance load. As the injected current is never large, the iterative solution for all ax. conditions is stable. When the rectifier model is modified to account for the dynamic behaviour of the d.c. load, its characteristic departs widely from that of an impedance. Immediately after a fault application, the voltage drops to a low value but the injected current magnitude does not change significantly. Similarly, on fault clearing, the voltage recovers instantaneously to some higher value while the current remains low.

Ip

t
I

0.5
Vterm

1.o

linj

~F.L.

Figure 8.33 Difference between impedance and static load rectifier characteristic (for vload # 0)

336

8 SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

When the load characteristic differs greatly from that of an impedance, a sequential solution technique can exhibit convergence problems, especially when the voltage is low. With small terminal voltages, the a.c. current magnitude of the rectifier load is related to the d.c. current but the current phase is greatly affected by the terminal voltage. Small voltage changes in the complex plane can result in large variations of the voltage and current phase angles. To avoid the convergence problems of the sequential solution, an alternative algorithm has been developed [ 151. This combines the rectifier and network solutions into a unified process. However, it does not affect the sequential solution of the other components of the power system with the network. The basis of this approach is to reduce the a.c. network, excluding the rectifier, to an equivalent Thevenin source voltage and impedance as viewed from the primary side of the rectifier transformer terminals. This equivalent of the system, along with the rectifier, can be described by a set of non-linear simultaneous equations which can be solved by a standard Newton-Raphson algorithm. The solution of the reduced system yields the fundamental a.c. current at the rectifier terminals. To obtain the network equivalent impedance, it is only necessary to inject 1 p.u. current into the network at the rectifier terminals while all other nodal injected currents are zero. With an injected current vector of this form, a solution of the nodal network Equation (7.48) gives the driving point and transfer impedances in the resulting voltage vector: (8.79) [Z] = [V']= [ T ] l [ 7 ; , 1 ,

(8.80)

The equivalent circuit shown in Figure 8.34 can now be applied to find the rectifier current ( 7,) by using the Newton-Raphson technique. The effect of the rectifier on the rest of the system can be determined by superposition: (8.81) [VI= [TI [ZII,,

where

[ T I = [r]-"l;j]

(8.82)

and [7Ynj]are the injected currents due to all other generation and loads in the system. If the network remains constant, vector is also constant and thus only needs re-evaluation on the occurrence of a discontinuity. Thus, the advantages of the unified and sequential methods are combined. That is, good convergence for a difficult element in the system is achieved while the programming for the rest of the system remains simple and storage requirements are kept low.

[z]

8.10 QUASI STEADY-STATE CONVERTER SIMULATION

337

Figure 8.34 Equivalent system for Newton-Raphson solution

'I
Rd

vd=0

Dynamic load element

Vload

The equivalent system of Figure 8.34 contains seven variables ( V , e r m , I , , 8, @, a, and I d ) . With these variables, four independent equations can be formed. They are Equation (3.24) and:
Vd

Vl!@- V t e r m L 8 - Z,hl!(IpL$'
Vdld

= 0,

(8.83) (8.84)

- &aVtermlp

cOS(6 - 9) = 0.

Equation (8.83) is complex and represents two equations. Substituting for V d and I , using Equations (3.34) and (8.53) reduces the number of variables to five. A fifth equation is necessary and with constant current control, i.e. with the delay angle (a) within its limits, this can be written as
Id

- I d s p = 0.

(8.85)

Equation (3.24), suitably reorganized, and Equations (8.83)-(8.85)represent [ F ( X ) ]= 0 of the Newton-Raphson process and
(8.86) [XIT = [Er, 8, a,I d ] . When the delay angle reaches a specified lower limit (omin), the control specification, given by Equation (8.85) changes to
$9

a - amin = 0.

(8.87)

Equation (3.24) is no longer valid. The d.c. current ( I d ) is now governed by the differential Equation (8.57). If the trapezoidal method is being used, this equation can be transformed into an algebraic form similar to that described in Chapter 7 . Equation (3.24) is replaced by:
Id

= kaE, cosa - kb = 0.

(8.88)

The variables ka and kb contain information from the beginning of the integration step only and are thus constant during the iterative procedure:
ka = h / ( 2

+ kc

h),

(8.89)

338

8 SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

where
(8.91)
t represents the time at the beginning of the integration step and h is the step length.

Commutation angle p is not explicitly included in the formulation, and since these equations are for normal operation, the value of k in Equation (3.35) is close to unity and may be considered constant at each step without loss of accuracy. On convergence, p may be calculated and a new k evaluated suitable for the next step. In Mode 3 operation, the value of k becomes more significant and for this reason the number of variables is increased to six to include the commutation angle p. The equations [ F ( X ) ] = 0 for the Newton-Raphson method in this case are:
VLp - VtemL8 -uVterm
7I

(8.92)

Jz

A cOs(8 - @ ) f ( p ) - -aVterm
7I
Id

cosa!'

x c + -3In d

= 0,

(8.93) (8.94) (8.95) (8.96)

- ka

aVterm cos CY'- kb = 0,

cos(a!

AXc + p + 30) - cos(Y' + -Id avterm

a!

= 0,

- CY,ln = 0.

Although k can be calculated explicitly, a linearized form of Equation (8.60) obtained for 01 = 30" can be used to simplify the expression. In the range 60" < 1 < 120", the value of k can be obtained from:
f(1) = 1.01 - 0.0573 1,

(8.97)

where p is measured in radians. In Mode 4, the a s . and d.c. systems are both short circuited at the rectifier and operate independently. In this case, the system equivalent of Figure 8.34 reduces to that shown in Figure 8.35. The network equivalent can be solved directly and the d.c. current is obtained from the algebraic form of the differential Equation (8.57).

Dynamic
element

Figure 8 . 3 5 Rectifier load equivalent in Mode 4 operation

8.11 STATIC VAR COMPENSATION SYSTEMS

339

d.c. links The problems associated with dynamic rectifier loads do not occur when the d.c. link is represented by a quasi steady-state model. Each converter behaves in a manner similar to that of a converter for a static rectifier load. A nominal bus shunt admittance (Lo) is calculated from the initial load flow for both the rectifier and inverter ends and injected currents are used at each step in the solution to account for the change from steady state calculated from Equation (8.76). Note that the steadywill have a negative conductance value as state shunt admittance at the inverter (YOoi) power is being supplied to the network. This is not so for a synchronous or induction generator as the shunt admittance serves a different purpose in these cases.

8.10.4 Inclusion of converters in the transient stability program

A flow diagram of the unified algorithm is given in Figure 8.36. It is important to note that the hyperplanes of the functions used in the Newtonian iterative solution process are not linear and good initial estimates are essential at every step in the procedure. A common problem in converter modelling is that the solution converges to the unrealistic result of converter reactive power generation. It is, therefore, necessary to check against this condition at every iteration. With integration step lengths of up to 25 mS, however, convergence is rapid.

8.11 Static VAR Compensation Systems

Static VAR compensation systems (SVS) of large ratings are now in common use to control the voltage at points remote from power generation. They are also installed to assist system stability and, therefore, to consider them as a fixed shunt element can produce erroneous information in a transient stability study. A composite static VAR compensator, shown in Figure 8.37, has been suggested by a CIGRE Working Group [16]. The model is not overly complex as this would make data difficult to obtain and would be incompatible with the overall philosophy of a multi-machine transient stability program. The SVS representation can be simplified to any desired degree, however, by a suitable choice of data. The basic control circuit consists of two lead-lag and one lag transfer function connected serially. The differential equations describing the action of the control circuit with reference to Figure 8.37 are:

Although electronically produced, the dead band may be considered as a physical linkage problem, as shown in Figure 8.38(a). In this example, the input ( x ) and output ( y ) move vertically. The diagram shows the initial steady-state condition in which x and y are equal. The input ( x ) may move in either direction by an amount Db/2 before y moves. Beyond this amount of travel, y follows x, lagging by &/2 as depicted in Figure 8.38(b). The effect of a dead band can be ignored by setting Db to zero.

340

8 SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

TS programme Rectifier subroutines Calculate constants for differential equation

Chec for switching No

I. a -

I I a 1

Obtain new Thevenin imDendancd

II
I
I I

Extract th_eveninvoltages from [ V ]

L

t
v

vuT Calculate K, if mAAn operation

Calculate new initial lconditons and mode

I I I

3
Calculate mismatches Convergence Yes given mode of operation lter + 11ter+ll

I
I

,
I

I
I

i
I

I ( %
Calculate rectifier variables

I
I

I II I I
I ! (Convergence?)

lter > 15

Yes Error messages

#

t
A.C. current on [ V ]

I
I
Figure 8.36 Unified algorithm flow diagram

Stepped output permits the modelling of SVS when discrete capacitor (or inductor) blocks are switched in or out of the circuit. It is usual to assume that all blocks are of equal size. During the study, the SVS operates on the step nearest to the control setting. Iterative chattering can occur if the control system output (B3) is on the boundary between two steps. The simplest remedy is to prevent a step change until B3 has from the mean setting of the step. moved at least 0.55BSep

8.1 1
Initial controlling vohage ( p u ~

STATIC VAR COMPENSATION SYSTEMS

341

"9v-t

Initial susceptanm (pu)

Dead band

Control system

Susceptance limits and steps

Figure 8.37 Composite static VAR compensation system (SVS) model

1x r + z 4
(a) Movement
Movement

input x

\n

Figure 8.38 Dead band analogy and effect. (a) Physical analogy of dead band; (b) The effect of a dead band on output

The initial MVAR loading of the SVS should be included in the busbar loading schedule data input. However, it is possible for an SVS to contain both controllable and uncontrollable sections (e.g. variable reactor in parallel with fixed capacitors or vice versa). It is the total MVAR loading of the SVS which is, therefore, included in the busbar loading. Only the controllable part should be specified in the SVS model input and this is removed from the busbar loading leaving an uncontrollable MVAR load which is converted into a fixed susceptance associated with the network. Note that busbar load is assumed positive when flowing out of the network. The sign is, therefore, opposite to that for the SVS loading. In order to clarify this, consider an overall SVS operating in the steady state, as shown in Figure 8.39(a). The busbar loading in this case must be specified as -50 MVAR and it may be varied between -10 MVAR and -80 MVAR provided the voltage remains constant. The SVS may be specified in a variety of ways, some more obvious than others, the response of the system being identical. Three possible specifications are given in Table 8.4. In the first example, the network static load will be +20 MVAR, while in the second case the static load will be zero. The third example may be represented by an overall SVS, as shown in Figure 8.39(b).

342

SYSTEM STABILITY UNDER POWER ELECTRONIC CONTROL

(limits 70MVAR 0 and

70 MVAR)

12z
Initial loading
70 50 -30

80 MVAR

Figure 8.39 Example of an overall SVS controllable and uncontrollable sections. (a) Example of overall SVS using controllable capacitors; (b) Alternative to overall SVS in (a) using a controllable reactor

Table 8.4 Examples of MVAR loading specification for SVS shown in Figure 8.39(a)
Example
1

Maximum limit
100

Minimum limit

30
10

2
3

80
0

-70

It is convenient, when specifying the initial steady-state operation, to use MVAR. However, this is a function of the voltage and, hence, all MVAR settings must be converted to their equivalent per unit susceptance values prior to the start of the stability study.

8.11.1 Representation of SVS in the overall system

The initial MVAR loading of the SVS is converted into a shunt susceptance (Bo) and added to the total susceptance at the SVS terminal busbar. During the system study, the deviation from a fixed susceptance device is calculated ( B 4 ) and a current equivalent to this deviation is injected into the network. A reduction in controlling voltage VSV will cause the desired susceptance B4 to increase. That is, the capacitance of the SVS will rise and the MVAR output will increase. The injected current (Ti,,,) into the network is given by:
(8.101)

8.12 REFERENCES

343

where
Y =0

+jB4.

Although not necessary for the solution process, the MVA output from the SVS into the system is given by:

(8.102)

8.12 References
1, Kulicke, B. Netomac digital program for simulating electromechanical and electromagnetic

transient phenomena in a x . systems, (198 1). Siemens Aktienngesel-lschaft, E15/1722- 101. 2. Woodford, D A, (1985). Validation of digital simulation of d.c. links, IEEE Transactions on Power Apparatus and Systems, PAS-104 (9), pp. 2588-2595. 3. Anderson, G W J, Arnold, C P, Watson, N R and Arrillaga, J, (1995). A new hybrid a.c. -d.c. transient stability program, International Conference on Power Systems Transients (IPST), pp. 535-540. 4. Anderson, G W J, (1995). Hybrid simulation of a.c.-d.c. power systems, Ph.D. thesis, University of Canterbury, New Zealand. 5 . Eguiluz, L I and Arrillaga, J, (1995). Comparison of power definitions in the presence of waveform distortion, International Journal of Electrical Engineering Education, 32 (2), pp. 141-153. 6. Heffernan, M D, Turner, K S, Arrillaga, J and Arnold, C P, (1981). Computation of a.c. -d.c. system disturbances -Parts I, I1 and 1 1 1 , Transactions on Power Apparatus and Systems, PAS-100 (1 l), pp. 4341 -4363. 7. Szechtman, M, Weiss, T and Thio, C V, (1991), First benchmark model for HVDC control studies, ELECTRA (133, pp. 55-75. 8. Clarke, E, (1950). Circuit Analysis o f a.c. Power Systems- Vol. 11, John Wiley and Sons, New York. 9. Kimbark, E W, (1968). Power System Stability- Vol. IIIs Synchronous Machines, Dover Publications, New York. 10. Reeve, J and Adapa, R, (1988). A new approach to dynamic analysis of a.c. networks incorporating detailed modelling of d.c. systems -Parts I and 11, IEEE Transactions, PD-3 (4), pp. 2005-2019. 1 I . Watson, N R, (1987). Frequency-dependent a.c. system equivalents for harmonic studies and transient converter simulation, Ph.D. thesis, University of Canterbury, New Zealand. 12. Arnold, C P, Turner, K S and Arrillaga, J, (1980). Modelling rectifier loads for a multimachine transient-stability programme, IEEE Transactions on Power Apparatus and Systems, PAS-99 (l), pp. 78-85. 13. Giesner, D B and Arrillaga, J, (1970). Operating modes of the three-phase bridge converter, International Journal of Electrical Engineering Education, 8, pp. 373-388. 14. IEEE Working Group on Dynamic Performance and Modeling of d.c. Systems, (1980). Hierarchical structure. 15. Turner, K S , (1980). Transient stability analysis of integrated a.c. and d.c. power systems, Ph.D. thesis, University of Canterbury, New Zealand. 16. CIGRE Working Group 31-01, (1977). Modelling of static shunt VAR systems for system analysis, ELECTRA (Sl), pp. 45-74.