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Digital Electronics

http://ptuece.loremate.com/die/node/12 March 7, 2012

Q 20. What is a voltage to frequency converter? How is it used for designing AID converter? Ans. Voltage to frequency converter: It is as shown in Here the input analog voltage is integrated and fed to a comparator. To the comparator, a reference voltage Vref is applied. Whenever input voltage exceeds the comparator reference voltage the comparator changes the state. This resets the integrator and the process repeats itself. The integration cycles are counted in a counter for fixed time duration. The output of counter gives the desired digital output. If the integrator is realized by an inverting amplifier and has time constant then the output of integrator at time t is given by:

If the Vref is the comparator reference voltage, then the time t = T and is given by: The frequency of the integration cycles is given by: Here, integrator time constant t and Vref are constants and it will be seen that output frequency. proportional to input voltage. Such a comparator is able to handle unipolar analog signals. Q 21. Describe the working of a successive approximation AID converter with the help of a suitable diagram and compare its performance in terms of speed, accuracy and resolution with other ADCs. Ans. Successive Approximation A/D Converter: It is the most widely used A/D converter. It has more complex circuitry than the digital ramp A/D converter but it has much shorter conversion time. For n-bit A/D converter n-successive steps are required for completing the approximation process. The various functional brakes of successive approximation A.D converter are 1. Comparator 2. D/A converter (Binary ladder may be used)

3. Control logic 4. Successive approximation register (SAR) SAR is consists of flip-flops and level amplifiers. It is as shown in fig. The control logic is used to set or reset the flip-flops. The O/P of there flip-flops are given to level amplifiers and then to D/A converter which is a binary ladder network. It gives digital O/Ps as well as the analog reference voltage. Initially the control logic resets all the flip-flops. There are three basic conditions: 1. If i.e. reference voltage from D/A converter is. less than the input analog voltage then MSB (most significant bit) is set to 1 by control logic. 2. . If then MSB is reset to (zero) 0 and next bit is set to 1. 3. If then the control logic disables the clock to flip flops and we can get digital O/P from SAR by using latches. For example : If 4 bit SAR is used. Q 22 Draw and explain the basic block diagram of (i) voltage of frequency conversion and (ii) voltage of time conversion Ans. (i) Voltage of frequency A/D Converter: It s as shown in fig. The output of the voltage to frequency converter is applied at the clock input of the counter. Let Va be the analog input given to the

integrator at time t = 0. The output Vo is given by:

From (1) it is clear that the output of integrator decreases as it increases As long as Vo> VR, the output Vd of comparator will be low i e 0 At time t = T1 Vo will become equal to - VR and Vd will become high i e 1 Vd is given to the reset logic which closes the switch for discharging of capacitor in integrator Thus, Vo again return to 0 The capacitor again discharges in time T2 when T2 <<T1.

When the increasing value of Vo becomes jut greater than VR, again Vd gives low value Hence pulse width of Vd is very small. The reset logic closes the switch for sufficient time to discharge the capacitor completely. Following fig. shows the variation of Vd and Vo w.r.t. time t. The Vd output from voltage to frequency converter is given as the clock input to the counter provided enable i.e. The frequency of V0 and Vd is given as:

Thus, frequency of voltage to frequency converter is directly proportional to the input- analog voltage. (ii) Voltage to time AID Converter: The block diagram of voltage of time A/D converter is shown above in fig. Va is given to the comparator and VR is given to the integrator. If VEN = 1 switch is open and if VEN = 0 switch is closed in the inegrator circuit. Let VEN = 1, Thus, switch is open and the output of the integrator will be:

Here, Vo is increasing with time. When Vo <Vs, the output of comparator goes high i.e. thus circuit is given to the counter. The counter counts at each circuit pulse. When,

Vo = Va, Vd becomes low, thus output of AND gate goes low. No circuit pulse to counter stops counter bps and the final value is stored in the counter which is the digital equivalent of Va. When VEN = 0, switch is closed in the integrator, and the capacitor is discharge until Vo reaches 0. For t = T and Vo = Va The equation (1) becomes:

Thus, T is proportional to Va. Q 23 Write note on the following Binary ladder D/A. converter. Ans Binary ladder D/A converter In a binary ladder D/A converter only two valued resistance R and 2R are used as shown in diagram The OP amp is an inverting amplifier By solving resistance N/W in parallel and series, finally voltage at node B is.

Q 24. How many bits are required for a DAC, so that Its full scale output is 12.6 V and resolution 20 mV? Ans. So, DAC required 10 bits. Q 25. Explain the operation of dual-slope A/D converter. Ans. The dual slop A/D converter provide very much accuracy and so mostly used. An analog input voltage is applied to Ramp Generator. The output of Ramp Generator app1ied to comparator. The output of comparator is given to AND gate. The second output AND gate is clock pulse. When input is high for AND gate clock pulse will be given to m-r. Counter is initially reset by control logic. Now counter counts up and binary output in form is provided. When counter stops, switch control again control the whole function.