Introduction to Digital Design using VHDL

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Digital Design using VHDL

What is VHDL? VHDL is VHSIC Hardware Description Language
Where VHSIC stands for Very High Speed Integrated Circuits
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VHDL is a general-purpose programming language that allows the behavior of complex electronic circuits to be captured into a design system for automatic circuit synthesis or for system simulation. Description Language, was developed in the early 1980s funded by the U.S. Department of Defense. The first publicly available version of VHDL, version 7.2, was released in 1985. IEEE 1076-1993, version released in 1994 and IEEE 1164 standards together form the complete VHDL standard in widest use www.xtrabits.in today.

Part I - Introduction to VHDL

Structure of a VHDL program

VHDL Terminologies
Identifiers in VHDL

Data types in VHDL

Data Objects in VHDL Operators in VHDL

Structure of a VHDL program

Library Declaration

Package Declaration
Entity Declaration

Architecture Declaration

Library Declaration
Syntax: library lib1,lib2,..libn; The library clause makes visible all libraries specified in the VHDL program For example library ieee; The above line makes visible the library named ieee in the design unit.

Package Declaration
Syntax: use library_name.package_name.all; OR
use library_name.package_name.component_name;

The library clause makes visible all libraries specified in the VHDL program
For example use ieee.std_logic_1164.all; The above line make visible all components included in the package std_logic_1164 which is residing in the library named ieee.

Entity Declaration
By entity we mean the external view of the hardware to be modeled.

Syntax:
Entity entity_name is
Port (list_of_interface_ ports:port_mode: data_type; list_of_interface_ ports:port_mode: data_type); End entity_name;
Entity mux2to1 is Port(A,B,S:in bit;Z:out bit); end mux2to1; Syntax for entity declaration is common for any type of modeling.

Architecture Declaration
By architecture we mean the internal view of the hardware to be modeled.

Syntax:
Architecture architecture_name of entity_name is
Various declarations; Begin Concurrent statements; End architecture_name;
Architecture a_mux2to1 of mux2to1 is Begin Z<=A and (not S) or (B and S); end a_mux2to1;

Let us consider
A two channel multiplexer
Two input channels A and B One channel select input S One output line - Z

External View

Internal View

VHDL code for Mux2to1

Modeling of a 2to1 Mux using dataflow style Library ieee; use ieee.std_logic_1164.all;
Entity mux2to1 is Port(A,B,S:in bit;Z:out bit); end mux2to1;

Architecture a_mux2to1 of mux2to1 is Begin

Z

Z<=A and (not S) or (B and S);

end a_mux2to1;

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The following lines are included to make library named ieee visible in the program. Library ieee;
The following lines makes visible all components in package std_logic_1164, residing in library ieee.

use ieee.std_logic_1164.all; Entity is declared whose name is mux2to1, with input ports A, B and S. The output port is declared as Z. All these ports can have bit type values.
Entity mux2to1 is Port(A,B,S:in bit;Z:out bit); end mux2to1;

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Architecture a_mux2to1 of mux2to1 is Begin Z<=A and (not S) or (B and S); end a_mux2to1; Z

The architecture or internal view is declared whose name is a_mux2to1. The architecture part of this program does not contain any declaration and so it is empty. The output port Z is written as Z=A.S+B.S, in simple English, which denotes the direction of data flow, so the name dataflow style of modeling. In VHDL syntax the above line should be written as
Z<=A and (not S) or (B and S);

VHDL Terminologies
Identifiers in VHDL
Basic identifiers in VHDL
Name of a Basic Identifier must start with an alphabet Name of a Basic Identifier must not end with an underscore(_) Two consecutive underscores are not allowed(__) Keywords like and, or are not allowed as a basic identifier. Not case sensitive MUX2to1 is same as mux2to
Some legal keywords: mux2to1, mux_2to1,mux2 Some illegal identifies: 2to1mux,mux__2to1,mux2to1_

Extended identifiers in VHDL

Slashes at the start and end - \Mux2to1\ Keywords can be used as an extended identifier - \and\, \or\ Case sensitive \nand\ and \NAND\ are not same.

Some legal identifiers: \nand\,\NAND\,\and\,\AND\

Let us identify the identifiers..

library ieee;
use ieee.std_logic_1164.all; Entity mux2to1 is Port(A,B,S:in bit;Z:out bit); end mux2to1;

Architecture a_mux2to1 of mux2to1 is Begin Z<=A and (not S) or (B and S); end a_mux2to1;
A,B and S are used to identify the input ports, Z is used to identify the output port, mux_2to1 is used to identify the entity and a_mux2to1 is used to identify the architecture. www.xtrabits.in

Ports in, out and inout

There are two types of ports unidirectional and bidirectional

Unidirectional ports input port and output port

Bidirectional port inout port

One can read an input port and write into the output port.
One can read and write into an inout port.

Ports in the VHDL code for Mux2to1

In the previous VHDL program for 2to1 multiplexer the letters A,B,S & Z indicates input and output ports. Ports A,B & S are used to carry data into the circuit. So these are the INPUT PORTS. The port Z is used to carry the output of the circuit under consideration. So this is the OUTPUT PORT.

Data Objects in VHDL

In VHDL data objects are used to hold some data. Each data object belongs to any of the following different classes Constant Variable Signal File Syntax:data_class data_object1,data_object2,data_objectn:data_type

As an example let us consider

signal A,B:bit; variable C:integer; constant M:std_logic_vector
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Data Types in VHDL

Data types refers to different types of data, a data-object can have. Different data types are
Scalar data type Array data type Access data type and File data type

Some pre-defined data types in VHDL are

BIT, STD_LOGIC, INTEGER, BOOLEAN
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Part II Different Modeling Styles

Different modeling styles in VHDL
Dataflow Style of Modeling
Modeling Example

Structural Style of Modeling

Modeling Example

Behavioral Style of Modeling

Modeling Example

Mixed Style of Modeling

Modeling Example
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Dataflow Style of Modeling

Uses statements that defines the actual flow of data. So the name Dataflow Modeling

such as,
x <= y -- this is NOT READ as less than equal to -- READ as x is defined as y This assigns the Boolean signal x to signal y. i.e. x = y, this will occur whenever y changes.... Z<=A and B Whenever A or B changes, the expression A and B is evaluated and result is assigned to Z.
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Example - Dataflow Modeling

2 Channel multiplexer with Enable input
External View - Entity

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Example - Dataflow Modeling

2 Channel multiplexer with Enable input
External View - Architecture
Z<=(A and (not S) and E) or (B and S and E)

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Example - Dataflow Modeling

library ieee; use ieee.std_logic_1164.all; --Entity Declaration Entity mux2to1e is Port(A,B,S,E:in bit;Z:out bit); end mux2to1e; --Architecture declaration Architecture d_mux2to1e of mux2to1e is Begin
Z<=(A and (not S) and E) or (B and S and E);

end d_mux2to1e ; www.xtrabits.in

Structural Style of Modeling

implements the module as a composition of subsystems contains signal declarations, for internal interconnections

the entity ports are also treated as signals

Contains component declaration in the declaration part Contains component instantiation in the architecture body
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Syntax of Structural Architecture

Syntax for entity declaration is common for any type of modeling.

Architecure arch_name of entity_name is Component declarations; Signal declarations; Begin comp_label1:comp_name port map(list of i/f ports); comp_label2:comp_name port map(list of i/f ports); comp_labeln:comp_name port map (list of i/f ports); End arch_name;

Component Instantiation

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Syntax for component declaration

Component declaration:Component component_name
The line as it appears in the entity declaration of the component;

End Component;
Eg: Component mux2to1e Port(A,B,S,E:in bit;Z:out bit); End Component;
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Syntax for component instantiation

Component Instantiation:comp_label:comp_label port map(list of i/f ports);

Eg:
M0: mux2to1e Port map(P,Q,S0,X,S1);

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Example Structural Modeling

Four Channel Multiplexer
External View - Entity

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Example Structural Modeling

Four Channel Multiplexer
Internal View - Architecture

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External View Entity Declaration

library ieee; use ieee.std_logic_1164.all; --Entity Declaration Entity mux4to1 is Port(P,Q,R,T,S1,S0,En:in bit; Y:out bit); end mux4to1;

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Internal View Architecture Declaration

--Architecture Declaration

Component Declaration

Architecture S_mux4to1 of mux4to1 is component mux2to1e Port(A,B,S,E:in bit;Z:out bit); end component; signal S2,S3; Begin
M0:mux2to1e port map(P,Q,S0,En,S2); M1:mux2to1e port map(R,T,S0,En,S3); M2:mux2to1e port map(S2,S3,S1,En,Y);

Component Instantiation

end S_mux4to1;
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Behavioral Modeling
Syntax for entity declaration is common for any type of modeling.

Behavioral architecture
describes the behavior of device to be modeled.
describes the algorithm performed by the module Contains Process Statement Sequential statements are included in process statement It is mandatory to have an End Process for the Process statement www.xtrabits.in

Syntax of Behavioral Architecture

Architecture arch_name of entity_name is Global/Shared declarations; Begin Process(Sensitivity list) Local declarations; Begin Sequnetial statement1; Sequential statement n; End process; End arch_name;
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Example Behavioral Modeling

Let us consider an AND gate

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Let us consider the behavior of an AND gate

If A=0 and B=0 then C=0 If A=0 and B=1 then C=0 If A=1 and B=0 then C=0 If A=1 and B=1 then C=1

In other words If A=1 AND B=1 then C=1 else C=0 Also If A=0 or B=0 then C=0 else C=1
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Example Behavioral Modeling

D Flip Flop - External View - Entity

Library ieee; Use ieee.std_logic_1164.all; Entity dff is

Entity Declaration

Port(Din,CLK:in bit;Q,Qb:out bit); End dff;

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Behavior of D Flip Flop

D CLK Q Qb

1
0 0 1 1

1 to 0
0 to 1 1 to 0 0 to 1 1 to 0

1
1 0 0 1

0
0 1 1 0

If there is a negative clock (when clock changes from 1 to 0) output is equal to input, else there is no change in output.

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Architecture/Internal View
Architecture b_dff of dff is Begin Process(Din,CLK) Begin If CLKevent AND CLK=0 then Q<=Din; Qb<= not(Din); End if; End process; End b_dff;
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sensitivity list

Mixed Style of Modeling

If any two of the modeling styles are used for the implementation of the architecture - the modeling is mixed style of modeling.

For example, an architecture can contain Behavioral and dataflow statements, structural and dataflow statements. process statements and component instances Component instances and signal assignments
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Realization of a 4 input Multiplexer External View - Entity

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External View Entity Declaration

library ieee; use ieee.std_logic_1164.all; --Entity Declaration Entity mux4to1 is Port(P,Q,R,T,S1,S0:in bit; Y:out bit); end mux4to1;

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Realization of a 4 input Multiplexer Internal View - Architecture

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Internal View Architecture Declaration

--Architecture Declaration

Component Declaration

Architecture S_mux4to1 of mux4to1 is component mux2to1e Port(A,B,S,E:in bit;Z:out bit); end component; signal S2,S3,S4; Begin
M0:mux2to1e port map(P,Q,S0,S4,S2); M1:mux2to1e port map(R,T,S0,S1,S3); Y<=S2 or S3; S4<=Not S1;
www.xtrabits.in end S_mux4to1;

Component Instantiation
(Structural Modeling)

Signal Assignment
(Dataflow modeling)

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