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Department of Mechanical Engineering

N A T I O N A L U N I V E R S I T Y O F S I N A G A P O R E
Jan 10, 2014 Chapter 0 Introduction Page 0.1
ME3241/ ME3241E
Microprocessors and Applications
Part I: Digital Electronics
By A/P GS HONG
CONTROL Group
MECHANICAL ENGINEERING DEPARTMENT
NATIONAL UNIVERSITY OF SINGAPORE
2013/2014
Rm: EA-05-24
Tel: 6516-2272
email: mpehgs@nus.edu.sg
Department of Mechanical Engineering
N A T I O N A L U N I V E R S I T Y O F S I N A G A P O R E
Jan 10, 2014 Chapter 0 Introduction Page 0.2
Time Table
ME3241 TM3241
Start Date: 13 J an, 2014 17 J an, 2014
Time: Monday 10:00-12:00
Friday 9:00-11:00
Friday 18:00 21:00
Venue: E1-06-04 LT4
Examination: Wednesday, 30-Apr-2014 (Afternoon)
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Jan 10, 2014 Chapter 0 Introduction Page 0.3
Module Learning Outcome
Students are able to represent number in various
bases and explain the different type of common codes
used in industries.
Students are able to explain various error detection
and correction techniques
Students are able to solve problem using
combinatorial logic and/or sequential logic.
Students are able to explain the basic structure of a
microprocessor.
Students are able to do assemble programming for a
microprocessor.
Department of Mechanical Engineering
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Jan 10, 2014 Chapter 0 Introduction Page 0.4
Course Outline
1. Numbering System And Codes
Review of numbering systems, Signed number represetation and binary
arithmetic. ASCII, BCD, Excess-3 and Gray Codes. Parity and data correction.
2. Microprocessor Architecture
Review of digital circuits, Memory devices. Data busing, data bus operation.
Central processing units: arithmetic logic unit, registers, instruction decoder,
timing and control. memory instruction cycle.
3. Assembly Language
Instruction set of a microprocessor. Use of instructions to programmes.
Addressing Modes, Flags. Stack and stack pointer. Subroutines.
4. Input/Output
Input/output instructions. Memory-mapped input/output. Interrupt and timer
facilities. Asynchronous and synchronous data communications. Digital i/o and
analogue i/o.
5. Microcomputer
Introduction to the IBM PC. System description. Hardware Description.
Programming of the PC.
6. Applications In Engineering
Physical variable measurement. Feedback control: P, PI and PID controllers. Case
studies example of microprocessor/microcomputer applications.
Department of Mechanical Engineering
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Jan 10, 2014 Chapter 0 Introduction Page 0.5
Reference books
1. RL Tokheim,
"Digital electronics: Principles and applications",
7th edition, 2008, McGrawHill.
2. RJ Tocci,
"Digital systems: Principles and applications,
6th edition, 1995, Prentice-Hall, Inc.
3. S Brown and Z Vranesic,
"Fundamentals of digital logic with Verilog design,
2nd edition, 2008, McGrawHill.
4. LD J ones,
"Principles and applications of digital lectronics,
Macmillan, 1986.
5. TF Bogart, J r.,
"Introduction to digital circuits,
McGraw-Hill International Student Edition, 1992
6. H-W Huang,
"PIC microcontroller : an introduction to software and hardware
interfacing,
Clifton Park, NY : Thomson/Delmar Learning, 2005.
Department of Mechanical Engineering
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.1
Chapter 1 Number System and Codes
Chapter Objective
Number Systems
Code
Binary Arithmetic
Number representation in Computer
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.2
1.1 Number Systems
A number is a quantified value one adopted for counting.
e.g.
number of people attending class,
the number of elective modules a student has to take, etc..
We use number everyday. Knowing how numbers work
will give us an insight into how a computer manipulates
and stores numbers.
Human start their ways of counting in many different
ways and finally evolved to the current approach of
number system representation.
http://mathforum.org/alejandre/numerals.html
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.3
1.1 Number Systems
Consider an example below, the number 6557
meant
Six thousand five hundred and fifty seven
i.e. 6 x 1000 + 5 x 100 + 5 x 10 + 7 x 1
The above example demonstrated a common number
system we adopted. It is known as weighted position
representation.
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.4
1.1.1 Number System Representation
Any number (N
r
) in any system can be represented in the form of
where
i = number of places the digit is relative to the radix point
r = radix or the base of the system
A
i
e {0, 1, 2, , r-1}
Also know as weighted positional number system

=

= =
n
m i
i
i m n n r
r A A A A A A N
1 0 1
.
(1.1.1)
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.5
1.1.1.1 Decimal System (Base 10)
The number system we are familiar with is the so-
called decimal system.
r = 10
A
i
e {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}
Examples
825
10
= 8 x 10
2
+ 2 x 10
1
+ 5 x 10
0
368.49
10
= 3 x 10
2
+ 6 x 10
1
+ 8 x 10
0
+ 4 x 10
-1
+ 9 x
10
-2
Decimal system is the current Universal Standard
used by human being. We normally just ignore the
subscript 10 in our notation.
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.6
1.1.1.2 Binary System (Base 2)
The number system that computer used.
r = 2
A
i
e {0, 1}
Example: 1101
2
= 13
10
1 1 0 1
2
3
2
2
2
1
2
0
Weights
= 1 x 2
3
+ 1 x 2
2
+ 0 x 2
1
+ 1 x 2
0
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.7
1.1.1.2 Binary System (Base 2)
Another example: 110.01
2
= 4 + 2 + 0 + 0 + 0.25
= 6.25
= 1 x 2
2
+ 1 x 2
1
+ 0 x 2
0
+ 0 x 2
-1
1 0 0 1 1 .
2
-1
2
2
2
1
2
0
Weights 2
-2
+ 1 x 2
-2
Radix point
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.8
1.1.1.3 Octal System (Base 8)
r = 8
A
i
e {0, 1, 2, 3, 4, 5, 6, 7}
Example: 405.3
8
= 4 x 64 + 5 x 1 + 3 x 0.125
= 261.375
10
= 4 x 8
2
+ 0 x 8
1
+ 5 x 8
0
+ 3 x 8
-1
0 5 3 4 .
8
-1
8
2
8
1
8
0
Weights
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.9
1.1.1.4 Hexadecimal System (Base 16)
r = 16
A
i
e {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F}
Example 1:
3B.4
16
= 3 x 16
1
+ 11 x 16
0
+ 4 x 16
-1
= 3 x 16 + 11 x 1 + 4 x 0.0625
= 59.25
10
Example 2:
102.2
16
= 1 x 16
2
+ 0 x 16
1
+ 2 x 16
0
+ 2 x 16
-1
= 1 x 256 + 0 x 16 + 2 x 1 + 2 x 0.0625
= 258.125
10
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.10
1.2 Conversion between number systems
Sometime, we need to represent a number of a given
base in another base.
We are familiar with decimal system, so, we are
concerned with
Other system to decimal system
Decimal system to other system
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.11
1.2.1 Binary to Decimal
We use the weighted sum approach.
Example:
The number 1010.01
2
can be converted to a decimal as
1010.01
2
= 1 x 2
3
+ 0 x 2
2
+ 1 x 2
1
+ 0 x 2
0
+ 0 x 2
-1
+ 1 x 2
-2
= 8 + 0 + 2 + 0 + 0 + 0.25
= 10.25
10

=
=
n
m i
i
i
A N 2
10
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.12
1.2.2 Decimal to Binary
We can also use the weighted sum approach as above.
Example:
34
10
= 3 x 10
1
+ 4 x 10
0
= 11
2
x 1010
2
+ 100
2
x 1
2
= 11110
2
+ 100
2
= 100010
2
However the above method involves binary arithmetic
that we are not familiar with. There are two other
methods to convert a decimal number to binary
number.
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.13
1.2.2.1 Method 1
Express the decimal number as a sum of powers of 2
and then 1s and 0s are written in the appropriate bit
position.
Example:
45.5
10
= 32 + 8 + 4 + 1 + 0.5
= 2
5
+ 0 + 2
3
+2
2
+ 0 + 2
0
+ 2
-1
= 101101.1
2
76
10
= 64 + 8 + 4
= 2
6
+ 0 + 0 + 2
3
+ 2
2
+ 0 + 0
= 1001100
2
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.14
1.2.2.2 Method 2
Earlier method require you to be familiar with the
various 2
i
values.
Consider a 3 digit base-r integer number
N
r
= A
2
r
2
+ A
1
r
1
+ A
0
r
0
Dividing N
r
by its radix value yields
N
r
/r = (A
2
r
2
+ A
1
r
1
+ A
0
r
0
)/r
= A
2
r
1
+ A
1
r
0
+ A
0
/r
Or, alternatively, we say
N
r
/r = (A
2
r
1
+ A
1
r
0
) remainder A
0
Similarly,
(A
2
r
1
+ A
1
r
0
) /r = A
2
r
0
remainder A
1
That is, we can use successive division technique to
convert a decimal number to a base-r representation.
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.15
1.2.2.2 Method 2 Fractional Number
For the case of fractional number, consider a base-r
fractional number with 3 radix places
N
r
= A
-1
r
-1
+ A
-2
r
-2
+ A
-3
r
-3
Multiplying N
r
by its radix yields
N
r
x r = (A
-1
r
-1
+ A
-2
r
-2
+ A
-3
r
-3
) r
= A
-1
r
0
+ A
-2
r
-1
+ A
-3
r
-2
That is, we can use successive multiplication technique to
convert a fractional decimal number into a base-r
representation.
A
-1
becomes integer part
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.16
1.2.2.2 Method 2 Example 1
Consider the case of decimal
to binary conversion
Example: 26.6875
10
26.6875
10
= 26
10
+ 0.6875
10
For fractional part:
0. 6875 x 2 = 1. 375
0. 375 x 2 = 0. 750
0. 75 x 2 = 1. 500
0. 5 x 2 = 1. 000
For the integer part:
Therefore,
26.6875
10
= 11010.1011
2
2 26 0 Remainder
2 13 1 Remainder
2 6 0 Remainder
2 3 1 Remainder
2 1 1 Remainder
0
LSB
MSB
LSB
MSB
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.17
1.2.2.2 Method 2 Example 2
Example: 43.6
10
43.6
10
= 43
10
+ 0.6
10
For fractional part:
0. 6 x 2 = 1. 2
0. 2 x 2 = 0. 4
0. 4 x 2 = 0. 8
0. 8 x 2 = 1. 6
0. 6 x 2 = 1. 2
: :
: :
: :
Therefore,
43.6
10
= 101011.10011
2
(up to 5 digit
approx.)
For the integer part:
2 43 1 Remainder
2 21 1 Remainder
2 10 0 Remainder
2 5 1 Remainder
2 2 0 Remainder
0
2 1 1 Remainder
LSB
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.18
1.2.3 Octal Decimal conversion
Octal to Decimal - weighted sum approach.
Example:
The number 326.4
8
can be converted to a decimal number by
326.4
8
= 3 x 8
2
+ 2 x 8
1
+ 6 x 8
0
+ 4 x 8
-1
= 192 + 16 + 6 + 0.5
= 214.5
10
Decimal to Octal successive division and multiplication
Example:
379.546875
10
= 379 + 0.546875
For the integer part:
8 379 Remai nder 3 LSD
8 47 Remai nder 7
8 5 Remai nder 5 MSD
0
For fractional part:
0. 546875 x 8 = 4. 375
0. 375 x 8 = 3. 000
Ther ef or e
379. 546875
10
= 573. 43
8
Question: How about, say, Octal to base-7?
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.19
1.2.4 Octal binary conversion
Noting that 8 = 2
3
.
Therefore, we can convert between binary and octal number easily
by bit mapping
Octal digit 0 1 2 3 4 5 6 7
Binary pattern 000 001 010 011 100 101 110 111
Example: Octal to binary
271. 65
8
= 010 111 001 . 110 101
2
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.20
1.2.4 Binary - Octal Conversion (continue)
Example: Binary to octal
1111100101. 001110
2
= 001 111 100 101 . 001 110
2
= 1 7 4 5 . 1 6
8
= 1745. 16
8
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.21
1.2. 5 Hexadecimal Decimal conversion
Hexadecimal to Decimal - weighted sum approach.
Example:
The number 3B.4C
16
can be converted to a decimal number by
3B.4C
16
= 3 x 16
1
+ 11 x 16
0
+ 4 x 16
-1
+ 12 x 16
-2
= 48 + 11 + 0.25 + 0.046875
= 59.296875
10
Decimal to Hexadecimal successive division and multiplication
Example:
379.546875
10
= 379 + 0.546875
For the integer part:
16 379 Remai nder 11=B LSB
16 23 Remai nder 7
16 1 Remai nder 1 MSB
0
For fractional part:
0. 546875 x 16 = 8. 75
0. 375 x 16 = 12. 00 = C. 00
Ther ef or e
379. 546875
10
= 17B. 8C
16
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.22
1.2.6 Hexadecimal - binary conversion
Noting that 16 = 2
4
.
Therefore, we can convert between binary and octal number easily
by bit mapping
Hexadecimal 0 1 2 3 4 5 6 7
Binary pattern 0000 0001 0010 0011 0100 0101 0110 0111
Hexadecimal 8 9 A B C D E F
Binary pattern 1000 1001 1010 1011 1100 1101 1110 1111
Example: Octal to binary
A94. 65
16
= 1010 1001 0100.
0110 0101
2
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.23
1.2.7 Binary - Hexadecimal Conversion
Example: Binary to Hexadecimal
1111100101. 00111
2
= 0011 1110 0101 . 0011 1000
2
= 3 E 5 . 3 8
16
= 3E5. 38
16
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.24
Small Summary number system conversion
Base-r to decimal
Use weighted sum approach
Decimal to base-r
Use successive division and multiplication
Base-r to Base-p
Base-2 to/from base-2
n
Table lookup

=
=
n
m i
i
i
r A N
10
Base-r Decimal Base-p
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.25
1.3 Codes and Coding
1.3.1 Binary Coded Decimal Code
8-4-2-1 BCD Code
Not a weighted position number system
Each digit of a decimal number is
represented by 4 binary bits as follows:
Example
Note that conversion from BCD code
to decimal is straight forward.
e.g.
The BCD code does not use
the number
1010 1011
1100 1101
1110 1111
Decimal Digit BCD
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
39
10
0011 1001
107
10
0001 0000 0111
0110 1000 0011 1001 (BCD Code) = 6839
10
6 8 3 9
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.26
1.3.1.3 Other variance of BCD Code
Decimal
Digit
BCD
8-4-2-1 Excess-3 Biquinary
5 0 4 3 2 1 0
0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1
1 0 0 0 1 0 1 0 0 0 1 0 0 0 1 0
2 0 0 1 0 0 1 0 1 0 1 0 0 1 0 0
3 0 0 1 1 0 1 1 0 0 1 0 1 0 0 0
4 0 1 0 0 0 1 1 1 0 1 1 0 0 0 0
5 0 1 0 1 1 0 0 0 1 0 0 0 0 0 1
6 0 1 1 0 1 0 0 1 1 0 0 0 0 1 0
7 0 1 1 1 1 0 1 0 1 0 0 0 1 0 0
8 1 0 0 0 1 0 1 1 1 0 0 1 0 0 0
9 1 0 0 1 1 1 0 0 1 0 1 0 0 0 0
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.27
Some interesting Binary Code
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.28
Some interesting Binary Code Bi-quinary Device
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.29
1.3.2 Gray Code
Decimal Binary Gray Code Decimal Binary Gray Code
0 0000 0000 8 1000 1100
1 0001 0001 9 1001 1101
2 0010 0011 10 1010 1111
3 0011 0010 11 1011 1110
4 0100 0110 12 1100 1010
5 0101 0111 13 1101 1011
6 0110 0101 14 1110 1001
7 0111 0100 15 1111 1000
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.30
1.3.2.1 Advantage of Gray Code
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
1
0
0
0
1 0
1 1
1
1 1 1 1
0 0 0 0
0
0
0
0
0
1
0
0
1
0
1
1
0
0
0
1 0
1 1
1
1 1 1 1
1 1 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 13 14 12 15
Binary Code
0 1 0 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 0 1 1 0 0 1 1
0 1 0 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11 13 14 12 15
Gray Code
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.31
1.3.2.2 Generation of Gray Code Method 1
Step 1: To generate a n-digit Gray Code, we start by a 1 digit Gray Code
Deci mal Gr ay Code
0 0
1 1
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.32
1.3.2.2 Generation of Gray Code Method 1
Step 2: For 2 digit Gray Code, we first repeat the 1 digit Gray Code in
the reverse order. Then insert 0s to the left of these code on the
upper half and 1s on the lower half.
Deci mal Gr ay Code
0 0
1 1
Deci mal Gr ay Code
0 0
1 1
2 1
3 0
Deci mal Gr ay Code
0 00
1 01
2 11
3 10
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.33
1.3.2.2 Generation of Gray Code Method 1
Step 3: For 3 digit Gray Code, repeat Step 2 with 2-digit Gray Code and so on.
Deci mal Gr ay Code
0 00
1 01
2 11
3 10
Deci mal Gr ay Code
0 00
1 01
2 11
3 10
4 10
5 11
6 01
7 00
Deci mal Gr ay Code
0 000
1 001
2 011
3 010
4 110
5 111
6 101
7 100
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.34
1.3.2.2 Generation of Gray Code Method 1
Step 4: For 4 digit Gray Code, repeat Step 2 with 3-digit Gray Code and so on.
Deci mal Gr ay Code
0 000
1 001
2 011
3 010
4 110
5 111
6 101
7 100
Deci mal Gr ay Code
0 000
1 001
2 011
3 010
4 110
5 111
6 101
7 100
8 100
9 101
10 111
11 110
12 010
13 011
14 001
15 000
Deci mal Gr ay Code
0 0000
1 0001
2 0011
3 0010
4 0110
5 0111
6 0101
7 0100
8 1100
9 1101
10 1111
11 1110
12 1010
13 1011
14 1001
15 1000
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.35
1.3.2.2 Generation of Gray Code Method 2
To convert a Binary number B = b
n-1
b
n-2
b
1
b
0
, to its corresponding Gray
code G = g
n-1
g
n-2
g
1
g
0
, we use the formula
for i = 0, 1, , n-1 with b
n
= 0
E.g. Say, we have B = b
3
b
2
b
1
b
0
= 1010
2
. Then we have

=
=
=
+
+
,
0 ,
1 , 1
1
1
i i
i i
i
b b
b b
g
1 0 1 1
0 ,
1 , 1
0
1 0
1 0
0
=

= =
=
=
= b
b b
b b
g

= =
=
=
= 1
0 ,
1 , 1
1
2 1
2 1
1
b
b b
b b
g
1 0 1 1
0 ,
1 , 1
2
3 2
3 2
2
=

= =
=
=
= b
b b
b b
g

= =
=
=
= 1
0 ,
1 , 1
3
4 3
4 3
3
b
b b
b b
g
Therefore, G = 1111
2
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1.3.2.2 Generation of Gray Code Method 2
E.g. More example
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1.3.2.2 Generation of Gray Code Method 2
To convert a Gray code G = g
n-1
g
n-2
g
1
g
0
to its corresponding Binary number
B = b
n-1
b
n-2
b
1
b
0
,,
We first define
Then the binary number can be calculated by
, for i = 0, 1, , n-1 with g
n
= 0
0 with , 2 ,
1
=
|
|
.
|

\
|
=

+ =
n
n
i j
j i
g g Mod s

=
=
=
0 ,
1 , 1
i i
i i
i
s g
s g
b
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1.3.2.2 Generation of Gray Code Method 2
E.g. Say, we have G = g
3
g
2
g
1
g
0
= 1010
2
. Then we have
( )

= =
=
=
=
= + + =
|
|
.
|

\
|
=

=
0
0 ,
1 , 1
0 2 , 1 0 1 2 ,
0
0 0
0 0
0
4
1
0
g
s g
s g
b
Mod g Mod s
j
j
Therefore, B = 1100
2
( )

= = =
=
=
=
= + =
|
|
.
|

\
|
=

=
0 1 1 1
0 ,
1 , 1
1 2 , 0 1 2 ,
1
1 1
1 1
1
4
2
1
g
s g
s g
b
Mod g Mod s
j
j
( )

= = =
=
=
=
= =
|
|
.
|

\
|
=

=
1 0 1 1
0 ,
1 , 1
1 2 , 1 2 ,
2
2 2
2 2
2
4
3
2
g
s g
s g
b
Mod g Mod s
j
j
( )

= =
=
=
=
= =
|
|
.
|

\
|
=

=
1
0 ,
1 , 1
0 2 , 0 2 ,
3
3 3
3 3
3
4
4
3
g
s g
s g
b
Mod g Mod s
j
j
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1.3.2.2 Generation of Gray Code Method 2
E.g. More example
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1.3.3 Alphanumeric Codes - ASCII Code
Used to encode the characters of the alphabet and other non-
numerical information in addition to the decimal digits
Used primarily for data transfer from computer to input/output
devices such as printers, keyboards, modem etc.
To standardize on the representation of symbols, international
codes are used.
ASCII - American Standard Code for Information Interchange
ANSI - American National Standard Institute
ISO - International Standard Organization
These abbreviations mean generally the same coding system;
there are differences in national interpretations, e.g. , $ signs.
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1.3.3 Alphanumeric Codes - ASCII Code
HEX MSD 0 1 2 3 4 5 6 7
LSD Bits 000 001 010 011 100 101 110 111
0 0000 NUL DLE SP 0 @ P ` p
1 0001 SOH DC1 ! 1 A Q a q
2 0010 STX DC2 " 2 B R b r
3 0011 ETX DC3 # 3 C S c s
4 0100 EOT DC4 $ 4 D T d t
5 0101 ENQ NAK % 5 E U e u
6 0110 ACK SYN & 6 F V f v
7 0111 BEL ETB ' 7 G W g w
8 1000 BS CAN ( 8 H X h x
9 1001 HT EM ) 9 I Y i y
A 1010 LF SUB * : J Z j z
B 1011 VT ESC + ; K | k {
C 1100 FF FG , < L \ l |
D 1101 CR GS - = M } m }
E 1110 SO RS . > N ^ n -
F 1111 SI US / ? O _ o DEL
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1.3.3 Alphanumeric Codes - ASCII Code
Special ASCII Symbols control characters
NUL Null VT Vertical Tabulation CAN Cancel
SOH Start of heading FF Form feed EM End of medium
STX Start of text CR Carriage return SUB Substitute
ETX End of text SO Shift out ESC Escape
EOT End of transmission SI Shift in FG File separator
ENQ Enquiry DLE Data link escape GS Group separator
ACK Acknowledge DC Device control RS Record separator
BEL Bell NAK negative ac knowledge US Unit separator
BS Back space SYN synchronous idle SP Space
HT Horizontal tab ETB end of transmission block DEL Delete
LF Line feed
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1.3.3 Alphanumeric Codes - ASCII Code
The ASCII code is a SEVEN bit code.
Use bit7 as parity (see later)
Use bit7 as to extend ASCII to accommodate more characters set
like graphical symbols (IBM PC), or
special character like (Mac)
Example 1:
The following is a message in ASCII. What is the message?
100 1000 100 0101 100 1100 101 0000
H E L P
Example 2:
An operator is typing in GOTO 25 at the keyboard of a computer. Determine
the ASCII Code that will be entered into memory.
G(100 0111) O(100 1111) T(101 0100) O(100 1111) V(010 0000) 2(011 0010) 5(011 0101)
Exercise:
1. Encode in ASCII, the string Cost = $72
2. The following ASCII message is stored in the memory. What is the message?
101 0011 101 0100 100 1111 101 0000
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1.3.4 Error Detection
The transfer of binary data from one location to another is the very common operation in
digital systems. For examples:
Transmission of digitized voice over a microwave link.
Storage and retrieval of data from external memory devices such as hard disks
Transmission of information from a computer to a remote user terminal and another
computer.
Whenever information is transmitted from one device (transmitter) to another device
(receiver), there is a possibility that errors can occur such that the receiver does not
receive the identical information that was sent by transmitter mainly caused by noise.
a 0 may be read as 1 or vice versa

Transmitter Receiver
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1.3.4 Error Detection
It would be nice if we can implement some kind of coding such
that any transmission error can be detected or corrected.
One example will be the Biquinary Code in the earlier section,
Biquinary Code Format: F
5
F
0
U
4
U
3
U
2
U
1
U
0
For a given number, there is only one 1 is each of the group, for
example the number 7 will have
10 00100
So, any single-bit error will make the code invalid. For example, say,
there is an error on U1, so, the code received will be
10 00110
which is not a valid Biquinary Code, hence error detected.
Are there alternative was of implementing error detection?
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Parity Bit
A common practice used is to attached an extra parity bit to the code
group that is being transferred from one location to another.
Even Parity:
The value of the parity bit is chosen such that the total number of
1s in the code group (including the parity bit) is an even number.
Example:
Suppose that the group is 100 0011 which is the ASCII code for
C.
ASCII Code
100 0011
Parity bit
1
Number of 1 = 3,
For even parity, we need an extra 1 to make it even.
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Parity Bit
Odd Parity:
The value of the parity bit is chosen such that the total number of 1s in
the code group (including the parity bit) is an odd number.
Example: For the ASCII code C.
If the receiver received 0100 0001, the receiver will know that an error
has occurred in the transmission.
Question: How about when two bits has error, say 0100 0101 is read
instead?
0 100 0011
ASCII Code
Parity bit is 0 in odd
parity mode
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1.3.4.1 Effect of Parity Check
Parity checking may be employed at major interfaces in a digital
system.
Since redundancy is added to each message, parity checks are
used only when the probability of errors occurring and the risk
associated with an error is high enough to warrant it
Consider a case that we are transmitting a 7-bit ASCII code
between two devices.
Case I: (Without parity bit)
For a given transmission technique, the probability of a bit be transmitted
wrongly is p (say, p = 3.1 x 10
-5
).
Transmission rate is r (say, r = 400 bps)
By transmitting without parity bit, the probability of transmitting an 7-bits
ASCII code is P
7
,
P
7
= 1 (1 - p)
7
= 1- 0.9999695 = 2.17 x 10
-4
and the transmission rate of R
7
,
R
7
= r/7 = 400/7 = 57.14 word per second
Alternatively, the average error rate is E
7
is
E
7
= 1/ P
7
x 1/ R
7
= 80 sec.
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1.3.4.1 Effect of Parity Check
Case II: (With parity bit)
With the parity bit implemented, the single bit error will
always be detected. Therefore we only look at chances that 2
bits or more errors happen together. Hence, by transmitting
with parity bit, the probability of transmitting an 8-bits ASCII
code is P
8
,
P
8
= 1 - (1-p)
8
8 p(1-p)
7
= 2.69 x 10
-8
and the transmission rate of R
8
,
R
8
= r/8 = 50 word per second
Alternatively, the average error rate is E
8
is
E
8
= 1/ P
8
x 1/ R
8
= 743273 sec. = 8.6 days
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1.3.5 Error Correction
Sometimes, beside detecting the error, we want to be
able to correct the error such that we can save the
time for re-sending the message.
Or, there may be situation that the message cannot
be re-sent. For example, reading a corrupted CD-
ROM.
A popular technique is the so-called Hamming Code
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1.3.5.1 Hamming Code
Hamming code involves the design of a code with m message
bits with r extra bits that will allow all single errors to be
corrected.
Question: What is the minimum value for r?
Answer: choose r such that
m + r + 1 s 2
r
Method:
1. add r parity bits to an m-bit number to form an r+m bits number
2. label the bits from 1 to (r+m)
3. bits in 2
i
positions, for i=0,1,..,r-1, are the r parity bits
4. the remaining bits are the message bits
5. Performs parity operation for each parity bit with the position
correspond to the 2
i
positions.
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1.3.5.1 Hamming Code Example Step 1
Example: Implement the Hamming Code on a 4 bit
BCD codes
Step 1:
For 4 bit BCD code
m = 4,
With
m + r + 1 s 2
r
Hence, a choice of
r = 3
will satisfy the above condition.
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1.3.5.1 Hamming Code Example Step 2-3
Step 2:
Hence, we need 3 parity bits in position
P
0
at 2
0
=1, P
1
at 2
1
=2 and P
2
at 2
2
=4.
Step 3:
Hence we have the code arranged as follows:
Position 1 2 3 4 5 6 7
Code P
0
P
1
M
3
P
2
M
2
M
1
M
0
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1.3.5.1 Hamming Code Example Step 4
Position 1 2 3 4 5 6 7
Code P
0
P
1
M
3
P
2
M
2
M
1
M
0
Step 4:
For parity assignment, we view the parity bits P
2
P
1
P
0
as a 3-bit number, and P
i
will performs parity operation with the position number with P
i
=1.
In this case,
P
0
= {001, 011, 101, 111} = {1,3,5,7} = {3,5,7}(Position 1 is parity bit)
P
1
= {010, 011, 110, 111} = {2,3,6,7} = {3,6,7}(Position 2 is parity bit)
P
2
= {100, 101, 110, 111} = {4,5,6,7} = {5,6,7}(Position 4 is parity bit)
Say, for even parity, the code is 0110 (BCD 6)
P
0
= even { M
3
, M
2
, M
0
} = even { 0, 1, 0} = 1
P
1
= even { M
3
, M
1
, M
0
} = even { 0, 1, 0} = 1
P
2
= even { M
2
, M
1
, M
0
} = even { 1, 1, 0} = 0
Hence the code is 11 0 0 110
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1.3.5.1 Hamming Code - Example Step 4
Error Correction
Say, during transmission, the code 110 0110 becomes 110
1110.
We check for the even parity of each parity bits
C
0
= even { M
3
, M
2
, M
0
} = even { 0, 1, 0} = 1 = P
0
E
0
=0
C
1
= even { M
3
, M
1
, M
0
} = even { 0, 1, 0} = 1 = P
1
E
1
=0
C
2
= even { M
2
, M
1
, M
0
} = even { 1, 1, 0} = 0 P
2
E
2
=1
Hence, the error position E
2
E
1
E
0
= 100 = 4
Position 4 has error (P
2
), it should be a 0 instead of 1.
the corrected code should be 110 0110
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1.3.5.1 Hamming Code
Graphical interpretation of Hamming Code
From previous slide, we have
P
0
check for { M
3
, M
2
, M
0
}
P
1
check for { M
3
, M
1
, M
0
}
P
2
check for { M
2
, M
1
, M
0
}
Homework: Any error in this code? if any, correct them, 10 1 0 011
M
0
P
0
P
1
P
2
M
1
M
2
M
3
In the previous example, we have
E
0
=0, E
1
=0 and E
2
=1
P
2
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1.4 Binary Arithmetic
1.4.1 Binary Addition
Basic addition rule
0 + 0 = 0
0 + 1 = 1
1 + 1 = 0 plus carry of 1
1 + 1 + 1 = 1 plus carry of 1
Example
0 1 1
2
= 3
10
+ 1 1 0
2
= + 6
10
1 0 0 1
2
= 9
10
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1.4.2 Binary Subtraction
Basic addition rule
0 - 0 = 0
1 - 1 = 0
1 - 0 = 1
0 - 1 = 1 wi t h a bor r ow of 1
Exampl e
1011
2
= 11
10
- 0101
2
= - 5
10
0110
2
= 6
10
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1.4.3 Binary Multiplication
By Successive addition
Similar to decimal multiplication
Example:
101101
2
multiplicand 45
10
x 101
2
multiplier x 5
10
101101
2
225
10
0000000
2
Partial products
10110100
2
11100001
2
Product
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1.4.4 Binary Division
Similar to decimal method
Example: 10 4
0010.1
100 1010
100
0010
0000
0010.0
0010.0
0000.0
=2.5
10
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1.4.5 Representing Signed Numbers
4 ways to represent a negative number.
Signed-Magnitude Representation
By pre-pending a sign indicator in the number.
Excess (Offset) Representation
By adding a bias to the number
Radix Complement Representation
By taking radix complement of an n-digit number is defined as
Diminished Radix Complement Representation
By taking diminished radix complement of an n-digit number is defined as
N N
sm
=
B N N
xs
+ =
N r N
n
rc
=
N r N
n
drc
= 1
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1.4.5.1 Negative number representation for decimal
number system
Signed-Magnitude Representation
The most common way of representation
Example:
+ 456.4 , -564.4 , 56.3 , etc
Excess (Offset) Representation
By adding a bias to the number (say, offset is 0.5 for number
between 0 to 1)
0.6 +0.1, 0.2 -0.3, etc
Radix Complement Representation
Say for a 2 digit decimal number, its radix complement is
Example:
the 10s complement of 75 is 10
2
75 = 25.
Diminished Radix Complement Representation
Say, for a 2 digit decimal number, its diminished radix complement is
Example:
the 10s diminished radix complement of 75 is 10
2
1 - 75 = 24.
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1.4.5.2 Signed number for Binary number.
Signed-Magnitude Representation
By pre-pending a sign indicator in the number.
For signed binary number, we can use the MSB of the number
as a sign bit. That is,
Sign bit = 0 positive number
Sign bit = 1 negative number
e.g.
However, such notation requires very complicated logic and
not commonly used in computer.
0 1 1 0 1 0 0 0 Positive number
1 0 1 1 1 1 0 1 Negative number
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1.4.5.2 Signed number for Binary number.
Excess (Offset) Representation
For an n-bit number, we use 2
n-1
as the offset. Hence
N
xs
= N + 2
n-1
We call it an excess 2
n-1
representation
Range = -(2
n-1
) ~ (2
n-1
-1)
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1.4.5.2 Signed number for Binary number.
1s complement form for binary number
The Diminished Radix Complement Representation for binary number
By taking diminished radix complement of an n-digit number. It is defined as
Or, just simply invert every bits of the number.
Also known as the logical complement.
Example: For a 4-bit number N
2
= 1001
2
2
1
2
1 2 N N
n
=
1 0 0 1 0 1 1 0
4-bit binary 1s compliment
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1.4.5.2 Signed number for Binary number.
Radix Complement Representation for binary number
By taking radix complement of an n-digit number is defined as
Or, by taking its 1s complement and then adds one to the
least significant bits.
Also known as the arithmetic complement.
Example: For a 4-bit number N
2
= 1001
2
101101 010010 010010
+ 1
010011
number 1s complement 2s complement
1 1 1 2
2
1
2 2
2
2
2
+ = + =
=
N N
N N
n
n
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1.4.5.2 Signed number for Binary number.
Consider a case of 3 bits binary number (n=3).
To avoid the duplicated representation,
the shaded cells are not used.
i.e., the 3 bit-binary with 2s complement signed
representation has the range of -4~3.
Decimal Binary 2s Complement
0 000 000 (-0)
1 001 111 (-1)
2 010 110 (-2)
3 011 101 (-3)
4 100 100 (-4)
5 101 011 (-5)
6 110 010 (-6)
7 111 001 (-7)
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1.4.5.3 Binary Arithmetic with 2s Complement
Consider the subtraction of an n-bit binary number N
B
from another n-bit binary number N
A
, we have.
Implies
Example: Consider 8-bits subtraction.
12
10
4
10
= 0000 1100 0000 0100
= 0000 1100 + 1111 1100
= 1 0000 1000
( )
n
B A
n
B
n
A B A
N N
N N N N
2
2 2
2
+ =
+ =
n
B A B A
N N N N 2
2
+ = +
Outside the n-bit range.
Outside the 8-bit range.
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1.5 Numeric Notation Used in Computers
It is known that the computer uses binary arithmetic.
That is, numbers are stored in its binary form.
Depending on the kind of problem we are solving, we
may require values of different range. In computer
systems, numbers can be stored in the following
notations
Integer Notation
Floating point notation
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January 14 Chapter 1 NUMBER SYSTEM AND CODES Page 1.70
1.5.1 Integer Notation
In computer, we can store integer value as signed or unsigned
integer.
Unsigned integer
Say, an 8-bit unsigned integer
Range: 0 ~ 255
Signed integer used 2s compliment representation
Say, an 8-bit signed integer
Range: -128 ~ 127
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
0 1 0 1 0 1 0 1 =85
10
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
1 1 1 1 0 1 0 1 =-11
10
Sign bit
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1.5.2 Floating Point Notation
an n-bit normalised floating point representation is defined as
Consists of 3 parts, the sign, mantissa and Exponent.
Exponent part:
uses bit23 to bit30.
uses excess 127 representation
Range = -126 ~ 127
Mantissa part:
uses bit 31 and bit0 to bit22
range: 1.0 s Mantissa < 2
1.0
2
is implied.
signed part:
bit 31 is used as sign indicator.
i.e. Signed-Magnitude Representation

31 30 thru 23 22 through 0
Sign
Bit
Exponent Mantissa
Assumed position of radix
point, with 1.0
2
hidden
( ) { } 2 1 and 1 , 0 , 2 1
2 2
2
< s e = F s F N
E
s
f
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1.5.2 Floating Point Notation
Example:
The number 101101.11001
2
is to be represented in its
Floating point notation.
101101.110012 = 1.0110111001
2
x 2
5
Sign bit = 0 (positive)
Exponent = 5 + 127 = 132
10
= 10000100
2
Mantissa = 011 0111 0010 0000 00000000 (1.0
2
is not stored)
Therefore, the entire number is
01000010 00110111 00100000 00000000
Department of Mechanical Engineering
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July 2002 Chapter 2 Digital Electronics Page 2.1
Chapter 2 Digital Electronics
Integrated Circuit Logic
Logic Gates
Combinational Logic
Flip-flops and Latches
Counters and Registers
Synchronous logic design
Encoder and decoder
Multiplexer and de-multiplexer
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2.1 Integrated Circuit Logic
2.1.1 Digital IC Terminology
Current and Voltage Parameters
V
IH
(min) High-Level Input Voltage
V
IL
(max) Low-Level Input Voltage
V
OH
(min) High-Level Output Voltage
V
OL
Low-Level Output Voltage
I
IH
High-Level Input Current
I
IL
Low-Level Input Current
I
OH
High-Level Output Current
I
OL
Low-Level Output Current
+
VOH
-
+
VIH
-
IOH IIH
+
VOL
-
+
VIL
-
IOL IIL
+5V
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2.1.1 Digital IC Terminology
Transition Times and Propagation Delays
Digital circuit response to types of inputs:
logic level(level triggered) and
rapid change in voltage (edge triggered).
RISE TIME (T
R
)
FALL TIME (T
F
)
A logical signal experiences delay
t
PLH
t
PHL
Typical values are 10 to 20 ns.
t
PLH
= t
PLH
and
varies depending on capacitive loading conditions.
1
0
1
0
50%
50%
Input
Output
tPHL tPLH
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2.1.1 Digital IC Terminology
Power Requirements
Sometimes it is given as an
average power dissipation (P
D
)
More commonly, it is indirectly
specified in terms of the current
drain (I
CC
) from the power supply.
Power dissipation is determined by:
P
D
= I
CC
V
CC
Digital logic usually has different I
CC
I
CCH
and I
CCL
Thus, average is used
I
CC
(avg) = (I
CCL
+I
CCH
)/2
or
P
D
= I
CC
(avg) VCC
ICCL
+VCC
ICCL
1
1
1
1
1
1
1
1
1
0
0
0
ICCH
+VCC
ICCH
0
1
1
0
1
1
0
1
1
1
1
1
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2.1.1 Digital IC Terminology
Noise Immunity
NOISE MARGIN:
allowable magnitude of input noise.
HIGH STATE NOISE MARGIN is
VNH = VOH(min) - VIH(min)
LOW STATE NOISE MARGIN is
VNL = VOL(max) - VIL(max)
LOGIC 1
Indeterminate
range
LOGIC 0
LOGIC 1
Indeterminate
range
LOGIC 0
V
OH
(Min)
V
IH
(Min)
V
NH
V
IL
(Max)
V
OL
(Max)
V
NL
2.4
0.4
2.0
0.8
Output Voltage Range Input Voltage Range
Parameter Min (V) Typical (V) Max (V)
V
OH
2.4 3.4
V
OL
0.2 0.4
V
IH
2.0
V
IL
0.8
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July 2002 Chapter 2 Digital Electronics Page 2.6
2.1.1 Digital IC Terminology
Current Sourcing and Current Sinking Logic
Low
IIH
Low
VOH
High
IIL
High
VOL
+VCC
Current Sourcing
Supplies current to load gate in
HIGH state
Current Sinking
receives current from load gate in
LOW state
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2.1.2 TTL Logic
The circuit above shows a basic two input TTL NAND gates (Totem-pole
Output Circuits).
Q1
R1
4 k
R2
1.6 k
R4
130
R3
1 k
Q2
Q3
Q4
D1
X
Output
Input A
Input B
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2.1.2.1 TTL Logic Operation
Low Case
Input B
Q
2
D
2
D
3
D
4
R
1
4k
5v
5 v
Input A
R
2
1.6 k
Q
3
D
1
Q
4
R
4
130
5 v
R
3
1k
ON
Input B
Q
2
D
2
D
3
D
4
R
1
4k
5v
5 v
Input A
R
2
1.6 k
Q
3
D
1
Q
4
R
4
130
5 v
R
3
1k
ON
ON
OFF
OFF
OFF
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July 2002 Chapter 2 Digital Electronics Page 2.9
2.1.2.1 TTL Logic Operation
High Case
Input B
Q
2
D
2
D
3
D
4
R
1
4k
5v
0 v
Input A
R
2
1.6 k
Q
3
D
1
Q
4
R
4
130
5 v
R
3
1k
OFF
Input B
Q
2
D
2
D
3
D
4
R
1
4k
5v
0 v
Input A
R
2
1.6 k
Q
3
D
1
Q
4
R
4
130
5 v
R
3
1k
OFF
OFF
ON
OFF
ON
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2.1.2.2 TTL loading and Fan-out
The number of input an output can drive.
Digital devices has different loading at
different states. Therefore,
Fan-out(High) = I
OH
(max)/I
IH
(max)
Fan-out(Low) = I
OL
(max)/I
IL
(max)
Example:
How many 7400 NAND gate inputs can be
driven by a 7400 NAND output?
Solution:
From the data sheet, we can see that
I
OL
(max) = 16 mA, I
IL
(max) = 1.6 mA
I
OH
(max) = 400 A, I
IH
(max) = 40 A
Therefore,
Fan-out(Low) = 16 mA/1.6 mA = 10
Fan-out(High) = 400 A/40 A = 10
R4
Q3
Q4
D1
OFF
ON
IOL
IIL IIL
R4
Q3
Q4
D1
OFF
ON
IOH
IIH IIH
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July 2002 Chapter 2 Digital Electronics Page 2.11
2.1.2.2 TTL loading and Fan-out
Unit Load:
Some manufacturers specify the device input and output
currents in terms of a unit load (UL), where a unit load is
defined as follows:

=
State LOW in 1.6mA
State HIGH in 40
UL 1
A
Example1:
Say, if a given IC is specified as having a fan-out of 10 UL in
both states, this implies that:
I
OL
(max) = 10 x 1.6 mA = 16 mA
I
OH
(max) = 10 x 40 A = 400 A
Department of Mechanical Engineering
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July 2002 Chapter 2 Digital Electronics Page 2.12
2.1.2.2 TTL loading and Fan-out
Example2:
For the 7400 NAND gate in previous slide we have,
I
OL
(max) = 16 mA, I
IL
(max) = 1.6 mA,
I
OH
(max) = 400 A, I
IH
(max) = 40 A
The output drive capability is
drive capability(Low) = I
OL
(max)/1.6 mA
= 16 mA/1.6 mA = 10 UL
drive capability (High) = I
OH
(max)/40 A
= 400 A/40 A = 10 UL
Therefore, in both HIGH and LOW states, the output can drive
10 UL.
Department of Mechanical Engineering
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July 2002 Chapter 2 Digital Electronics Page 2.13
2.1.2.2 TTL loading and Fan-out
Example2 (Continue):
From previous slide, we have
in both HIGH and LOW states, the output can drive 10 UL.
The input requirement for this IC can be expressed as
Loading(Low) = I
IL
(max)/1.6 mA
= 1.6 mA/1.6 mA = 1 UL
Loading (High) = I
IH
(max)/40 A
= 40 A / 40 A = 1 UL
Therefore, in both HIGH and LOW states, the input has a
loading factor of 1 UL.
That is, if the output of 7400 is connected to identical 7400 IC,
the fan-out in both LOW and HIGH states is
(10 UL/ 1 UL) = 10.
Department of Mechanical Engineering
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July 2002 Chapter 2 Digital Electronics Page 2.14
2.1.2.2 TTL loading and Fan-out
Example3:
Consider the 74S00 IC. The specs are as follows:
I
OL
(max) = 20 mA, I
IL
(max) = 2 mA,
I
OH
(max) = 1000 A, I
IH
(max) = 50 A
The output drive capability is
drive capability(Low) = I
OL
(max)/1.6 mA
= 20 mA/1.6 mA = 12.5 UL
drive capability (High) = I
OH
(max)/40 A
= 1000 A/40 A = 25 UL
Therefore, 74S00 can drive
25 UL in HIGH state and
12.5 UL in LOW state.
Department of Mechanical Engineering
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July 2002 Chapter 2 Digital Electronics Page 2.15
2.1.2.2 TTL loading and Fan-out
Example3 (Continue):
From previous slide, we know that, 74S00 can drive 25 UL in
HIGH state and 12.5 UL in LOW state.
The input requirement for this IC can be expressed as
Loading(Low) = I
IL
(max)/1.6 mA
= 2 mA1.6 mA = 1.25 UL
Loading (High) = I
IH
(max)/40 A
= 50 A/40 A = 1.25 UL
Therefore, 74S00 has a loading factor of 1.25 in both HIGH
and LOW states.
Hence, if the output of 74S00 is connected to identical 74S00
IC, the fan-out will be
25/1.25 = 20 in the HIGH state and
12.5/1.25 = 10 in the LOW state.
Department of Mechanical Engineering
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July 2002 Chapter 2 Digital Electronics Page 2.16
2.1.2.2 TTL loading and Fan-out
Example4:
Consider now the output of 7400 driving the input of 74S00.
From the unit load calculated in previous examples, the fan-
out of 7400 to drive 74S00 in both HIGH and LOW states will
be
10/1.25 = 8.
Home work:
How about 74S00 driving 7400?
Department of Mechanical Engineering
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July 2002 Chapter 2 Digital Electronics Page 2.17
Unused and unconnected inputs
Any unconnected input will be treated as a HIGH
However, it is not advisable to let the input floating.
Although it behave like a HIGH, but this unconnected
input also as an antenna which can pick up stray
signals causing the gate to operate improperly.
Some common method to unconnected inputs is by
Use a pull-up resistor
Connect to ground
Connect the input together
+5V
1 kO
A
B
X=AB
A
B
X=A+B
A
B
X=A+B
A
B
X=AB
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2.1.2.4 Open-collector devices
By removing Q3 and D1
from the totem-pole
circuit for the NAND gate.
The collector of Q4 is
used as the output.
Have to be used with an
additional external pull-up
resistor.
Often used to drive some
load (e.g. LED).
Q1
Q2
Q4
R1 R2
R3
Output
Input
A
B
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2.1.2.5 Tri-state logic devices
Tri-state digital integrated circuit
devices are extremely important
particularly with respect to their
use in computer circuits. As the
name implies, these devices have
three output states.
HIGH state
LOW state
HIGH IMPEDANCE output state
Consist of an extra input called
Enable/disable input
During Enabled state the device
behaves like a NOT gate
During disabled state - the
output seems to be disconnected
to the input.
Input
Enable
Output
Department of Mechanical Engineering
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July 2002 Chapter 2 Digital Electronics Page 2.20
2.2 Logic Gates
AND and NAND Gates
OR and NOR Gates
Truth Table
A B A.B A.B
0 0
0 1
1 0
1 1
0
0
0
1
1
1
1
0
&
0
0
0
7408
&
0
0
0
>=1
0
0
0
7432
>=1
0
0
0
7402
Truth Table
A B A+B A+B
0 0
0 1
1 0
1 1
0
1
1
1
1
0
0
0
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2.2 Logic Gates
XOR Gates
Three-State Outputs
Truth Table
A B A B
0 0
0 1
1 0
1 1
0
1
1
0
=1
0
0
0
A Y
C
A Y
C
Y
A
Off
=

,
,
if C is high
if C is low
Y
A
Off
=

,
,
if C is low
if C is high
Department of Mechanical Engineering
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July 2002 Chapter 2 Digital Electronics Page 2.22
2.2.1 Properties of NAND Gate
The NAND gate is the most versatile digital logic device. All of
the Boolean logic gates we have discussed can be constructed
using only NAND gates. The logic diagrams below illustrate the
NAND-equivalence of various logic gates.
A
B
AB
A
B
A+B
A
B
A+B
A
B
A +B
A
B
A +B
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2.2.2 Some combinatorial logic examples
2.2.2.1 Half Adder
We know from previous chapter that binary addition
satisfy the following condition:
B A B A B A S = + = . .
Truth Table
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
B A C . =
Half Adder
A
B
C
S
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2.2.2.2 Full Adder
Beside the input A and B, the full adder should also
consider the Carry forward from the lesser significant
bit.
1
1 1 1 1
. . . . . . . .


=
+ + + =
n
n n n n
C B A
C B A C B A C B A C B A S
( )
( ) B A C B A
B A B A C B A
C B A C B A C B A C B A C
n
n
n n n n n
+ =
+ + =
+ + + =


. .
. . . .
. . . . . . . .
1
1
1 1 1 1
C
n-1
A B S C
n
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
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2.2.2.2 Full Adder
Therefore, the full adder can be constructed from two
half adder as shown below.
Full Adder
Half Adder
A
n
B
n
Half Adder
S
n
C
n-1
C
n
FA
B
C
-1
C
S
A
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2.2.2.2 Full Adder
A 4-bit adder can be constructed by cascading 4 FAs
as shown below.
FA
0
A B
C
-1
C
S
FA
1
A B
C
-1
C
S
FA
2
A B
C
-1
C
S
FA
3
A B
C
-1
C
S
Carry
S
0
S
1
S
2
S
3
B
0
B
1
B
2
B
3
A
3
A
2
A
1
A
0
Department of Mechanical Engineering
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July 2002 Chapter 2 Digital Electronics Page 2.27
2.2.2.2 Full Adder
Note:
Sum and carry bits do not appear simultaneously.
Carry bits have to propagate from one stage to the next.
Inherent propagation delays associated with this.
Output of each FA is therefore not stable until the carry-in
from the previous stage is calculated.
Outputs become stable from right to left as the carries ripple
through the chain.
Commercial Adder IC - 74283
Department of Mechanical Engineering
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2.3 flip-flops and Latches
In general, digital systems
are made up of combinational
circuits and memory elements.
An important memory
element is the flip-flop (an
assembly of logic gates).
Sometime called as latch or
bistable multivibrator.
Combinational
logic gates
Memory
elements
Combinational
outputs
Memory outputs
External inputs
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Tutorial 1
Submit by 26 J an 2012 (Thur) 23:59hr
Submit to IVLE Workbin/Student_submission/Tutorial 1
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SET
CLEAR
Q
1
0
1
0
1
0
T
1
T
2
T
3
T
4
T
5
SET
CLEAR
Q
1
0
1
0
1
0
T
1
T
2
T
3
T
4
T
5
SET
CLEAR
Q
1
0
1
0
1
0
T
1
T
2
T
3
T
4
T
5
SET
CLEAR
Q
1
0
1
0
1
0
T
1
T
2
T
3
T
4
T
5
2.3.1 NAND gate Latch:
SET CLEAR Q
1 1 No change
0 1 1
1 0 0
0 0
Q=Q=1
invalid!
SET
Q
Q
CLEAR
SET
CLEAR
Q
1
0
1
0
1
0
T
1
T
2
T
3
T
4
T
5
Department of Mechanical Engineering
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Application example of Flip-flop
An application of the SC latch is to use it to prevent
phenomena called the contact bounce.
V
OUT
+5V
1
2
Switch to
position 2
Switch come
to rest in
position 2
Bouncing
V
OUT
+5V
1
2
S
C
Q
+5V
Switch to
position 2
Switch back
to position 1
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2.3.2 Clocked Flip-Flops
Digital systems can operate either asynchronously or synchronously.
Asynchronous systems: outputs can change state at any time.
Synchronous systems: outputs state change determined by clock.
A clock is a square pulse train that is distributed to most part of the system
such that the outputs change state only when the clock makes a transition.
Two way of synchronization:
Positive-going transition (PGT)
Negative-going transition (NGT)
Synchronizing action of the clock is accomplished by clocked flip-flops that
are designed to change states on one of the clock transition.
NGT
Clk
PGT
Time
Department of Mechanical Engineering
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2.3.2 Clocked Flip-Flops
A typical clocked flip-flop consists of:
clock input (CLK or CK or CP)
two output usually termed as Q and Q where Q is also a
complement of Q.
one or more control inputs which have not have effect on Q
until the flip-flop is clocked.
2 initialization input (to be discussed later) to momentarily
change the state of Q.
NGT activated flip-flop
PGT activated flip-flop
Control
inputs
Clk
Q
Q
Init i/p
Control
inputs
Clk
Q
Q
Init i/p
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July 2002 Chapter 2 Digital Electronics Page 2.34
2.3.3 Making of Clocked S-C Flip-Flop
The NAND flip-flop in section 2.2.2 does not have any enable/disable facilities. In
order to have some level of control when the inputs can controls the output Q, we add
two more NAND gate at the input as such.
SET
Q
Q
CLEAR
SET
E
CLEAR
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2.3.3 Making of Clocked S-C Flip-Flop
To acquire an edge-triggered flip-flop, we insert an
edge detector before pin E.
Clk
SET
Q
Q
CLEAR
SET
CLEAR
Edge
detector
Clk*
Positive-going transition Negative-going transition
CLK CLK
CLK*
CLK
CLK
CLK*
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2.3.3 Making of Clocked S-C Flip-Flop
Positive Edge Triggered SC Flip-Flop
S
C
Q
1
0
1
0
1
0
Clk
1
0
S
C
Q
Q
S
C
Q
1
0
1
0
1
0
Clk
1
0
S
C
Q
1
0
1
0
1
0
Clk
1
0
S
C
Q
1
0
1
0
1
0
Clk
1
0
S
C
Q
1
0
1
0
1
0
Clk
1
0
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2.3.3 Making of Clocked S-C Flip-Flop
Asynchronous Inputs
Most clocked flip-flops also have one or more asynchronous inputs
which operate independently.
Used to set/clear the flip-flop.
SC Flip-flop
Set
Clear
Q
Q
S
CLK
C
Clocked Mode
Not Allowed
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2.3.4 Clocked J -K Flip-Flop
PGT J K Flip-Flop
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NGT J -K Flip-Flop
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J K Flip-flop with Asynchronous Inputs
J
K
Q
Q
Preset
Clear
Preset Clear Q
1
Clocked Mode
0
1
Not Allowed
1
0 1
1 0
0 0
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J K Flip-flop with Asynchronous Inputs
J
K
Q
Q
PRE
CLR
+5V
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2.3.5 Clocked D Flip-Flop
D Q
Q
D Clk Q
0 | 0
1 | 1
R
C
Q
Q
D
Clk
J
K
Q
Q
D
Clk
Equivalent D Flip-flop by RC Flip-Flop
Equivalent D Flip-flop by J K Flip-Flop
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2.3.6 D Latch (74 373)
A digital device that stores a
1 or a 0 on its output.
if the enable input EN is low,
the logic level present on the
input will have no effect on
the Q and Q outputs.
if the enable input is high, a
high or a low on the D input
will be passed to the Q output.
when the enable input is
made low again, the state on
Q at that time will be latched
there.
D Q
Q EN
EN D Q
0 X Q
0
(no change)
1 0 0
1 1 1
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2.3.7 Timing Consideration for Flip-flop
Setup and Hold Times
Two timing requirements must be met if a clocked FF is to respond
reliably to its control inputs when the active CLK transition occurs.
Setup time, t
S
, is the time interval immediately preceding the active
transition of the CLK signal during which the synchronous input has to be
maintained at the proper level. (Usually specified in t
S
(min)).
Hold time, t
H
, is the time interval immediately following the active
transition of the CLK signal during which the synchronous input has to be
maintained at the proper level. (Usually specified in t
H
(min)).
Synchronous
control input
Clock input
t
H
Hold time
t
s
Setup time
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2.3.7 Timing Consideration for Flip-flop
Propagation Delay
Whenever a signal is to change the state of a FFs output,
there is a delay from the time the signal is applied to the time
when the output makes its change.
Usually referred to as t
PLH
and t
PHL
Maximum Clocking Frequency
The highest frequency that may be applied to the CLK input
of a FF.
Usually referred to as fMAX
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2.3.7 Timing Consideration for Flip-flop
Clock Pulse HIGH and LOW Times
The minimum time duration that the clock must remain LOW
before it goes HIGH, t
W
(L)
The minimum time duration that the clock must remain HIGH
before it goes LOW, t
W
(H)
0
1
Clock
t
W
(H) t
W
(L)
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2.3.7 Timing Consideration for Flip-flop
Asynchronous Active Pulse Width
The minimum time duration that a PRESET or CLEAR input
has to be kept in its active state in order to reliably set or
clear the FF.
0
1
PRE
or
CLR
t
W
(L)
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2.4 Counters and Registers
2.4.1 Registers
A register is a device you use to store
some information, in its simplest form, a
flip-flop.
However, one flip-flop can only store
two possible values, i.e. a ONE or a
ZERO.
S
D Q
Clk Q
R
Write pulse
Storage
+5V
Input
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2.4 Counters and Registers
2.4.1 Registers
We usually group a few flip-flop to form one set of storage e.g.
1 nibble 4 bits
1 byte 8 bits
The most commonly used group is byte (8 flip-flop).
Write
pulse
Storage
+5V
I
1
I
0
Input
S
D Q
Q
R
S
D Q
Q
R
S
D Q
Q
R
S
D Q
Q
R
S
D Q
Q
R
S
D Q
Q
R
S
D Q
Q
R
S
D Q
Q
R
I
3
I
2
I
5
I
4
I
7
I
6
Q
1
Q
0
Q
3
Q
2
Q
5
Q
4
Q
7
Q
6
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2.4.1.1 Transferring of Registers content
Parallel transfer of value from
register A to Register B
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2.4.1.1 Transferring of Registers content
Serial Transfer of value from Register A to Register B(Shift Register)
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2.4.1.1 Transferring of Registers content
Asynchronous Shift Register
In previous slide, synchronous input D
are used for serial transfer. How to pre-
set the content of register A?
Solution:
We make use of the asynchronous input.
D Q
Set
Clear
X PL Set . =
( )
( )
Set PL
X PL PL
PL X PL
PL PL X PL
X PL Clear
.
. .
.
. .
.
=
+ =
+ =
=
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Asynchronous Shift Register
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2.4.2 Counters
2.4.2.1 Asynchronous (Ripple)
Counters
Assume all unconnected terminal
as connected to HIGH
FF outputs can only toggle
(J =K=1).
Clock connected to first (LSB) FF
only. Succeeding FFs get their
clock input from output of
previous FF.
Each FF A, B, C, and D
successively halves the clock
input frequency.
Counter counts in sequence
from 0000 (0) 1111 (15)
Counter has 16 distinct count
states, and is called a mod-16
counter.
In general, N-FFs connected up
this way will have 2
N
states a
mod-2
N
counter.
Clk
0
J A
Set
Clear
K
0
J B
Set
Clear
K
0
J C
Set
Clear
K
0
J D
Set
Clear
K
A
B
C
D
Clk
1
J A
Set
Clear
K
0
J B
Set
Clear
K
0
J C
Set
Clear
K
0
J D
Set
Clear
K
A
B
C
D
Clk
0
J A
Set
Clear
K
1
J B
Set
Clear
K
0
J C
Set
Clear
K
0
J D
Set
Clear
K
A
B
C
D
Clk
1
J A
Set
Clear
K
1
J B
Set
Clear
K
0
J C
Set
Clear
K
0
J D
Set
Clear
K
A
B
C
D
Clk
0
J A
Set
Clear
K
0
J B
Set
Clear
K
1
J C
Set
Clear
K
0
J D
Set
Clear
K
A
B
C
D
Clk
1
J A
Set
Clear
K
1
J B
Set
Clear
K
1
J C
Set
Clear
K
0
J D
Set
Clear
K
A
B
C
D
Clk
0
J A
Set
Clear
K
0
J B
Set
Clear
K
0
J C
Set
Clear
K
1
J D
Set
Clear
K
A
B
C
D
Clk
1
J A
Set
Clear
K
1
J B
Set
Clear
K
1
J C
Set
Clear
K
1
J D
Set
Clear
K
A
B
C
D
Clk
0
J A
Set
Clear
K
0
J B
Set
Clear
K
0
J C
Set
Clear
K
0
J D
Set
Clear
K
A
B
C
D
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2.4.2.2 Counter with mod-X < 2N
Assume counter starts from 0.
Find which FFs will be in
HIGH state when count = X.
Feed those FF outputs to a
NAND gate.
Connect NAND gate output to
the asynchronous CLR input
of all FFs.
Example: A Mod-6 Counter
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More examples
Mod-14 Counter
J
K
A J
K
B J
K
C
Clr Clr Clr
J
K
D
Clr
Mod-10 Counter
J
K
A J
K
B J
K
C
Clr Clr Clr
J
K
D
Clr
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2.4.2.3 Ripple Counter that counts down
Connect complements of FF outputs to clock inputs of
succeeding FFs.
J
K
A
+5V
J
K
B
+5V
J
K
C
+5V
J
K
D
+5V
A B C D
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2.4.2.4 Problems in Ripple Counters.
Accumulation of Propagation Delay
Ripple counters are easy to implement but have one major
drawback:
Cant operate beyond a limiting frequency. So, only used for low
freq. applications.
The limitation is due to the propagation delays of the FFs in the
chain add up:
Clock input to FF1: t
0
(clock transition time)
Clock input to FF2: t
0
+ t
pd
Clock input to FF3: t
0
+ 2 t
pd
..
Clock input to FFn: t
0
+ (n-1) t
pd
This implies that the n
th
FF rather than changing state at t
0
it
changes state at t
0
+ n t
pd
.
Hence t
clock
> n t
pd
or f
max
s 1/(n t
pd
)
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Effect of porpagation delay Mod 8 counter
Case I: Period = 1 us
Propagation delay after NGT of
the Clock Signal
t
pd
(Max) = 150ns << 1 ms -- OK
Case II: Period = 100 ns
Note:
No 100 in the counts!!!
A
1 2 3 4
5
Clk
B
C
1000ns
50ns
100ns
150ns
A
1 2 3 4
5
Clk
B
C
100ns
50ns
100ns
150ns
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Maximum allowable clock frequency
Example:
A 4-bit ripple counter is constructed using the 74LS112 J -K flip-flop.
From the spec., we have
t
PLH
= 16 ns and
t
PHL
= 24 ns.
To calculate the maximum allowable clock frequency, we use the worst
case (i.e. tpd = 24ns)
MHz
ns t n
f
pd
4 . 10
24 4
1 1
max
=

s
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Decoding Glitches
Another problem encountered with ripple counters if the states have to be
decoded.
Again, due to propagation delays.
Example:
FF and decoding waveform for a mod-4 ripple counter showing glitches at X0 and X2 outputs.
J
K
A J
K
B
A B
X
0
X
1
X
2
X
3
Clk
1
0
#1 #2 #3 #4
Clk
1
0
A
1
0
B
Temporay
00 state
Temporay
10 state
1
0
X
0
1
0
X
1
1
0
X
2
1
0
X
3
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Decoding Glitches
These decoding glitches can be eliminated by a strobe signal.
t
D
is chosen be greater than the total time it takes the counter to
reach a stable count (depends on FF delays and number of FFs).
This method need not be used when the decoder drives a display
glitch is not visible
But must be used when decoder drives other circuitry.
X
0
A
B
X
1
A
B X
2
A
B
X
3
A
B
Strobe
signal
1
0
#1 #2 #3 #4
Clk
1
0
Strobe
Decoder
disabled
t
D
Decoder enabled
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2.4.2.5 IC Asynchronous Counters (74x293)
Consist of 4 J K flip-flops with output
Q
0
(LSB), Q
1
, Q
2
and Q
3
(MSB)
The clock inputs of Q
0
and Q
1
are
externally accessible and labeled as
CP
0
and CP
1
, respectively.
Each FF has an asynchronous CLEAR
input, C
D
. These are connected
together to the output of a 2-input
NAND gate with inputs MR
1
and MR
2
Need MR
1
= MR
2
= 1 to reset the
counter to 0000.
Q
1
, Q
2
and Q
3
are already connected
as a 3-bit ripple counter. FF Q
0
is
not connected to anything internally.
(Some flexibility here)
J
K
Q
1
1
C
D
J
K
Q
1
1
C
D
J
K
Q
1
1
C
D
J
K
Q
1
1
C
D
Q
1
Q
2
Q
3
(MSB)
Q
0
(LSB)
CP
0
CP
1
MR
1
MR
2
74293
Q
0
Q
1
Q
2
Q
3
MR
1
MR
2
CP
1
CP
0
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Some Examples
Example 1: Mod-16 Counter Example 2: Mod-10 Counter
74293
Q
0
Q
1
Q
2
Q
3
MR
1
MR
2
CP
1
CP
0
74293
Q
0
Q
1
Q
2
Q
3
MR
1
MR
2
CP
1
CP
0
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More Example
Example 3: Mod-50 Counter
74293
Q
0
Q
1
Q
2
Q
3
MR
1
MR
2
CP
1
CP
0
74293
Q
0
Q
1
Q
2
Q
3
MR
1
MR
2
CP
1
CP
0
Not
Used
f
in
/10
f
in
/50
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2.4.2.6 Synchronous (Parallel Counters)
The propagation delay problem encountered with ripple counters can be
overcome by using synchronous or parallel counters.
Technique used:
When J =K=0, output does not change on the clock pulse
When J =k=1, output toggles on the clock pulse.
The total delay involved in this sync. counter is
tpd = tpd(FF) + tpd(AND)
Hence counter operates at higher frequency than corresp. ripple counter.
J
K
A J
K
B J
K
C J
K
D
Input
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2.4.2.7 Synchronous Down and Up Counters
When Counting up
A = 1 to toggle B
A = B = 1 to toggle C
When Counting down
A = 0 to toggle B
A = B = 0 to toggle C
recycle
C B A
7 1 1 1
6 1 1 0
5 1 0 1
4 1 0 0
3 0 1 1
2 0 1 0
1 0 0 1
0 0 0 0
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2.4.2.8 Presettable Counters
Many synchronous counters that are available as ICs
are designed to be presettable
Can be pre-set to any desired count asynchronously
or synchronously.
Clock
J
K
Q
A
Clr
Pre J
K
Q
B
Clr
Pre J
K
Q
C
Clr
Pre
P
2
P
1
P
0 PL
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2.4.2.9 IC Presettable Counter (74x193)
Pin Description
CP
U
Count-up clock input (PGT)
CP
D
Count-down clock input (PGT)
MR Asynchronous master reset input (active HIGH)
PL - Asynchronous parallel load input (active LOW)
P
0
-P
3
Parallel data inputs
Q
0
-Q
3
flip-flop outputs
TC
U
Terminal count-up (carry) output (active LOW)
TC
D
Terminal count-down (borrow) output (active
LOW)
MR PL CP
U
CP
D
Mode
H X X X Asyn. reset
L L X X Asyn. preset
L H H H No change
L H | H Count up
L H H | Count down
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(74x193) Example 1 (Up-counter)
Parallel data inputs = 1011
Initial flip-flops output = 0000
1
0
CP
U
1
0
PL
1
0
MR
1
0
Q
0
1
0
Q
1
1
0
Q
2
1
0
Q
3
1
0
TC
U
t
0
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
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(74x193) Example 2 (Down-counter)
1
0
CP
D
1
0
PL
1
0
Q
0
1
0
Q
1
1
0
Q
2
1
0
Q
3
1
0
TC
D
t
0
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
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2.4.2.10 Synchronous Counter Design
A subset of Sequential Circuit Design
Approach:
Given the state diagram of a counter realize it using common FFs and
combinational logic.
All FFs are clocked at the same time.
Must make sure the logic level at every FFs input pins stabilize to a
correct level before each clock pulse.
Combinational
Logic
FFs
E
x
t
e
r
n
a
l
I
n
p
u
t
Clk
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2.4.2.10 Synchronous Counter Design
Choices of flip-flops
For a given choice of flip-flop, we need to know an appropriate
input to its synchronous input such that it output changes as desired.
For example:
For J K flip-flop to change from 0 to 1, we have the choice of J =1,
K=0 or J =1, K=1.
Hence, J =1, and K = X (either 0 or 1).
0
Q
0
Transition
J K Flip-flop D Flip-flop
J K D
00
01 1 X 1
0 X 0
10 X 1 0
11 X 0 1
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2.4.2.10 Synchronous Counter Design
Design Steps
1. Determine the desired number of bits and choice of
FF used.
2. Draw the state transition diagram showing all
possible states.
3. Use the state transition diagram to set up a table
that list all PRESENT states and their NEXT states
4. Add the column to this table for each flip-flop input.
5. Design the logic circuits to generate the levels
required at each flip-flop input.
Department of Mechanical Engineering
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July 2002 Chapter 2 Digital Electronics Page 2.75
Synchronous Counter Design Example 1
Design a 3-bit counter that counts from 000 to 111 and back to 000.
Step 1: Since it is 3 bit counter, we need 3 flip-flops. Say, use D flip-
flops.
Step 2: State transition diagram. Determine the desired number of
bits and choice of FF used.
000
001
010
011
100
101
111
110
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Synchronous Counter Design Example 1
Design a 3-bit counter that counts from 000 to 111 and back to 000.
Step 3&4: Generate the truth table
Present State Next State Flip-flops input
Q
2
Q
1
Q
0
Q
2
Q
1
Q
0
D
2
D
1
D
0
0 0 0
000
010 110
100
101 011
001 111
0 0 1 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
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Synchronous Counter Design Example 1
Design a 3-bit counter that counts from 000 to 111 and back to 000.
Step 5: Logic Design for flip-flops.
Present State Flip-flops input
Q
2
Q
1
Q
0
D
2
D
1
D
0
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0
0
0 2 0 2
0 1 2 0 1 2 0 1 2 0 1 2 0
. .
. . . . . . . .
Q
Q Q Q Q
Q Q Q Q Q Q Q Q Q Q Q Q D
=
+ =
+ + + =
( ) ( )
( )
0 1
0 1 0 1
0 1 0 1 2 0 1 0 1 2
0 1 2 0 1 2 0 1 2 0 1 2 1
. .
. . . . . .
. . . . . . . .
Q Q
Q Q Q Q
Q Q Q Q Q Q Q Q Q Q
Q Q Q Q Q Q Q Q Q Q Q Q D
=
+ =
+ + + =
+ + + =
0 2 1 2 0 1 2
0 1 2 0 1 2 0 1 2 0 1 2 2
. . . .
. . . . . . . .
Q Q Q Q Q Q Q
Q Q Q Q Q Q Q Q Q Q Q Q D
+ + =
+ + + =
Department of Mechanical Engineering
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Synchronous Counter Design Example 1
Homework: Repeat this with J K flip-flops
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Synchronous Counter Design Example 2
Design a 3-bit counter that counts from
000001010011100000
Step 1: Since it is 3 bit counter, we need 3 flip-flops. Say, use J K flip-
flops.
Step 2: State transition diagram.
000
001
010
011
100
Department of Mechanical Engineering
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Synchronous Counter Design Example 2
Design a 3-bit counter that counts from 000 to 111 and back to 000.
Step 3&4: Generate the truth table
Present State Next State Flip-flops input
Q
2
Q
1
Q
0
Q
2
Q
1
Q
0
J
2
K
2
J
1
K
1
J
0
K
0
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 0 0 0
0 X
0 X
1 X
X 1
X X
X X
X X
000
010
100
011
001
1 0 1 X X X
1 1 0 X X X
1 1 1 X X X
J K
00 0 X
01 1 X
10 X 1
11 X 0
1 X
X X
X 0
0 1
X X
X X
X X
X 1
1 X
X 1
0 X
X X
X X
X X
Department of Mechanical Engineering
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July 2002 Chapter 2 Digital Electronics Page 2.81
Synchronous Counter Design Example 2
Design a 3-bit counter that counts from 000 to 111 and back to 000.
Step 5: Logic Design for flip-flops.
Present State FFs input
Q
2
Q
1
Q
0
J
0
K
0
0 0 0 1 X
0 0 1 X 1
0 1 0 1 X
0 1 1 X 1
1 0 0 0 X
1 0 1 X X
1 1 0 X X
1 1 1 X X
2 0
Q J =
1
0
= K
Department of Mechanical Engineering
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July 2002 Chapter 2 Digital Electronics Page 2.82
Synchronous Counter Design Example 2
Design a 3-bit counter that counts from 000 to 111 and back to 000.
Step 5: Logic Design for flip-flops.
Present State FFs input
Q
2
Q
1
Q
0
J
1
K
1
0 0 0 0 X
0 0 1 1 X
0 1 0 X 0
0 1 1 X 1
1 0 0 0 X
1 0 1 X X
1 1 0 X X
1 1 1 X X
0 1 1
Q K J = =
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Synchronous Counter Design Example 2
Design a 3-bit counter that counts from 000 to 111 and back to 000.
Step 5: Logic Design for flip-flops.
Present State FFs input
Q
2
Q
1
Q
0
J
2
K
2
0 0 0 0 X
0 0 1 0 X
0 1 0 0 X
0 1 1 1 1
1 0 0 X X
1 0 1 X X
1 1 0 X X
1 1 1 X X
Q
0
Q
2
Q
0
Q
0
Q
2
Q
1
Q
1
0 0 1 0
X X X X
J
2
0 1 2
.Q Q J =
1
2
= K
Department of Mechanical Engineering
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Synchronous Counter Design Example 2
Hence, we have
0 1 2
.Q Q J = 1
2
= K
0 1 1
Q K J = =
2 0
Q J =
1
0
= K
J Q
Q
2
K
J Q
Q
1
K
J Q
Q
0
K
Q
0
Q
1
Q
2
1
1
Clk
Department of Mechanical Engineering
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2.4.2.11 Synchronous vs. asynchronous circuit designs
Sync. operations generally preferred to async.
operations, since latter require great care to address
problems such as
Races due to unequal path delays.
Transients and glitches which can cause incorrect
operation.
Output changes that depend on order of async. input
changes.
Synchronous circuits bypass these problems by use of
the clock which allows outputs to change only at
discrete time instants.
This allows time for transients and glitches to settle
down, races to be resolved etc.
Department of Mechanical Engineering
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2.4.2.12 Counter Applications: Digital Clock
Pulse
shaper
Mod-50
Counter
Mod-2 Mod-10 Mod-6 Mod-10 Mod-6 Mod-10
Decoder/
Display
Decoder/
Display
Decoder/
Display
Decoder/
Display
Decoder/
Display
Decoder/
Display
50 Hz
Main
50 pps 1 pps
"Seconds"
section
0-9
Units
0-9
Units
0-9
Units
0-5
Tens
0-5
Tens
0-1
Tens
"Minutes"
section
"Hours" section
Department of Mechanical Engineering
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2.4.2.13 Other Counters
Register Based Counters - Ring
Counter
A circulating arrangement where a
single 1 moves from FF to FF.
In most instances, only a single 1
circulates.
Counter is initialized by presetting
a 1 into one FF and clearing the
rest.
Mod-N counter needs N FFs (more
hardware than other counters for
same mod-#).
N FFs mod-N counter.
On the other hand, this counter
does not need any decoding gates
at all (saving).
Example:
A Mod-4 ring counter consists of 4
flip-flops.
0001
0010
0100
1000
D Q
Q
d
D Q
Q
c
D Q
Q
b
D Q
Q
a
0
1
0
1
0
1
0
1
Clk
Q
d
Q
c
Q
b
Q
a
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July 2002 Chapter 2 Digital Electronics Page 2.88
2.5 Encoders, Decoders
2.5.1 Decoders
2.5.1.1 3-8 Decoders
A decoder is a circuit element that will
decode an N-bit code.
It activates an appropriate output line as a
function of the applied N-bit input code.
Example: a 3-8 decoder.
A
0
A
1
A
2
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
A
2
A
1
A
0
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
A decoder can have up to 2N output lines for N
inputs.
Department of Mechanical Engineering
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MSI 3-8 decoder (74138)
74138
1-of-8 decoder
A
0
A
1
A
2
O
0
123
E
O
1
O
2
O
3
O
4
O
5
O
6
O
7
E
1
E
3
E
2
123
E
1
E
3
E
2
A
2
A
0
A
1
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Department of Mechanical Engineering
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MSI 3-8 decoder (74138)
Example:
Use 4 74138 decoders to set up a 1-32 decoder.
74138
A
0
A
1
A
2
123
E
01234567
74138
A
0
A
1
A
2
123
E
01234567
74138
A
0
A
1
A
2
123
E
01234567
74138
A
0
A
1
A
2
123
E
01234567
A
0
A
1
A
2
A
3
A
4
O
0
- - - - - - -O
7
O
8
-- - - - - - O
15
O
16
-- - - - -- O
23
O
24
-- - - - -- O
31
Department of Mechanical Engineering
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2.5.1.2 BCD-to-Decimal Decoder
Used whenever an output or
group of outputs is to be activated
only on the occurance of a specific
combination of input levels.
Commercially available decoders
are
7442 BCD-to-decimal decoder, or
7445 BCD-to-decimal
decoder/driver (Open collector
version)
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2.5.1.2 BCD-to-Decimal Decoder
Example:
Design a circuit which consists of 5 LEDs arranged in a line
such that these LED will lights up in the following sequence.
L1 ON for 1 s and OFF for 1s,
L2 ON for 1 s and OFF for 1s,
L3 ON for 1 s and OFF for 1s,
L4 ON for 1 s and OFF for 1s, and
L5 ON for 1 s and OFF for 7s.
After that L1 start again and repeat itself.
Solution:
7445
b
3
b
2
b
1
b
0
O
9
O
8
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
74293
O
3
O
2
O
1
O
0
CP
1
CP
0
MR
2
MR
1
5V
1pps
Department of Mechanical Engineering
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2.5.1.3 BCD to 7 Segment decoder
Converts a BCD number into signals required to display that
number on a 7-segment display.
7-segment displays are of 2 types:
common anode - all LED anodes connected active low
common cathode - all LED cathodes connected active High.
Each segment is an LED which will light when a logic signal is
applied to it.
a
b
c
d
e
f
g
Department of Mechanical Engineering
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2.5.1.3 BCD to 7 Segment decoder
Commercial BCD to 7 Segment decoder 7447 and 7448
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Department of Mechanical Engineering
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2.5.1.3 BCD to 7 Segment decoder
Uses of RBO and RBI
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2.5.2 Encoders
Perform the inverse of the decoding function.
For N different inputs, an encoder is a circuit element
that generates an M-bit binary code (2
M
> N) that
uniquely identifies the input.
Example: An 8-3 encoder.
O
0
O
1
O
2
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
Department of Mechanical Engineering
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July 2002 Chapter 2 Digital Electronics Page 2.97
Decimal to BCD Priority encoder (74147)
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
74147
Decimal
to-BCD
priority
encoder
O
1
O
2
O
3
O
0
Inverted
BCD
I
n
p
u
t
s
Department of Mechanical Engineering
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2.6 Multiplexers & demultiplexers
2.6.1 Multiplexers
A multiplexer (MUX) is a combinational circuit element that
selects data from one of many inputs and directs it to a single
output.
Example: A 4-input multiplexer
I
0
I
1
I
2
I
3
Output
Z
S
0
S
1
I
0
Z
I
1
I
2
I
3
S
0
S
1
S
1
S
0
Output
0 0 Z =I
0
0 1 Z =I
1
1 0 Z =I
2
1 1 Z =I
3
Department of Mechanical Engineering
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8-input multiplexer (74151)
Multiplexer has an active-low ENABLE pin
When E=0, the select inputs S2S1S0 will select one data input (I
0
~I
7
) for
passage to output Z.
When E=1, multiplexer is disabled.
Both normal and inverted output are provided
74151
8-input MUX
I
0
I
1
I
2
I
3
I
4
I
5
I
6
I
7
S
0
S
1
S
2
E
Z Z
E S
2
1
S
1
S
0
X X X 1 0
0 0 0 0 I
0
I
0
Z Z
0 0 0 1 I
1
I
1
0 0 1 0 I
2
I
2
0 0 1 1 I
3
I
3
1 0 0 0 I
4
I
4
1 0 0 1 I
5
I
5
1 0 1 0 I
6
I
6
1 0 1 1 I
7
I
7
Department of Mechanical Engineering
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8-input multiplexer (74151)
S
0
S
1
S
2
E
I
0
I
1
I
2
I
3
I
4
I
5
I
6
I
7
Z Z
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Quad Two-input MUX (74157)
74157
Quad 2 input MUX
I
1a
I
1b
I
1c
I
1d
I
0a
I
0b
I
0c
I
0d
S
E
Z
a
Z
b
Z
c
Z
d
S
E
I
1a
I
1b
I
1c
I
1d
I
0a
I
0b
I
0c
I
0d
Z
a
Z
b
Z
c
Z
d
Department of Mechanical Engineering
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2.6.2 Multiplexer Applications
Logic Function Generation
Truth Table
C B A Z
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
74151 MUX
I
0
I
1
I
3
I
4
I
5
I
6
I
2
I
7
S
0
S
1
S
2
E
Z
1KO
A
B
C
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2.6.2 Multiplexer Applications
- Operation Sequencing
- Say, in an automation process, it requires 7 actions to be
activated in a pre-scribed sequence A
1
~A
7
.
- Each of this actuator can be activated by a TTL HIGH signal
- An end-of-action sensor is attached to its actuator to detect
the completion of the action S
1
~S
7
.
- Solution: We can break the problem into smaller block as
follows.
- Counter to keep track of the sequence order
- Decoder to decode counter output to activate corresponding
actuator
- Multiplexer to multiplex the corresponding sensor information
for decision making
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2.6.2 Multiplexer Applications
- Operation Sequencing
- Counter to keep track of the sequence order
- Required a count of 1 to 7 plus an idle state (i.e. 8 states)
- Mod-8 ripple counter will be just nice.
Department of Mechanical Engineering
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2.6.2 Multiplexer Applications
- Operation Sequencing
- Decoder Use (74136)
Multiplexer
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2.6.2 Multiplexer Applications Operation Sequencing
Reset
J Q
1
Set
Clear
K Q
J Q
2
Set
Clear
K Q
Start
J Q
0
Set
Clear
K Q
5v
Physical Process
Actuator
1
Actuator
2
Actuator
3
Actuator
4
Actuator
5
Actuator
6
Actuator
7
Sensor
1
Sensor
2
Sensor
3
Sensor
4
Sensor
5
Sensor
6
Sensor
7
74151
8-input MUX
I
7
I
6
I
5
I
4
I
3
I
2
I
1
I
0
E
S
2
S
1
S
0
Z
Z
74138
3-to-8 decoder
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
E
2
E
1
E
3
A
2
A
1
A
0
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2.6.2 Multiplexer Applications
- Data Routing
7447
BCD to 7 Seg
Decoder/Driver
7-Segment
Display
Units
7447
BCD to 7 Seg
Decoder/Driver
7-Segment
Display
Tens
74157
MUX
E
S
I
1
I
0
Z
a
Z
b
Z
c
Z
d
74157
MUX
E
S
I
1
I
0
Z
a
Z
b
Z
c
Z
d
Select
BCD
Counter
BCD
Counter
BCD
Counter
BCD
Counter
Counter 1 Counter 2
Tens Tens Units Units
Clk #1 Clk #2
(Tens)
(Units)
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2.6.3 Demultiplexers
Demultiplexer takes a single input and distributes it over several outputs.
The select input code determines to which output the DATA input will be
O
0
DEMUX
O
1
O
2
O
3
Data
input
S
0
S
1
Select Outputs
S
2
S
1
S
0
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
0 0 0 0 0 0 0 0 0 0 D
0 0 1 0 0 0 0 0 0 D 0
0 1 0 0 0 0 0 0 D 0 0
0 1 1 0 0 0 0 D 0 0 0
1 0 0 0 0 0 D 0 0 0 0
1 0 1 0 0 D 0 0 0 0 0
1 1 0 0 D 0 0 0 0 0 0
1 1 1 D 0 0 0 0 0 0 0
Example: 1-line-to-8-line Demultiplexer
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July 2002 Chapter 2 Digital Electronics Page 2.109
2.6.3 Demultiplexers
S
0
S
1
S
2
Data
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Department of Mechanical Engineering
N A T I O N A L U N I V E R S I T Y O F S I N A G A P O R E
July 2002 Chapter 2 Digital Electronics Page 2.110
74138 decoder as a demultiplexer
Use the enable input E1 as the the data input I.
Department of Mechanical Engineering
N A T I O N A L U N I V E R S I T Y O F S I N A G A P O R E
July 2002 Chapter 2 Digital Electronics Page 2.111
Demultiplexer Applications
Security Monitoring System
330 O
+5 V
Mod-8
Counter
Q
2
Q
1
Q
0
door 7 door 6
door 0
+5 V
+5 V
+5 V
74LS151
MUX
S
2
S
1
S
0
E
I
0
I
6
I
1
I
2
I
3
I
4
I
5
I
7
Z
74LS138
DEMUX
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
A
2
A
1
A
0
1
2
3
Clock
+5 V
Department of Mechanical Engineering
N A T I O N A L U N I V E R S I T Y O F S I N A G A P O R E
Jan-14 Chapter 3 Microprocessor architecture Page 3.1
Chapter 3 Microprocessor architecture
Making of a microprocessor
Registers, ROMs, Rams and Buses
Digital Arithmetic Circuits
A Very Simple microprocessor
Department of Mechanical Engineering
N A T I O N A L U N I V E R S I T Y O F S I N A G A P O R E
Jan-14 Chapter 3 Microprocessor architecture Page 3.2
3.1 Making of a microprocessor
3.1.1 Registers, ROMs, Rams and Buses
3.1.1.1 Register
A register is a device you use to store some information.
In its simplest form, a flip-flop.
However, one flip-flop can only store two possible values, i.e. a ONE
or a ZERO.
We usually group a few flip-flop to form one set of storage e.g.
1 nibble 4 bits
1 byte 8 bits
1 word 16 bits.
The most commonly used group is byte (8 flip-flop).
S
D Q
Clk Q
R
Write pulse
Storage
+5V
Input
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
I
7
I
6
I
5
I
4
I
3
I
2
I
1
I
0
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
Write
Pulse
3.1 Making of a microprocessor
3.1.1 Registers, ROMs, .
Department of Mechanical Engineering
N A T I O N A L U N I V E R S I T Y O F S I N A G A P O R E
Jan-14 Chapter 3 Microprocessor architecture Page 3.3
3.1.1.1 Register
we sometime wish to share the input and output line together.
This can be achieved by the use of a D Latch as such.
Say, a 1-bit register requires
1 pin for data
1 pin for enable/disable
1 pin for read/write
Make use of tri-state buffer
3.1 Making of a microprocessor
3.1.1 Registers, ROMs, .
D
L
Q
Q
CE
R/W
Data
1
1 0
1
D
L
Q
Q
CE
R/W
Data
0
1 0
0
D
L
Q
Q
CE
R/W
Data
0
0 1
1
W R CE W R CE L / / .
W R CE E / .
Department of Mechanical Engineering
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Jan-14 Chapter 3 Microprocessor architecture Page 3.4
3.1.1.1 Register
Cascading four of these latches form a nibble of register.
3.1 Making of a microprocessor
3.1.1 Registers, ROMs, .
Q
Q
D
L
R/W
CE
Q
Q
D
L
Q
Q
D
L
Q
Q
D
L
Q
0
Q
1
Q
2
Q
3
Department of Mechanical Engineering
N A T I O N A L U N I V E R S I T Y O F S I N A G A P O R E
Jan-14 Chapter 3 Microprocessor architecture Page 3.5
3.1.1.1 Register
To transfer data between Register A & B.
3.1 Making of a microprocessor
3.1.1 Registers, ROMs, .
Q
Q
D
L
R/W
CE
Q
Q
D
L
Q
Q
D
L
Q
Q
D
L
Q
0
Q
1
Q
2
Q
3
To transfer from Register A to B.
1
0
0
0
To transfer from Register B to A.
0
0
1
0
Department of Mechanical Engineering
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Jan-14 Chapter 3 Microprocessor architecture Page 3.6
3.1.1.1 Register
Transferring between accumulator and two other registers
3.1 Making of a microprocessor
3.1.1 Registers, ROMs, .
Acc
R/W
CE
D
3
. . D
0
Reg X
R/W
CE
D
3
. . D
0
Reg Y
R/W
CE
D
3
. . D
0
Read/
Write
X/Y
Department of Mechanical Engineering
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Jan-14 Chapter 3 Microprocessor architecture Page 3.7
3.1.1.1 Register
Transferring many to one
3.1 Making of a microprocessor
3.1.1 Registers, ROMs, .
2-to-4 Decoder
Acc
R/W
CE
D
3
. . D
0
Read/
Write
R/W
CE
D
3
. . D
0
R/W
CE
D
3
. . D
0
R/W
CE
D
3
. . D
0
R/W
CE
D
3
. . D
0
0
1
2
3
A
0
A
1
Department of Mechanical Engineering
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Jan-14 Chapter 3 Microprocessor architecture Page 3.8
3.1.1.1 Register
A 4-Nibble RAM
3.1 Making of a microprocessor
3.1.1 Registers, ROMs, .
R/W
CE
D
0
D
3
R/W
CE
D
0
D
3
R/W
CE
D
0
D
3
R/W
CE
D
0
D
3
Decoder
A
0
D
0
D
3
A
1
D
a
t
a
D
0
D
3
A
0
A
1
R/W
CE
Department of Mechanical Engineering
N A T I O N A L U N I V E R S I T Y O F S I N A G A P O R E
Jan-14 Chapter 3 Microprocessor architecture Page 3.9
3.1.1.2 RAM
Acronym for random access memory,
can be accessed randomly;
Commonly found in computers and other devices,
such as printers.
Usually consists of the following pins
READ/WRITE to control read/write status of the memory
A0~An to select a specific memory cell
D0-D7 to read/write the actual data
CE to enable or disable the chip.
Also known as volatile memory, meaning that they
lose their contents when the power is turned off.
3.1 Making of a microprocessor
3.1.1 Registers, ROMs, .
Department of Mechanical Engineering
N A T I O N A L U N I V E R S I T Y O F S I N A G A P O R E
Jan-14 Chapter 3 Microprocessor architecture Page 3.10
3.1.1.2 RAM
Acronym for random access memory,
can be accessed randomly;
Commonly found in computers and other devices,
such as printers.
Usually consists of the following pins
READ/WRITE to control read/write status of the memory
A0~An to select a specific memory cell
D0-D7 to read/write the actual data
CE to enable or disable the chip.
Also known as volatile memory, meaning that they
lose their contents when the power is turned off.
3.1 Making of a microprocessor
3.1.1 Registers, ROMs, .
Department of Mechanical Engineering
N A T I O N A L U N I V E R S I T Y O F S I N A G A P O R E
Jan-14 Chapter 3 Microprocessor architecture Page 3.11
3.1.1.3 ROM
Acronym for read-only memory
Computer memory on which data has been prerecorded. Once data has
been written onto a ROM chip, it cannot be removed and can only be
read.
Unlike RAM, ROM retains its contents even when the computer is turned
off. ROM is referred to as being nonvolatile, whereas RAM is volatile.
usually consists of the following pins
A0~An to select a specific memory cell
D0-D7 to read the actual data
CE to enable or disable the chip.
PCs usually contain ROM that stores critical programs such as the
program that boots the computer.
(e.g. BIOS in your IBM compatible PC)
Also used extensively in calculators and peripheral devices such as laser
printers, whose fonts are often stored in ROMs.
Variation of a ROM are
PROM (programmable read-only memory).
EPROM (erasable programmable read-only memory)
EEPROM (electrically erasable programmable read-only memory)
Flash RAM
3.1 Making of a microprocessor
3.1.1 Registers, ROMs, .
Department of Mechanical Engineering
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Jan-14 Chapter 3 Microprocessor architecture Page 3.12
3.1.1.4 Concepts of bus
Some Bus Example
3.1 Making of a microprocessor
3.1.1 Registers, ROMs, .
4 nibble RAM
D
0
D
3
A
0
A
1
R/W
CE
4 nibble RAM
D
0
D
3
A
0
A
1
R/W
CE
4 nibble RAM
D
0
D
3
A
0
A
1
R/W
CE
4 nibble RAM
D
0
D
3
A
0
A
1
R/W
CE
MicroP
D
0
D
3
A
0
A
3
R/W
CE
Decoder
Data Bus
Address Bus
Control Bus
Department of Mechanical Engineering
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Jan-14 Chapter 3 Microprocessor architecture Page 3.13
3.1.2 Digital Arithmetic Circuits
From previous chapter, we have constructed a full
adder
3.1 Making of a microprocessor
4 Bit Adder
FA
B
C
-1
C
S
A
FA
B
C
-1
C
S
A
FA
B
C
-1
C
S
A
FA
B
C
-1
C
S
A
A
3
A
2
A
1
A
0
B
3
B
2
B
1
B
0
S
3
S
2
S
1
S
0
C
0
C
4
Department of Mechanical Engineering
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Jan-14 Chapter 3 Microprocessor architecture Page 3.14
Adding with register
3.1 Making of a microprocessor
3.1.2 Digital Arithmetic Circuits
Reg A
d
0
d
1
d
2
d
3
q
0
q
1
q
2
q
3
R/W
CE
Reg B
d
0
d
1
d
2
d
3
q
0
q
1
q
2
q
3
R/W
CE
D-Latches
d
0
d
1
d
2
d
3
q
0
q
1
q
2
q
3
L
Tristates
d
0
d
1
d
2
d
3
q
0
q
1
q
2
q
3
E
4-bit Adder .
b
0
b
1
b
2
b
3
a
0
a
1
a
2
a
3
c
0
c
4
s
0
s
1
s
2
s
3
Department of Mechanical Engineering
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Jan-14 Chapter 3 Microprocessor architecture Page 3.15
Parallel Add/ Subtract using 2s complement
3.1 Making of a microprocessor
3.1.2 Digital Arithmetic Circuits
Reg A
d
0
d
1
d
2
d
3
q
0
q
1
q
2
q
3
R/W
CE
Reg B
d
0
d
1
d
2
d
3
q
0
q
1
q
2
q
3
R/W
CE
D-Latches
d
0
d
1
d
2
d
3
q
0
q
1
q
2
q
3
L
Tristates
d
0
d
1
d
2
d
3
q
0
q
1
q
2
q
3
E
Reg B
d
0
d
1
d
2
d
3
q
0
q
1
q
2
q
3
R/W
CE
Add/Sub
4-bit Adder .
b
0
b
1
b
2
b
3
a
0
a
1
a
2
a
3
c
0
c
4
s
0
s
1
s
2
s
3
Department of Mechanical Engineering
N A T I O N A L U N I V E R S I T Y O F S I N A G A P O R E
Jan-14 Chapter 3 Microprocessor architecture Page 3.16
3.1.3 A Very Simple microprocessor
3.1 Making of a microprocessor
Microprocessor
Accumulaor Tmp Reg 1
Arithmetic Unit
Add/
Subtract
Tmp Reg 2
Internal Data Bus
Tri-state Buf
Data Bus
Instr Regs
Instr
Decoder
Address
Register
Address Bus
RAM ROM PIO
External I/O
Control Bus
Department of Mechanical Engineering
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January 14 Tutorial 3 - Solution Page T3.17
The End