ISSCC 2011 / SESSION 9 / WIRELESS & mm-WAVE CONNECTIVITY / 9.

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9.1 A 60GHz 16QAM/8PSK/QPSK/BPSK DirectConversion Transceiver for IEEE 802.15.3c
The antenna built in a package can radiate in the direction parallel to the printed circuit board [5]. The antenna is connected with the CMOS chip through a 270m bonding wire. There are no 60GHz connections between the package and the board. This implementation is practically cost-effective since usual PCB materials can be applicable. The antenna in the package has a 2dBi gain, which is designed with the wire parasitics. The beam widths in the E- and H-planes are 120 and 72, respectively. The transceiver is fabricated in 65nm CMOS technology. The core areas of the transmitter and the receiver including all matching blocks are 3.5mm2 and 3.8mm2, respectively. Figure 9.1.5 shows the measured spectrum in QPSK mode with the IEEE802.15.3c spectrum mask. The input I/Q signal is generated by an arbitrary waveform generator (AWG) with a symbol rate of 1.76GS/s and a rolloff factor of 25%. The TX output signal is received by a horn antenna and is measured by a spectrum analyzer with a downconversion mixer. The measured spectrum meets the IEEE802.15.3c standard. Figure 9.1.6 shows the measured constellation and performance summary, and Fig. 9.1.7 shows the die photo. Two test boards are used as TX and RX, and the 20GHz PLL on a probe station provides the injection signal for the boards. An AWG generates I/Q modulated signals for 16QAM/8PSK/QPSK/BPSK modes, and an oscilloscope is used to evaluate the constellation, EVM, and BER with a built-in software. Full-rate communication speed is possible for channel 1 (57.24 to 59.40GHz) and channel 2 (59.40 to 61.56GHz) of IEEE802.15.3c within a BER of < 103. The measured EVM is from 12% (-18dB) to 14% (-17dB), and it can be improved up to 4% (-28dB) by using decision feedback equalization (DFE) realized by the software. The /2 modulation series are also capable. Figure 9.1.6 also shows the communication distance range using the 2dBi antenna, and the low-gain mode of the LNA is used for short-distance receiving. The minimum BER is also confirmed up to <107 in QPSK mode (limited by measurement time). The symbol rate is 1.76GS/s with a roll-off factor of 25%, and the data rates with 2.16GHz BW are 1.76, 3.52, 5.28 and 7.04Gb/s for BPSK, QPSK, 8PSK and 16QAM, respectively. The maximum data rates using wider bandwidth in QPSK and 16QAM with a 25% roll-off are at least 8Gb/s and 11Gb/s within a BER of < 103.

Kenichi Okada, Kota Matsushita, Keigo Bunsen, Rui Murakami, Ahmed Musa, Takahiro Sato, Hiroki Asada, Naoki Takayama, Ning Li, Shogo Ito, Win Chaivipas, Ryo Minami, Akira Matsuzawa
Tokyo Institute of Technology, Tokyo, Japan This paper presents a 60GHz direct-conversion transceiver using 60GHz quadrature oscillators as shown in Fig. 9.1.1. The 65nm CMOS transceiver realizes the IEEE802.15.3c full-rate wireless communication for every 16QAM/8PSK/QPSK/BPSK mode. The maximum data rates with an antenna built in the package are 8Gb/s in QPSK mode and 11Gb/s in 16QAM mode within a BER of < 103, and the transmitter and the receiver consume 186mW and 106mW, respectively. The transmitter design is shown in Fig. 9.1.2. The transmitter consists of a 4stage PA, I/Q mixers and a quadrature oscillator. A direct-conversion architecture is employed because of energy efficiency [1]. The PA is implemented with a lowloss transmission line, which has a loss of 0.7dB/mm. A MIM transmission line (MIM TL) is also used for the de-coupling, which is characterized as a scalable transmission line. A MIM capacitor array is arranged along the MIM TL to lower the characteristic impedance. Transistors in the PA have a finger width of 2m, and the total gate width of the final stage is 80m. A double-balanced Gilbert mixer is used, and only one side is outputted in consideration of power consumption, LO leak, and layout area. The measured output power is shown in Fig. 9.1.2, and it is 9.5dBm at 1dB-compression. The conversion gain is 18.3dB, which is measured through the antenna. The large-signal measurement is calibrated with the saturated output power, which is measured by a probe station. The peak PAE is 8.8%. The PA consumes 114.6mW, and the two mixers consume 46.0mW from a 1.2V supply. The receiver design is shown in Fig. 9.1.3. The receiver consists of a 4-stage LNA, I/Q passive mixers, and a quadrature oscillator. The LNA has a CS-CS topology to improve the noise figure [2], and is connected to the passive mixer through a parallel-line transformer and a 2-stage differential amplifier. Since a transformer balun generally causes an imbalance in differential signals, the differential amplifiers are used to compensate the imbalance with common-mode rejection in the matching blocks. Moreover, 2 resistors are inserted into the power line to avoid a parasitic oscillation. The measured conversion gain and noise figure are also shown in Fig. 9.1.3. The LNA realizes a gain control, and the conversion gain is 17.3dB in high-gain mode and 4.7dB in low-gain mode. The lower cut-off frequency of the IF amplifier is less than 4MHz. The entire noise figure is less than 6.8dB in the high-gain mode, and the measured IIP3 of the LNA is 5dBm in the low-gain mode. The LNA consumes 20.7mW and the two mixers with IF amplifiers consume 60.8mW from a 1.0V supply. The LO consists of a quadrature injection-locked oscillator (QILO) [3] and a 20GHz PLL. The QILO design is shown in Fig. 9.1.4. The QILO works as a frequency tripler with a 20GHz injection-lock input, and it has a tail I/Q coupling. The I/Q coupling is carefully designed so that it can robustly keep the I/Q balance. The poly-phase filter for the 20GHz injection is not used to improve the I/Q mismatch over the entire frequency range. The measured free-running frequency is from 54 to 61GHz, and the phase noise is 85dBc/Hz at 1MHz offset in the free-running mode. Two quadrature oscillators are used, one for the TX and the other for the RX, to avoid insertion loss in the 60GHz LO distribution, which also contributes to maintain I/Q phase balance. The core area of the QILO is only 0.014mm2, and it consumes 14.9mW from a 1.0V supply. The LO buffers consume 10.0mW and can be turned off in sleep mode. The 20GHz PLL in [4] is used for the injection-locking signal. The core area of the PLL is 1.2mm2, and it consumes 66mW from a 1.2V supply. The PLL has a 2-stage divide-by-4 CML divider, a divide-by-5 static divider, and a programmable divider, /27, /28, /29 and /30, to generate 58.32GHz, 60.48GHz, 62.64GHz and 64.80GHz with a 36MHz reference, respectively. The measured frequency range of the PLL is from 17.9GHz to 21.2GHz. The overall phase noise is 94.2dBc/Hz@1MHz-offset at 60.48GHz, which is measured through the entire TX path including QILO, mixer and PA.

Acknowledgments: This work was partially supported by MIC, MEXT, STARC, NEDO, Canon Foundation, and VDEC in collaboration with Cadence Design Systems, Inc., and Agilent Technologies Japan, Ltd. The authors thank Dr. Hirose, Dr. Suzuki, Dr. Sato, and Dr. Kawano of Fujitsu Laboratories, Ltd., Dr. Taniguchi of JRC, Dr. Hirachi of AMMSys Inc., Dr. Noda, Mr. Kondo, Mr. Yamagishi, and Dr. Fukuzawa of SONY, and Prof. Ando of Tokyo Institute of Technology for their valuable discussions and technical supports. References: [1] C. Marcu, D. Chowdhury, C. Thakkar, J.-D. Park, L.-K. Kong, M. Tabesh, W. Yanjie, B. Afshar, A. Gupta, A. Arbabian, S. Gambini, R. Zamani, E. Alon, and A. M. Niknejad, A 90nm CMOS low-power 60GHz transceiver with integrated baseband circuitry, ISSCC Dig. Tech. Papers, pp. 314-315, Feb. 2009. [2] N. Li, K. Bunsen, N. Takayama, Q. Bu, T. Suzuki, M. Sato, T. Hirose, K. Okada, and A. Matsuzawa, A 24dB gain 51-68GHz CMOS low noise amplifier using asymmetric-layout transistors, ESSCIRC Dig. Tech. Papers, pp. 342-345, Sep. 2010. [3] W. Chan, and J. Long, A 56-65GHz injection-locked frequency tripler with quadrature outputs in 90-nm CMOS, IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2739-2746, Dec. 2008. [4] A. Musa, R. Murakami, T. Sato, W. Chaivipas, K. Okada, and A. Matsuzawa, A 58-63.6GHz quadrature PLL frequency synthesizer in 65nm CMOS, A-SSCC Dig. Tech. Papers, pp.189-192, Nov. 2010. [5] R. Suga, H. Nakano, Y. Hirachi, J. Hirokawa, and M. Ando, Cost-effective 60GHz antenna-package with end-fire radiation from open-ended post-wall waveguide for wireless file-transfer system, IMS Dig. Tech. Papers, pp. 449-452, May 2010.

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Figure 9.1.1: Block diagram of the 60GHz direct-conversion transceiver. Figure 9.1.2: Schematics of the transmitter and measured output power.

Figure 9.1.3: Schematics of the receiver, measured CG and NF.

Figure 9.1.4: Schematics of the quadrature injection-locked oscillator.

Figure 9.1.5: Measured spectrum for QPSK at TX output.

Figure 9.1.6: Measured constellation and performance summary.

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Figure 9.1.7: Die micrograph.

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