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NITHIN S. PODUVAL 2200 Waterview Parkway Apt 24303 Richardson, TX-75080 nspod491@gmail.

com (214) 436-7246

OBJECTIVE To seek a challenging internship opportunity in the field of Digital VLSI/Computer Architecture EDUCATION University of Texas at Dallas, Richardson, Texas, USA Master of Science in Electrical Engineering (Circuits and Systems) Birla Institute of Technology and Sciences (BITS), Pilani, India BS in Mechanical Engineering

Expected May 2015 GPA: 3.84/ 4.0 May 2013 GPA: 7.84/10.0

TECHNICAL SKILLS EDA Tools: Cadence Layout and Schematic, Cadence Encounter, Primetime , Synopsys, HSpice Programming Languages: C/C++ , Python, Perl, Embedded C, Verilog, Assembly Language Software Packages: Matlab, ComSol, AutoCAD, Microwave Office Platforms: Windows, Unix, Mac COURSEWORK VLSI Design Digital Circuits High Speed Data Communication Circuits Analog Integrated Circuit Design

Computer Architecture

ACADEMIC PROJECTS VLSI Design 16-Bit Microprocessor architecture design and implementation in IBM-130nm technology RTL design and verification of a 16-Bit Microprocessor which was then synthesized using Synopsys. Designed a standard cell library for various standard gates, Multiplexer and Dflipflop using Cadence Schematic and Layout editor. Extracted parasitics using Cadence Assura. Optimized the inverter design for the low power, consumption, delay and box area. Characterized the library using Liberty NCX and mapped it onto the Verilog netlist. Used Cadence encounter for floor planning. Completed final DRC and LVS checks of the design. Used Primetime to perform static timing analysis and determine the worst case delay

Analog IC Design: CMOS Fully Differential Operational Amplifier in CMOS TSMC 350Nm technology Designed a fully differential low power two stage Operational Amplifier which achieves the following 0, specifications-Gain of 74 dB, unity gain frequency 195 MHZ, phase margin of 60 ,etc. The amplifier used RC Miller compensation technique.

Computer Architecture: Cache design optimization of Alpha 21264 EV6 Microprocessor Fine tuning the cache hierarchy of an Alpha microprocessor using parameters such as cache levels, size, associativity and block size using the SimpleScalar Simulator. Suggested the optimum cache configuration considering cost of hardware and the CPI (Cycles per iteration) as a benchmark of performance. Perl Scripting used to automate execution process. High Speed Data Communication Circuits Designed a 4 stage ring oscillator with differential amplifier as delay stage with oscillation frequency of 200MHZ. Body Monitoring System: Design of a portable embedded system that monitors a persons vital conditions and reports anomalies via bluetooth. INTERNSHIPS/WORK EXPERIENCE Research Intern, VSSC (Vikram Sarabhai Space Centre), Indian Space Research Organization June-Dec 2012 Developed and implemented a 3-D fluid flow algorithm using C++ based on the Finite Element Method This algorithm helps improve speed and accuracy for computation of fluid flow. Project Intern, BHEL Bharat Heavy Electricals Limited) June-July, 2011 Conducted a feasibility study on Air Separation Units for the Combined Cycle Demonstration Plant, BHEL. ACADEMIC DISTINCTIONS Recipient of Jonsson School Graduate Scholarship award for 2013-2014, from UT Dallas. Ranked among top 2% in the national level college admission test (BITSAT).

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