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ECS Journal of Solid State Science and Technology, 2 (9) P362-P367 (2013)
2162-8769/2013/2(9)/P362/6/$31.00 The Electrochemical Society

Abrasive-Free Polishing for Extreme Ultraviolet Lithography Mask Substrates

H. P. Amanapu,a U. R. K. Lagudu,a A. John-Kadaksham,b S. V. Babu,a, ,z and R. Tekib
a Center for Advanced Materials Processing, Clarkson University, Potsdam, New b Mask Blank Development Center, SEMATECH, Albany, New York 12203, USA

York 13699, USA

In the development of photo-masks for extreme ultraviolet (EUV) lithography, it is a formidable task to achieve the stringent requirements of angstrom-scale surface roughness, sub-30 nm peak-valley atness and defectivity in single digits. The majority of the defects present on the substrate arise from the polishing/cleaning processes. Here we describe the effectiveness of depositing an amorphous silicon (a-silicon) thin lm to cover the existing defects (e.g. pits, scratches, bumps, embedded and adhered particles) on the surface of EUV substrates followed by polishing the a-silicon lm using abrasive-free liquids to help meet the EUV substrate requirements of surface roughness and defectivity (ideally zero pits or bumps greater than 1 nm in depth or height). Chemical mechanical planarization (CMP) using an abrasive-free poly (ethyleneimine) solution showed that both the nal surface roughness and removal rate are strongly dependent on polishing pressure. We developed a hybrid two-step CMP process consisting of polishing rst at 1 psi to remove sufcient material to eliminate the underlying defects, followed by polishing at 0.5 psi to achieve low surface roughness. Under these polishing conditions, CMP of a-silicon lms deposited on EUV mask substrates resulted in a root mean square (RMS) surface roughness of 0.09 nm. 2013 The Electrochemical Society. [DOI: 10.1149/2.015309jss] All rights reserved. Manuscript submitted April 29, 2013; revised manuscript received June 14, 2013. Published June 26, 2013. This was Paper 2510 presented at the Honolulu, Hawaii, Meeting of the Society, October 712, 2012.

Extreme ultraviolet (EUV) lithography is one of the leading nextgeneration techniques seen as a successor to the current lithographic techniques using 193 nm light, which are expensive and cumbersome at the current process nodes.1 Since EUV uses an exposure wavelength of 13.5 nm which is absorbed by most materials including air, all optical elements in a EUV scanner need to be reective. The EUV mask substrates are made of titania-doped fused silica,2 which is a low thermal expansion material (LTEM). To make the masks reective, they are coated with a series of alternative Mo/Si bilayers of 7 nm period thickness to enable reection at 13.5 nm.3 The masks must be free of defects that may be printed onto the silicon wafer and ruin the circuit. Most of these defects, especially the ones smaller than 70 nm size, originate on the surface of substrates4 during the chemical mechanical polishing (CMP) and cleaning processes,5 which are then translated through Mo/Si bilayers during the conformal deposition process. Hence, LTEM substrates of high surface quality, i.e. surface roughness of sub-0.1 nm RMS, sub-30 nm peak-valley atness, and defects greater than 1 nm in depth or height numbering only in single digits, are required before depositing the Si/Mo bilayers.6 Conventional CMP processes for achieving low surface roughness typically lead to some scratch/pit type of defects due to the use of abrasive particles in the slurry.79 However, abrasive-free CMP may offer a way to achieve low defectivity substrates, as the polishing slurry does not contain any abrasives. Also the post-CMP cleaning process becomes easier since it doesnt have to remove the abrasive particles that may remain on the surface after polishing. Currently, however, there are no abrasive-free solutions available for the polishing of quartz (QZ). Recently, we developed abrasive-free solutions of some cationic polymers such as poly (diallyldimethylammonium chloride), poly (ethyleneimine), poly (allylamine), etc. to polish polysilicon substrates.10 Here, we extend this process to EUV mask preparation by depositing 150250 nm a-silicon thin lm on the substrate to transfer the defects from it to the silicon surface, followed by polishing using abrasive-free solutions to achieve a high quality surface for the deposition Si/Mo bi-layers.11 In earlier publications10,12,13 we investigated the role of polycation charge density, pH, and polishing pad and proposed a polishing mechanism for the removal of polysilicon lms using the above mentioned abrasive-free solutions. Here our goal is to apply this process to achieve angstrom level surface smoothness on QZ/ LTEM substrates. This proposed method saves research effort and time when compared to the conventional process development procedures for EUV
z

substrates. In conventional development, preliminary experiments are performed on QZ and then transferred to LTEM substrates due to the high cost of LTEM substrates. However, polishing performance between the QZ and LTEM substrates is different as shown in Figure 1. When polished at the same CMP conditions (described in the experimental section) QZ substrates yield a lower surface roughness and average removal rate (RR) of 0.07 nm and 2.5 nm/min, respectively, compared to the 0.09 nm roughness and 3.9 nm/min for LTEM substrates. LTEM substrates are titania-doped quartz substrates; it is well known that doping of substrates affects the polishing performance. For example, phosphorous doped silicon wafers are polished faster than undoped silicon wafers while boron-doped silicon wafers are polished slower than undoped silicon.14 Doping is also likely to change material structure and properties such as hardness and brittleness, which can also affect the polishing behavior of QZ and LTEM substrates.15 Our analysis also shows that LTEM substrates usually have a higher defectivity (pits/scratches) as compared to QZ.4 This shows that the polishing recipe developed on QZ for achieving high quality surface may not be transferable directly to LTEM substrates, and may require further renement. LTEM substrates also have additional challenges with regards to post-CMP cleaning when compared to QZ.16

0.1

3.5

0.06 3 2.5 0.04 2 0.02

0 QZ LTEM

Electrochemical Society Active Member. E-mail: babu@clarkson.edu

Figure 1. The same CMP conditions on a QZ and LTEM substrate resulted in different nal roughness and removal rates.

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RMS Surface Roughness (nm)

0.08

Removal Rates (nm/min)

ECS Journal of Solid State Science and Technology, 2 (9) P362-P367 (2013) Using our proposed alternate procedure, we can develop the polishing recipe on a-silicon-coated QZ and then transfer it to LTEM substrates without any need of further optimization. This can also increase the yield of good quality substrates, since even poorly polished (with higher roughness and/or defectivity) LTEM substrates can be made better by coating them with the a-silicon layer and using abrasive-free CMP. There is also the potential to reclaim polished substrates with poor quality by stripping the a-silicon layer and then re-coating and re-polishing. In this work, we describe the inuence of various polishing parameters, namely polishing pressure, rotational speed, and chemical additives on the polishing performance of a-silicon substrates. Our experimental results suggest that polishing pressure has a strong inuence on polish rates as well as the nal surface roughness. Results from an earlier preliminary study were presented at the 2012 ECS annual conference in Honolulu and were accepted for publication in the conference proceedings (volume 50, issue 12) Experimental Materials. Since EUV mask substrates are expensive, preliminary experiments were performed on 1000 nm thick a-silicon lms, deposited using plasma enhanced chemical vapor deposition (PECVD), on 8 diameter Si (100) wafers supplied by WRS Materials. Later, the best process conditions obtained from these preliminary experiments were repeated on a-silicon lms deposited by ion beam deposition on QZ substrates supplied by SEMATECH. Aqueous dispersions of colloidal silica abrasives with dmean 50 nm, supplied by Nyacol Technology, were used for removing any native oxide/sub-oxide on the a-silicon surface. Poly (ethyleneimine) (Molecular Wt. 800), ornithine, and pH adjusting agents (KOH and HNO3 ) were all obtained from Sigma-Aldrich and used without any further purication. The polishing pads (IC-1000) and 4 diamond-grit conditioner were supplied by Dow Electronic Materials and 3M, respectively. Polishing conditions, removal rate and surface roughness determination. The 8 diameter wafers were polished on a G&P Poli-500 polisher at different polishing pressures (0.51.0 psi), 15/15 rpm carrier/platen speeds, and a slurry ow rate of 200 mL/min. In-situ coefcient of friction (COF) can also be measured with this polisher. Ex-situ conditioning was performed to regenerate the polishing pad surface using the 4 diamond grit conditioner. A Filmetrics interferometer F20 was used to measure the thickness of lms on the wafers before and after polishing. The RR of each of these lms was determined from the difference between pre- and postpolished lm thickness values. The reported RR for each experiment is an average of the RRs measured for two different wafers, each at 20 points located across a diameter of the wafer. The standard deviation in the RRs was calculated based on the data from these 40 points. When the observed RRs were lower than 1 nm/min, polishing was continued for 8 minutes and time averaged RRs were calculated. The experimental conditions at which the RMS surface roughness was approximately equal to or less than 0.1 nm were used for the polishing of 150250 nm thick a-silicon lms deposited on 152 152 6.35 mm3 QZ substrates. A modied substrate xture was built to accommodate the thick square substrates on the wafer CMP tool. Surface roughness was measured using a Veeco D5000 SPM tool over a 1 1 m2 area at radial distances of 0, 25, 50, 75 and 100 mm along a mask diagonal. To enable proper cleaning of these substrates, they were shipped, while submerged in DI water adjusted to pH 9 in a special sealed container, from Clarkson University in Potsdam, NY to SEMATECH in Albany, NY since it is much harder to remove particles attached to a surface once it dries. They were then cleaned on a Hamatech mask cleaning tool while the surface was still wet using an SPM (H2 SO4 :H2 O2 :H2 O) + SC1 (NH4 OH:H2 O2 :H2 O) + megasonic activation (3 Hz)-based cleaning recipe. For comparing polishing of QZ and LTEM substrates, the CMP conditions used were: 5 wt% colloidal silica slurry, pH 2, 45/45 rpm carrier/platen speed, 1 psi pressure

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polishing for 10 minutes followed by 0.5 psi pressure polishing for 1 minute.

Selection of abrasive-free solution. It has been shown that abrasive-free solutions of amino acids such as ornithine, arginine, and lysine, can polish polysilicon lms.17 Later, it was found that several abrasive-free aqueous solutions of 250 ppm of cationic polymers such as poly(diallyldimethyl ammonium chloride) (PDADMAC), poly(ethyleneimine) (PEI), poly(allyl amine) (PAAm) etc., can be used for the polishing of polysilicon lms, but only using the harder IC-1000 pads and not the softer politex pads.10,12,13 The adsorption and desorption of PDADMAC and PEI on polysilicon powders was studied and it was found that PDADMAC adsorbs strongly on a polysilicon surface and can remain as organic contamination whereas the adsorbed PEI on a post-CMP polysilicon surface can be easily removed by bufng with DI water at pH 2.10 Hence, abrasive-free solutions of one amino acid (ornithine) and one polymer (PEI) were used in our experiments.

Experimental Plan As shown in Figure 2, pits on the EUV substrate have a typical depth of 10 nm while the bumps have peak heights of 70 nm and all the pits and bumps need to be reduced to 1 nm in depth and height, respectively. Hence, the goal of polishing is to remove at least 20 nm of material to clear even the deepest pit without creating any new ones. A 30 nm/min target removal rate was chosen as a preliminary goal for the polishing process to smooth the bumps, remove the pits and produce sub-angstrom level surface roughness. In CMP, in the absence of abrasives in the slurry, removal rate is inuenced by the polishing pressure, rotational speed of platen and carrier (shear) and polishing pad. As abrasive-free a-silicon CMP can be performed only on harder pads such as IC-1000,13 we rst investigated the effect of polishing pressure and rotational speed on the surface roughness and removal rates of a-silicon lms on silicon wafers using such pads. The best polishing condition obtained on a-silicon wafers was then transferred to a-silicon lms deposited on the QZ substrates.

Figure 2. Schematic of (a) typical surface quality before, and (b) desired surface quality after abrasive-free CMP.

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ECS Journal of Solid State Science and Technology, 2 (9) P362-P367 (2013)

Table I. Effect of various polishing parameters on post-polish RMS surface roughness of a-silicon lms deposited on Si wafers. All polishings were done using IC-1000 pad. RMS roughness (nm) 0.28 0.02 0.27 0.03 0.26 0.02 0.10 0.02 0.26 0.02 0.28 0.04 0.10 0.02 0.11 0.02 0.48 0.08 Removal Rates (nm/min) 30 3 30 3 30 3 0.2 1 0.3 30 3 0.2 0.2 6 1.3

Slurry (pH)

Polishing time (sec) 60 120 300

Polishing pressure (psi) 1.0 0.5 0.7 1.0 0.5 0.5

Rotation speed (rpm) 15/15

250 ppm PEI (pH = 8)

60 60

15/15 15/15 60/60 15/15

1 wt% Ornithine (pH = 10)

60

Results and Discussion New a-silicon wafers, as received, had an average RMS roughness of 0.34 nm. These wafers are covered with a thin layer of native oxide that must be removed to initiate the polishing rates during the abrasive-free CMP. Hence, prior to any abrasive-free CMP, all wafers were polished with a 5 wt% colloidal silica dispersion at pH 2 and 1 psi pressure for 1 min to remove any native oxide. Table I shows the effect of various polishing parameters, namely polishing time, polishing pressure, rotational speed, and additive, on the polishing performance of a-silicon wafers. Polishing for 1 min using 250 ppm of PEI on an IC-1000 pad at pH 8, 1 psi and 15/15 rpm carrier/platen speed resulted in a polish rate and post-polish RMS surface roughness of 30 nm/min and 0.28 nm, respectively. Even though this polish rate is sufcient for the removal of pit/bumps on the surface, the RMS surface roughness of 0.28 nm is not acceptable. To keep the polish rates the same but hoping to improve the surface roughness, the lms were then polished for an additional 4 mins. However, RMS surface roughness remained almost the same at 0.26 nm. Hence, an alternate idea of decreasing the polishing pressure to below 1 psi was considered. Indeed, when the polishing pressure was decreased from 1 to 0.5 psi, RMS surface roughness decreased from 0.28 to 0.1 nm which is acceptable. Unfortunately, the a-silicon RRs decreased signicantly from 30 nm/min to 0.2 nm/min. This suggests that both the post-polish RMS roughness and polish rate are strongly dependent on polishing pressure. Even though 0.5 psi polishing pressure can produce the desired RMS roughness of 0.1 nm, the polishing process at this low RR requires long polishing times (>100 mins) to eradicate 20 nm pits. These higher polishing times will undoubtedly add more defects to the surface and therefore are undesirable. Later, rotational speed of platen and carrier were increased from 15/15 rpm to 60/60 rpm to possibly enhance the RRs while not affecting the RMS roughness. However, both RRs and RMS roughness remained almost unaffected. Experiments using 1 wt% Ornithine, which can polish polysilicon lms at 500 nm/min at 4 psi pressure on IC-1000 polishing pad,17 also resulted in negligible removal rates and even higher surface roughness of 0.48 nm compared to 250 ppm PEI at 0.5 psi pressure and 15/15 rpm speed. All the above results suggest that the post-polish RMS roughness and RRs of a-silicon wafers are strongly dependent on the polishing pressure but not on the rotational speed. To understand the possible role of the lubrication regime, we measured the COF in situ during polishing. The measured average COFs were 0.04 and 0.13 at 0.5 psi and 1 psi, respectively. The lower COF of 0.04 corresponds to a hydrodynamic polishing regime while 0.13 corresponds to a partial lubrication regime between the pad and the wafer.18,19 In the hydrodynamic regime, signicantly lower material removal rates and lower RMS roughness can be expected,20 while both will be higher in the partial lubrication regime, consistent with our results.

A closer look into the RR data (Table I) suggests that the pressure dependence of the RRs is non-prestonian. It is well known21,22 that such non-prestonian RRs can lead to excellent surface planarization by removing the protrusions more readily, which can lead to very low post-polish RMS surface roughness values for blanket lms, as was observed in our experiments. Rotational speed does not have the same inuence since both the low and high regions of the wafer surface experience the same velocity. Nevertheless, since the QZ/LTEM substrates have deep (10 nm) pits, it is crucial to remove more material (20 to 30 nm) from the substrate surface than that removed at 0.5 psi. Hence, we tested a two-step CMP process, i.e. polishing at 1 psi for 1 min. to remove the deep pits followed by polishing at 0.5 psi for 1 min to achieve 0.1 nm post-polish RMS roughness. Indeed, a material removal of 30 nm and an RMS surface roughness of 0.1 nm were achieved using this two-step process as shown in Figure 3. Hence, these process conditions were chosen to investigate polishing of a-silicon coated QZ substrates. Polishing of a-silicon coated QZ substrates. Figure 4 shows the RMS surface roughness values of a-silicon lms deposited by ion beam deposition (IBD) technique23 on a 152 152 6.35 mm QZ substrate before and after CMP. A fresh a-silicon lm deposited on the QZ substrate has a surface roughness of 0.15 nm which is better than the RMS roughness of as-received a-silicon lms on wafers deposited by the PECVD method. As mentioned earlier, a-silicon surface is covered with thin native oxide layer. Without prior native

0.45

35 30 25
0.26

RMS Surface Roughness (nm)

0.4 0.35 0.3 0.25 0.2 0.15

0.1 0.1 0.28

20 15 10 5 0 1 0.7 0.5 1 psi followed by 0.5 psi

0.1 0.05 0

Pressure (psi)
Figure 3. Effect of polishing pressure on post-polish surface roughness and removal rates (red line) of a-silicon wafer.

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Removal Rates (nm/min)

ECS Journal of Solid State Science and Technology, 2 (9) P362-P367 (2013)
0.3

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RMS Surface Roughness (nm)

0.24

0.25

0.21

0.2 0.15 0.15

0.09

of the new surface since the abrasive-free solutions cannot polish the native oxide present on the a-silicon lms. When the native oxide was removed by polishing for 1 min using 5 wt% silica at pH 2, IC-1000 pad, 1 psi, and 45/45 rpm, the RMS surface roughness increased to 0.24 nm. However, as expected, the proposed two-step PEI polish process resulted in an excellent and acceptable surface roughness of 0.09 nm. Smoothing of pit type defects. In order to verify whether the existing pit/scratch defects on the substrate were indeed removed by the PEI polishing, an a-silicon coated substrate was prepared and inspected on a Lasertec M1350 mask inspection tool at SEMATECH. Four pyramidal punch marks (about 300 nm deep and 2.5 m wide) were made approximately 10 m away in a diamond pattern from a few selected pit defects. An AFM was then used to scan and determine the relative location of the defects with respect to the punch marks and to measure the dimensions (depth and width) of the defects. The substrate was then polished at Clarkson using the two-step abrasivefree process identied above and the defect locations were revisited on the AFM. Analysis of multiple such pit defects both before and after the abrasive-free CMP process showed complete removal of the defects. One such example is shown in Figure 5, where a 3.2 nm deep pit was undetectable on the post-CMP AFM scan. Surface roughness. The surface was scanned post-polish over 1 1 m2 areas on the AFM to estimate the high spatial frequency

0.1

0.05

0 New substrate After native oxide Two-step CMP Two-step CMP removal without native with native oxide oxide removal removal

Figure 4. Surface roughness of a-silicon lms deposited on 152 152 6.35 mm QZ substrates and then polished at different process conditions.

oxide removal, two-step PEI CMP, i.e. polishing at 1 psi for 1 min followed by 0.5 psi for min using 250 ppm PEI at pH 8 on IC-1000 pad at 15/15 rpm, resulted in an RMS surface roughness of 0.21 nm. Not surprisingly, the RMS surface roughness is no better than that

Figure 5. AFM scans of the defect location before PEI polishing with a zoomed-in scan of the pit in the inset (left) and after PEI polishing (right), indicating complete removal of the defect.

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ECS Journal of Solid State Science and Technology, 2 (9) P362-P367 (2013) Conclusions It is challenging to simultaneously meet the atness, roughness and defectivity requirements on EUV mask substrates. Current global/local polishing processes are unable to produce good quality substrates with sufcient yield. We explored the possibility of decreasing the defect numbers and/or increasing the yield of low defectivity substrates by adopting a different surface material which can be polished without abrasive particles. Surface roughness of a-silicon lms polished using abrasive-free slurries is strongly dependent on the polishing pressure. A lower polishing pressure of 0.5 psi yielded a post-polish surface roughness of 0.1 nm RMS but almost negligible RRs while a polishing pressure of 1 psi resulted in a desired RR of 33 nm/min but in an unacceptable surface roughness of 0.28 nm RMS. So, a two-step CMP process consisting of polishing at 1 psi for 1 min followed by polishing at 0.5 psi for 1 min was used to achieve both surface roughness and RR requirements on a-silicon coated QZ substrates. Detailed AFM analysis of pit defects before and after the PEI CMP showed complete removal of the existing defects. A further investigation is underway to evaluate the number and type of defects, if any, generated by the abrasive-free CMP process. From this study, it is clear that the abrasive-free a-silicon CMP can easily meet the surface roughness requirement of EUV mask substrates and can also potentially reduce the number of defects on the post-polish surface. Hence, abrasive-free a-silicon CMP can be a promising route to prepare defect free EUV mask substrates. Acknowledgments The authors acknowledge SEMATCH for nancial support. We thank NYACOL, Dow Electronic Materials and 3M for the supply of colloidal silica particles, polishing pads, and conditioners, respectively. We also thank Timothy Owen, Jon Underwood, Edward Maillet, Butch Halliday and Mark Maloney from SEMATECH for support with AFM measurements. References
1. P. J. Silverman, J. Microlith., Microfab., Microsyst., 4, 011006 (2005). 2. W. Rosch, L. Beall, J. Maxon, R. Sabia, and R. Sell, Proc. of SPIE, 6517, 651724 (2007). 3. C. Montcalm, S. Bajt, P. B. Mirkarimi, E. Spiller, F. J. Weber, and J. A. Folta, Emerging Lithographic Technologies II, Proceedings of SPIE, 3331, 42 (1998). 4. R. Teki, A. J. Kadaksham, M. House, J. Harris-Jones, A. Ma, S. V. Babu, A. Hariprasad, P. Dumas, R. Jenkins, R. Provine, J. Richmann, J. Stowers, S. Meyers, U. Dietze, T. Kusumoto, T. Yatsui, M. Ohtsu, and F. Goodwin, Proc. of SPIE, 8322, 83220B (2012). 5. A. Rastegar and V. Jindal, Proc. of SPIE, 8352, 83520W (2012). 6. R. Teki, A. J. Kadaksham, F. Goodwin, T. Yatsui, and M. Ohtsu, Proc. of SPIE, 8679, 86790F (2013). 7. M. Krishnan, J. W. Nalaskowski, and L. M. Cook, Chem. Rev., 110, 178 (2010). 8. K. Wang, Y. Z. Li, R. K. Kang, and D. M. Guo, Appl. Surf. Sci., 256, 2691 (2010). 9. J.-G. Choi, Y. N. Prasad, I.-K. Kim, I.-G. Kim, W.-J. Kim, A. A. Busnaina, and J.-G. Park, J. Electrochem. Soc., 157, H186 (2010). 10. N. K. Penta, P. R. Dandu Veera, and S. V. Babu, Langmuir, 27, 3502 (2011). 11. U.S. Patent Application No. 61/694,303, Unpublished (ling date Aug. 29, 2012) (S. V. Babu, H. P. Amanapu, U. R. K. Lagudu, and R. Teki, applicants). 12. N. K. Penta, P. R. Dandu Veera, and S. V. Babu, ACS Appl. Mater. Interfaces, 4126, 3 (2011). 13. N. K. Penta, J. B. Matovu, P. R. Dandu Veera, S. Krishnan, and S. V. Babu, Colloids and Surfaces A: Physicochem. Eng. Aspects, 388, 21 (2011). 14. M. Forsberg, N. Keskitalo, and J. Olsson, Microelec. Eng., 60, 149 (2002). 15. T. A. Ring, P. Feeney, D. Boldridge, J. Kasthurirangan, S. Li, and J. A. Dirksen, J. Electrochem. Soc., 154, H239 (2007). 16. A. J. Kadaksham, R. Teki, M. Godwin, M. House, and F. Goodwin, Proc. of SPIE, 8679, 86791R (2013). 17. P. R. Dandu Veera, B. C. Peethala, N. K. Penta, and S. V. Babu, Colloids and Surfaces A: Physicochem. Eng. Aspects, 366, 1 (2010). 18. D. DeNardis, J. Sorooshian, M. Habiro, C. Rogers, and A. Philipossian, Jpn. J. Appl. Phy., 42, 6809 (2003). 19. A. Philipossian and S. Olsen, Jpn. J. Appl. Phy., 42, 6371 (2003). 20. N. Gitis and R. Mudhivarthi, in Microelectronic Applications of Chemical Mechanical Planarization ( Y. Li, Editor), p. 83, John Wiley & Sons, New Jersey (2007). 21. K. W. Chen, Y. L. Wang, C. P. Liu, L. Chang, and F. Y. Li, Thin Solid Films, 498, 50 (2006).

Figure 6. Variation of cumulative RMS roughness over different spatial wavelengths for the bare substrate, after 250 nm a-silicon lm deposition and after non-abrasive CMP.

roughness. The raw data was converted to the form of a power spectral density (PSD) function,24 and then the cumulative RMS roughness over various spatial wavelengths was plotted in Figure 6. The plot indicates that initial QZ substrate (previously CMP polished using abrasives at the supplier) roughness increases up to a wavelength of about 100 nm and then remains constant until 1000 nm at an RMS value of 0.07 nm. Depositing a 250 nm thick a-silicon thin lm using IBD increases the roughness mainly in the wavelength region of 10 to 200 nm, and reaches 0.15 nm RMS. Polishing the a-silicon lm with PEI reduces the surface roughness to 0.09 nm RMS over a wavelength of 1000 nm. It is interesting to compare the roughness variation over wavelength for the abrasive-based CMP used on the QZ substrate and the abrasive-free CMP used on the a-silicon thin lm. Compared to abrasive CMP, the abrasive-free CMP achieves lower roughness up to a 100 nm wavelength, which then starts to increase. This may be due to the size of the slurry particles used in the abrasive CMP and the mechanism of material removal. While the ability of abrasive-free a-silicon CMP to eradicate existing pits/scratches and sufcient material removal was more or less expected, the ability to meet sub-angstrom surface roughness levels without using slurry particles has not been previously demonstrated. The most critical reason for evaluating the abrasive-free CMP process is its potential for lower defectivity compared to a CMP process that uses slurry particles. Even without slurry particles, there are other potential sources of CMP defects such as the pad inhomogeneities/asperities and presence of foreign particles in the solution. The real test for abrasive-free CMP is whether it adds fewer new defects on the a-silicon surface while removing the existing ones. Our preliminary data hint at the potential of abrasive-free CMP to generate fewer defects, and we are currently in the process of obtaining concrete data to support this. Another advantage of the abrasive-free CMP is related to post-CMP cleaning. Pit defects on the current substrates are created not only by slurry/foreign particles during the CMP process itself, but also from the megasonic activation-induced cavitation during post-CMP cleaning. Abrasive-based CMP needs a carefully integrated post-CMP cleaning process to remove all the abrasive particles added to the surface during the polishing process. This typically requires some megasonic activation to dislodge the particles attached to the substrate surface. The megasonic activation results in cavitationinduced pit creation25 and increases the pit counts at the cost of lowering the particle counts on the substrates.26 Not having any solids in the CMP slurry removes the necessity of using stronger megasonic activation and thus lowers the likelihood of cavitation-induced pit creation.

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ECS Journal of Solid State Science and Technology, 2 (9) P362-P367 (2013)
22. H. Chou, W. Kim, J. Noh, and I. Lee, International Conference on Planarization and CMP Technology (ICPT), 1 (2007). 23. V. Jindal, P. Kearney, J. Sohn, J. Harris-Jones, A. John, M. Godwin, A. Antohe, R. Teki, A. Ma, F. Goodwin, A. Weaver, and P. Teora, Proc. of SPIE, 8322, 83221W (2012).

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24. J. F. Borrull, A. Duparr e, and E. Quesnel, Appl. Opt., 40, 2190 (2001). 25. V. Kapila, P. A. Deymier, H. Shende, V. Pandit, S. Raghavan, and F. O. Eschbach, Proc. of SPIE, 6283, 628324 (2006). 26. A. Rastegar, S. Eichenlaub, K. Goncher, and P. Marmillion, Proc. of SPIE, 6283, 628301 (2006).

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