Tutorial 2

High-Speed I/Os and PLLs for Data Communication Applications

Krzysztof (Kris) Iniewski and Shahriar Mirabbasi

Outline

The wireline communication industry is working on the communication systems with

data rates of beyond 10 Gb/s. Mixed-signal circuits are required to transmit and receive
Gb/s signals over high-speed serial interfaces, and to synthesize and recover GHz clocks,
typically using phase-locked loop circuitry. This tutorial will start with setting up a
system environment for high-speed serial link applications. Long-haul and metropolitan
area networks undergoing transition from OC-48 (2.488 Gb/s) to OC-192 (9.953 Gb/s or
10.7 Gb/s using forward error correction) will be discussed. Upgrades of local area
networks (LANs) from 1.25 Gb/s to 10.3 Gb/s Ethernet I/Os are mentioned. Movement of
disk drives and storage area networks (SANs) to 10.5 Gb/s Fibre Channel interfaces is
described. A brief overview of chip to chip data transfer schemes follows, with an
emphasis on the serial I/O. Then fundamentals of phase-locked loop (PLL) design will be
discussed. First, the overall system specification for (charge-pump based) PLL systems is
presented. Open- and closed-loop PLL transfer functions are briefly reviewed. Loop
stability and jitter sources are discussed. Design issues for circuit blocks like voltage-
controlled oscillators (VCOs), phase-frequency detectors (PFDs) and charge pumps are
discussed. Key PLL based systems, e.g., Clock Synchronizer and Clock/Data Recovery
(CDR), are described. The tutorial ends with discussion and design issues of output driver
and receiver input blocks of serial links. Pre-emphasis and equalization concepts are
described. Implementation schemes for I/O termination and ESD protection are
discussed.

List of Topics and Associated Presenters:

x System requirements for 10 Gb/s+ SONET/SDH, Ethernet, and Fibre Channel networking
technologies. Summary of new developments in Metropolitan and Storage Area Networking.
Brief overview of Evolution of chip to chip data transfer and serial I/O interfaces. – Kris
Iniewski
x System level overview of charge pump based Phase Locked Loops (PLLs). Open loop and
closed loop transfer function. Bode plot and stability. Jitter sources and loop bandwidth
considerations. – Shahriar Mirabbasi
x PLL design issues. Voltage Controlled Oscillator (VCO) and Current Controlled Oscillator
(ICO) – frequency control range, phase noise, power dissipation. Charge pump, loop filter,
phase frequency detector (PFD) and frequency divider. Intrinsic jitter specifications –
Shahriar Mirabbasi
x Clock recovery design issues. Full rate vs. fraction rate architecture. Phase and frequency
detectors – Jitter tolerance specifications – Shahriar Mirabbasi

Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC’04)
0-7695-2182-7/04 $ 20.00 IEEE
 x Output driver design issues. CMOS vs. CML. Internal or external termination. Signal
bandwidth increase with on-chip inductors. Pre-emphasis implementation. ESD
considerations. – Kris Iniewski
x Input receiver design issues. Internal vs. external termination. Equalization implementation.
Signal bandwidth increase with on-chip inductors. ESD considerations. – Kris Iniewski

Tutorial Presenters

Krzysztof (Kris) Iniewski, Associate Professor, University of Alberta

Krzysztof (Kris) Iniewski is an Associate Professor at the Electrical Engineering and
Computer Engineering Department of University of Alberta. His research interests are in
advanced CMOS devices and circuits for System on Chip (SoC) applications. He is also a
founder and president of SilicoMOS, a consulting firm in Vancouver, Canada and serves
as an Adjunct Professor at Simon Fraser University. Dr. Iniewski has over 15 years of
technical experience in semiconductor and communication IC industry.
From 1995 to 2003, he was with PMC-Sierra and held various technical and management
positions in Research & Development. Prior to joining PMC-Sierra, from 1990 to 1994
he was an Assistant Professor at the University of Toronto’s Electrical Engineering and
Computer Engineering department.
Dr. Iniewski has published over 64 research papers in international journals and
conferences. He holds 10 international patents granted in USA, Canada, France,
Germany, and Japan. In 1988 he received his Ph.D. degree in electronics (honours) from
the Warsaw University of Technology (Warsaw, Poland).
Dr. Iniewski is presently working with Canadian Microelectronics Corporation (CMC) on
establishing a collaboration framework with international links for coordinated university
research access to advanced technologies such as sub-100nm CMOS.

Shahriar Mirabbasi, Assistant Professor, University of British Columbia

Shahriar Mirabbasi received the B.Sc. degree in electrical engineering from Sharif
University of Technology, Tehran, Iran in 1990 and the M.A.Sc and Ph.D. degrees in
electrical and computer engineering from the University of Toronto, ON, Canada in 1997
and 2002, respectively.
During the summer of 1997, he was with Gennum Corporation, Burlington, ON, Canada
working on the system design of cable equalizers for serial digital video and HDTV
applications. From 2001 to 2002, he was with Snowbush Microelectronics, Toronto, ON,
Canada, as a Designer where he worked on high-speed mixed-signal CMOS integrated
circuits including ADC and serializer/deserializer blocks.
Since 2002, he has been an Assistant Professor in the Department of Electrical and
Computer Engineering of the University of British Columbia, Vancouver, BC, Canada.
His current research interests include analog and mixed-signal integrated circuits and
systems design for high-speed wireless and wireline data communications applications
and low-power integrated transceiver design.

Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC’04)
0-7695-2182-7/04 $ 20.00 IEEE