CHAPTER 4 - LANGUAGE AND FPGA TOOLS

5. Various digital modeling techniques such as algorithmic descriptions, finite state machine descriptions and Boolean equations can be modeled using this language [25].

4.1.2 VHDL

VHDL is a hardware description language which can be used to describe model for a digital hardware device. The digital system can be as simple as a logic gate or as complex as a complete digital electronic system. The basic building blocks of this language are called as design units of this language. There are four main design units in VHDL language to describe an entity (hardware abstraction of the digital system) [24] 1. Entity declaration. 2. Architecture declaration. 3. Configuration declaration. 4. Package (Package declaration and Package body). 5. Test-bench

The VHSIC Hardware Description Language (VHDL) is a formal notation intended for use in all phases of the creation of electronic systems. Because it is machine understandable as well as human understandable, it supports the synthesis, development, verification, and testing of hardware designs; the communication of hardware design data; modification, maintenance, procurement of hardware [24].

The main difference between VHDL and another programming language more widely used in computers for eg. C, is that VHDL enables the execution of concurrent statements. In contrast with a sequential statement, a concurrent statement is so called because conceptually it can be activated to perform its task together with any other concurrent statements [25].

VHDL Implementation of DS-SS CDMA based Mac protocol for Ad-hoc Networks 58

CHAPTER 4 - LANGUAGE AND FPGA TOOLS

a) Entities

The design entity is the initial hardware abstraction in VHDL. It represent a part of a hardware design that has well defined inputs and outputs and performs a well defined function. Entity may represent system, a subsystem, a board, a chip, a cell, a logic gate [24]. A configuration can be used to describe how design entities are put together to form a complete design. An entity may be described in form of a hierarchy of blocks, which represents a portion of whole design. The top level block is the design entity itself; such a block is an external block that resides in a library and may be used as a component of design. [24].

a) Architectures

Architecture, continuing with the analogy of an IC, is equivalent to the internal electronic circuit that performs the function for which the component has been designed. At this stage all the signals the entity uses to communicate with the external world are defined and unalterable. Inside entity, in its place, the programmer can write any type of statements allowed by the VHDL syntax, like other components, representing sub-circuits, other signals, for connection, or processes, which has sequential statements operating on values. The purpose is to apply some operations to data on input ports and generate some results to assign to output ports [25].

b) Configurations

In the previous two subsections we saw that the same entity can be usefully described, unless the functional behaviors match, with different approaches that correspond to different architectures. Due to this, nothing prevents us from choosing architecture of an entity regardless of architectures chosen for other entities. The configuration declaration permits of assembling the system based on our goal, architectures availability. To explain this idea, let us assume we have n entities {E1,, En}. Let also suppose each of them has got two architectures, Ai 1 and Ai 2 with i in {1,,n}. If the entire system is only composed of all the entities {E1,,En}, combining the two architectures for each of them we can virtually have 2n different representation of the same system [26]. VHDL Implementation of DS-SS CDMA based Mac protocol for Ad-hoc Networks 59

CHAPTER 4 - LANGUAGE AND FPGA TOOLS

c) Generic Parameters

The generic interface list is another powerful tool provided by VHDL language. Its aim is to allow parameterized descriptions of entities. In fact, from an architecture point of view, generic element can be seen as a constant whose visibility extends into the whole architecture body corresponding to that entity declaration [24]. The actual generic value, on the other hand, it can be defined in the entity that lies on a upper level in the hierarchy and is passed down to the component as a parameter [26].

VHDL Implementation of DS-SS CDMA based Mac protocol for Ad-hoc Networks 60

CHAPTER 4 - LANGUAGE AND FPGA TOOLS

4.1.3 High Level Design Flow It is a design flow used to create a complex FPGA and ASIC devices [24]. The designer starts with a design specification, then creates an RTL report, verifies that report, synthesizes the report to gates, uses place and route tools to implement the design in the chip and verifies the final result is correct in terms of function and timing [24]. The high level design flow is illustrated in figure 3.1.
Design Specification

HDL Capture

RTL Simulation

RTL Synthesis

Functional Gate Simulation

Place and Route

Post Layout Timing Simulation

Fig. 4.1 High Level Design Flow

VHDL Implementation of DS-SS CDMA based Mac protocol for Ad-hoc Networks 61

CHAPTER 4 - LANGUAGE AND FPGA TOOLS

Each step of the high level design flow is explained as below:-

4.1.3.1 HDL Capture

After the design specification has been completed, the designer can begin the process of implementation. The designer firstly creates the VHDL description which describes the clock-by clock behaviour of the design. The VHDL code for entities of the design is entered. The designer then checks the design for any syntax errors in the design. When all syntax errors are removed, the VHDL code is verified for correctness by simulating it [24].

4.1.3.2 RTL Simulation

The RTL simulation step is used to verify the correctness of RTL VHDL description. In RTL Simulation, the designer uses stimulus that represents the design environment to drive the design and check to make sure that the result are correct. A standard VHDL simulator can be used to read the RTL VHDL description and verify the correctness of the design [24].

4.1.3.3 VHDL Synthesis

The objective of the VHDL Synthesis step is to create a design that implements the required functionality and matches the designers constraints in speed, area, or power. The VHDL synthesis tools convert the VHDL description into a net list in the target FPGA or ASIC technology. For the VHDL synthesis tool to perform this step properly, the VHDL code must be written in a particular style [26]. The designer reads the VHDL design into the VHDL synthesis tool. The synthesizer produces an output net list in the target technology and a number of report files to determine the quality of the synthesis output [26].The most common output files are the timing report and the area report. Most synthesis tools produce a number of other reports which are hierarchy reports, instances reports, nets reports, power reports, and others but the most useful reports initially are the timing reports, as these are usually the most critical factors. VHDL Implementation of DS-SS CDMA based Mac protocol for Ad-hoc Networks 62

CHAPTER 4 - LANGUAGE AND FPGA TOOLS

The area report shows the designer how much of the resources of the chip the design has consumed. Designer can tell if the design is big for a particular chip and the designer needs to target a larger chip, if the design should go into a smaller chip, or if the current chip will work better. The designer can also derive the relative size of the design to use in later stages of the design process [25]. The timing report shows the timing of critical paths or specified paths of the design. The designer examines the timing because these paths ultimately determine how fast the design can run [24].

4.1.3.4 Functional Gate Level Verification

Some designers might want to do a quick check on the output of the synthesis tool to make sure that the synthesis tool produced a functionally correct design. For doing this the designer executes a functional gate level verification. The designer reads the output VHDL net list from the synthesis tool and a library of the synthesis primitives into the VHDL simulator and then runs the simulation using the RTL Verification vectors. After running the simulation, if the design matches then the synthesis tool did not produce logic mismatches but if it does not match, the designer needs to debug the VHDL RTL description to see what is wrong [24].

4.1.3.5 Place and Route

Place and route tools are used to take the design net list and implement the design in the target technology device. The place and route tools are used to place each primitive from the net list into an appropriate location on the target device and then route signals between the primitives to connect the devices according to the net list of the design [25]. One input to the place and route tools is the net list in EDIF or in another format of net list. For some place and route tools the another input is the timing constraints, for giving the place and route tools an indication about the signals that which have critical timing associated with them and to route these nets in the most efficient manner of timing [24]. Typically these nets are identified during the static timing analysis process during synthesis. These constraints tell the place and route tool to place the primitives in close proximity to one another and to use VHDL Implementation of DS-SS CDMA based Mac protocol for Ad-hoc Networks 63

CHAPTER 4 - LANGUAGE AND FPGA TOOLS

the fastest routing. The closer the cells are, the shorter the routed signals will be and the shorter the time delay.

4.1.3.6 Post Layout Timing Simulation

After the place and route process has completed, the designer will want to verify the results of the place and route process. There are a number of methods to accomplish this task but the most common method is to use post route gate level simulation. This post layout timing simulation combines the net list used for place and route with the timing file from the place and route process into a simulation that checks both functionality and timing of the design.

4.1.4 Modeling of Finite State Machine

4.1.4.1 Finite State Machine

Finite-State Machines is a primitive but it is useful computational model for both hardware and certain types of software [27]. FSM provide a simple computational model with many applications. State machine designs are used for sequential control logic, that forms the heart of many digital systems. State machines are compulsory in a variety of applications covering a broad range of performance and complexity; low-level controls of microprocessor to peripheral interfaces, timing generation in conventional microprocessors, custom bit-slice microprocessors, and transmission protocols are but a few examples [27]. Typically, the details of control logic are the last to be settled in the design cycle, since they are continuously exaggerated by changing system requirements and feature enhancements [27]. Its flexibility provides an escape valve that permits design changes without impacting time-to-market. A majority of registered PAL device applications are sequential control designs where state machine design techniques are working. Since technology advances, new high-speed and high-functionality devices are being introduced which simplify the task of state machine design. A wide range of different functionality and performance solutions are available for state machine design [27].

VHDL Implementation of DS-SS CDMA based Mac protocol for Ad-hoc Networks 64

CHAPTER 4 - LANGUAGE AND FPGA TOOLS

A state machine is a digital device that traverses through a predetermined sequence of states in an orderly fashion. A simple state machine can consist programmable array logic device based combinatorial logic, output registers and state registers. A general form of a state machine can be depicted as a device shown in Figure 4.2. In addition to the device inputs and outputs, a state machine consists of two necessary elements: combinatorial logic and memory (registers) [27]. This is similar to the registered counter designs discussed before, which are basically simple state machines. The memory is used to store up the state of the machine. The combinatorial logic can be view as two distinct functional blocks: the next state decoder and the output decoder Fig. 4.2. The next state decoder determines the next state of the state machine while the output decoder generate the actual outputs. Although they perform two separate functions, these are usually join into one combinatorial logic array as in Fig. 4.2 [27].

Fig. 4.2 Block Diagram of a Simple State Machine [27]

The necessary operation of a state machine is twofold: 1. It traverses through a sequence of states, where the after that state is determined by next state decoder, depending upon the present state as well as input conditions [27]. 2. It provides sequences of output signals based upon state transitions [27]. The transitions from one state to another are called control sequencing and the logic necessary for deciding the next states is called the transition function [27]. The utilization of VHDL Implementation of DS-SS CDMA based Mac protocol for Ad-hoc Networks 65

CHAPTER 4 - LANGUAGE AND FPGA TOOLS

input signals in the decision-making process for output generation determines the kind of a state machine. There are two broadly known types of state machines: Mealy State Machine Moore State Machine Both state machine models are shown in figure Fig 4.3. Moore state machine outputs are a function of the present state only [27]. Most practical state machines are synchronous sequential circuits that rely on clock signals to trigger the state transitions. A single clock is coupled to all of the state and output edge-triggered flip-flops, it allows a state change on the rising edge of the clock. Asynchronous state machines utilize the propagation delay in combinatorial logic for the memory function of the state machine. Such machines are extremely vulnerable to hazards, hard to design and are seldom used.

Fig. 4.3 The Two Standard State Machine Models [27]

VHDL Implementation of DS-SS CDMA based Mac protocol for Ad-hoc Networks 66

CHAPTER 4 - LANGUAGE AND FPGA TOOLS

4.2

FPGA DESIGN IMPLEMENTATION

In this paper, uses the VHDL Implementation on Xilinx 14.1 and Model sim Xilinx

Edition 10.1C (MXE) tool will be used for functional simulation and logic verification at each block level and system level. The Xilinx Synthesis Technology (XST) of Xilinx ISE tool will be used for synthesis of transmitter and receiver on FPGA. In DS CDMA transmission user data is spread by a PN sequence then modulated using DPSK modulation. Then the modulated signals from different users are combined and transmitted. In the receiver end we demodulated the data using DPSK demodulator then recover the traffic channel information and detecting original data. In Our project, the following specifications are considered for design and implementation of the MAC Based DS-SS CDMA Forward link Tx and Rx frame for Ad-hoc network.

Table 4.1 Following specification is considered for Design & Implementation for MAC based DS-SS CDMA Forward link for Ad-hoc Network
Type of PN sequence Gold code

Walsh code

N x N matrix

Front end design entity

VHDL

Back end synthesis

Virtex 5

Synthesis software

Xilinx 14.1

Simulation

Modelsim 14.1c

VHDL Implementation of DS-SS CDMA based Mac protocol for Ad-hoc Networks 67

CHAPTER 4 - LANGUAGE AND FPGA TOOLS

VHDL Implementation of DS-SS CDMA based Mac protocol for Ad-hoc Networks 68