Design & Implementation of Non-Linear Turbo Equalization Based Uplink Receiver for LTE Advanced Release 11 Group 6

Telecommunication industry plays a critical role in the global economy connecting billions of people around the globe. The importance of telecommunication services have rapidly risen in past few decades and hence there exists a never ending requirement for services with higher data rates, low latency and high quality of service. To facilitate that need ITU along with 3GPP introduced LTE first and LTE Advanced subsequently which is considered as a 4th generation technology. Many researches have undertaken substantial work in the area of improving performance in LTE Advanced downlink receivers, to facilitate the high data rates specified in the standard. In contrast not much attention has been given to the improving performance in receiver schemes of LTE Advanced uplink, though near Shannon capacity receiver schemes are required to sustain the specified uplink data rates as well. Therefore our project is to design and implement a nonlinear turbo equalization based uplink receiver for LTE-Advanced release 11(which is the latest LTE-Advanced standard issued by 3GPP in August 2012). This task will be undertaken by a group of 4 students namely J.M.H.G. Jayasundara, P.H.M.A. Jayawardena, N.C Madawanarachchi, W.L.P.H.S. Wijayasinghe. The need and the motivation for this project came through the extensive literature review carried out on LTE Advanced proposed receiver schemes. The project includes a transmitter and a channel in addition to the receiver for simulation purposes and performance evaluation purposes. Therefore the entire system comprises of a transmitter, channel and receiver. The scope of this project is limited to software implementation of system, hardware implementation of system and finally performance evaluation and comparison of both software and hardware implementations. The design of system including all three parts transmitter, channel and receiver was carried out using Matlab 2013a. The performance evaluation of the software implementation was also carried out on the same platform. The receiver includes a complex MLSE equalization block and also feedback from the decoder is given to equalizer block in accordance with turbo equalization principles. These steps added more complexity into the project. Then the Verilog codes are generated using Matlab HDL generation functionalities and they are modified thoroughly to facilitate implementation on Xilinx Virtex 7 FPGA development platform. However significant comprises have to be made to compensate for hardware limitations of hardware platform used; therefore achieved hardware performance is below the expected hardware performance.