Dr.

Cuong Huynh Telecommunications DepartmentHCMUT

CMOS ANALOG IC DESIGN
Spring 2013


1
Dr. Cuong Huynh
cuonghpm@yahoo.com

Department of Telecommunications
Faculty of Electrical and Electronics Engineering
Ho Chi Minh city University of Technology
Dr. Cuong Huynh Telecommunications DepartmentHCMUT
CMOS ANALOG IC DESIGN
Spring 2013


2
Dr. Cuong Huynh
cuonghpm@yahoo.com

Department of Telecommunications
Faculty of Electrical and Electronics Engineering
Ho Chi Minh city University of Technology
Lecture 4: Differential Amplifiers
A single-ended signal is measured with respect to a fixed
potential (ground)
A differential signal is measured between two equal and
opposite signals which swing around a fixed potential
(common-mode level)
You can decompose differential signals into a differential
mode (difference) and a common-mode (average
Single-Ended & Differential Signals
3
2

+
+
+
= =
out out
CM out out DM
V V
V V V V
Differential Signal Single-Ended Signal
Single-Ended & Differential Amplifiers
4
Differential signaling
advantages
Common-mode noise
rejection
Higher (ideally double)
potential output swing
Simpler biasing
Improved linearity
Main disadvantage is area,
which is roughly double
Although, to get the same
performance in single-ended
designs, we often have to
increase the area
dramatically
( )
Tn GS DD
V V V
Swing Output Max
( ) ( )
Tn GS DD
V V V 2
Swing Output Max
Common-Mode Level Sensitivity
5
A design which uses two single-ended amplifiers to realize a
differential amplifier is very sensitive to the common-mode
input level
The transistors bias current and transconductance can vary
dramatically with the common-mode input
Impacts small-signal gain
Changes the output common-mode, which impacts the maximum
output swing
Differential Pair
6
An improved differential amplifier topology utilizes a tail
current source to keep the transistor bias current ideally
constant over the common-mode input range
Allows for a constant small-signal gain and output common-
mode level
Note, you still have to have keep the input pair and tail current
source transistors in saturation
D
SS
DD CM O
D D D m m m
D m
in in
out out
DM
R
I
V V
R R R g g g
R g
V V
V V
A
|

\
|
=
= = = =
=

=
2
and where
,
2 1 2 1
2 1
2 1
Differential Pair Input-Output Characteristics
7
For large-signal differential inputs, the maximum output
levels are well defined and ideally independent of the input
common-mode
For small-signal differential inputs, the small-signal gain is
maximum at low-input signal levels
As the differential input level increases, the circuit becomes more
nonlinear and the gain decreases
Differential Pair I-V Characteristics
8
( ) ( )
( ) ( )
( )
( ) ( ) ( )
( ) ( ) ( )
2
2 1
4
2 1
2
2
2 1
2
2 1
2
2
2 1
2
2 1 2 1
2 1
2
2 1
2 1
2
2 1
2 1
2 1
2 1
2 1 2 1 2 1
4
1
4 using and sides both Squaring
2
2
1
2
2
using and sides both Squaring
2 2
: Difference Voltage Input
in in ox n SS in in ox n D D
D D ss D D D D D D
D D SS in in ox n
D D SS
ox n
in in
SS D D
ox n
D
ox n
D
in in
T GS T GS GS GS in in
V V
L
W
C I V V
L
W
C I I
I I I I I I I I I
I I I V V
L
W
C
I I I
L
W
C
V V
I I I
L
W
C
I
L
W
C
I
V V
V V V V V V V V
+
|

\
|
=
= + =
=
=
= +
=
= =

( ) ( )
2
2 1 2 1 2 1
4
2
1
in in
ox n
ss
in in ox n D D
V V
L
W
C
I
V V
L
W
C I I =

Differential Pair I-V Characteristics

9
( ) ( )
2
2 1 2 1 2 1
4
2
1
in in
ox n
ss
in in ox n D D
V V
L
W
C
I
V V
L
W
C I I =

The differential current is an odd function

of the differential input voltage which
increases linearly for small inputs
For large differential input voltages, the
output differential current compresses due
to the sqrt term
The differential output current maxes out
when all the current flows through one
transistor at AV
in1
L
W
C
I
V
ox n
ss
in

2
1
= A
Differential Pair I-V Characteristics
10
The differential output current will saturate if
the differential input voltage exceeds sqrt(2)
times the equilibrium input overdrive voltage
( )
2
: Overdrive Input al Differenti Zero
overdrive input al differenti zero the to this relate can We
2
: Input al Differenti Maximum
of all support must M1 , At this
ideally , 0 For
0
M1 through flows current all when case he consider t range current maximum For the
1
2 , 1
1 1
1
1 1 2 1
2 2
1 1 2 1
in
ox n
SS
T GS
ox n
SS
T GS in
SS in
in T GS GS GS in
T GS D
SS D SS D D D
V
L
W
C
I
V V
L
W
C
I
V V V
I V
V V V V V V
V V I
I I I I I I
A
= =
= = A
A
A = = = A
= =
= = =

Differential Pair Transconductance

11
The differential pair transconductance and gain is maximum near zero
input differential voltage
( ) ( )
D ss ox n D m v
D
ss ox n m
in
in
ox n
ss
in
ox n
ss
ox n
in
D
m
in in in D D D
in in
ox n
ss
in in ox n D D
R I
L
W
C R G A
R
I
L
W
C G
V
V
L
W
C
I
V
L
W
C
I
L
W
C
V
I
G
V V V I I I
V V
L
W
C
I
V V
L
W
C I I

= =
=
= A
A
A
=
A c
A c
=
= A = A
=
is gain signal - small the , resistors load the g Considerin
is 0 at uctance transcond signal - small The
4
2
4
2
1
and Define
4
2
1
2
2
2 1 2 1
2
2 1 2 1 2 1
Differential Pair Small-Signal Analysis
Method 1 - Superposition
12
The X output from Vin1 is modeled as a
degenerated CS amplifier
Find V
out
(V
in1
)
2
1
and that Note
2
1
1 1
1
2 1 2 1
D m
m
m
D m
in
X
D D D m m m
R g
g
g
R g
V
V
R R R g g g
=
+

=
= = = =
Differential Pair Small-Signal Analysis
Method 1 - Superposition
13
The Y output from Vin1 is modeled as a
Thevenin equivalent driving a CG amplifier
Find V
out
(V
in1
)
2
1
and that Note
1
2
1 2
1
2 1 2 1
D m
m
m
D m
in
Y
D D D m m m
R g
g
g
R g
V
V
R R R g g g
=
+
=
= = = =
Differential Pair Small-Signal Analysis
Method 1 - Superposition
14
( )
( )
( ) ( )
D m
in in
in in D m
in in
tot Y X
in D m
V
Y X
V
out
V
out
V
out
in D m in
D m D m
in
m
m
D m
m
m
D m
V
Y X
V
out
V
out
R g
V V
V V R g
V V
V V
V R g V V V
V V
V R g V
R g R g
V
g
g
R g
g
g
R g
V V V
V
in in
in in
in in
in
=

= =
=
=
|

\
|

=
|
|
|
|

\
|
+

= =
2 1
2 1
2 1
2
1 1 1
1
2
1 2
2
1
1 1
: Gain al Differenti
symmetry, circuit the From
2 2
1 1
total the find To
2 2
1 2
1 1
1
Differential Pair Small-Signal Analysis
Method 2 Half Circuit
The symmetric differential pair can be modeled as a
Thevenin equivalent to observe how the tail node P
changes with the differential input signal
If R
T1
=R
T2
and the input is a truly differential signal, node
P remains constant
This allows the tail node to be treated as a virtual ground
15
Differential Pair Small-Signal Analysis
Method 2 Half Circuit
16
( )
( )
D m
in
in D m
in in
Y X
D m
in
Y
D m
in
X
R g
V
V R g
V V
V V
R g
V
V
R g
V
V
= =


=

=
1
1
1 1
1
1
2
2
: Gain al Differenti
Applying the virtual ground concept allows modeling as
two half circuits
Differential Pair Common-Mode Response
Ideally, a differential amplifier completely rejects
common-mode signals, i.e. A
v,CM
=0
In reality, the finite tail current source impedance results
in a finite common-mode gain
17
SS m
D m
SS m
D
m
CM in
out
CM v
R g
R g
R g
R
g
V
V
A
2 1 2 1
2
2
,
,
+
=
+
|

\
|
= =
Differential Pair with Diode Loads
While the gain of this amplifier is relatively small,
it is somewhat predictable, as it is defined by the
ratio of the transistor sizes and the n/p mobility
18
3
1
3
1
3
1
3
1
3 3 1
1
0 Assuming
|

\
|
|

\
|
=
|

\
|
|

\
|
= ~
~
+ +
=
=
L
W
C
L
W
C
I
L
W
C
I
L
W
C
g
g
A
g
g
g g g
g
A
ox p
ox n
SS ox p
SS ox n
m
m
v
m
m
o m o
m
v

Differential Pair w/ Current-Source Loads

While the gain of this amplifier is higher, it is somewhat
unpredictable, as it is defined by the transistor output
resistance, which changes dramatically with process
variations
19
3 1
1
0 Assuming
o o
m
v
g g
g
A
+
=
=
Differential Pair w/
Diode & Parallel Current-Source Loads
Adding a parallel current source to a diode connected load
allows for increase gain which is still somewhat predictable
20
( )
load diode the from steals" " source current that the percentage current the is where
1
0 Assuming
3
1
3
1
3
1
5 3 3 1
1
o
o

SS ox p
SS ox n
m
m
v
m
m
o o m o
m
v
I
L
W
C
I
L
W
C
g
g
A
g
g
g g g g
g
A

\
|
|

\
|
= ~
~
+ + +
=
=
Cascode Differential Pair
21
( ) ( ) ( )
( )
5 7 5 3 1 3 1
5 7 5 7 5 3 1 3 1 3 1
0 Assuming
o o m o o m m v
o o m o o o o m o o m v
r r g r r g g A
r r g r r r r g r r g A
~
+ + + + =
=
Using a cascode differential
pair and cascode current-
source loads allows for a
considerable increase in gain
However, a relatively large
power supply may be required
to supply the necessary voltage
headroom to keep all the
transistors in saturation