Microelectronics Solution Problem

Microelectronics Today Problems and Solutions
Frank Sill Torres

OptMAlab / ART Universidade Federal de Minas Gerais (UFMG), Brazil
Sill Torres: Microelectronics
About Me
Im German (from the NorthEast)
Master / PhD. in Electrical Engenering / Microelectronics (Universitt Rostock, Germany) Research areas:
Low Power Integrated Circuit (IC) Design IC Design for Reliability (analog / digital) Nanoelectronics ...
Outline 1. Areas of Microelectronics 2. Chip Design 3. State of the Art 4. Problems 5. Solutions 6. Microelectronics at UFMG and in Brazil
Areas of Microelectronics
Process/Devices
All activities related to chip fabrication (Lithography, Etching, Ion Implantation,) Design of new transistor devices (Bulk-CMOS, SOI, FinFet,) Work on materials for semiconductors MicroElectroMechanical Systems (MEMS), e.g. Microphone of the iPhone4 Micro-lenses Related laboratory at UFMG / EE OptMAlab
Knowles S1950 MEMS Die Clean room - UFMG
Circuits
Design of integrated analog circuits Design of logic cells Design of integrated sensors and actuators Related laboratories at UFMG / EE OptMAlab OptMAlab / ART
high-Vth/Tox Active pixel for digital camera (OptMAlab)
low-Vth/Tox Advanced low leakage cell (OptMAlab/ART)
Systems
Design of integrated systems Application Specific Integrated Systems (ASIC) Processors System on Chip (SOC) Digital / Analog / Mixed-Signal Design of Intellectual Property (IP) blocks FPGA design Related laboratories at UFMG / EE OptMAlab / ART LSI LabSCI
Copyright: ELV.de
Chip Design
Chip Design
Standard Designflow
VHDL, SystemC Synthesis Floorplanning Placement Routing
Textual description of the design Mapping of the design onto logic cells Planing of basic structure of the chip (Size, I/O, power supply, blocks, ) Placement of logic cell on chip
Wiring of logic cells
Production
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ASIC Design
Task Description
Up to 25 years ago: chips developed on drawing board End of 80s: Hardware Description Languages (HDL) Verilog - 1985 VHDL - 1987 Newest developments Object orientated approach SystemC
ASIC Design
Representation with logic cells
Called: Synthesis Conversion of high-level description into logic cells Happens automatic by special tools
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Chip Design
Synthesis Tool (Synopsys DesignVision)
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Chip Design
Determination of Chip Sizes
Called: Floorplanning Planning of basic structure of the chip (Size, Inputs/Outputs, power supply, blocks) What decides the chip size?
PAD-limited CORE-limited BLOCK-limited
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Chip Design
Floorplanning Tool (Cadence Second Encounter) Menu Layer selection
Tools
Coordinates Overview window Control output
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Chip Design
Placement
Placement of logic cells Usually: Standard cells Uniform cell height Different widths Tool support
Copyright: Weste, 2011
Copyright: Yu, UC Davies
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Chip Design
Placement - Example
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Chip Design
Routing
Placing of wires that connect logic cells Two Phases: Global Routing Detailed Routing Tool support
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Chip Design
Routing - Examples
Ref.: Wikipedia
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Chip Design
Fabrication
Design project saved as file (e.g. GDS2) sent to fab Fab: Fabrication, packing, and testing Very expensive (e.g. Intel 14 nm - USD 5 Billion, GlobalFoundries 28 nm USD 4.6 Billion, source: Wikipedia)
CEITEC S.A., Rio Grande do Sul (Work in Progress, 0.6 um)

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Chip Design
Design Houses
In the past
Chip designer and factories together Intellectual Property belongs to factory
Today
Chip designers and factories separate Intellectual Property stays with designer
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State of the Art
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State of the Art

Overview
Technology sizes: starting from 22 nm Processors with 64 bit Multi-cores Processors for Servers (Opteron, Xeon, ) PCs (Core i3/i5/i7, Fusion, ) Smartphones / Pads (ARM, Atom, ...) High integration of functionalities Memory controller Graphic card
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State of the Art

Processors
500 500
Transistors [Mill.] [Mill.] Transistors
130 nm 400 400 300 300 200 200 100 100 0 0

Northwood 55 Mill.
Wolfdale 410 Mill.
150 nm
90 nm
Yonah 65 nm 151 Mill. Prescott 125 Mill. Yonah, 151 Mill.
100 nm
45 nm
50 nm
0 nm
2002 2002
2004 2004
Year Year
2006 2006
2008 2008
Technology
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State of the Art

Dimensions
1 m 10 cm 100 nm 10 1 1 mm cm m m
Source: Spektrum der Wissenschaften
22 nm-Transistor
Source: Intel
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Problems
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Problems
Power Dissipation
SoC Consumer Portable Power Trend [Source: ITRS, 2010 Update]

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Problems
Power Density
Nuclear Reactor
Hot Plate
Source: http://cpudb.stanford.edu/
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Problems
Leakage
MOS-Transistor: Basic Element
Conducting:
Current flow Dynamic power dissipation Until early 2000s dominating
Closed (ideal):
No Current No power dissipation
Closed (real):
Still current flow (Leakage) Power dissipation
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Problems
Subthreshold Leakage Isub
Threshold Voltage Vth

Transistor characteristic If: Gate-Source-Voltage Vgs higher than Vth Current between Drain and Source If: Vgs lower than Vth (ideal) No current Source
Source
Vgs > Vth

Gate
Gate
Drain
Isub
Drain
Subthreshold leakage Isub

Leakage between Drain and Source when Vgs < Vth Based on: Short Channels Diffusion Thermionic Emission
high Concentration Diffusion
Low concentration
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Problems
Gate Leakage Igate
Tunneling effect Electromagnetic wave strikes at barrier: Reflection + Intrusion into barrier If thickness is small enough: Wave interfuses barrier partially: (Electrons tunnel through barrier) Gate oxide leakage Igate At transistors with Tox< 2 nm Electrons tunnel through gate oxide Leakage current
Igate
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Problems
Process Failures
Occur at production phase Based on Process Variations Particles
Source: Mak
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Problems
Electromigration
Transport of material caused by the gradual movement of ions in a conductor Major failure mechanisms in interconnects Proportional to width and thickness of metal lines Inversely proportional to current density
Top View
Void Metal 1
Metal 1
Whisker, Hillock Cross Section View Metal 1 Metal 2

Source: Plusquellic, UMBC
31
Problems
Electromigration contd Void in 0.45mm Al-0.5%Cu line
Source: IMM-Bologna
Whiskers in Sn
Source: EPA Centre
Hillocks in ZnSn
Source: Ku&Lin,2007
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Problems
Gate Oxide Breakdown
Tunneling currents Wear out of gate oxide Creation of conducting path between Gate and Substrate, Drain, Source Depending on electrical field over gate oxide, temperature (exp.), and gate oxide thickness (exp.) Also: abrupt damage due to extreme overvoltage
Source: Pey&Tung Source: Pey&Tung
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Problems
Soft Errors
Source: Automotive 7-8, 2004
In 70s observed: DRAMs occasionally flip bits for no apparent reason Ultimately linked to alpha particles and cosmic rays Collisions with particles create electron-hole pairs in substrate These carriers are collected on dynamic nodes, disturbing the voltage
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Problems
Soft Errors contd
Internal state of node flips shortly If error isnt masked by

Logic: Wrong input doesnt lead to wrong output Electrical: Pulse is attenuated by following gates Timing: Data based on pulse reach flipflop after clock transistion
wrong data
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Problems
Temperature Variations
Drain current IDS [pA]
Temperature [C]
Threshold voltage Vth changes with temperature drain-source current changes delay changes Source: Burleson, UMASS, 2007
Delay [s]
36
Problems
Failures due to Increasing Delay Data are processed before clock phase is over
Clk
Clock (Clk)
Logic too slow!
Data processing
Clk
longer than clock phase Wrong Data in next clock phase! 37
Solutions
38
Solutions
New Technologies
For example: Intel
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Solutions
Basics: Delay and Power versus VDD
6 Relative Delay td 5 4 3 2 1 0 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 Supply voltage (VDD) 10
td
6 4 2 0
Dynamic Power can be traded by delay

Relative Pdyn
Pdyn
40
Solutions
Adaptive Dynamic Voltage/Frequency Scaling (DVS/DFS)
Slow down processor to fill idle time More Delay lower operational voltage
Active
Idle
Active
Idle
3.3 V 2.4 V
Active
Runtime Scheduler determines processor speed and selects appropriate voltage Transitions delay for frequencies <150s Potential to realize 10x energy savings E.g.: Intel SpeedStep, AMD PowerNow, Transmeta Longrun
41
Solutions
DVS/DFS with Transmeta LongRun
100 % of max powerl consumption 90 80 70 60 50 40 30 20 10 0 300
300 Mhz 0.80 V
Typical operating region
Peak performance region
400
433 Mhz 0.87 V
500
533 Mhz 0.95 V
600
700
667 Mhz 1.05 V
800
800 Mhz 1.15 V
900
900 Mhz 1.25 V
1000
1000 Mhz 1.30 V
Frequency (MHz)
Source: Transmeta
42
Solutions
Clock Gating
Most popular method for power reduction of clock signals and functional units Gate off clock to idle functional units Logic for generation of disable signal necessary Strong reduction of dynamic power dissipation
clock disable
R Functional e unit g
43
Solutions
Clock Gating: Example Without clock gating
30.6mW
With clock gating
8.5mW
VDE
DEU
10
15
Power [mW]
20
25
MIF 896Kb SRAM
DSP/ HIF
90% of FlipFlops clock-gated 70% power reduction by clock-gating
MPEG4 decoder
Source: M. Ohashi, Matsushita, 2002
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Solutions
Power-orientated Programming
14000
Switched Capacitance (nF)
12000 10000 8000 6000 4000 2000 0 bubble.c heap.c quick.c

Source: Irwin, 2000
Others Functional Unit Pipeline Registers Register File
Algorithms can differ in power dissipation

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Solutions
Basics: Stack Effect
Transistor stack: at least two transistors in a row Based on behavior of internal nodes: The more transistors are non-conducting (off) the lower the leakage
Source: Roy, Lecture
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Solutions
Sleep Transistors
Idea: Insertion of additional transistors between logic block and supply lines These transistors: connected with SLEEP-signal
sleep
Vdd Virtual Vdd
If circuit has nothing to do: SLEEP signal is active: Stack effect (additional off transistor in row to other)
Circuit sleep Virtual Vss Vss
Mostly insertion only of 1 transistor
Source: Kaijian Shi, Synopsys
47
Solutions
Basics: Relation of Vth, Delay and Leakage
Threshold Voltage Vth:

Influence on sub-threshold leakage Isub Influence on delay of logic gates
Isub
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Solutions
Dual-Vth
LVT- Cells
Cells consist of transistors with low Vth Low delay High leakage For critical paths
HVT- Cells
Cells consist of transistors with high Vth Longer delay Low leakage For uncritical paths
Leakage reduction at constant performance

49
Solutions
Dual-Vth Example
LVT- Cells HVT- Cells
Critical Path
50
Solutions
Triple Module Redundancy (TMR)
Input
Logic L
A
Copy of Logic L Copy of Logic L
B C
Voter
Output
51
Solutions
Self Adaptive Design
Extend idea of clock domains to Adaptive Power Domains Tackle static process and slowly varying timing variations Control VDD, Vth (indirectly by body bias), fclk by calibration at Power On
Test inputs and responses
VDD
fclk
Test Module VBB
Module
52
Solutions
Reliability Enhancement via Sleep Transistors
Basic idea: Reduction of degradation via module deactivation Problem: What to do at run-time? Module 1 Instance 1 Module 2
SLEEP
Module 1 Instance 2
MUX
53
Opportunities in Brazil and Activities at UFMG
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Opportunities in Brazil
CEITEC S.A. Design House and Chip factory (Rio Grande do Sul) Over 22 Design Houses DHBH in Belo Horizonte MINASIC in Itajub CTI, Eldorado, LSI-TEC, von Braun, Many other companies, e.g.: AEGIS / SEMIKRON: Power devices SMART / HT Micron: Back-end for memories FREESCALE: Design center
55
Opportunities in Brazil contd

Minas Gerais InventVision - Optical Systems, FPGA Jasper - Verification CBS (wafer production) - planned CMinas (MEMS) - planned Foxconn (Displays) - planned
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Activities at UFMG / EE
OptMAlab
Laboratory for Optronics and Microtechnologies (OptMAlab) Located at PPGEE / UFMG Coordinator: Dr. Davies William de Lima Monteiro Adaptive Optics: wavefront aberration, components and systems Microelectronics: Analog Integrated-Circuit design custom pixels, image sensors and optical position-sensitive devices (PSDs) Micromachining: silicon wet processing micro-optics Ophthalmic Optics: technology and characterization of intraocular lenses Photovoltaics: alternative self-configurable cells
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OptMAlab - IC for read-out for infrared sensor CMOS AMS 0.35m Chip area: 12 mm2 3.3V e 5.0V > 90 pins > 60 structures Digital circuits Analog circuits Mixed-Signal Circuits Photo-diodes Photo-resistors
58
OptMA - ART
Asic-ReliabiTiy (OptMAlab / ART) Extension of OptMAlab at PPGEE/UFMG Coordinator: Frank Sill Torres Dedicated to reliability in micro- and nanoelectronics applications Activities in the field of Design for Reliability Low Leakage / Low Power Chip Design Development of CAD tools extensions Robust Nanoelectronics More information: www.asic-reliabity.com
59
OptMA ART / Reliable Adder CMOS AMS 0.35m Chip area: 1 mm2 3.3V > 10 pins Test structures Modified logic cells Sleep Transistors Prepared for Controlled Destruction
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LSI Laboratrio de Sistemas Inteligentes

Projeto: Desenvolvimento de um Sistema de Determinao de Atitude com Tolerncia a Falhas para Satlites de Baixa rbita. Projeto Financiado pela AEB Programa UNIESPAO
Colaboradores: INPE, UFABC, OptMa
Sntese do Projeto:
O que Atitude Satlites que operam em Baixa rbita Terrestre O ambiente hostil a que os CIs so colocados em funcionamento. Condies limitadoras: alta preciso de apontamento, baixa potncia, baixo peso, baixo custo e confiabilidade 99,99999% durante a misso.
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62

reas de atuao da Microeletrnica: Entender e modelar o efeito de falhas em CIs. Diversidade de Dispositivos Diversidade de Arquiteturas Diversidade de Ambientes e Situaes Emular o efeito de falhas em CIs. Mitigar o efeito das falhas dos CIs nos Sistemas que os compreendem Tcnicas de Tolerncia a Falhas
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Equipe atual: Fernando Esqurio Torres (bolsista de mestrado CPDEE) Thalles Hermes R. Gomes (bolsista PET-EE) Wagno Alves Bragana J. (bolsista PET-EE) Bruno Henrique S. Guimares (voluntrio IC-EE) ... ???? Contato: Prof. Ricardo de Oliveira Duarte Email: ricardoduarte@ufmg.br Sala pessoal: 2521 Sala do LSI: 2515
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Thank you!
franksill@ufmg.br
OptMAlab / ART www.asic-reliability.com
66
Solutions
Network on Chip
67

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Microelectronics Today Problems and Solutions

Frank Sill Torres

Sill Torres: Microelectronics

Sill Torres: Microelectronics

Sill Torres: Microelectronics

low-Vth/Tox Advanced low leakage cell (OptMAlab/ART)

Sill Torres: Microelectronics

Sill Torres: Microelectronics

VHDL, SystemC Synthesis Floorplanning Placement Routing

Wiring of logic cells

Sill Torres: Microelectronics

Sill Torres: Microelectronics

Sill Torres: Microelectronics

Coordinates Overview window Control output

Sill Torres: Microelectronics

Copyright: Yu, UC Davies

Sill Torres: Microelectronics

Copyright: Yu, UC Davies

Sill Torres: Microelectronics

Sill Torres: Microelectronics

Copyright: Yu, UC Davies

Sill Torres: Microelectronics

CEITEC S.A., Rio Grande do Sul (Work in Progress, 0.6 um)

State of the Art

Sill Torres: Microelectronics

State of the Art

Sill Torres: Microelectronics

State of the Art

Transistors [Mill.] [Mill.] Transistors

130 nm 400 400 300 300 200 200 100 100 0 0

Wolfdale 410 Mill.

Sill Torres: Microelectronics

State of the Art

Source: Spektrum der Wissenschaften

Sill Torres: Microelectronics

Sill Torres: Microelectronics

SoC Consumer Portable Power Trend [Source: ITRS, 2010 Update]

Sill Torres: Microelectronics

MOS-Transistor: Basic Element

Threshold Voltage Vth

Vgs > Vth

Subthreshold leakage Isub

Sill Torres: Microelectronics

Occur at production phase Based on Process Variations Particles

Sill Torres: Microelectronics

Whisker, Hillock Cross Section View Metal 1 Metal 2

Sill Torres: Microelectronics

Sill Torres: Microelectronics

Internal state of node flips shortly If error isnt masked by

Sill Torres: Microelectronics

Drain current IDS [pA]

Logic too slow!

longer than clock phase Wrong Data in next clock phase! 37

Sill Torres: Microelectronics

For example: Intel

Sill Torres: Microelectronics

Dynamic Power can be traded by delay

Sill Torres: Microelectronics

Typical operating region

Peak performance region

Sill Torres: Microelectronics

Sill Torres: Microelectronics