Expt.

2:

INTRODUCTION TO ARM PROCESSOR/LPC2103

Aim: To study the ARM processor / LPC2103 The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as THUMB, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind THUMB is that of a superreduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets: The standard 32-bit ARM instruction set. A 16-bit THUMB instruction set. The THUMB sets 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARMs performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because THUMB code operates on the same 32bit register set as ARM code. The LPC2101/02/03 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with 8 kB, 16 kB, or 32 kB of embedded high speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical performance in interrupt service routines and DSP algorithms, this increases performance up to 30 % over the Thumb mode. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty.

Features: 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP48 package. 2 kB/4 kB/8 kB of on-chip static RAM and 8 kB/16 kB/32 kB of on-chip flash program memory. 128-bit wide interface/accelerator enables high-speed 70 MHz operation. In-System/In-Application Programming (ISP/IAP) via on-chip boot loader software. Single flash sector or full chip erase in 100 ms and programming of 256 bytes in 1 ms. EmbeddedICE RT offers real-time debugging with the on-chip RealMonitor software. The 10-bit A/D converter provides eight analog inputs, with conversion times as low as 2.44 s per channel, and dedicated result registers to minimize interrupt overhead. Two 32-bit timers/external event counters with combined seven capture and seven compare channels. Two 16-bit timers/external event counters with combined three capture and seven compare channels. Low power Real-Time Clock (RTC) with independent power and dedicated 32 kHz clock input. Multiple serial interfaces including two UARTs (16C550), two Fast I2C-buses (400 kbit/s), SPI and SSP with buffering and variable data length capabilities. Vectored interrupt controller with configurable priorities and vector addresses. Up to thirty-two 5 V tolerant fast general purpose I/O pins. Up to 13 edge or level sensitive external interrupt pins available. 70 MHz maximum CPU clock available from programmable on-chip PLL with possible input frequency of 10 MHz to 25 MHz and a settling time of 100 s. On-chip integrated oscillator operates with an external crystal in the range from 1 MHz to 25 MHz. Power saving modes include Idle mode, Power-down mode, and Power-down mode with RTC active. Individual enable/disable of peripheral functions as well as peripheral clock scaling for additional power optimization. Processor wake-up from Power-down mode via external interrupt or RTC.

Block diagram:

Applications: Industrial control Medical systems Access control Point-of-sale Communication gateway Embedded soft modem General purpose applications.

Expt. 3:

ADDRESSING MODES OF ARM PROCESSOR

Aim: To write a program to explore various addressing modes of ARM processor. Hardware/Software requirement(s): 1. ARM processor / LPC2013 2. Crossware 3. Flash Magic Theory: There are different ways to specify the address of the operands for any given operations such as load, add or branch. The different ways of determining the address of the operands are called addressing modes. Name Alternative Name ARM Examples -----------------------------------------------------------------------------------------------------------------Register to register Register direct MOV R0, R1 -----------------------------------------------------------------------------------------------------------------Absolute Direct LDR R0, MEM -----------------------------------------------------------------------------------------------------------------Literal Immediate MOV R0, #15 ADD R1, R2, #12 -----------------------------------------------------------------------------------------------------------------Indexed, base Register indirect LDR R0, [R1] -----------------------------------------------------------------------------------------------------------------Pre-indexed, Register indirect LDR R0, [R1, #4] base with displacement with offset ------------------------------------------------------------------------------------------------------------------Pre-indexed, Register indirect LDR R0, [R1, #4]! autoindexing pre-incrementing -----------------------------------------------------------------------------------------------------------------Post-indexing, Register indirect LDR R0, [R1], #4 autoindexed post-increment -----------------------------------------------------------------------------------------------------------------Double Reg indirect Register indirect LDR R0, [R1, R2] Register indexed -----------------------------------------------------------------------------------------------------------------Double Reg indirect Register indirect LDR R0, [R1, r2, LSL #2] with scaling indexed with scaling ----------------------------------------------------------------------------------------------------------------Program counter relative LDR R0, [PC, #offset]

// Program to explore the Addressing Modes for ARM7 ORG main B basic LDR MOV B offset MOV MOV MOV LDR STRB STRB STRB B preindex MOV MOV MOV STRB STRB STRB B postindex MOV MOV MOV STRB STRB B ORG table END basic R0,table R0,#table offset R0,#0X00 R1,#0X50 R2,#0X10 R0,[R1] R0,[R1,#0x10] R0,[R1,R2] R0,[R1,R2,LSL #02] preindex R0,#0X00 R1,#0X50 R2,#0X10 R0,[R1,#0x10]! R0,[R1,R2]! R0,[R1,R2, LSL #2]! postindex R0,#0X33 R1,#0X50 R2,#0X3 R0,[R1],#0x10 R0,[R1],R2,LSL #02 main 0x0100 DCDU 0X12345678 ; ; ; 0x0000

; ; ; ; ; ; ; ;

Go & Set RAM50=0x33 define the offset load using offset store using offset R1+R2

; define the offset ; ; store using preindex ; R1+R2 ;

; define the offset ; ; store using postindex ; ; ;

Expt. 4:

INTERRUPTS IN ARM PROCESSOR

Aim: To write a program to generate software interrupt using ARM processor.

Hardware/Software requirement(s): 1. ARM processor / LPC2013 2. Crossware 3. Flash Magic

Theory: The processor has two interrupt inputs, for normal interrupts (nIRQ) and fast interrupts (nFIQ). Each interrupt pin, when asserted and not masked, causes the processor to take the appropriate type of interrupt exception. The CPSR.F and CPSR.I bits control masking of fast and normal interrupts respectively. A number of features exist to improve the interrupt latency, that is, the time taken between the assertion of the interrupt input and the execution of the interrupt handler. By default, the processor uses the Low Interrupt Latency (LIL). The processor also has a port for connection of a Vectored Interrupt Controller (VIC), and supports Non-Maskable Fast Interrupts (NMFI).

Conclusion: Thus we demonstrate the working of a software interrupt in ARM processor.

// Program to demonstrate the working of software interrupt ORG B ORG swi MOV ORG main MOV MOV loop ADD CMP B END 0x0000 main 0x0008 R15,R14 0x0050 R0,#0x05 R1,#0x00 R1,R1,#0x1 R0,R1 0x55 loop ; Keep small number ; ; increment by 1 ; compare R0,R1 ; ; ; RETURN

SWIEQ

Expt. 5:

LED INTERFACING IN ARM PROCESSOR

Aim: To write a program to interface LED using ARM processor.

Hardware/Software requirement(s): 1. ARM processor / LPC2013 2. Crossware 3. Flash Magic

Theory: The port pins of the LPC2103 microcontrollers have a 4 mA driving capacity, enough to directly drive the LEDs in a 7-segment display. There are actually 8 LEDs since there is also a dot LED. The LEDs in the display are connected to pin P0.16 - P0.18, P0.26 P0.30. The 470 ohm resistors limit the current to about 3.5 mA. A low output pin drives current through the LEDs and they will light.

Conclusion: Thus we are able to blink the LED on the ARM processor.

// Simple LED flashing program using delay ALL32 ORG B ORG main MOV LDR STR MOV LDR STR MOV LDR STR flash MOV LDR STR BL MOV LDR STR BL B delay LDR R5,dcount ; load in r1 R0,#0xFF R0,[R1] delay R0,#0xFF R0,[R1] delay flash ; ; pioclr =f ; our delay loop ; R1,PIOCLR ; ; ; pioset =f ; our delay loop R1,PIOSET ; R0,#0 R1,PINSEL0 R0,[R1] R0,#0 R1,PINSEL1 R0,[R1] R0,#0xFF R1,PIODIR R0,[R1] ; ; ; pinsel0 =0 ; ; ; pinsel1 =0 ; ; ; pinsel0 =0 EQU main 0x0050 0xFFFFFFFF 0x0000

loop BNE MOV ORG PINSEL0 PINSEL1 PIOPIN PIOSET PIODIR PIOCLR dcount END

MOV loop

R5,R5

; like NOP ; decrement by 1 ; RETURN

SUBS R5,R5,#0x001 R15,R14 0x0150

DCDU 0xE002C000 DCDU 0xE002C004 DCDU 0xE0028000 DCDU 0xE0028004 DCDU 0xE0028008 DCDU 0xE002800C DCDU 0x0000F005 ; LED flash frequency

Expt. 6:

SERIAL COMMUNICATION USING ARM PROCESSOR

Aim: To write a program to display a message serially, using ARM processor.

Hardware/Software requirement(s): 1. ARM processor / LPC2013 2. Crossware 3. Flash Magic

Theory: ARM processor includes a blend of serial communications interfaces, ranging from multiple UARTS, SPI, and SSP to two I2Cs, and on-chip SRAM of 2 kB/4 kB/8 kB make these devices very well suited for communication gateways and protocol converters. Multiple serial interfaces including two UARTs (16C550), two Fast I2C-buses (400 kbit/s), SPI and SSP with buffering and variable data length capabilities Pin Type Description: RXD0 Input Serial Input - Serial receive data. TXD0 Output Serial Output - Serial transmit data.

The APB interface provides a communications link between the CPU or host and the UART0. The UART0 receiver block, U0RX, monitors the serial input line, RXD0, for valid input. The UART0 RX Shift Register (U0RSR) accepts valid characters via RXD0. After a valid character is assembled in the U0RSR, it is passed to the UART0 RX Buffer Register FIFO to await access by the CPU or host via the generic host interface. The UART0 transmitter block, U0TX, accepts data written by the CPU or host and buffers the data in the UART0 TX Holding Register FIFO (U0THR). The UART0 TX Shift Register (U0TSR) reads the data stored in the U0THR and assembles the data to transmit via the serial output pin, TXD0.

Conclusion: Thus, we can successfully transfer any message serially, using the ARM processor.

// Initial C Source File #include "xstdsys.h" #include <stdio.h> #define CR 0x0D #define BAUDRATE 9600 #define XTAL 16000000 void UART0(void); void putch (unsigned char ch); void putch (unsigned char ch) { /* Write character to Serial Port*/ if (ch == '\n') { while (!(U0LSR & 0x20)); U0THR = CR; } while (!(U0LSR & 0x20)); U0THR = ch; return; }

/* output CR */

/* Please note PCLK is 1/4 of XTAL */ void UART0 (void) { PINSEL0 = 0x05; // Select TxD and RxD on pin connect block U0LCR = 0x80; //Enable programming of divisor latches // The APB Divider register contains two bits, allowing three divider values // At reset APB = 00 hence PCLK = XTAL/4 = 11059200/4 /* U0DLL = 0xC2; //Program the divisor latch for 19200 baud */ //U0DLL = (PCLK/(16L * BAUDRATE)); //16 clock periods per machine cycle U0DLL = 0x1A; // 10Mhz = 10h, 16Mhz = 1Ah, 11.0592 = 12h U0DLM = 0x00; U0LCR = 0x03; 8\N\1 U0FCR = 0x07; } //Program the line control

main() { // use the Wizards (see Wizards menu) to configure the onchip peripherals // later or alternatively right mouse click on a source code view to access an alternative interface to the Wizards UART0 (); //Initilise the UART printf("Hello, Welcome to K.C.College \n"); while(1) { //Do nothing loop requires reset to come out } }