DIGITAL ELECTRONICS

Chew Chee Meng

Department of Mechanical Engineering
National University of Singapore
2
3
Objectives
Understand different digital representations
Know the characteristics of different logic
gates
Use Boolean Algebra to analyze logic circuits
Use Karnaugh map to minimize logic
expression
Able to design a logic network given a
combinational logic problem
4
Introduction
Analog signal
Each amplitude in a continuous range has a unique
significance, E.g. analog position sensor
Examples of analog signals:
0
DC Voltage
Sinusoidal Voltage
Random Voltage
t
t
t
Potentiometer
Position Sensor
5
Introduction
Digital signal
Only a few restricted ranges of amplitude are allowed
Each amplitude in a given range has same
significance
Examples of digital signals: Binary signals
t
t
5
10
-10
1 1
1
1 1
0 0 0
0
0
1 0 1
1
0
1
0
6
Introduction
Binary signals
ON or OFF
1 or 0
Represented by voltage levels
Positive logic
Negative logic
7
Advantages of Digital System
Robust to noise
Provided that the noise
amplitude is not too
large, the logic values
represented by a digital
signal can still be
determined after noise is
added
8
Advantages of Digital System
Component values in digital circuits need not
be as precise as in analog circuits
9
Advantages of Digital System
Low power dissipation
With modern IC technology, it is possible to
manufacture complex digital circuits
economically.
Most quantities in the real world are analog!
Digital Representations
Base 10 (Decimal) Number System
Base 10 (10 different symbols to represent a digit) symbols
are: 0,1,2,3,4,5,6,7,8,9
Each digit a placeholder for different powers of 10:
n = number of digits
d
i
(one of the ten symbols)
10
Digital Representations
Base 2 (Binary) Number System
Base 2 (2 different symbols to represent a digit) symbols
are: 0,1
Each digit a placeholder for different powers of 2:
n = number of digits or bits
d
i
(0 or 1)
11
d
o
: least significant bit (LSB) (smallest power of 2)
d
n-1
: most significant bit (MSB) (largest power of 2)
Digital Representations
Base 16 (Hexadecimal)
Number System
Base 16 (16 different symbols
to represent a digit) symbols
are:
0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
To convert a binary number to
hexadecimal in groups of four
digits beginning with the least
significant bit
E.g. 0111 1011
2
= 7B
16
12
Hexadecimal symbols
and equivalents
Digital Representations
BCD (Binary Coded Decimal)
4 bits used to represent a single
decimal
Eg. 123
10
= 0001 0010 0011
bcd
cf. 123
10
= 0111 1011
2
13
14
Digital Devices
Convert digital inputs into digital outputs
(D/D)
Two categories of digital devices:
Combinational logic: outputs depend only on
the instantaneous values of the inputs.
Sequential logic: the timing, or sequencing
history, of the input signals plays a role in
determining the output.
15
Logic Gates
Basic components in digital devices
Basic logic gates:
AND gates,
OR gates,
NOT gates (Inverters) .
16
Logic Gates
AND Gates
Symbol
Truth table of AND gate
A
B
A B Z
0 0 0
0 1 0
1 0 0
1 1 1
With 'n' inputs, 2
n
input combinations possible
Z
7408/5408
Quad 2-Input AND Gate
17
Logic Gates
AND Gates
Truth table of a 3-input
AND gate
A B C Z
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
Z
A
B
C
7411/5411
Triple 3-Input AND Gate
18
Logic Gates
OR Gates
Symbol
Truth table of OR gate
Z
A
B
A B Z
0 0 0
0 1 1
1 0 1
1 1 1
7432/5432
Quad 2-Input OR Gate
19
Logic Gates
OR Gates
Truth table of a 3-input
OR gate
A B C Z
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
Z
Triple 3-Input OR Gates
74HC4075
20
Logic Gates
Exclusive OR Gate (XOR,EOR)
Symbol
Truth table of XOR gate
A B Z
0 0 0
0 1 1
1 0 1
1 1 0
Z=AB
A
B
Define for 2 inputs
only
7486/5486
Quad 2-Input Exclusive-OR Gate
21
Logic Gates
NOT Gate
Symbol
Truth table of NOT gate
A Z
0 1
1 0
A Z
7404/5404
Hex inverters
22
Logic Gates
Universal Building Blocks
NANDGates (NAND NOT AND)
2-input NANDGate
A B Z
0 0 1
0 1 1
1 0 1
1 1 0
A
B
Z
7400/5400
Quad 2-input
NAND gates
23
Logic Gates
Universal Building Blocks
NANDGates
3-input NANDGate
A B C Z
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
In general, the output of a NAND
gate is a '0' only if all the inputs
are '1's.
A
B
Z
C
24
Logic Gates
Universal Building Blocks
NOR Gates (NOR =NOT OR)
2-input NOR Gate
A B Z
0 0 1
0 1 0
1 0 0
1 1 0
Z
A
B
7402/5402
Quad 2-Input NOR Gate
25
Logic Gates
Universal Building Blocks
NOR Gates (NOR =NOT OR)
3-input NOR Gate
A B C Z
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
In general, output of a NOR gate is a
'1' only if all inputs are '0' s.
26
Logic Gates
Universal Building Blocks
Universality of NAND Gates and NOR Gates
Possible to implement combinational logic circuits using only
NANDs or NORs
COMPLEMENT operation with NANDS, NORS
AND operation using NAND gates
OR operation using NAND gates
X
X
X
X

A
B
A
B

A
B
A
B
OR
28
Logic Gates Applications
Example : A Seat Belt Alarm System
An AND gate is used in a simple automobile seat
belt alarm system to detect when the ignition switch
is on and the seat belt is unbuckled.
Input A: HIGH if ignition switch is on.
Input B: HIGH if seat belt is not properly buckled.
Input C: HIGH when ignition switch is turned on for 30
seconds.
If all three inputs are HIGH, output of AND gate is HIGH
and an audible alarm is energized to remind driver.
29
Logic Gates Applications
Example: (cont)
Alarm
circuit
Timer
Ignition
switch
Seat
belt
HIGH =On
LOW =Off
HIGH =Unbuckled
LOW =Buckled
Ignition on
30 s HIGH
A
B
C
30
Boolean Algebra
Mathematical tool for digital systems which
contain of variables having 2 states ( ie either
'1' or '0')
What are basic Boolean operations and rules?
How they can be applied to logic circuits
analyses?
31
Boolean Operations
Boolean addition (OR function) (symbol = '+')
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 1
Note: Not binary addition.
32
Boolean Operations
Boolean multiplication (AND function) (symbol =
.)
0 . 0 = 0
0 . 1 = 0
1 . 0 = 0
1 . 1 = 1
Note: same as binary multiplication
33
Boolean Operations
Complement (NOT function) (symbol= )
(sometimes prime symbol (') is used)
0 1 1
1 0 0
=
'
=
=
'
=
Note: Corresponds to inversion of signal
34
Boolean Operations
Physical realizations of '+' or '' operations are
through 'OR' and 'AND' gates, respectively.
NOT operation is through NOT gate.
In a logical expression involving both '+' and '.',
the '.' operation is performed first. E.g. A . B + C
= (A.B) + C
35
Boolean Expressions of Basic Logic Gates
A Z=
B A Z =
ABC Z=
B
A
B A Z =
B
A
Z=A+B
Alternative Expression: B A Z =
NOT
AND
OR
NOR
NAND
EOR
(XOR)
36
Boolean algebra Laws and Rules
The following basic laws of Boolean algebra are
same as in ordinary algebra.
Commutative Laws
X + Y = Y + X ( 3-1)
XY = YX ( 3-2)
Associative Laws
X + (Y + Z) = (X + Y) + Z ( 3-3)
X(YZ) = (XY)Z ( 3-4)
Distributive Law
X(Y + Z) = XY + XZ ( 3-5)
37
Boolean algebra Laws and Rules
Fundamental rules:
Useful identities:
10) X + XZ = X
11) X(X + Y) = X
12) X +XY = X + Y
13) (X+Y)(X+Y)=X
14) (X+Y)(X+Z)=X+YZ
Etc..
1
1 1
0
= +
= +
= +
= +
X X
X X X
X
X X
0 0
1
0
X
X X
X X X
X X
=
=
=
=
X X =
OR
AND
NOT
1)
2)
3)
4)
5)
6)
7)
8)
9)
38
Boolean algebra Laws and Rules
Example : Proof of Identity 10
X+XZ=X(1+Z) Distributive law
= X.1 Rule 2
= X Rule 6
Example : Proof of Identity 14
(X+Y)(X+Z)=XX+XZ+XY+YZ Distributive law
= X+XZ+XY+YZ Rule 7
= X+XY+YZ Rule 10
= X + YZ Rule 10
39
De Morgan's theorems
Example:
( )
Z X Y X
Z Y X
YZ X YZ X
+ =
+ =
= +
C B A C B A = + + +
+ + + = C B A C B A
( 3-6)
( 3-7)
Augustus De Morgan
(1806-1871)
Remark: They can be used for:
rearranging or simplifying Boolean expressions
conversion between AND and OR gates
40
Obtaining Boolean Expressions for Gate Networks
Gate Networks: Two or more logic gates
connected together
41
Obtaining Boolean Expression from Truth Table
Given : Desired truth table.
Problem : To derive Boolean expression
INPUTS OUTPUT
A B Z
0 0 1
0 1 0
1 0 1
1 1 1
42
Sum-of-product (SOP) form
Procedure :
1. Form "product of inputs" column
2. Complement variables in each product if corresponding input is a
'0'.
3. Form "sum of products" expression from rows where Z = 1.
A B Z PRODUCT
OF INPUTS
0 0 1
0 1 0
1 0 1
1 1 1
AB
Z AB AB AB = + +
AB
AB
AB
Inputs Output
43
Sum-of-product (SOP) form
Remark:
Sum-of-products (SOP) expression is two or more
ANDfunctions ORed together. Eg:
AB+CD
ABC+D

A single bar cannot extend over more than one

variable in a term, eg. is not allowed.
Any logic expression can be changed into SOP form
by Boolean algebra
AEG FG E D C B A + +
C AB
44
Sum-of-product (SOP) form
Example
I/P's O/P PRODUCTS
A B C Z TERMS
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
C B A
C B A
BC A
C B A
C B A
C AB
ABC
C B A
C AB C B A C B A C B A Z + + + =
Given
45
Product-Of-Sum form
Procedure:
1. Form "sum of inputs" column
2. Complement variables in each sum if corresponding
input is a 'l'
3. Form "product of sums" expression from rows where
output Z = 0
46
Product-Of-Sum form
Example:
I/P's O/P SUM OF
X Y Z INPUTS
0 0 1
0 1 0
1 0 0
1 1 1
Y X +
Y X +
Y X +
Y X +
Y) X )( Y (X Z + + =
Remark: Can always convert to SOP form:
X Y XY Y Y X Y XY X X Z + = + + + =
Given
47
Product-Of-Sum form
Remark:
ANDof two or more OR functions.
Examples of (POS) form:
(A+B)(B+C)
A(B+C)

) )( )( ( G E A G F E D C B A + + + + + + +
48
Boolean Expression from Truth Table
For SOP (sum of products) and POS (product of
sums) canonical expressions, the corresponding
circuit implementation is always a two-level gate
network
=> input signals pass through maximum of 2
gates (excluding input variable inversions)
49
Boolean Expression from Truth Table
'SUM-OF-PRODUCTS' NETWORKS
'AND OR' gate 2-level system
D
E
F
A
B
C
ABC
DEF
ABC+DEF
50
Boolean Expression from Truth Table
or using only NAND gates, we get
A
B
D
C
E
F
ABC +DEF
ABC
DEF
51
Boolean Expression from Truth Table
'PRODUCT-OF-SUMS' NETWORKS
'OR AND' gate 2-level system
52
Boolean Expression from Truth Table
using only NOR gates,
A
B
D
C
E
F
(A+B+C)(D+E+F)
A+B+C
D+E+F
53
Simplification of Boolean expression
More than 1 Boolean expression can be derived for a
given combinational logic problem
Redundancies may exist
Example:
54
Simplification of Boolean expression
Simpler circuit with the same logic
55
Simplification of Boolean expression
Example : Consider
ABC BC A C B A C AB Z + + + =
Redundant in B and C
C A AB Z + =
X X and
X X
=
= +
1 .
1
) ( ) ( B B C A C C AB Z + + + =
56
Simplification using Boolean Algebra
Example:
XZ
Z X X
Z X X X
Z X XY Y X X
Z X Y Y XY Y X XX Z X Y X Y X
=
+ =
+ + =
+ + + + =
+ + + + = + + +
) (
) ))( 1 ( (
) )( 0 (
) )( ( ) )( )( (
57
Simplification using Boolean Algebra
Using Boolean Algebra approach sometimes
lead to a blind alley, e.g.
C A C B A B
C A C A B
C A C A A B
C AB C A B A
C AB C B A
C AB C B B A
C AB B A C B A
C AB C C B A C B A
C AB BC A C B A C B A Z
+ + =
+ + =
+ + =
+ + =
+ + =
+ + =
+ + =
+ + + =
+ + + =
) (
) (
12) (rule ) (
) (
) (
No further reduction appears possible!
58
Simplification using Boolean Algebra
If we know there are 2 redundancies B and A,
C B C A
C AB BC A C B A C B A Z
+ =
+ + + =
59
Simplification using Karnaugh Map
Systematic technique to obtain the minimal
form (suggested by Maurice Karnaugh)
Graphical approach consists of array of
squares
Based on:
Assume expression is in SOP form
1 = + A A
Maurice Karnaugh
(1924- )
60
Simplification using Karnaugh Map
Three variables map (8 squares/cells)
C B A
C B A
C AB
C B A
C B A
BC A ABC C B A
B A B A AB
B A
C
C
Remark: Only one variable changes between
two adjacent cells or squares
61
Simplification using Karnaugh Map
Another way to label the map
C B A
C B A C AB
C B A
C B A
BC A
ABC
C B A
00
AB
0
C
1
01 11 10
From SOP expression, 1 is input to map for
each of its term
62
Simplification using Karnaugh Map
Example : Two-cell groups (redundant of one
variable)
1
1 1 1
00
AB
0
C
1
01
11 10
Z ABC ABC ABC ABC = + + +
63
Simplification using Karnaugh Map
Example (cont): Two-cell groups (redundant of one
variable)
1
1 1 1
00
AB
0
C
1
01
11 10
Z AC = +
Z ABC ABC ABC ABC = + + +
64
Simplification using Karnaugh Map
Example (cont): Two-cell groups (redundant of one
variable)
1
1 1 1
00
AB
0
C
1
01
11 10
AB
+
Z ABC ABC ABC ABC = + + +
Z AC =
65
Simplification using Karnaugh Map
Example : Four-cell groups (redundant of two variables)
1 1 1 1
1 1
00
AB
0
C
1
01 11 10
Z ABC ABC ABC ABC ABC ABC = + + + + +
66
Simplification using Karnaugh Map
Example (cont) : Four-cell groups (redundant of two
variables)
1 1 1 1
1 1
00
AB
0
C
1
01 11 10
Z C =
+
Z ABC ABC ABC ABC ABC ABC = + + + + +
67
Simplification using Karnaugh Map
Example (cont): Four-cell groups (redundant of two
variables)
1 1 1 1
1 1
00
AB
0
C
1
01 11 10
A + Z C =
Z ABC ABC ABC ABC ABC ABC = + + + + +
68
Simplification using Karnaugh Map
Example : Four-cell groups (redundant of two variables)
1 1
1 1
00
AB
0
C
1
01 11 10
Z B =
Z ABC ABC ABC ABC = + + +
69
Simplification using Karnaugh Map
Example :
1
1 1 1
00
AB
0
C
1
01 11 10
( ) ( ) ( )
( ) 1 1 1
0 1 1 1 0 1 1 1 0
C
C C C F
B A
+ B A + B A + B A =
70
Simplification using Karnaugh Map
Example (cont):
1
1 1 1
00
AB
0
C
1
01 11 10
BC
( ) ( ) ( )
( ) 1 1 1
0 1 1 1 0 1 1 1 0
C
C C C F
B A
+ B A + B A + B A =
+
71
Simplification using Karnaugh Map
Example (cont):
1
1 1 1
00
AB
0
C
1
01 11 10
BC
( ) ( ) ( )
( ) 1 1 1
0 1 1 1 0 1 1 1 0
C
C C C F
B A
+ B A + B A + B A =
AB
+
+
72
Simplification using Karnaugh Map
Example (cont):
1
1 1 1
00
AB
0
C
1
01 11 10
BC
( ) ( ) ( )
( ) 1 1 1
0 1 1 1 0 1 1 1 0
C
C C C F
B A
+ B A + B A + B A =
AC
AB
+
+
73
Simplification using Karnaugh Map
Example :
1 1
1 1
00
AB
0
C
1
01
11 10
Z ABC ABC ABC ABC = + + +
74
Simplification using Karnaugh Map
Example (cont):
1 1
1 1
00
AB
0
C
1
01
11 10
C A
+
Z ABC ABC ABC ABC = + + +
75
Simplification using Karnaugh Map
Example (cont):
1 1
1 1
00
AB
0
C
1
01
11 10
C A C B
+
Z ABC ABC ABC ABC = + + +
76
Simplification using Karnaugh Map
Example :
Z A B B = C + +ABC + C
77
Simplification using Karnaugh Map
Example :
Z A B B = C + +ABC + C
78
Simplification using Karnaugh Map
Example :
Z A B B = C + +ABC + C
C
+
Z=
79
Simplification using Karnaugh Map
Example :
Z A B B = C + +ABC + C
C
A
+
+
Z=
80
Simplification using Karnaugh Map
Example :
Z A B B = C + +ABC + C
C
A
B
+
+
Z=
86
Simplification using Karnaugh Map
Four variables map (16 Squares)
D C B A
D C B A D C AB
D C B A
D C B A
ABCD
B A B A
AB
B A
D C
D C
CD
D C
D C B A D C AB D C B A
BCD A
CD B A
CD B A
D C B A D BC A
D ABC D C B A
87
Simplification using Karnaugh Map
Four variables map
D C B A D C B A D C AB
D C B A
D C B A
ABCD
AB
CD
D C B A D C AB D C B A
BCD A
CD B A
CD B A
D C B A D BC A
D ABC D C B A
00
01 11 10
00
01
11
10
88
Simplification using Karnaugh Map
Group of 2 (1 redundant variable)
89
Simplification using Karnaugh Map
Group of 2 (1 redundant variable)
90
Simplification using Karnaugh Map
Group of 4 (2 redundant variables)
91
Simplification using Karnaugh Map
Group of 4 (2 redundant variables)
92
Simplification using Karnaugh Map
Group of 8 (3 redundant variables)
93
Simplification using Karnaugh Map
Group of 8 (3 redundant variables)
94
Simplification using Karnaugh Map
Example :
F ABCD ABCD ABCD ABCD = + + +
( ) ( ) ( ) ( ) 1100 1110 0001 1001
= + F ABD BCD imal form (min )
95
Simplification using Karnaugh Map
Dont Care States
Example:
A B C Z
0 0 0 1
0 0 1 X
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 X
1 1 1 0
AB
C 0 1
00
01
11
10
0
X
X
0
0
1
1 1
96
Simplification using Karnaugh Map
Dont Care States
Example:
A B C Z
0 0 0 1
0 0 1 X
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 X
1 1 1 0
AB
C 0 1
00
01
11
10
0
X
X
0
0
1
1 1
1 = C B A
Set:
1
97
Simplification using Karnaugh Map
Dont Care States
Example:
A B C Z
0 0 0 1
0 0 1 X
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 X
1 1 1 0
AB
C 0 1
00
01
11
10
0
X
X
0
0
1
1 1
1 = C B A
Set:
minimal expression
=
B
1
101
Procedure for Combinatorial Logic
implementation
Procedure:
Obtain truth table for problem
Obtain Boolean expression from truth table
Minimization of Boolean expression (by
Boolean algebra or Karnaugh map)
Circuit implementation
102
Procedure for Combinatorial Logic
implementation
EXAMPLE
The 4Ks company comprises four partners, P1, P2, P3 and
P4 who own 35%, 30%, 15%and 20%of the business,
respectively.
Company decisions are made by voting and a total vote of at
least 70% of the ownership is required to pass a motion.
Each partner has a 2-position switch which must be
switched ON to vote YES.
A lamp will light up if the total voted is YES.
Draw up a truth table for the voting scheme and design
combinational logic circuit for the scheme.
Input
Output
103
Procedure for Combinatorial Logic
implementation
P1
35%
A
P2
30%
B
P3
20%
C
P4
15%
D
Total
Vote
%
Lamp
L
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
15
20
35
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
30
45
50
65
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
35
50
55
70
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
65
80
85
100
0
1
1
1
Example (cont)
Solution:
PARTNER'S
SWITCHES A, B, C, D :
ON = 1 (YES)
OFF = 0 (NO)
LAMP L:
ON=1 (YES)
OFF=0 (NO)
104
Procedure for Combinatorial Logic
implementation
P1
35%
A
P2
30%
B
P3
20%
C
P4
15%
D
Total
Vote
%
Lamp
L
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
15
20
35
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
30
45
50
65
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
35
50
55
70
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
65
80
85
100
0
1
1
1
Example (cont)
Solution:
PARTNER'S
SWITCHES A, B, C, D :
ON = 1 (YES)
OFF = 0 (NO)
LAMP L:
ON=1 (YES)
OFF=0 (NO)
105
Procedure for Combinatorial Logic
implementation
P1
35%
A
P2
30%
B
P3
20%
C
P4
15%
D
Total
Vote
%
Lamp
L
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
15
20
35
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
30
45
50
65
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
35
50
55
70
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
65
80
85
100
0
1
1
1
Example (cont)
Solution:
PARTNER'S
SWITCHES A, B, C, D :
ON = 1 (YES)
OFF = 0 (NO)
LAMP L:
ON=1 (YES)
OFF=0 (NO)
106
Procedure for Combinatorial Logic
implementation
Example (cont):
1
1 1
1
AB
CD
00
01 11 10
00
01
11
10
L ABD ACD ABC = + +
CD B A D ABC ABCD D C AB L + + + =
Minimalization of Boolean Expression
107
Procedure for Combinatorial Logic
implementation
Example (cont):
Circuit implementation:
L ABD ACD ABC = + +
A B C D
ABD
ACD
ABC
L
108
Procedure for Combinatorial Logic
implementation
NAND and NOR gates are universal
building blocks
To implement logic circuit using only
NAND or NOR gates.
DeMorgans theoremis used to convert
expression convenient for
implementation
109
Procedure for Combinatorial Logic
implementation
Example
Implement Boolean expression
using only NAND gates.
AD AB Z + =
AD AB
AD AB Z
- =
+ =
Solution:
Using De Morgans theorem,
so that desired circuit is
A
B
D
Z
AB
AD
TTL and CMOS Integrated Circuits
TTL (Transistor-Transistor Logic) (based on BJ T
technology):
Digital Input:
Logic zero (0) or low (L): less than 0.8V
Logic one (1) or high (H): greater than 2.0V
Voltage range 0.8V to 2.0V is a dead zone where the input
state is undefined.
Digital output: ranges between 0 and 0.5V for low and
between 2.7V and 5V for high.
110
TTL and CMOS Integrated Circuits
CMOS (Complementary Metal Oxide
Semiconductor) (based on FET technology):
The logic levels depend on the supply voltage.
Very little power consumption, but susceptibility to
damage from static electricity.
111
TTL and CMOS input and
output levels (assume that
both devices are powered
by a 5 V DC supply)
Manufacturer IC Data Sheets
Labeling System of TTL IC - AAxxyzz
AA: manufacturers prefix (SN: TI and others; DM:
National Semiconductor)
xx: military (xx=54) and industrial (xx=74) quality
y: different internal designs (no letter: standard TTL; L:
low power dissipation; H: high power dissipation; S:
Schottky type; AS: advanced Schottky; LS: low power
Schottky; ALS: advanced low power Schottky)
(Schottky devices have faster switching speeds and
require less power.)
zz: sequence number in data book (For example,
DM74ALS00 (QUAD NAND))
112
Digital IC Output Configurations
Open collector output type TTL devices (e.g., 7401,
7403, 7405, 7406)
Normally, a pull-up resistor is added to the output.
114
117
The Data Sheets for 5400 and 7400 NAND
gate IC
118
The Data Sheets for 5400 and 7400 NAND
gate IC
119
The Data Sheets for 5400 and 7400 NAND
gate IC