MDLC21

USN j1

M S RAMAIAH INSTITUTE OF TECHNOLOGY (AUTONOMOUS INSTITUTE, AFFILIATED TO VTU) BANGALORE - 560 054

SEMESTER END EXAMINATIONS - JUNE 2010

Course & Branch : Subject : Subject Code : M.Tech ( Digital Electronics and Communication) Real Time Embedded System MDLC21 Se mester Max. Mark s Du rati on : : II 10 0 3 Hrs

Instructions to the Candidates: Answer any Five Full questions.

a)

b)

Compare i) Hard and Soft Real Time Systems ii) RAM and EPROM features iii) Harvard and Princeton Architectures Explain the following terms with an example.
i) Single purpose processor ii) Deterministic system

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iii) Embedded system iv) Immediate addressing mode

2. a) i) Describe ii) UART (12)

DMA

with block diagrams and timing diagrams.

b) A processor has an onchip WDT and ADC. A 16 bit register operating (08) at a clock frequency of 40 MHz is used for the WDT design. Determine its resolution and also the terminal count value for generating a delay of 1 msec. If the overflow interrupt is generated

after the last count FFFFH, what is the delay generated? The ADC has 8 bits for the digital output and operates in the range - 5V to +5V. Determine the digital output when analog input is -3V. What is the analog input for generating an output of 40H and also its resolution? 3. a) Explain the differences between hardware and software interrupts (12) with examples. What are the actions taken by the processor when an interrupt occurs? How the shared data problem can be solved using interrupt instructions? Illustrate with an example.

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b) Explain the terms interrupt latency and context switching. There are (08) 3 processes with low, medium and high priorities. The execution time
of these processes are 250sec, 180sec and 100sec respectively. The deadline of the low priority process is 700sec and the minimum interrupt latency for starting any ISR is 150sec. Is it possible to complete the execution for the low priority process well within the deadline, if all the three processes interrupt the system together. Context switching time is negligible. What is the worst case latency for the low priority process? 4. a) Describe i) Function queue scheduling and (12) ii) RTOS architectures, with algorithms. b) Explain the algorithm for a simple bridge using RR with interrupts (08) architecture. 5. a) Explain i) Polled loop system (12)

ii) Interrupt driven system iii) Foreground - background systems.

b) Explain Kernel hierarchy and different types of kernel with a (08) diagram. 6. a) Explain scheduling and dispatching mechanisms. Describe rate (12) monotonic scheduling and also priority based preemptive scheduling schemes. b) Describe the function of the various states and the switching (08) operation using a Task control block structure and state transition diagram, in a multitasking system. 7. a) Explain the terms : Semaphores i) Mailboxes for interprocess communication ii) iii) POSIX features
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b)

Mention the fifteen point strategies for synchronization.

Compare MFT and MVT memory management techniques i) ii) VxWorks and cos RTOS

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Describe automatic chocolate vending machine design with a block diagram. ***************
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