Intels Tri-Gate Transistor Technology

With High-K gate dielectrics, metal gates and strain engineering

Why this technology was introduced?

Silicon-only planar transistors are fast approaching their scaling limit. Short channel effects limiting scaling into sub nanometer regime. Oxide thickness cannot be scaled down further, problems of tunneling. Need to keep Silicon technology as the base technology while innovating future devices; cost is an important factor. Performance and power dissipation need to be improved. Smaller is faster !!

Introduction

Smaller transistors consume less power but With increasing density, the overall chip consumes more power and generates more heat. Also, power leakage becomes more problematic

What is a transistor?
A simple switch - current flows from source to drain when gate is at certain voltage; otherwise it doesnt flow. A traditional planar transistor has a source, drain, channel with the gate and an insulating layer above the plane.
Courtesy: IEEEspectrum
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Silicon industry has been scaling twodimensional or planar transistors just fine for 50 years.
With further shrinking, it gets very difficult to turn off.

For 250-nm transistors,the power-supply voltage was 2.5 volts; for 180 nm-1.8 V; for 130 nm-1.3 V. The pattern was very regular until 90 nm, but it reached a limit. Instead of 0.9 V, the industry used--1.2 V. Even at 45 nm, the industry still used 0.9 V instead of 0.45 V This was due to body current leakage.

Courtesy: Intel Corp

Solutions

Two very powerful ways to boost the effectiveness of the transistor gate

Ultrathin Body Silicon-On-Insulator (UTB SOI)

Tri-Gate transistors.

These schemes focus on making the channel easier to control.

UltraThin Body SOI

replaces the bulk silicon of a normal transistor with a thin layer of silicon built on an insulating layer. also known as a fully depleted SOI

Courtesy: IEEEspectrum
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FD-SOI vs. Bulk and PD-SOI transistors

Courtesy: Intel Corp.

In Bulk Transistors, the silicon substrate voltage exerts some electrical influence on the inversion layer and this influence of substrate voltage degrades electrical sub-threshold slope (transistor turn-off characteristics). In Partially Depleted SOI, the floating body voltage exerts some electrical influence on the inversion layer, degrading subthreshold slope.
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Fully depleted-SOI

FD SOI

The floating body is eliminated =>improves the subthreshold slope. The very thin silicon layer enables the silicon under the transistor gate (the body of the transistor) to be fully depleted of charges. Gate can now very tightly control the full volume of the transistor body

Why UTB SOI?

Issues

similar to conventional planar CMOS transistors Most existing designs and manufacturing techniques will work don't need doped channels Very appealing in lowpower applications

The channel of a UTB SOI should be no more than about one-fourth as thick as the length of the gate Hence, current carrying capacity is reduced=>lower speed Ultra thin wafers hard to find.
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Tri-Gate Transistor

This design turns the transistor channel on its side, creating a protruding fin between the source and drain that can be controlled by a gate on three sides instead of one.

Courtesy: Intel Corp.

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Intels 22nm process technology

By integrating the 3D design of the tri-gate transistor with advanced semiconductor technology such as strain engineering and high-k/metal gate stack. The tri-gate transistor significantly improves the electrostatics and short-channel performance of the device. For faster and cooler operation of the non-planar transistors=> strain engineering and high-k/metal gate stack
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Planar vs. tri-gate transistor

Fins

Gates

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Strain engineering

natural tendency for atoms inside compounds to align with one another. When deposited on top of a substrate with atoms spaced farther apart, the atoms in silicon stretch to line up with the atoms beneath. Electrons experience less Stretch the n-doped resistance and flow up to 70 areas while percent faster, which can lead compressing the pto chips that are up to 35 doped ones percent faster Courtesy: IBM 14

High-K dielectric/metal gate electrodes

Dielectric constant, K refers to a material's ability to concentrate an electric field => greater capacitance =>more charge stored for the same thickness of insulator SiO2 is running out of atoms for further scaling but still scaling continues Materials chosen for replacing SiO2 should be thicker (to reduce leakage power) but should have a high-K value. "High-k" materials, such as hafnium dioxide (HfO2), zirconium dioxide (ZrO2) and titanium dioxide (TiO2) inherently have a dielectric constant or "k" above 3.9, the "k" of SiO2 Capacitance >60% =>much faster;gate dielectric leakage- >100x reduction => cooler operation
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Problems with High-K

Threshold Voltage Pinning- high-K and Polysilicon gate are incompatible due to Fermi level pinning at the High-K and Polysilicon interface which causes high threshold voltages in transistors Phonon scattering - High-K/ Polysilicon transistors exhibit severely degraded channel mobility due to the coupling of phonon modes in high-K to the inversion channel charge carriers.

Courtesy:Intel Corp.
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Metal gate electrodes

To switch from a polysilicon gate to a metal one is the solution As a conductor, metal can pack in hundreds of times more electrons than silicon.

bond between the high- k dielectric and the metal gate is much better than that between the dielectric
and the silicon gate=>solves fermi level pinning enhances transistor mobilities and hence overall

transistor performance
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Why tri-gate transistor technology over UTB SOI?

gate brackets the channel on three sides=>bigger channel=>higher current carrying capacity best R&D results suggest that a 25-nm trigate can carry about 25 percent more current than a UTB SOI The vertical structure supports a higher density, as the fins can be placed as close together By using multiple fins traversed by the gate, high drive current can be obtained

Courtesy: Intel Corp.

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Issues

to pattern the fins with the required fidelity of the fin width and height, and do it for billions of transistors Controlling the width of the fin is important to limiting the short-channel effect Too wide, and we dont get nice fully depleted behavior. Too narrow, and there is too much series resistance A taller fin delivers more drive current, but at a higher gate capacitance. For a 20-nm transistor-fin must be about 10 nm wide and 25 nm high unusual geometry also poses challenges for doping
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Experimental results
Increase in drive current

Decrease in Off current

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Tri-gate vs. planar-gate delay

Courtesy: Intel Corp.

22nm Tri-Gate transistors provide improved performance at high voltage and an performance gain at low voltage

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Future developments

The fins on the 22nm tri-gate appear to be relatively short, and over the next two nodes Intel will likely try to make them taller. That provides more area. Tri-Gate needs to be as repeatable for other types of less regular SoCs as for processors New channel materials such as indium gallium arsenide in the NFET and germanium in the PFET are being researched full 2D confinement architectures gate-all-around (GAA), nanowire etc.

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GAA and Nanowires

GAA devices have gate wrap entirely around the device Nanowires are an extreme case of GAA devices, having height and width dimensions roughly the same (or even cylindrical) and small (<10nm) dimensions.
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Conclusions

The 22 nm tri-gate transistor technology has shown following results: Dramatic performance gain at low operating voltage, better than Bulk, PDSOI or FDSOI--37% performance increase at low voltage and >50% power reduction at constant performance. Improved switching characteristics (On current vs. Off current) Higher drive current for a given transistor footprint Only 2-3% cost adder (vs. ~10% for FDSOI).
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References

http://www.intel.com http://spectrum.ieee.org www.research.ibm.com/resources/press/strainedsilicon/

J. Kavalieros, B. Doyle, S. Datta, G. Dewey, M. Doczy, B. Jin, D. Lionberger, M. Metz, W. Rachmady, M. Radosavljevic, U. Shah, N. Zelick, and R. Chau. Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates, and Strain Engineering, A. Breed and K.P. Roenker, Dual-gate (FinFET) and TriGate MOSFETs: Simulation and design, Proceedings of the International Semiconductor Device Research Symposium (ISDRS2003) Doyle, B.S. Datta, S. Doczy, M. Hareland, S. Jin, B. Kavalieros, J. Linton, T. Murthy, A. Rios, R. Chau, R. Components Res., Intel Corp.High performance fully-depleted tri-gate CMOS transistors, IEEE Electron Devices Letters
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