1) Explain the cadence spectre power analysis methodology of transistor level circuits.

2) As an ASIC engineer, you are familiar with library files slow.lib, fast.lib and typical.lib. Comment on the comparative static power dissipation values obtained while using the corner models individually. 3) Name two specific types of low power techniques followed in industry using the following abstraction levels. a) Device level b) Circuit level c) Logic level 4) As a CEO of service based VLSI Company existing in 1996, you demonstrated different ways to reduce the power dissipation, as employed in your company to your customers. List them. 5) What is the difference between parallel and pipelined architectures? Explain typical structures for the following function F = AT2+BT+C Note that A, B, T and C are sampled data obtained at every 5nsec. 6) The decoder logic of a processor performs the following operation repeatedly: Up load MUL ADD STORE JUMP Up Design an FSM with the following Guidelines: a) Assign the states for the above operation b) Draw the state transition diagram c) Change individual states and compare power dissipation for 3 typical state values for FSM. 7) While performing STA, you encounter setup violation. What are the possible ways to overcome the problem by not affecting the power dissipation of the design? 8) Your colleague doesnt want to use sense amplifier while reading the data from SRAM. Warn him about possible disadvantages in not using the sense amplifier in his design. 9) A series of 32 bit data are being received. The numbers divisible by 4 only are to be passed to compute f(x). The other numbers are to be rejected. Design a suitable Pre-computation logic and draw the scheme. 10) Assuming the following fanout cases for a 2 input NAND gate: a) Cg b) 10Cg c) 0.1Cg

Draw the Input/Output voltage, Short circuit current and total Current curves 11) Derive the effective power dissipation considering cases for an Inverter as shown in following figure. Assume CL is the load capacitance at OUT node. a) Input is zero b) output changes
VDD

from 0 to 1

IN

OUT

GND

12) Given a 3 input NAND gate, derive the time constant for the following cases. Assume the device resistance=R and the intermodal capacitance=load capacitance=CL. a) Pervious state: A=1, B=1, C=0 next state: A=1, B=1, C=1; b) Pervious state: A=1, B=1, C=0 next state: A=1, B=0, C=0; c) Pervious state: A=0, B=1, C=1 next state: A=1, B=1, C=1; 13) Is static power equal to sub threshold leakage? a) Yes b) NO c) Numerically same d) none of the above Justify your answer. 14) A memory operates using a power supply of 1.8V. Assume the total capacitive load offered by memory is 100fF. The pre charging voltage is 1.2V. The frequency of clock being 10 MHz and the activity factor for read operation begin 0.5, calculate the power dissipation. Compare the power dissipation with that of another memory operating in full swing of Vdd. 15) A 32 bit data is considered to have 5 bits of sign bit with an effective capacitance value of 10fF per bit, the remaining bits being uniform noise margin of capacitance value 1fF per bit. Assuming frequency of operation to be 1GHz, and a supply voltage of 1V, calculate the power dissipation of the system.