VHDL process statements

Recall that concurrent signal assignment statements all operate in parallel. The VHDL process statement is effectively a block around a bunch of logic and control. Inside of a process statement, statements are executed sequentially which allows us to introduce sequencing and control. Inside of a process statement, we can use additional VHDL syntax like if-thenelse and case statements. Each VHDL process statement operates in parallel with other processes and in parallel with other concurrent VHDL statements. Note: Operations with sequencing (like Case and If-Then-Else) must, and can only, be used inside of a process.

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Example of a VHDL process statement (using if-else)

The following code implements a 2-to-1 multiplexer inside of a process statement.

library ieee; use ieee.std_logic_1164.all; entity multiplexer_2to1 is port (x0,x1 : in std_logic; s : in std_logic; f : out std_logic ); end multiplexer_2to1;

-- multiplexer inputs -- multiplexer select line -- multiplexer output

architecture prototype of multiplexer_2to1 is begin process (x0,x1,s) -- process has a sensitivity list. begin if (s = '0') then -- can use if-then-else inside of a process f <= x0; else f <= x1; end if; end process; end prototype;

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Breakdown of a process statement

The syntax of a process statement is:

[process_name] : process sensitivity_list begin -- statements. end process;

A process can be named; the naming of a process is optional. The statements inside of the beginend are evaluated sequentially.

A process has a sensitivity list.

The execution of the statements inside of the process happens when the value of any signal in the sensitivity list changes. So, the signals that should be listed in the sensitivity list are those that can cause outputs to change inside of the process.
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Comments
Signals changed inside of the process are not changed until the process has completed evaluating every statement inside of the beginend. There is no delay associated with the process itself; i.e., a process is a programming construct and is assumed to execute in 0 time. Of course, the statements inside of the process can have delays associated with them.

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Example of a VHDL process statement (using if-elsif-else)

The following code implements a 4-to-1 multiplexer inside of a process statement.
library ieee; use ieee.std_logic_1164.all; entity multiplexer_4to1 is port (x0,x1,x2,x3 : in std_logic; s : in std_logic_vector(1 downto 0); f : out std_logic); end multiplexer_4to1;

-- multiplexer inputs -- select lines -- multiplexer outputs

architecture prototype of multiplexer_4to1 is begin process (x0,x1,x2,x3,s) begin if (s = "00") then f <= x0; elsif (s = "01") then -- notice the syntax elsif without spaces f <= x1; elsif (s = "10") then f <= x2; else f <= x3; end if; end process; end prototype;

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Example of a VHDL process statement (using case) (1)

Consider a circuit that receives a code for a decimal digit 09 encoded using 4-bits. We want to decide how to drive the segments of a 7-segment display in order to illuminate the decimal digit we receive at the circuit input.

segment 3

segment 2

segment 4 segment 6

segment 1

segment 5

segment 0

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Example of a VHDL process statement (using case) (2)

We can write a VHDL Description using a process and a case statement:
library ieee; use ieee.std_logic_1164.all; entity bcd_decoder is port (code : in std_logic_vector(3 downto 0); -- coded inputs leds : out std_logic_vector(6 downto 0)); -- signal outputs end bcd_decoder; architecture prototype of bcd_decoder is begin process (code) begin case code is when "0000" => leds <= 0111111" ; when "0001" => leds <= 0110000" ; when "0010" => leds <= 1011011" ; when "0011" => leds <= 1111000" ; when "0100" => leds <= 1110100" ; when "0101" => leds <= 1101101" ; when "0110" => leds <= 1101111" ; when "0111" => leds <= 0111000" ; when "1000" => leds <= "1111111" ; when "1001" => leds <= 1111100" ; when others => leds <= null ; end case; end process; end prototype;

-- the default case.

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Comments on the case statement

Notice that our process still has a sensitivity list.

The syntax of the case statement is:

case signal_name is when (condition1) => (signal_assignment1) ; when (condition2) => (signal_assignment2) ; when others => (default_assignment); end case;

Note: Our case statement has a default for situations where no condition matches (we use the others keyword).

In the default assignment we can use the null keyword which is much like saying doesnt matter, so do nothing/whatever.
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Simulation of the BCD decoder (using case statement)

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Comments
In addition to statements like case statements and if-then-else statements, the concurrent signal assignment (i.e., lhs <= rhs ;) works inside a process (we used it!). However, other concurrent assignment statements do not work! We cannot use a selected or conditional signal assignment statement inside of a VHDL process.

This is to keep concurrent and sequential statements separated.

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VHDL for sequential circuits

Now that we have VHDL process statements at our disposal, we can describe synchronous circuits in VHDL. Describing latches is straight-forward. Describing flip-flops requires the concept of signal attributes (since flip-flops are edge triggered).

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VHDL description of a d-latch

The following implements a gated D-latch (active high) in VHDL.

library ieee; use ieee.std_logic_1164.all; entity dlatch is port (d, g : in q, qbar end dff;

std_logic; : out std_logic);

-- data and gate inputs -- q and qbar output

architecture prototype of dlatch is begin process (d,g) begin if (g=1) then q <= d; qbar <= not d; end if; end process; end prototype;

-- q becomes d when g is high.

-- otherwise, does not change.

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Signal attributes
Definition: When the value of a signal has changed (i.e., a signal transition), we say that an event has occurred on the signal. Definition: Signals have properties that we can pay attention to these properties are called attributes. An event is a type of attribute. The syntax for observing an attribute on a signal is: signal_nameattribute_name -- notice tick mark between the -- signal_name and the -- attribute_name

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Detecting edge triggering

Using the event attribute, we can now detect both the rising edge and falling edge of a signal. Detection of the rising edge (assuming a signal called temp): (tempevent and temp = 1) This detects a change in the value of temp to a value of 1.

Detection of the falling edge (assuming a signal called temp): (tempevent and temp = 0)

This detects a change in the value of temp to a value of 0.

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VHDL description of a dff (positive edge-triggered)

We need the event attribute to detect the rising edge of the clock. We need a process because we will need an if-then statement to change the output when we see the rising edge of the clock.

library ieee; use ieee.std_logic_1164.all; entity dff is port (d, clk : in std_logic; q : out std_logic); end dff; architecture prototype of dff is begin process (clk) begin if (clkevent and clk=1) then q <= d; end if; end process; end prototype;

-- data and clock inputs -- dff output

-- q becomes d on rising edge of clock -- otherwise, does not change.

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Simulation if dff (positive edge triggered)

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VHDL description of a 16-bit register (composed of positive edge-triggered dffs)

If we had multiple DFF (i.e., a register), we only need to change signals d and q in the VHDL Description from type std_logic to type std_logic_vector. Example: A VHDL Description of a register consisting of 16-bits:
library ieee; use ieee.std_logic_1164.all; entity reg16 is port (d : in std_logic_vector(15 downto 0); clk : in std_logic; q : out std_logic_vector(15 downto 0)); end reg16; architecture prototype of reg16 is begin process (clk) begin if (clkevent and clk=1) then q <= d; end if; end process; end prototype;

-- data input (16-bits). -- clock input -- register output (16-bits).

-- q becomes d on rising edge of clock -- otherwise, does not change.

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VHDL description of a dff (negative edge triggered)

Just change the if-then statement in the previous example to be: if (clkevent and clk=0) then

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DFF with asynchronous set and reset signals

We can add signals to set and reset (in an asynchronous manner). We only need to change our if-then statement to account for these signals and our process sensitivity list. Note that there is a precedence due to the order of the if-then statement.
library ieee; use ieee.std_logic_1164.all; entity dffsr is port (d s, r, clk q end dffsr;

: in std_logic; : in std_logic; : out std_logic);

-- data input -- clock and control -- data output

architecture prototype of dffsr is begin process (clk,s,r) begin if (s = 1) then q <= 1; elsif (r = 1) then q <= 0; elsif (clkevent and clk=1) then q <= d; end if; end process; end prototype;

-- active high (precedence over reset). -- active high -- positive edge triggered.

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Simulation of the DFF with asynchronous set and reset

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Useful functions included in the std_logic_1164 package

It is so common to require positive and negative edge-triggering that the IEEE std_logic_1164 package defines two functions: rising_edge(clk) falling_edge(clk) is the same as (clkevent and clk = 1) is the same as (clkevent and clk = 0)

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Comments
There are other types of signal attributes in addition to the event attribute. We dont need them, so we wont talk about them.

You can add other types of control signals in addition to the set and reset in a similar fashion to what we have seen. You can make the set and reset signals synchronous by changing the structure of the if-then statement inside the process. You can make other types of flip-flops (e.g., TFF) using code very similar to what we have seen.

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Describing state machines in VHDL

Its easy to describe a Moore machine in VHDL using two VHDL processes. The first process is coded to determine the next state based on the current state and the current inputs. The second process is coded to use the clock and clockevent attribute to update the current state with the next state (update on the clock edge). We also introduce an enumerated type to maintain the possible states of our state machine. We do this using VHDL syntax for defining a type.

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VHDL types
We need to introduce a new type to represent the states of our state machine. The syntax to declare a new type is: type type_name is ( value_1, value_2, , value_n ) ; We also declared two signals in the declarative section of the architecture (as we normally might do), but have restricted their values to our new type.

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Example (1)
To illustrate Moore Machines in VHDL, we need a problem. Consider the following verbal description of a circuit: A circuit has one input X and one output Z. A 1 is asserted at its output Z when it recognizes the following input bit sequence 1011. The circuit does not reset once the pattern is found, but continues to recognize the string. E.g., if the input is ..1011011, then the output will be high twice: Z=..0001001.

We can proceed to draw a state diagram for a Moore Machine, and develop the VHDL from the state diagram.

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Example (2)
The state diagram for our verbal description is:

0
S0/0

1 1
S1/0 ..1

0 0
S2/0 ..10

1 1
..1011

1
..101

S3/0

S4/1

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Example (3)
We see that we have input X, output Z and Moore States 0 through 4.

We also have a clock and a reset signal.

The VHDL Description (entity and architecture declaration section only) is:
library ieee; use ieee.std_logic_1164.all; entity moore_machine is port (x, reset, clk : in std_logic; z : out std_logic); end moore_machine; architecture prototype of moore_machine is type moore_state is (moore_s0, moore_s1, moore_s2, moore_s3, moore_s4); signal curr_state, next_state : moore_state; begin -- architecture body here (see later) end prototype;

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Example (4)
First process: computes the next state of the system (the following VHDL process statement would be placed in the architecture body):
(curr_state, x) -- continued from previous box when moore_s3 => if (x = '1') then next_state <= moore_s4; else next_state <= moore_s2; end if; when moore_s4 => if (x = '1') then next_state <= moore_s1; else next_state <= moore_s2; end if; end case; end process;

process begin case when if

curr_state is moore_s0 => (x = '1') then next_state <= moore_s1; else next_state <= moore_s0; end if; when moore_s1 => if (x = '1') then next_state <= moore_s1; else next_state <= moore_s2; end if; when moore_s2 => if (x = '1') then next_state <= moore_s3; else next_state <= moore_s0; end if; -- continued in next box

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Example (5)
We see that the next state process has in its sensitivity list the current state and the input signal. These are the two things that are required to determine the next state. Based on the current state and the current input value, we can determine the next state value

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Example (6)
Second process (the following VHDL process statement would be placed in the architecture body): Update current state with the next state at the rising edge of the clock; If we have a reset, we need to return to our initial state.
process (clk, reset) begin if (reset = '1') then curr_state <= moore_s0; elsif (clk = 1 and clkevent) then curr_state <= next_state; end if; end process;

Note that the sensitivity list of this process includes the clock and reset signals which are those signals that can change the outputs that are possibly changed by the process.

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Example (7)
Our circuit also has output Z, which should also be included.

We can include a concurrent signal assignment statement (in addition to the two processes previously described) in the architecture body of the VHDL Description:

-- simple concurrent signal assignment to determine outputs. -- placed in the architecture body along with the two process statements. z <= '1' when (curr_state = moore_s4) else '0';

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Simulation

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Visualization of the two-process state machine description

Perhaps useful to visualize how the 2-process VHDL Description matches with the block diagram of a state machine:

Outputs CONCURRENT VHDL STATEMENTS

outputs

Circuitry for next state computation

next state

Registers to hold current state SECOND VHDL PROCESS

curr state

inputs

FIRST VHDL PROCESS

clock

reset

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