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2010 2nd IEEE International Symposium on Power Electronics for Distributed Generation Systems

Analysis of Topology and PWM Strategy for A New Multiple Input and Multilevel Inverter
Xuefeng Hu*,**, Chunying Gong*, Xiaolan*, Chen xin*, Jiayan Zhang**
* College of Automation EngeneeringNanjing University of Aeronautics and Astronautics, Nanjing 210016,China ** School of electrical Engineering and Information, Anhui University of Technology Ma anshan 234001,china Abstract-- In the multi-level inverter with two or more separate DC sources, the cascaded topology is usually used. in this paper, a new two-input multi-level inverter for interfacing with renewable energy resources is developed. The objective of this research is to propose an alternative topology of hybrid cascaded multilevel inverter. The proposed topology can reduce the number of required power switches compared to the traditional cascaded multilevel inverter. And the modified PWM technique is developed to reduce switching losses. PSIM (PowerSim) and Simulink in MATLAB are used to simulate the circuit operation and control signal. The simulation results show that this alternative topology can be applied for interfacing with renewable Energy resources as a hybrid multilevel inverter. Index Terms-- inverter seven-level; coordinate control; simulation

Fig.1 Proposed seven-level inverter

1. Mode I of operation As shown in figure 2 (a), when Q2 Q3 S5 are turned on, and all other controllable switches are turned off, The direction of the arrows shows the current paths through the load at this stage. Bridge output voltage UAB equals VD1 at this mode. 2. Mode II of operation Switchs Q1S5 are on,connecting the load positive terminal to VD1 and Q4 is on,connecting the load negative terminal to ground.all other controllable switches are Off, figure 2 (b)shows the current paths through the load at this stage. 3. Mode III of operation The two main switchs Q2Q3 and a auxiliaryS6 are on, and all other controllable switches are off. The figure 2 (c)shows the current paths through the load at this stage. Bridge output voltage UAB equals VD2 at this mode. 4. Mode IV of operation At this mode,main Switchs Q1Q4 and auxiliary S6 are on, all other controllable switches are off. The directions of the arrows show the current paths through the load at this stage. Bridge output voltage UAB equals (-VD2) at this mode,As shown in figure 2 (d). 5. Mode V of operation As shown in figure 2 (e), when Q1Q3 and all other controllable switches are off. Short-circuiting the load.Here, Define bridge output voltage UAB =+0 when Q1 andQ3 are on, and UAB =-0 when Q2Q4 are on at this mode. 6. Mode of operation At this mode Q2Q3 S6S7 are on, and all other controllable switches are off,As shown in figure 2 (g),The directions of the arrows show the current paths through the load at this stage. Bridge output voltage UAB equals 0.5*VD2. 7. Mode of operation

I. INTRODUCTION Recently, multilevel inverters have been studied, to obtain high qualified output voltage with lower harmonics and to reduce the EMI resulted from the highswitching frequency of the power devices[1]-[4]. with two or more separate DC sources, Conventional multilevel inverter employing cascaded combination of full-bridge is often used, which is consisted of simple power circuit Comparing with diode clamping method or flying capacitor method[5]-[6]. However, it requires multi-winding transformer to supply independent DClink voltages with a large number of switching devices. As a result, power losses by the multi-winding transformer and switching devices are increased. To reduce the number of switching devices, this paper presents a novel multilevel inverter with two independent DC voltages sources that have similar configuration or not,such as wind energy, solar energy, water energy, utility grid or some other kinds of energy The proposed multilevel inverter can synthesize an 7-level output. II. TOPOLOGY AND OPERATIONAL PRINCIPLE ANALYSIS Fig.1 shows the structure of the proposed seven-level inverter. The H-bridge is formed by four main power devices, Q1 to Q4. while S5, S6 and S7 are three auxiliary switches. VD1 =1.5*VD2. A. Operational Analysis The required seven voltage output levels are VD1, VD2, 0.5* VD2, 0, -0.5*VD2, -VD2, -VD1, which are generated as follows:

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The main switch Q4, is on, connecting the load negative terminal to ground.the auxiliary switch S7 is on, connecting the load positive terminal to C,and all other controllable switches are off. at this stage,Bridge output voltage UAB equals (-0.5*VD2 ) As shown in figure 2 (h).

2(f) Mode V-0

2(g) Mode

2(a)

Mode I

2(h) Mode Fig.2 Seven-level inverter operation mode

2(b) Mode II

2(c) Mode III

2(d) Mode IV

2(e) Mode V+0

B. Control Strategy Analysis In this paper, schematic diagram of the control strategy is shown in figure 3. First of all, determine logical partition of the reference signals according to the number of output voltage levels and amplitude modulation. When the reference signal is greater than zero and is in the C region, Q3 is turned on, Q4 is turned off. On the contrary, when the reference signal is less than zero and is in the D region, Q4 is on, Q3 is turned off. After the reference signal is entering the C range from 0 (Figure 4), we compare the reference signal with the carrier1to get the drive signals of S6 and S7, the drive signal of Q1 is complementary with (S6 + S7), then the output is twolevel for 0 and C1; When the reference signal is in the B area, compare it with the carrier 2, to get the driver signals of S5, S7 . S6 and S5 are complementary each other. At this area, the bridge output level is C2 or C1; when the reference signal into the area A, compare the reference signal with the carrier 3, to get the driver signals of S5andQ2 . S6 is complementary with S5, At this area, the bridge output level is C3 and C2; Where the C1, C2 and C3 is triangular carrier with the same amplitude and phase exactly ,but different positions. When the reference signal enter into the negative halfcycle in the D area, we compare the absolute value of it with the carrier 1, to get the drive signal of Q2, the drive signal of S7 is complementary with of Q2, At this area, the bridge output level is -0 and -C1; In the area E and F, the corresponding switch signals can be obtained by the same method. All the drive signals are shown in Figure 3 and 4.

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Fig. 3 Seven-level inverter control block diagram

Fig.7 Simulation waveform and Spectrum of Load voltage

IV. CONCLUSIONS In this paper, the topology of dual-input and multilevel single phase inverter has been proposed, the proposed topology can reduce the number of required power switches compared to a traditional cascaded multilevel single phase inverter. This configuration will be adequate for low-medium power UPS system. Also, a new PWM scheme has been developed to achieve the improvement in harmonics. Simulation results confirming this research have been presented.
Fig.4 inverter switching waveform

REFERENCES III. SIMULATION RESULTS In order to verify the proposed inverter and control method, a simulation model is established. Main parameters are: VD1 =690V VD2=460V L=1mH, C=10uF, R=100 , fs=3KHz m=0.65. Output voltage frequency is 50Hz. Simulation waveforms are shown in Fig.5 and Fig.6. Figure 5 is the bridge output voltage waveform and FFT result. It can be seen from this figure, the bridge output voltage waveform has seven-level, THD=18.15% Figure 6 depicts the load voltage waveform after LC filter and FFT result, THD=1.90%, it is close to ideal sinusoidal wave.
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Fig.6 Simulation Waveform and Spectrum of Leg Output Voltage

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